Array substrate and manufacturing method thereof, and display panel

Abstract

The present application belongs to the field of display panels and provides an array substrate and a method for preparing the same, as well as a display panel. The array substrate includes a base substrate, a first signal line, a first insulating layer, a second signal line, a thin film transistor, a second insulating layer, a third insulating layer, a fourth insulating layer, and a pixel electrode. The first insulating layer covers the first signal line, the second signal line is located in the first insulating layer and is connected to the first signal line through a first via hole; the second insulating layer covers the thin film transistor and has a second via hole; the third insulating layer covers the second insulating layer and has a third via hole connected to the second via hole; the fourth insulating layer covers the third insulating layer and is partially located in the second via hole and has a fourth via hole exposing the first electrode; the pixel electrode is connected to the first electrode through the fourth via hole. In the present application, the first via hole only needs to be etched by etching the first insulating layer. The second and fourth via holes are made separately, and the single etching depth is small, which is conducive to improving the yield of the array substrate.

Description

Technical Field

[0001] The present application relates to the field of display panels, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has the advantages of good image quality, small size, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and occupies a dominant position in the display field.

[0003] The array substrate is a crucial component of a thin-film transistor liquid crystal display (TFT-LCD) device. It comprises a base substrate and the circuitry formed on its surface. The manufacturing process often varies depending on the structure of the circuitry on the array substrate. A well-structured array substrate generally improves the yield of the array substrate. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a manufacturing method thereof, and a display panel, which can improve the yield of the array substrate.

[0005] A first aspect of an embodiment of the present application provides an array substrate, comprising:

[0006] A base substrate having a display area and a non-display area;

[0007] A first signal line is located in the non-display area;

[0008] a first insulating layer, covering at least the first signal line and having a first via hole exposing the first signal line;

[0009] a second signal line, located on a side of the first insulating layer away from the base substrate, and connected to the first signal line through the first via hole;

[0010] a thin film transistor, located in the display area, wherein a gate of the thin film transistor is connected to the second signal line;

[0011] a second insulating layer covering the thin film transistor and having a second via hole exposing a first electrode of the thin film transistor, wherein the first electrode is one of a source electrode and a drain electrode;

[0012] a third insulating layer covering a side of the second insulating layer away from the base substrate, and having a third via hole communicating with the second via hole;

[0013] a fourth insulating layer, covering a side of the third insulating layer away from the base substrate, and partially located in the second via hole, and having a fourth via hole exposing the first electrode;

[0014] The pixel electrode is located on a side of the fourth insulating layer away from the base substrate and is connected to the first electrode through the fourth via hole.

[0015] In some examples, the second insulating layer and the third insulating layer are made of different materials.

[0016] In some examples, the array substrate also includes a common electrode and a conductive protective layer that are insulated from each other, the common electrode and the conductive protective layer are both located between the third insulating layer and the fourth insulating layer, the conductive protective layer is at least located in the second via hole and covers the first electrode, and the conductive protective layer connects the pixel electrode and the first electrode.

[0017] In some examples, the conductive protection layer covers a hole wall of the second via hole and at least a portion of a hole wall of the third via hole.

[0018] In some examples, the conductive protection layer and the common electrode are arranged in the same layer and made of the same material.

[0019] A second aspect of the embodiments of the present application further provides a method for preparing an array substrate, the method comprising:

[0020] A first signal line, a first insulating layer, a second signal line, and a thin film transistor are formed on a base substrate, wherein the base substrate has a display area and a non-display area, the first signal line is located in the non-display area, the first insulating layer at least covers the first signal line and has a first via hole exposing the first signal line, the second signal line is located on a side of the first insulating layer away from the base substrate, and is connected to the first signal line through the first via hole, the thin film transistor is located in the display area, and the gate of the thin film transistor is connected to the second signal line;

[0021] forming a second insulating layer, wherein the second insulating layer covers the thin film transistor;

[0022] forming a third insulating layer on a side of the second insulating layer away from the base substrate, the third insulating layer having a third via hole, wherein an orthographic projection of the third via hole on the base substrate at least partially overlaps with an orthographic projection of a first electrode of the thin film transistor on the base substrate, the first electrode being one of a source electrode and a drain electrode;

[0023] forming a second via hole in the second insulating layer exposing the first electrode, wherein the second via hole is located in the third via hole;

[0024] forming a fourth insulating layer on a side of the third insulating layer away from the base substrate, wherein a portion of the fourth insulating layer is located in the second via hole and has a fourth via hole exposing the first electrode;

[0025] A pixel electrode is formed on a side of the fourth insulating layer away from the base substrate, and the pixel electrode is connected to the first electrode through the fourth via hole.

[0026] In some examples, forming a second via hole in the second insulating layer to expose the first electrode includes:

[0027] The second insulating layer is etched using the third insulating layer as a mask to form the second via hole in the third via hole.

[0028] In some examples, before forming a fourth insulating layer on a side of the third insulating layer away from the base substrate, the preparation method further includes:

[0029] forming a conductive material layer on a side of the third insulating layer away from the base substrate;

[0030] The conductive material layer is processed to form a common electrode and a conductive protection layer that are insulated from each other. The conductive protection layer is at least located in the second via hole and covers the first electrode.

[0031] In some examples, forming a fourth insulating layer on a side of the third insulating layer away from the substrate includes:

[0032] forming an insulating material layer on a side of the third insulating layer away from the base substrate, wherein the insulating material layer covers the conductive protection layer;

[0033] The insulating material layer is etched to form a fourth via hole exposing at least a portion of the conductive protection layer, thereby obtaining the fourth insulating layer.

[0034] A third aspect of the embodiments of the present application provides a display panel, comprising a cell substrate and the array substrate as described in the first aspect, wherein the cell substrate is arranged opposite to the array substrate.

[0035] In a first aspect of an embodiment of the present application, a first via hole exposing the first signal line is provided on the first insulating layer, and the second signal line is directly connected to the first signal line by using the first via hole. The structure is simple, and only the first insulating layer needs to be etched. The etching depth is small, and the preparation difficulty is low, which is beneficial to improving the yield of the array substrate. By making the fourth insulating layer partially located in the second via hole, that is, forming the fourth insulating layer before forming the second via hole, the second via hole and the fourth via hole are made separately, rather than forming the second via hole and the fourth via hole in the same etching process, the problem of poor via morphology and high process difficulty caused by excessive single etching depth is avoided, which is beneficial to improving the yield of the array substrate.

[0036] It can be understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 is a schematic top view of an array substrate provided by an example of the present application;

[0039] Figure 2 yes Figure 1 A schematic cross-sectional view of the array substrate in the non-display area is shown;

[0040] Figure 3 yes Figure 1 The cross-sectional view of the array substrate in the display area is shown;

[0041] Figure 4 is a schematic cross-sectional view of the non-display area of ​​the second array substrate provided in the second embodiment of the present application;

[0042] Figure 5 This is a schematic cross-sectional view of the display area of ​​the second array substrate provided in the second embodiment of the present application;

[0043] Figure 6 is a schematic cross-sectional view of the display area of ​​the third array substrate provided in Example 3 of the present application;

[0044] Figure 7 This is a flow chart of a method for preparing an array substrate provided in Example 4 of the present application;

[0045] Figure 8 This is a flow chart for preparing another array substrate provided in Example 5 of the present application;

[0046] Figure 9 This is a schematic diagram of a preparation process of an array substrate provided in Example 5 of the present application;

[0047] Figure 10 This is a schematic diagram of the preparation process of an array substrate provided in Example 5 of the present application.

[0048] Figure Number:

[0049] Base substrate: 10; first signal line: 11; bridging layer: 111; second signal line: 12; first insulating layer: 21; second insulating layer: 22; third insulating layer: 23; fourth insulating layer: 24; insulating material layer: 240; thin film transistor: 30; first electrode: 31; second electrode: 32; gate: 33; active layer: 34; pixel electrode: 41; common electrode: 42; conductive material layer: 420; conductive protective layer: 43; display area: 10a; non-display area: 10b; first via hole: 21a; second via hole: 22a; third via hole: 23a; fourth via hole: 24a. DETAILED DESCRIPTION

[0050] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0051] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0052] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0053] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0054] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0055] References to "one embodiment" or "some embodiments" in the present specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "Multiple" means two or more.

[0056] Example 1

[0057] Figure 1 FIG. 1 is a top view of an array substrate provided by an example of the present application. Figure 1 As shown, an embodiment of the present application provides a first array substrate, which includes a base substrate 10 and circuits formed on one side of the base substrate 10. The base substrate 10 serves as a carrier and has a display area 10a and a non-display area 10b. The display area 10a is generally located in the middle of the base substrate 10, and the non-display area 10b is generally located at the edge of the base substrate 10. A first signal line 11 is provided in the non-display area 10b of the base substrate 10, and a second signal line 12 is provided in the display area 10a.

[0058] Figure 2 yes Figure 1 The cross-sectional view of the array substrate in the non-display area is shown in FIG. Figure 2As shown, the first signal line 11 is covered with a first insulating layer 21 on the side away from the base substrate 10, and the second signal line 12 is located on the side of the first insulating layer 21 away from the base substrate 10. The second signal line 12 is also covered, in sequence, with a second insulating layer 22, a third insulating layer 23, and a fourth insulating layer 24 on the side away from the base substrate 10. The second signal line 12 extends to the display area 10a of the base substrate 10. The first signal line 11 and the second signal line 12 are connected via a bridge layer 111 disposed between the third insulating layer 23 and the fourth insulating layer 24. The bridge layer 111 is connected to the first signal line 11 and the second signal line 12 via vias. The vias connecting the bridge layer 111 and the first signal line 11 are relatively deep and require etching of the first insulating layer 21, the second insulating layer 22, and the third insulating layer 23 to form them. During fabrication, the first insulating layer 21 and the second insulating layer 22 are typically etched in the same etching process, which results in a relatively deep single etch and a relatively long etching time. Furthermore, the first insulating layer 21 and the second insulating layer 22 are often designed as a multilayer structure. Specifically, the first insulating layer 21 includes at least two stacked sublayers, with adjacent sublayers typically made of different materials. The second insulating layer 22 also includes at least two stacked sublayers, with adjacent sublayers typically made of different materials. Films made of different materials exhibit different etching rates. This makes the via morphology more difficult to control the deeper the etching and the longer the etching time. For example, defects such as burrs are more likely to form at the edges of the via. Furthermore, the deeper the via, the more difficult it is to clean the photoresist used as a mask, potentially leading to accumulation within the via.

[0059] Figure 3 yes Figure 1 The cross-sectional view of the array substrate in the display area is shown in FIG. Figure 3 As shown, a thin film transistor 30 is distributed in the display area 10a. The gate 33 of the thin film transistor 30 is connected to the second signal line 12. The second insulating layer 22 covers the thin film transistor 30, and a pixel electrode 41 is provided on the side of the fourth insulating layer 24 away from the base substrate 10. The pixel electrode 41 is connected to one of the source and drain electrodes of the thin film transistor 30 through a via. When forming the via, the fourth insulating layer 24 is usually formed first, and then the second insulating layer 22 and the fourth insulating layer 24 are etched in the same etching process. This etching process also has the problem of large single etching depth and long etching time. In addition, the material of the fourth insulating layer 24 is different from that of the second insulating layer 22, which makes it difficult to control the morphology of the via. The via is deep, and the photoresist used as a mask is difficult to clean, and it may accumulate in the via.

[0060] Poor via morphology or accumulation of photoresist in the via will have adverse effects, such as affecting the morphology of subsequent film layers in the via. The most intuitive manifestation is the decrease in the yield of the prepared array substrate.

[0061] Example 2

[0062] An embodiment of the present application provides a second array substrate, which includes a base substrate 10 and circuits located on a surface of the base substrate 10 .

[0063] After the array substrate is made into a display panel, the central area of ​​the base substrate 10 corresponds to the area where the screen is displayed, usually called the display area 10a, and the area outside the display area 10a is usually called the non-display area 10b. The non-display area 10b is usually arranged around the display area 10a.

[0064] Figure 4 is a cross-sectional schematic diagram of the second array substrate in the non-display area provided in the second embodiment of the present application, Figure 5 : is a cross-sectional schematic diagram of the display area of ​​the second array substrate provided in the second embodiment of the present application. Figure 4 and Figure 5 As shown, the circuit in the array substrate includes a first signal line 11 , a first insulating layer 21 , a second signal line 12 , a thin film transistor 30 , a second insulating layer 22 , a third insulating layer 23 , a fourth insulating layer 24 and a pixel electrode 41 .

[0065] The first signal line 11 is located in the non-display area 10b. The first insulating layer 21 covers at least the first signal line 11 and has a first via 21a exposing the first signal line 11. The second signal line 12 is located on a side of the first insulating layer 21 away from the base substrate 10. The second signal line 12 is connected to the first signal line 11 through the first via 21a.

[0066] In the embodiments of the present application, unless otherwise specified, connection through a via refers to achieving electrical connection, and the electrical connection is achieved by a structure located within the via. The structure within the via used to achieve electrical connection can be a part of either of the two structures at either end of the via, or can be a structure other than the two structures at either end of the via. For example, the second signal line 12 and the first signal line 11 are connected through the first via 21a, which means that the second signal line 12 and the first signal line 11 form an electrical connection, and the structure within the first via 21a used to achieve electrical connection between the second signal line 12 and the first signal line 11 is the portion of the second signal line 12 located within the first via 21a.

[0067] like Figure 5As shown, the thin film transistor 30 is located in the display area 10a. The thin film transistor 30 has a gate 33, a first electrode 31, and a second electrode 32. The first electrode 31 is one of the source and drain electrodes, and the second electrode 32 is the other of the source and drain electrodes. The gate 33 of the thin film transistor 30 is connected to the second signal line 12. The second insulating layer 22 covers the thin film transistor 30 and has a second via 22a that exposes the first electrode 31 of the thin film transistor 30. The third insulating layer 23 is located on the side of the second insulating layer 22 away from the base substrate 10. The third insulating layer 23 has a third via 23a that communicates with the second via 22a. The fourth insulating layer 24 is located on the side of the third insulating layer 23 away from the base substrate 10. The fourth insulating layer 24 is partially located in the second via 22a. The fourth insulating layer 24 also has a fourth via 24a that exposes the first electrode 31 of the thin film transistor 30. The pixel electrode 41 is located on a side of the fourth insulating layer 24 away from the base substrate 10 . The pixel electrode 41 is connected to the first electrode 31 of the thin film transistor 30 through a fourth via hole 24 a .

[0068] By providing a first via 21a in the first insulating layer 21, which exposes the first signal line 11, the second signal line 12 is directly connected to the first signal line 11 through the first via 21a. This simplifies the structure and only requires etching the first insulating layer 21, resulting in a small etching depth and low manufacturing difficulty, which helps improve the yield of the array substrate. The fourth insulating layer 24 is partially located in the second via 22a, which means that the second via 22a is formed before the fourth insulating layer 24 is formed. The second via 22a and the fourth via 24a are produced separately, rather than formed in the same etching process. This avoids the problem of poor via morphology and high manufacturing difficulty caused by a single etching depth that is too large, and helps improve the yield of the array substrate.

[0069] The circuits on the surface of the substrate 10 typically include a pixel circuit located in the display area 10a and a drive circuit located in the non-display area 10b. The drive circuit in the non-display area 10b may, for example, include a gate driver on array (GOA) circuit. In the embodiment of the present application, the first signal line 11 may be a signal line in the gate driver circuit. The thin film transistor 30 may be a thin film transistor in the pixel circuit. The first signal line 11 is connected to the gate 33 of the thin film transistor 30 via the second signal line 12 to control the operation of the pixel circuit.

[0070] As an example, the first signal line 11 is arranged in the same layer as the gate electrode 33 of the thin-film transistor 30 and is made of the same material. Since they are arranged in the same layer and made of the same material, the first signal line 11 and the gate electrode 33 of the thin-film transistor 30 can be formed through the same patterning process, thereby saving process steps. For example, the first signal line 11 can be a single-layer structure made of a metal material, such as a single-layer structure formed of copper (Cu), or a multi-layer structure made of a metal material, such as an Al / Mo / MTD material, i.e., a multi-layer structure of aluminum layers, molybdenum layers, and molybdenum nickel-titanium alloy layers.

[0071] The first insulating layer 21 may be located in the display area 10a and the non-display area 10b. For example, the first insulating layer 21 may be a gate insulating layer. The first insulating layer 21 may be made of an inorganic non-metallic material. For example, the first insulating layer 21 may include at least one of a silicon nitride layer and a silicon oxide layer. For example, the first insulating layer 21 may include SiN x layers and stacks in SiN x The SiO layer on the side away from the base substrate 10 x layer.

[0072] The active layer 34 of the thin film transistor 30 is located on the side of the first insulating layer 21 away from the substrate 10. For example, the thin film transistor 30 may be an oxide thin film transistor, and the active layer 34 may be a metal oxide semiconductor layer. In some examples, the thin film transistor 30 may also be a polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, or other thin film transistors.

[0073] The first electrode 31 and the second electrode 32 of the thin film transistor 30 are located on the side of the first insulating layer 21 away from the base substrate 10. At least two of the first electrode 31, the second electrode 32 and the second signal line 12 of the thin film transistor 30 can be arranged in the same layer and made of the same material. For example, in an embodiment of the present application, the first electrode 31, the second electrode 32 and the second signal line 12 of the thin film transistor 30 are arranged in the same layer and made of the same material, that is, the first electrode 31, the second electrode 32 and the second signal line 12 of the thin film transistor 30 can be formed by the same patterning process to achieve the purpose of saving process. Exemplarily, the second signal line 12 can be a single-layer structure made of metal material, such as a single-layer structure formed by metal copper Cu, or it can be a multi-layer structure made of metal material, such as Al / Mo / MTD material, that is, a multi-layer structure of aluminum layer, molybdenum layer and molybdenum nickel titanium alloy layer.

[0074] The first insulating layer 21 may also have a via hole in the display area 10a, through which the second signal line 12 is connected to the gate of the thin film transistor 30. For example, a gate line may be provided in the display area 10a, the gate line being connected to the gate 33 of the thin film transistor 30, and the second signal line 12 being connected to the gate line through the via hole to achieve electrical connection between the second signal line 12 and the gate 33 of the thin film transistor 30.

[0075] The second insulating layer 22 may be located in the display area 10a and the non-display area 10b of the base substrate 10, covering the second signal line 12 and the thin film transistor 30. For example, the second insulating layer 22 may be a passivation layer (PVX), and the second insulating layer 22 may be made of an inorganic non-metallic material. For example, the second insulating layer 22 may include at least one of a silicon nitride layer and a silicon oxide layer. For example, the second insulating layer 22 includes SiO x Layers and stacks in SiO x The SiN layer on the side away from the substrate 10 x layer.

[0076] The third insulating layer 23 may be located in the display area 10 a and the non-display area 10 b of the base substrate 10 . The third insulating layer 23 covers a side of the second insulating layer 22 away from the base substrate 10 .

[0077] The third insulating layer 23 can be made of an inorganic non-metallic material, for example, a resin layer, a photoresist layer, or an acrylic layer. For example, the third insulating layer 23 can be made of perfluoroalkoxy resin PFA.

[0078] Optionally, the thickness of the third insulating layer 23 is 1.5 μm to 3 μm. The thickness of the third insulating layer 23 is set relatively thick to form a relatively flat surface, so that the film layer formed subsequently is relatively flat.

[0079] In some examples, the third insulating layer 23 is a photoresist layer, and the second insulating layer 22 and the third insulating layer 23 are made of different materials.

[0080] Because the second insulating layer 22 and the third insulating layer 23 are made of different materials, when etching the third insulating layer 23, an etchant that easily etches the third insulating layer 23 but not the second insulating layer 22 can be used, thereby reducing the impact of etching the third insulating layer 23 on the second insulating layer 22. When etching the second insulating layer 22, an etchant that easily etches the second insulating layer 22 but not the third insulating layer 23 can be used, thereby reducing the impact of etching the second insulating layer 22 on the third insulating layer 23. Furthermore, when etching the second insulating layer 22, the third insulating layer 23 can be used as a mask to simplify the process.

[0081] like Figure 5 As shown, the array substrate further includes a common electrode 42, a fourth insulating layer 24 and a pixel electrode 41. The common electrode 42 is located between the third insulating layer 23 and the fourth insulating layer 24, and is located outside the third via hole 23a.

[0082] The fourth insulating layer 24 may be located in the display area 10a and the non-display area 10b and covers the surface of the third insulating layer 23 away from the base substrate 10 and covers the hole wall of the third via hole 23a and the hole wall of the second via hole 22a.

[0083] Because the second via hole 22a is formed before the fourth insulating layer 24 is formed, the fourth insulating layer 24 covers the hole wall of the second via hole 22a. When forming the fourth via hole 24a, only the film layer forming the fourth insulating layer 24 is etched, and the second insulating layer 22 is not etched. The etching depth is small, which helps improve the morphology quality of the fourth via hole 24a and avoids defects such as burrs on the hole wall.

[0084] A portion of the pixel electrode 41 is located on the surface of the fourth insulating layer 24 away from the base substrate 10 , and another portion is located in the second via hole 22 a , the third via hole 23 a , and the fourth via hole 24 a , and is electrically connected to the first electrode 31 of the thin film transistor 30 .

[0085] For example, the common electrode 42 and the pixel electrode 41 can be made of ITO (Indium tin oxide). The fourth insulating layer 24 can be made of SiN x Made of material.

[0086] Example 3

[0087] The embodiment of the present application provides a third array substrate, Figure 6 : is a cross-sectional schematic diagram of the display area of ​​the third array substrate provided in the third embodiment of the present application. Figure 6 As shown, compared to Figure 5 The array substrate shown further includes a conductive protective layer 43 that is insulated from the common electrode 42. The common electrode 42 and the conductive protective layer 43 are both located between the third insulating layer 23 and the fourth insulating layer 24. The conductive protective layer 43 is located at least in the second via hole 22a and covers the first electrode 31 of the thin film transistor 30.

[0088] The conductive protective layer 43 protects the first electrode 31 of the thin-film transistor 30. For example, during dry etching, when a conductive material is used to form the common electrode 42, the conductive material in the second via 22a and the third via 23a is etched away, exposing the first electrode 31 of the thin-film transistor 30 and subjecting it to ion bombardment. The conductive protective layer 43 protects the first electrode 31 of the thin-film transistor 30, preventing damage.

[0089] In an embodiment of the present application, the conductive protective layer 43 and the common electrode 42 are arranged in the same layer and are made of the same material. For example, both can be made of ITO material. In other words, the conductive protective layer 43 and the common electrode 42 can be formed by the same patterning process to achieve the purpose of saving process. In this case, when the conductive material is etched to form the conductive protective layer 43 and the common electrode 42, a mask is provided on the side of the conductive protective layer 43 away from the base substrate 10 and the side of the common electrode 42 away from the base substrate 10. The mask on the side of the conductive protective layer 43 away from the base substrate 10 plays a protective role, preventing the conductive protective layer 43 and the first electrode 31 of the thin film transistor 30 from being etched.

[0090] In some examples, the conductive protection layer 43 may also be formed before the common electrode 42 , so that the first electrode 31 of the thin film transistor 30 is not affected when the common electrode 42 is manufactured.

[0091] like Figure 6 As shown, the conductive protection layer 43 covers the hole wall of the second via hole 22 a and a portion of the hole wall of the third via hole 23 a.

[0092] The conductive protective layer 43 shields and protects the first electrode 31 of the thin-film transistor 30. By increasing the area of ​​the conductive protective layer 43 so that it covers the wall of the third via hole 23a, the shielding range of the conductive protective layer 43 can be increased, thereby preventing the conductive protective layer 43 from not completely shielding the bottom of the second via hole 22a due to errors or other reasons, thereby preventing the first electrode 31 of the thin-film transistor 30 from being damaged.

[0093] In an embodiment of the present application, the conductive protective layer 43 covers part of the hole wall of the third via hole 23a. In other examples, the conductive protective layer 43 can cover the entire hole wall of the third via hole 23a, and can even cover a part of the surface of the third insulating layer 23 away from the base substrate 10.

[0094] like Figure 6 As shown, the fourth insulating layer 24 may cover the surface of the third insulating layer 23 away from the base substrate 10 , and cover the hole wall of the third via hole 23 a and the surface of the conductive protection layer 43 away from the base substrate 10 .

[0095] The pixel electrode 41 is located on a side of the fourth insulating layer 24 away from the base substrate 10 and is partially located in the fourth via hole 24 a. The conductive protection layer 43 connects the pixel electrode 41 to the first electrode 31 of the thin film transistor 30 .

[0096] Since the conductive protection layer 43 is conductive, after the pixel electrode 41 is manufactured, the pixel electrode 41 can be electrically connected to the first electrode 31 of the thin film transistor 30 through the conductive protection layer 43 .

[0097] Example 4

[0098] Figure 7 This is a flow chart of a method for preparing an array substrate provided in Example 4 of the present application. This method can be used to prepare Figures 4 to 6 Any of the array substrates shown. Figure 7 As shown, the method includes:

[0099] In step S11 , a first signal line 11 , a first insulating layer 21 , a second signal line 12 and a thin film transistor 30 are formed on a surface of a base substrate 10 .

[0100] The base substrate 10 has a display area 10a and a non-display area 10b, the first signal line 11 is located in the non-display area 10b, the first insulating layer 21 at least covers the first signal line 11 and has a first via 21a exposing the first signal line 11, the second signal line 12 is located on the first insulating layer 21 and is connected to the first signal line 11 through the first via 21a, the thin film transistor 30 is located in the display area 10a, and the gate 33 of the thin film transistor 30 is connected to the second signal line 12.

[0101] In step S12 , a second insulating layer 22 is formed.

[0102] The second insulating layer 22 covers the thin film transistor 30 .

[0103] In step S13 , a third insulating layer 23 is formed on a side of the second insulating layer 22 away from the base substrate 10 .

[0104] The third insulating layer 23 has a third via hole 23 a , the orthographic projection of the third via hole 23 a on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 of the thin film transistor 30 on the base substrate 10 . The first electrode 31 is one of the source and the drain.

[0105] In step S14 , a second via hole 22 a exposing the first electrode 31 is formed in the second insulating layer 22 .

[0106] The second via hole 22a is located in the third via hole 23a.

[0107] In step S15 , a fourth insulating layer 24 is formed on a side of the third insulating layer 23 away from the base substrate 10 .

[0108] The fourth insulating layer 24 is partially located in the second via hole 22 a and has a fourth via hole 24 a exposing the first electrode 31 .

[0109] In step S16 , a pixel electrode 41 is formed on a side of the fourth insulating layer 24 away from the base substrate 10 , and the pixel electrode 41 is connected to the first electrode 31 through the fourth via hole 24 a .

[0110] By providing a first via 21a in the first insulating layer 21 that exposes the first signal line 11, the second signal line 12 is directly connected to the first signal line 11 through the first via 21a. This simplifies the structure and only requires etching the first insulating layer 21, resulting in a small etching depth and low manufacturing difficulty, which is beneficial for improving the yield of the array substrate. The fourth insulating layer 24 formed on the side of the third insulating layer 23 away from the base substrate 10 is partially located in the second via 22a. In other words, the second via 22a is formed before the fourth insulating layer 24 is formed. The second via 22a and the fourth via 24a are produced separately rather than formed in the same etching process. This avoids the problem of poor via morphology and high manufacturing difficulty caused by a single etching depth that is too large, and is beneficial for improving the yield of the array substrate.

[0111] Example 5

[0112] Figure 8 This is a flow chart of another array substrate preparation method provided in Example 5 of the present application. This method can be used to prepare Figure 6 The array substrate shown. Figures 9 and 10 : is a schematic diagram of a preparation process of an array substrate provided in Example 5 of the present application, Figure 9 FIG. 2 shows the structural changes in the non-display area 10b and the display area 10a in steps S21 to S27. Figure 10 FIG2 shows the structural changes in the non-display area 10b and the display area 10a in steps S28 to S32. Figure 9 and Figure 10 right Figure 8 The preparation method shown is described below. Figure 8 As shown, the preparation method comprises:

[0113] In step S21 , the first signal line 11 and the gate 33 of the thin film transistor 30 are formed on the surface of the base substrate 10 .

[0114] As an example, a conductive film layer can be formed on one side of the base substrate 10, and then processed using a patterning process to form the first signal line 11 and the gate 33 of the thin-film transistor 30. The first signal line 11 and the gate 33 of the thin-film transistor 30 are formed using the same patterning process, saving process steps.

[0115] Exemplarily, the conductive film layer used to prepare the first signal line 11 and the gate 33 of the thin film transistor 30 can be a single-layer structure made of a metal material, such as a single-layer structure formed by metal copper Cu, or a multi-layer structure made of a metal material, such as Al / Mo / MTD material, that is, a multi-layer structure of an aluminum layer, a molybdenum layer, and a molybdenum-nickel-titanium alloy layer.

[0116] In some examples, the display area 10a further includes a gate line connected to the gate 33 of the thin film transistor 30. The gate line can also be made of the aforementioned conductive film layer through the same patterning process as the first signal line 11 and the gate 33 of the thin film transistor 30.

[0117] In step S22 , a first insulating layer 21 is formed on the surface of the base substrate 10 .

[0118] The first insulating layer 21 may be a gate insulating layer, and may be formed of an inorganic non-metallic material, such as at least one of silicon nitride and silicon oxide. For example, the first insulating layer 21 includes SiN x layers and stacks in SiN x SiO on the layer x layer.

[0119] In some examples, an insulating film layer can be formed on the surface of the base substrate 10 by deposition, and then etched to form the first via hole 21a in the non-display area 10b. In addition, to facilitate the connection of the subsequently formed second signal line 12 to the gate 33, a via hole exposing the gate 33 or gate line can also be formed in the display area 10a. This via hole can be formed in the same patterning process as the first via hole 21a.

[0120] In step S23 , an active layer 34 is formed on a side of the first insulating layer 21 away from the base substrate 10 .

[0121] Exemplarily, the thin film transistor 30 may be an oxide thin film transistor, and the active layer 34 may be a metal oxide semiconductor layer.

[0122] In step S24 , the second signal line 12 , the first electrode 31 and the second electrode 32 of the thin film transistor 30 are formed on a side of the first insulating layer 21 away from the base substrate 10 .

[0123] The second signal line 12 is connected to the first signal line 11 through the first via 21a in the non-display area 10b, and is connected to the gate line or the gate 33 of the thin film transistor 30 in the display area 10a through the aforementioned via.

[0124] The second signal line 12 and the first electrode 31 and the second electrode 32 of the thin film transistor 30 can be fabricated similarly to the first signal line 11. A conductive film layer is formed on the surface of the first insulating layer 21 and then patterned to form the second signal line 12 and the first electrode 31 and the second electrode 32 of the thin film transistor 30.

[0125] Exemplarily, the conductive film layer used to prepare the second signal line 12, the first electrode 31 and the second electrode 32 of the thin film transistor 30 can be a single-layer structure made of a metal material, such as a single-layer structure formed by metal copper Cu, or a multi-layer structure made of a metal material, such as Al / Mo / MTD material, that is, a multi-layer structure of an aluminum layer, a molybdenum layer, and a molybdenum-nickel-titanium alloy layer.

[0126] In step S25 , a second insulating layer 22 is formed on a side of the first insulating layer 21 away from the base substrate 10 .

[0127] In step S25 , the second insulating layer 22 may not be etched temporarily, that is, the second via hole 22 a is not yet formed. The second via hole 22 a may be formed after the third insulating layer 23 is formed.

[0128] The second insulating layer 22 may be a passivation layer, and may be formed of an inorganic non-metallic material, such as at least one of silicon nitride and silicon oxide. For example, the second insulating layer 22 includes SiN x layers and stacks in SiN x SiO on the layer x layer.

[0129] In step S26 , a third insulating layer 23 is formed on a side of the second insulating layer 22 away from the base substrate 10 .

[0130] In this step, a third via hole 23 a is formed by a patterning process, and an orthographic projection of the third via hole 23 a on the base substrate 10 at least partially overlaps with an orthographic projection of the first electrode 31 of the thin film transistor 30 on the base substrate 10 .

[0131] The third insulating layer 23 can be made of an inorganic non-metallic material, such as resin, photoresist, or acrylic. For example, the third insulating layer 23 can be made of perfluoroalkoxy resin PFA.

[0132] The material of the third insulating layer 23 may be different from that of the second insulating layer 22 , so that when the third insulating layer 23 is etched to form the third via hole 23 a , the impact on the second insulating layer 22 during the process is reduced.

[0133] In step S27 , the second insulating layer 22 is etched using the third insulating layer 23 as a mask to form a second via hole 22 a in the third via hole 23 a.

[0134] The second insulating layer 22 is directly etched using the third insulating layer 23 as a mask, without the need to set up an additional mask, thus saving process.

[0135] In step S28 , a conductive material layer 420 is formed on a side of the third insulating layer 23 away from the base substrate 10 .

[0136] Exemplarily, the conductive material layer 420 may be an ITO film layer.

[0137] In step S29 , the conductive material layer 420 is processed to form a common electrode 42 and a conductive protection layer 43 that are insulated from each other.

[0138] The conductive protection layer 43 is at least located in the second via hole 22 a and covers the first electrode 31 .

[0139] In step S29, a patterning process can be used to process the conductive material layer 420 to form the common electrode 42 and the conductive protective layer 43. During the processing, a mask is provided on the surface of the conductive material layer 420 away from the base substrate 10, in the area located within the second via 22a, and in the portion of the area located outside the third via 23a. The area of ​​the conductive material layer 420 covered by the mask is retained after processing and becomes the common electrode 42 and the conductive protective layer 43. During the formation of the conductive protective layer 43, the mask covering the conductive protective layer 43 acts as a barrier, preventing the etching process from affecting the first electrode 31 of the thin film transistor 30.

[0140] In step S30 , an insulating material layer 240 is formed on a side of the third insulating layer 23 away from the base substrate 10 .

[0141] like Figure 10 As shown, the insulating material layer 240 covers the conductive protection layer 43 and also covers the common electrode 42 and the surface of the third insulating layer 23 .

[0142] In step S31 , the insulating material layer 240 is etched to form a fourth via hole 24 a exposing at least a portion of the conductive protection layer 43 , thereby obtaining a fourth insulating layer 24 .

[0143] In this step, the fourth insulating layer 24 is formed by etching the insulating material layer 240. The fourth via hole 24a exposes at least a portion of the conductive protective layer 43, so that when the pixel electrode 41 is subsequently formed, the pixel electrode 41 can contact the conductive protective layer 43 and be electrically connected to the first electrode 31 of the thin film transistor 30 via the conductive protective layer 43.

[0144] In step S32 , a pixel electrode 41 is formed on a side of the fourth insulating layer 24 away from the base substrate 10 .

[0145] like Figure 10 As shown, the pixel electrode 41 is connected to the first electrode 31 of the thin film transistor 30 through the fourth via hole 24a.

[0146] In this example, a conductive protective layer 43 is provided, and the conductive protective layer 43 indirectly connects the pixel electrode 41 and the first electrode 31 of the thin-film transistor 30, thereby achieving electrical connection between the pixel electrode 41 and the first electrode 31 of the thin-film transistor 30. In other examples, when the conductive protective layer 43 is not provided, the pixel electrode 41 and the first electrode 31 of the thin-film transistor 30 may be in direct contact with each other to achieve electrical connection.

[0147] As can be seen from step S22, only the first insulating layer 21 needs to be etched to form the first via 21a; as can be seen from step S26, only the third insulating layer 23 needs to be etched to form the third via 23a; as can be seen from step S27, only the second insulating layer 22 needs to be etched to form the second via 22a; and as can be seen from step S30, only the fourth insulating layer 24 needs to be etched to form the fourth via 24a. In other words, the first via 21a, the second via 22a, the third via 23a, and the fourth via 24a are formed separately, each etching depth is small, the etching time is short, the preparation difficulty is low, and the via morphology is good, which is conducive to improving the yield rate of the array substrate.

[0148] Example 6

[0149] Embodiment 6 of the present application provides a display panel, which can be, but is not limited to, a display panel in a mobile phone, tablet computer, laptop computer, monitor, smart wearable device, or vehicle-mounted display device. The display panel includes a cell substrate and an array substrate, which can be any of the array substrates described in the preceding embodiments.

[0150] Example 7

[0151] Embodiment 7 of the present application provides a display device, which includes the display panel of the aforementioned embodiment. The display device can be, but is not limited to, a mobile phone, a tablet computer, a laptop computer, a monitor, a smart wearable device, or a vehicle-mounted display device.

[0152] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: A base substrate (10) having a display area (10a) and a non-display area (10b); A first signal line (11) is located in the non-display area (10b); a first insulating layer (21), covering at least the first signal line (11), and having a first via hole (21a) exposing the first signal line (11); a second signal line (12), located on a side of the first insulating layer (21) away from the base substrate (10), and connected to the first signal line (11) through the first via hole (21a); A thin film transistor (30) is located in the display area (10a), and a gate electrode (33) of the thin film transistor (30) is connected to the second signal line (12); a second insulating layer (22), covering the thin film transistor (30) and having a second via hole (22a) exposing a first electrode (31) of the thin film transistor (30), wherein the first electrode (31) is one of a source electrode and a drain electrode; a third insulating layer (23), covering a side of the second insulating layer (22) away from the base substrate (10), and having a third via hole (23a) communicating with the second via hole (22a); a fourth insulating layer (24), covering a side of the third insulating layer (23) away from the base substrate (10), and partially located in the second via hole (22a), and having a fourth via hole (24a) exposing the first electrode (31); The pixel electrode (41) is located on a side of the fourth insulating layer (24) away from the base substrate (10), and is connected to the first electrode (31) through the fourth via hole (24a).

2. The array substrate according to claim 1, wherein: The second insulating layer (22) and the third insulating layer (23) are made of different materials.

3. The array substrate according to claim 1, wherein: The invention also includes a common electrode (42) and a conductive protective layer (43) that are insulated from each other. The common electrode (42) and the conductive protective layer (43) are both located between the third insulating layer (23) and the fourth insulating layer (24). The conductive protective layer (43) is at least located in the second via hole (22a) and covers the first electrode (31). The conductive protective layer (43) connects the pixel electrode (41) and the first electrode (31).

4. The array substrate according to claim 3, wherein: The conductive protective layer (43) covers the hole wall of the second via hole (22a) and at least a portion of the hole wall of the third via hole (23a).

5. The array substrate according to claim 3, wherein: The conductive protection layer (43) and the common electrode (42) are arranged in the same layer and made of the same material.

6. A method for preparing an array substrate, characterized in that: include: A first signal line (11), a first insulating layer (21), a second signal line (12), and a thin film transistor (30) are formed on the surface of a base substrate (10), wherein the base substrate (10) has a display area (10a) and a non-display area (10b), the first signal line (11) is located in the non-display area (10b), the first insulating layer (21) at least covers the first signal line (11), and has a first via hole (21a) exposing the first signal line (11), the second signal line (12) is located on a side of the first insulating layer (21) away from the base substrate (10), and is connected to the first signal line (11) through the first via hole (21a), the thin film transistor (30) is located in the display area (10a), and the gate electrode (33) of the thin film transistor (30) is connected to the second signal line (12); forming a second insulating layer (22), wherein the second insulating layer (22) covers the thin film transistor (30); A third insulating layer (23) is formed on a side of the second insulating layer (22) away from the base substrate (10), the third insulating layer (23) having a third via hole (23a), an orthographic projection of the third via hole (23a) on the base substrate (10) at least partially overlapping with an orthographic projection of a first electrode (31) of the thin film transistor (30) on the base substrate (10), the first electrode (31) being one of a source electrode and a drain electrode; forming a second via hole (22a) exposing the first electrode (31) in the second insulating layer (22), wherein the second via hole (22a) is located in the third via hole (23a); forming a fourth insulating layer (24) on a side of the third insulating layer (23) away from the base substrate (10), wherein the fourth insulating layer (24) is partially located in the second via hole (22a) and has a fourth via hole (24a) exposing the first electrode (31); A pixel electrode (41) is formed on a side of the fourth insulating layer (24) away from the base substrate (10), and the pixel electrode (41) is connected to the first electrode (31) through the fourth via hole (24a).

7. The preparation method according to claim 6, characterized in that The second via hole (22a) formed in the second insulating layer (22) to expose the first electrode (31) comprises: The second insulating layer (22) is etched using the third insulating layer (23) as a mask to form the second via hole (22a) in the third via hole (23a).

8. The preparation method according to claim 7, characterized in that Before forming a fourth insulating layer (24) on a side of the third insulating layer (23) away from the base substrate (10), the preparation method further comprises: forming a conductive material layer (420) on a side of the third insulating layer (23) away from the base substrate (10); The conductive material layer (420) is processed to form a common electrode (42) and a conductive protection layer (43) that are insulated from each other, wherein the conductive protection layer (43) is at least located in the second via hole (22a) and covers the first electrode (31).

9. The preparation method according to claim 8, characterized in that The forming of a fourth insulating layer (24) on a side of the third insulating layer (23) away from the base substrate (10) comprises: forming an insulating material layer (240) on a side of the third insulating layer (23) away from the base substrate (10), wherein the insulating material layer (240) covers the conductive protective layer (43); The insulating material layer (240) is etched to form a fourth via hole (24a) exposing at least a portion of the conductive protection layer (43), thereby obtaining the fourth insulating layer (24).

10. A display panel, characterized in that: The invention comprises a cell substrate and the array substrate according to any one of claims 1 to 5, wherein the cell substrate is arranged opposite to the array substrate.

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