A system for implementing a hyperthreading architecture for multiple threads in parallel in a processor

Abstract

The present invention discloses a system for implementing a hyperthreading architecture of multiple threads in parallel in a processor, including: an FU operation domain, a GS state domain, and a physical channel switch array. The FU operation domain describes the FU mapping state, and the FU includes a time series layer part FU_TL and a current synthesis layer part FU_CL; the GS state domain is converted from the VLcore operation domain, and the GS state domain can be converted from the VLcore operation domain back to the FU operation domain, and the VLcore operation domain conversion is an analysis of the current use state of the FU with VLcore as the medium. The present invention has only one set of hardware for logic cores and operators, saving resources; by dividing FU functional units and dynamically mapping, multi-core logic cores and operators are virtualized to achieve the effect of synchronous multi-threading; reducing system complexity and ensuring feasibility.

Description

Technical Field

[0001] The present invention relates to the technical field of processor multithreading, and in particular to a system for implementing a hyperthreading architecture for parallelizing multiple threads in a processor. Background Art

[0002] The common existing thread kernel technologies include the following:

[0003] 1. Non-hyperthreaded core: mainstream core technology, unable to run multithreaded parallel; each physical core contains only one logical core and one arithmetic unit (ALU);

[0004] 2. Intel Hyper-Threading Core: Intel proprietary technology, each physical core contains two logical cores and one arithmetic unit;

[0005] 3. Ideal synchronous multi-threaded kernel: Each physical core contains multiple logical cores and multiple operators; the execution efficiency is very high, the hardware resource overhead is high, and the implementation is very difficult. Compared with multi-physical core technology, it has no advantage. Summary of the invention

[0006] Therefore, it is necessary to provide a system for implementing a hyperthreading architecture of multiple threads in parallel in a processor, while avoiding the problem of difficulty in implementing existing multithreading kernels on the basis of realizing multithreading.

[0007] To achieve the above-mentioned object, the present invention provides a system for implementing a hyperthreading architecture for multiple threads in parallel in a processor, comprising: an FU operation domain, a GS state domain, and a physical channel switch array, wherein the FU operation domain describes the FU mapping state, wherein the FU includes a time series layer part FU_TL and a current synthesis layer part FU_CL; wherein the GS state domain is converted from the VLcore operation domain, wherein the GS state domain can be converted from the VLcore operation domain back to the FU operation domain, wherein the VLcore operation domain conversion is an analysis of the current use state of the FU using the VLcore as a medium, wherein the VLcore includes a virtual logic core input VLc ore_in and virtual logic core output VLcore_out, the time series layer part FU_TL is converted to the virtual logic core input VLcore_in through the physical channel switch array, the virtual logic core input VLcore_in is converted to the current synthesis layer part FU_CL through the physical channel switch array, the current synthesis layer part FU_CL is converted to the virtual logic core output VLcore_out through the physical channel switch array, and the virtual logic core output VLcore_out is converted to the current synthesis layer part FU_CL at the next moment through the physical channel switch array.

[0008] Further, the physical channel switch array includes an input mapping multiplexer, a modulation and demodulation matrix, a decimation matrix and an output mapping multiplexer;

[0009] The time series layer part FU_TL is converted to the virtual logic core input VLcore_in through the input mapping multiplexer, the virtual logic core input VLcore_in is converted to the current synthesis layer part FU_CL through the modulation and demodulation matrix, the current synthesis layer part FU_CL is converted to the virtual logic core output VLcore_out through the extraction matrix, and the virtual logic core output VLcore_out is converted to the current synthesis layer part FU_CL at the next moment through the output mapping multiplexer.

[0010] Furthermore, it also includes a one-dimensional time domain switch array, which controls the connection relationship between the FU and the VLcore, and the one-dimensional time domain switch array refreshes the connection relationship between the FU and the VLcore at every moment.

[0011] Furthermore, the state of the one-dimensional time-domain switch array includes normally open or not normally open.

[0012] Furthermore, it includes a switch control signal 1 and a switch control signal 2, wherein the switch control signal 1 is used to control the time series layer part FU_TL to flow to the current synthesis layer part FU_CL, and the switch control signal 2 is used to control the current synthesis layer part FU_CL to flow to the time series layer part FU_TL at the next moment.

[0013] Furthermore, a physical logical core is discretized into multiple logical core FU functional units, and the logical core FU functional units are divided according to system requirements, and the logical core includes multiple logical core FU functional units; the multiple logical core FU functional units are respectively mapped to multiple virtual logical cores; the FU operation domain analyzes the mapping status of multiple FU functional units, and the VLcore operation domain conversion analyzes the current usage status of multiple virtual logical cores for the FU functional units.

[0014] Furthermore, the logic core FU functional unit includes an instruction code fetching unit, an instruction code decoding unit, an execution unit, a storage access unit and a write-back unit.

[0015] Furthermore, the physical logic core is replaced by a physical operator, the virtual logic core is replaced by a virtual operator, and the logic core FU functional unit is replaced by an operator FU functional unit.

[0016] Different from the prior art, the above technical solution has the following advantages:

[0017] (1) Only one set of logic core and arithmetic unit hardware, saving resources;

[0018] (2) By dividing the FU functional units and dynamically mapping them, multi-core logical cores and operators are virtualized to achieve the effect of simultaneous multi-threading;

[0019] (3) Reduce system complexity and ensure feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A diagram comparing the overall architecture of the present invention with that of the prior art;

[0021] Figure 2 It is a structural diagram of the polling dynamic mapping method of the present invention;

[0022] Figure 3 It is a structural diagram of the GS fixed-length advanced dynamic mapping method of the present invention;

[0023] Figure 4 This is a structural diagram of the GS variable-length advanced dynamic mapping method of the present invention;

[0024] Figure 5 It is a time domain analysis diagram of the advanced dynamic mapping of the GS of the present invention with variable length;

[0025] Figure 6 A schematic diagram of a loading arbitration algorithm of the FU functional unit of the present invention;

[0026] Figure 7 It is a structural diagram of FU and FUn in the FU functional unit of the present invention;

[0027] Figure 8 It is a connection diagram for the conversion of the FU functional unit of the present invention;

[0028] Fig. 9 Modeling diagram for the main implementation method of the mapping of the present invention;

[0029] Fig.10 is the main flow chart of the mapping of the present invention;

[0030] Fig.11 is a system block diagram of the present invention;

[0031] Fig.12 An input mapping switch diagram of the present invention;

[0032] Fig.13 The modulation matrix diagram of the FU functional unit of the present invention;

[0033] Fig.14 Extracting a matrix diagram for the virtual logic kernel of the present invention;

[0034] Fig.15is the output mapping switch diagram of the present invention;

[0035] Fig.16 It is a diagram illustrating the structure and functions of FUX_TL and FUn_TL of the present invention;

[0036] FIG. 17 (1) is a diagram showing the structure and functions of FUY_CL and FUn_CL of the present invention. Figure 1 ;

[0037] FIG. 17(2) is a diagram showing the structure and functions of FUY_CL and FUn_CL of the present invention. Figure 2 ;

[0038] FIG. 17 (3) is a diagram showing the structure and function of FUY_CL and FUn_CL of the present invention. Figure 3 ;

[0039] Fig.18 Two mode diagrams of the FU functional unit refresh controller of the present invention;

[0040] Fig.19 An example diagram of a refresh controller for polling dynamic mapping of the present invention;

[0041] Fig. 20 It is the FU_trans hardware and interface release diagram of the present invention;

[0042] Fig.21 A detailed flowchart of the mapping of the present invention;

[0043] Fig. 22 A diagram of the method from behavior modeling to implementation of the present invention;

[0044] Fig.23 The polling dynamic mapping workflow diagram of the present invention;

[0045] Fig.24 It is a block diagram for realizing the polling dynamic mapping of the present invention;

[0046] Fig.25 It is the advanced dynamic mapping workflow diagram of GS fixed length of the present invention;

[0047] Fig.26 It is a block diagram of implementing the high-level dynamic mapping of the GS fixed length of the present invention;

[0048] Fig. 27 It is the workflow diagram of the GS variable length advanced dynamic mapping of the present invention;

[0049] Fig.28 It is a block diagram for realizing the high-level dynamic mapping of GS with variable length of the present invention;

[0050] Fig.29This is an example diagram of the application of the polling dynamic mapping of the present invention from a macro perspective;

[0051] Fig.30 This is an example diagram of the application of the polling dynamic mapping of the present invention at a microscopic perspective. DETAILED DESCRIPTION

[0052] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0053] Reference to "embodiment" herein means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The term "embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or association with other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the various technical features mentioned in the embodiments can be combined in any way to form a corresponding implementable technical solution.

[0054] Unless otherwise defined, the technical terms used in this document have the same meanings as those generally understood by those skilled in the art to which this application belongs; the use of relevant terms in this document is only for describing specific embodiments and is not intended to limit this application.

[0055] In the description of this application, the term "and / or" is an expression used to describe the logical relationship between objects, indicating that three relationships may exist, for example, A and / or B, which means: A exists, B exists, and A and B exist at the same time. In addition, the character " / " in this article generally indicates that the objects before and after are in an "or" logical relationship.

[0056] In the present application, terms such as “first” and “second” are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship of quantity, priority or sequence between these entities or operations.

[0057] Without further limitations, in this application, the words "include", "comprises", "has" or other similar expressions used in the sentences are intended to cover non-exclusive inclusion. These expressions do not exclude the presence of additional elements in the process, method or product including the elements, so that the process, method or product including a series of elements may include not only those limited elements, but also other elements not explicitly listed, or also include elements inherent to such process, method or product.

[0058] Similar to the understanding in the Examination Guidelines, in this application, expressions such as "greater than", "less than", "exceed" and the like are understood to exclude the number itself; expressions such as "above", "below", "within" and the like are understood to include the number itself. In addition, in the description of the embodiments of this application, "multiple" means more than two (including two), and similar expressions related to "multiple" are also understood in this way, such as "multiple groups", "multiple times", etc., unless otherwise clearly and specifically limited.

[0059] In the description of the embodiments of the present application, space-related expressions used, such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the specific embodiments or drawings, and are only for the convenience of describing the specific embodiments of the present application or facilitating the reader's understanding, and do not indicate or imply that the referred device or component must have a specific position, a specific orientation, or be constructed or operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0060] Unless otherwise expressly specified or limited, in the description of the embodiments of the present application, the terms such as "install", "connect", "connect", "fix", "set", etc. used should be understood in a broad sense. For example, the "connection" can be a fixed connection, a detachable connection, or an integrated setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. For technicians in the technical field to which the present application belongs, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0061] See also Figures 1 to 30 The present invention provides a system for implementing a hyperthreading architecture for multiple threads in parallel in a processor. Figure 1 As shown, Figure 11-3 respectively show 1-non-hyperthreading core, 2-Intel hyperthreading core, 3-ideal simultaneous multithreading core in the prior art. And 4-core architecture of the embodiment of the present invention. The method of the present invention is to discretize a physical logical core (Logical core hardware) and an arithmetic unit (ALU) into multiple FU (functional unit) functional units. The FU functional units are divided according to system requirements, follow the principle of functional mutual exclusion in a streamlined system, and follow the principle of performance efficiency in a complex system. The present invention is illustrated with 5 functional units as an embodiment. In fact, there can be different numbers of divisions according to the functional structure of the core. After division, the logical core includes multiple logical core FU functional units, and the arithmetic unit includes multiple arithmetic unit FU functional units. Then, the multiple FU functional units are mapped to multiple virtual logical cores respectively, so that the multiple virtual logical cores can execute different FU functional units in different global states or at different times, so as to achieve the effect of simultaneous multithreading; reduce system complexity and ensure feasibility.

[0062] The following focuses on the process and method of dynamic mapping. The virtual logic operator VALU and the virtual logic core VLcore are two independent systems, and the implementation ideas (discretization + mapping) of the two systems are completely consistent. Therefore, only the mapping of the virtual logic core VLcore is discussed, and the virtual logic operator VALU can refer to the virtual logic core VLcore of this application.

[0063] There are three types of mapping methods:

[0064] (1) Polling dynamic mapping;

[0065] (2) Advanced dynamic mapping - GS fixed length

[0066] (3) Advanced dynamic mapping - GS variable length

[0067] See also Figure 2 : Polling dynamic mapping method. In this embodiment, a virtual logical core is sequentially mapped with multiple logical core FU functional units, and the virtual logical core returns to the first logical core FU functional unit after running the last logical core FU functional unit; different logical core FU functional units are mapped to different virtual logical cores at the same time; different virtual logical cores are mapped by different FU functional units at the same time.

[0068] Figure 2 (1) Relationship between VLcore and FU - FU operation domain analysis:

[0069] VLcore is used as the horizontal axis and FU is used as the vertical axis, which is called FU operation domain analysis. The FU operation domain intuitively expresses the current mapping and subsequent mapping status of FU1~FU5 resources, and implies the execution status or time advancement information;

[0070] 1-functional unit, hereinafter referred to as FU;

[0071] 2--each Vlcore has multiple VLcores, as shown in the figure: VLcore1, VLcore2...VLcore5.

[0072] 5 virtual logical cores;

[0073] 3--time&state scale The scale of time and state; under polling mapping, time operation and state operation are unified, "1" represents the current state, and "2" to "5" represent the subsequent state;

[0074] 4-FU mapping current, current FU mapping status; see the black FU box. The figure shows: currently FU1 is mapped to VLcore1; FU2 is mapped to VLcore4; FU3 is mapped to VLcore3; FU4 is mapped to VLcore2; FU5 is mapped to VLcore5;

[0075] 5-FU mapping future, subsequent FU mapping status; see the white FU box. For example, analyzing the current next moment "2", we will get: FU1 is mapped to VLcore2; FU2 is mapped to VLcore5; FU3 is mapped to VLcore4; FU4 is mapped to VLcore3; FU5 is mapped to VLcore1;

[0076] 6-VLcore number, corresponding to VLcore1, VLcore2, VLcore3, VLcore4, VLcore5.

[0077] As shown in the figure: In polling mode, each FU (FU1 to FU5) polls mapping between VLcore1 to VLcore5. All FUs poll in the same direction, such as the counterclockwise direction in the figure.

[0078] Figure 2 (2) Relationship between VLcore and GS - State domain (time domain) analysis:

[0079] GS: global state. VLcore is the horizontal axis and GS is the vertical axis, which is called state domain analysis. In polling mode, GS and time (T) are unified, that is, GS also represents T. Therefore, state domain analysis is time domain analysis.

[0080] 1-GS, represents T, and illustrates 5 GS state cycle execution cycles. It should be noted that the present invention is illustrated with 5 state cycles, and the actual state can be selected according to needs.

[0081] 2- At each moment, the mapping status of FU, as shown in the figure, in the GS5 state: FU4 is mapped to VLcore1; FU3 is mapped to VLcore2; FU2 is mapped to VLcore3; FU5 is mapped to VLcore4; FU1 is mapped to VLcore5;

[0082] 3-Time and status scale; in the figure, "1" corresponds to GS1, "2" corresponds to GS2... "5" corresponds to GS5;

[0083] 6-VLcore number, corresponding to VLcore1, VLcore2, VLcore3, VLcore4, VLcore5;

[0084] 7- Rotation source. In the figure, the rotation source of VLcore5 is FU1 mapped to VLcore5 in GS5;

[0085] 8- Rotation target. In the figure, the rotation target of VLcore5 is FU5 mapped to VLcore5 in GS1;

[0086] 9- Rotation status. As shown in the figure, the rotation status of VLcore1, VLcore2, VLcore3, VLcore4, and VLcore5 all correspond to "5".

[0087] Polling mapping features:

[0088] (1) At any time, FU1-FU5 are mapped to different VLcores, that is, different FUs are mapped to different VLcores;

[0089] (2) Any FU is mapped to VLcoreA at the current moment and to VLcoreB at the next moment, and A is not equal to B;

[0090] (3) The VLcore trajectory of any FU is consistent (see Figure 2 (1) running loop), the FU trajectory of any VLcore is consistent (see Figure 2 (2) the operating ring).

[0091] See also Figure 3 : Advanced dynamic mapping-GS fixed length method. The present invention also includes a virtual logic priority core, the virtual logic priority core includes a priority core number, and the mapping of multiple logical core FU functional units to multiple virtual logical cores includes:

[0092] Multiple logical core FU functional units are mapped to multiple virtual logical priority cores respectively, and multiple virtual logical priority cores are mapped to multiple virtual logical cores respectively. When different virtual logical cores need to use the same logical core FU functional unit at the same time, arbitration is performed according to the priority of the virtual logical priority core corresponding to the virtual logical core, and the logical core FU functional unit is mapped to the virtual logical core corresponding to the virtual logical priority core with a high priority. The specific instructions are as follows:

[0093] Figure 3 (1) Relationship between Virtual Logic Priority Core VLcorep and FU - FU Operation Domain Analysis:

[0094] Most of the concepts are related to Figure 2 :Polling dynamic mapping method" is the same, the differences are:

[0095] 6-VLcore current priority core number, where each VLcorep (VLcorep0~VLcorep5) can correspond to VLcore1~VLcore5, and the corresponding relationship between VLcorep and VLcore changes with time. For details, see the following example:

[0096] Figure 3 (2) Example of the correspondence between VLcorep and VLcore - VLcore instantiation analysis:

[0097] VLcore instantiation analysis is an immediate analysis with VLcore as the main expression object. Both FU operation domain analysis and VLcore instantiation analysis are immediate (current and future) analysis of their respective expression objects (FU and VLcore), which implies and dilutes the execution status or time advancement information.

[0098] In advanced dynamic mapping-GS fixed length, GS and T are also unified, that is, GS also represents T;

[0099] It can be seen from the table that the corresponding relationship between VLcorep and VLcore changes irregularly with time (GS changes).

[0100] GS1~GS7 are the 7 states of cyclic execution; Figure 2 The polling example has two more states.

[0101] Figure 3 (3) Relationship between VLcore and GS - State domain (time domain) analysis:

[0102] based on" Figure 3 (1) Relationship between VLcorep and FU——Analysis of FU Operation Domain” and Figure 3(2) Example of the correspondence between VLcorep and VLcore - VLcore instantiation analysis", it is derived that Figure 3 (3) Conclusions of VLcore and GS:

[0103] 1-GS, stands for T, and illustrates 7 GS state loop execution cycles with fixed execution length;

[0104] 2- At each moment, the mapping status of FU, as shown in the figure, in the GS7 state: FU2 is mapped to VLcore1; FU5 is mapped to VLcore2; FU1 is mapped to VLcore3; FU3 is mapped to VLcore4; FU4 is mapped to VLcore5;

[0105] 3-Time and status scale; in the figure, "1" corresponds to GS1, "2" corresponds to GS2... "7"

[0106] Corresponds to GS7;

[0107] 6-VLcore number, corresponding to VLcore1, VLcore2, VLcore3, VLcore4, VLcore5;

[0108] 7- Rotation source. In the figure, the rotation source of VLcore5 is FU4 mapped to VLcore5 in GS7;

[0109] 8- Rotation target. In the figure, the rotation target of VLcore5 is FU4 mapped to VLcore5 in GS1;

[0110] 9- Rotation status. As shown in the figure, the rotation status of VLcore1, VLcore2, VLcore3, VLcore4, and VLcore5 all correspond to "7".

[0111] Advanced Dynamic Mapping-GS Fixed Length Features:

[0112] (1) At any time, FU1-FU5 are mapped to different VLcores, that is, different FUs are mapped to different VLcores;

[0113] (2) Any FU is mapped to VLcorepA at the current moment and to VLcorepB at the next moment, and A is not equal to B;

[0114] (3) The VLcorep trajectory of any FU is consistent, and the FU trajectory of any VLcorep is consistent;

[0115] (4) The correspondence between VLcorep and VLcore changes irregularly with time (GS changes);

[0116] (5) Any FU is mapped to VLcoreA at the current moment and to VLcoreB at the next moment, and A can be equal to B;

[0117] (6) The VLcore trajectories of any FU can be inconsistent, and the FU trajectories of any VLcore can be inconsistent;

[0118] (7) The GS loop execution period is fixed length.

[0119] Figure 2 The FU functional units will be cyclically used and executed by the virtual logic core in the order of time (global state); each virtual logic core uses the same FU in turn; the number of FU functional units included in the cycle is generally less than or equal to the total number of FU functional units.

[0120] Figure 3 In the , FU functional units will be cyclically used and executed by the virtual logic core in the order of time (global state). From the perspective of the virtual logic priority core: each virtual logic priority core uses the same FU functional unit in turn, and the number of FU functional units included in the cycle is generally less than or equal to the total number of FU functional units. From the perspective of the virtual logic core: each virtual logic core uses the same FU functional unit arbitrarily, not in a sequential relationship, and can be occupied continuously. It only needs to follow "different logical core FU functional units are mapped to different virtual logic cores at the same time; different virtual logic cores are mapped by different FU functional units at the same time". The cycle period is determined by the mapping relationship between the virtual logic priority core and the virtual logic core; the number of FU included in the cycle period is generally greater than or equal to the total number of FU functional units; it can support the situation of less than. .

[0121] See also Figure 4 :Advanced dynamic mapping-GS variable length method.

[0122] Figure 4 (1) Relationship between VLcorep and FU - FU operation domain analysis:

[0123] Most of the concepts are related to Figure 2 :Polling dynamic mapping method" is the same, the differences are:

[0124] 8-VLcore current priority core number, where each VLcorep (VLcorep0~VLcorep5) can correspond to VLcore1~VLcore5, and the corresponding relationship between VLcorep and VLcore changes with time. Figure 4 (2)Example:

[0125] Figure 4(2) Example of the correspondence between VLcorep and VLcore - VLcore instantiation analysis:

[0126] In advanced dynamic mapping-GS indefinite length, GS does not directly represent time (T);

[0127] It can be seen from the table that the corresponding relationship between VLcorep and VLcore changes irregularly with time (GS changes).

[0128] The GS corresponding to VLcoreX(1) and VLcoreX(2) indicates a global state that may not necessarily be executed (can be skipped); the GS corresponding to VLcoreX indicates a global state that will definitely be executed.

[0129] For example: VLcore3: GS1 and GS2 correspond to VLcore3(1); GS3 to GS6 correspond to VLcore3; GS7 corresponds to VLcore3(2). Therefore, GS3 to GS6 are mandatory states, and others may be skipped. There is no regularity in the specific execution. Please refer to " Figure 5 :Advanced dynamic mapping-GS indefinite length-time domain analysis".

[0130] Figure 4 (3) Relationship between VLcore and GS - state domain (non-time domain) analysis:

[0131] This is a non-time domain analysis of advanced dynamic mapping-GS indefinite length mode: In this state domain analysis, GS does not directly represent T.

[0132] based on" Figure 4 (1) Relationship between VLcorep and FU——Analysis of FU Operation Domain” and Figure 4 (2) Example of the correspondence between VLcorep and VLcore - VLcore instantiation analysis", it is derived that Figure 4 (3) Conclusions of VLcore and GS:

[0133] 1-GS, does not represent T, and shows that 7 GS are the longest execution cycle, with no fixed length, and some GS can be skipped;

[0134] 2- FU mapping relationship 2 in GS state that can be skipped, for example, VLcore3 in the figure; can be skipped: mapping relationship of FU1 in GS7 state;

[0135] 3- The FU mapping relationship 1 in the GS state can be skipped, for example, VLcore3 in the figure; the mapping relationship of FU2 in the GS1 state and the mapping relationship of FU2 in the GS2 state can be skipped;

[0136] 4- Rotation source, for example, the rotation source of VLcore3 in the figure is FU1 mapped to VLcore3 in GS7 or FU3 mapped to VLcore3 in GS6;

[0137] 5- Rotation target, for example, the rotation target of VLcore4 in the figure is FU3 mapped to VLcore4 in GS1 or FU4 mapped to VLcore4 in GS2;

[0138] 6- Rotation state X1~X5, as shown in the figure, VLcore1 rotation state corresponds to X1...VLcore5 rotation state corresponds to X5; each rotation state indicates the end of an execution cycle;

[0139] 7-Status scale; in the figure, "1" corresponds to GS1, "2" corresponds to GS2... "6" corresponds to GS6; "X1~X5" correspond to the rotation state of each VLcore;

[0140] 8-VLcore number, corresponding to VLcore1, VLcore2, VLcore3, VLcore4, VLcore5. Please refer to Figure 5 :Advanced dynamic mapping-GS indefinite length-time domain analysis.

[0141] based on" Figure 4 : Advanced dynamic mapping - GS variable length method", and the conclusion of advanced dynamic mapping - GS variable length time domain analysis is derived. In a system, the mapping behavior of FU functional units with different GS lengths is unified with the reference time scale, which forms a time domain analysis; the time domain is a specific abstract form of the GS state domain. The diagram shows the situation where each VLcore executes three cycles. Since the GS execution cycle is of variable length, the execution of each VLcore is different:

[0142] 1- Time scale, T1~T22;

[0143] 6- Rotation state X1~X5, as shown in the figure, VLcore1 rotation state corresponds to X1...VLcore5 rotation state corresponds to X5; each rotation state indicates the end of an execution cycle;

[0144] 7-Status scale; in the figure, "1" corresponds to GS1, "2" corresponds to GS2... "6" corresponds to GS6; "X1~X5" correspond to the rotation state of each VLcore;

[0145] 8-VLcore number, corresponding to VLcore1, VLcore2, VLcore3, VLcore4, VLcore5;

[0146] 9-FU loads the preset arbitration; arbitration is performed according to the VLcore number and the preset priority; as shown in the figure, both VLcore1 and VLcore5 need to use FU5, and the default priority of VLcore1 is higher than that of VLcore5, that is, arbitration is also performed according to the sequence number of the virtual logical core (which can be the number of the logical core or the set sequence number), and the logical core FU functional unit is mapped to the virtual logical core corresponding to the virtual logical priority core with the preceding sequence number. Therefore, FU5 is mapped to VLcore1, and VLcore5 loads FUn1 (standby functional unit); that is, the standby functional unit FUn is mapped to the virtual logical core with a low priority. Among them, the normal functional unit FU = FUX_TL + FUY_CL. The standby functional unit FUn = FUn_TL + FUn_CL, please refer to the details. Fig.16 and Figure 17(1)-Figure 17(3) .

[0147] 10-FU load weighted arbitration; arbitration is performed according to the executed FUn1 and the preset priority weight value; such as Figure 5 At time T13, VLcore2 has executed FUn1, and the priority of VLcore2 will be increased, that is, after the standby functional unit FUn is loaded, the priority of the virtual logic priority core that loads the standby functional unit FUn is increased. At time T14, both VLcore1 and VLcore2 need to use FU1, FU1 will be mapped to VLcore2, and VLcore1 will load FUn1.

[0148] 11- The mapping status of FU at each moment, such as at moment T18 in the figure: FU5 is mapped to VLcore1; Fun1 is mapped to VLcore2; FU3 is mapped to VLcore3; Fun2 is mapped to VLcore4; FU2 is mapped to VLcore5;

[0149] 12- Standby function unit FUn, such as FUn1 to FUn3, etc., the time scale "nos" indicates that the "no operation state" corresponds to the standby function unit;

[0150] 13-Three execution cycles loop1, loop2, loop3, different cycles of the same VLcore may be different, and different cycles of different VLcores may be different.

[0151] See also Figure 6 :FU loads the arbitration algorithm.

[0152] In the advanced dynamic mapping-GS indefinite length system, FU loading may encounter conflicts (two VLcores use one FU at the same time, which will cause conflicts). The VLcore with high priority will load FU, and the VLcore with low priority will load FUn for standby buffering. Among them, the priority is calculated by the preset priority and the user-defined preset priority. The preset priority is the priority of the preset virtual logic core, and the user-defined preset priority is the priority that can be configured by the user. The specific arbitration will be carried out according to the following algorithm:

[0153] 1-VLcore preset priority, referred to as PVLCN1 to PVLCN5, corresponding to VLcore1, VLcore2, VLcore3, VLcore4, VLcore5; the default preset priority is PVLCN1(5)>PVLCN2(4)>PVLCN3(3)>PVLCN4(2)>PVLCN5(1);

[0154] 2-User-defined preset priority, referred to as PCTOM1~PCTOM5, the default value is 0; it can be reconfigured to the user's required value, the configuration range is 0~5;

[0155] 3-Preset priority, referred to as PPROT1~PPROT5;

[0156] PPROT1=PCTOM1+PVLCN1

[0157] PPROT2=PCTOM2+PVLCN2

[0158] PPROT3=PCTOM3+PVLCN3

[0159] PPROT4=PCTOM4+PVLCN4

[0160] PPROT5=PCTOM5+PVLCN5

[0161] 4-FUn load weighted value, referred to as PFUNL1~PFUNL5, the default value is 0; for each VLcore, after FUn is loaded, PFUNL will add the user-defined weighted value (WCTOM), that is, adjust to the highest level;

[0162] 5-User-defined weighted value, referred to as WCTOM1~WCTOM5, the default value is 5; it can be reconfigured to the user's required value, the configuration range is 0~5;

[0163] 6-weighted priority, referred to as PWROT1 to PWROT5;

[0164] PWROT1=(|WCTOM1)*PFUNL1

[0165] PWROT2=(|WCTOM2)*PFUNL2

[0166] PWROT3=(|WCTOM3)*PFUNL3

[0167] PWROT4=(|WCTOM4)*PFUNL4

[0168] PWROT5=(|WCTOM5)*PFUNL5

[0169] 7-FU loads arbitration result:

[0170] PVCFU1=PPROT1+PWROT1

[0171] PVCFU2=PPROT2+PWROT2

[0172] PVCFU3=PPROT3+PWROT3

[0173] PVCFU4=PPROT4+PWROT4

[0174] PVCFU5=PPROT5+PWROT5

[0175] Advanced dynamic mapping-GS variable length features:

[0176] (1) In addition to FU1 to FU5, FUn1 to FUn3 are also required;

[0177] (2) At any time or state, FU1-FU5 and FUn1-FUn3 are mapped to different VLcores, that is, different FUs or FUns are mapped to different VLcores;

[0178] (3) Any FU’s current state is mapped to VLcorepA, and the next state is mapped to VLcorepB, and A is not equal to B;

[0179] (4) The VLcorep trajectories of any FU can be inconsistent, and the FU trajectories of any VLcorep can be inconsistent;

[0180] (5) The correspondence between VLcorep and VLcore changes irregularly with the change of GS;

[0181] (6) VLcorep can skip some VLcores, thus creating GS execution cycles of different lengths;

[0182] (7) Any FU is mapped to VLcoreA at the current moment and to VLcoreB at the next moment, and A can be equal to B;

[0183] (8) The VLcore trajectories of any FU can be inconsistent, and the FU trajectories of any VLcore can be inconsistent;

[0184] (9) There may be FU mapping conflicts between multiple VLcores. Follow the " Figure 6 :FU load arbitration algorithm" for processing.

[0185] See also Figure 7 : FU functional unit and standby functional unit FUn configuration diagram.

[0186] It is divided into FU_TL and FUn_TL: the time sequence layer part of the FU functional unit and the time sequence layer part of the standby functional unit FUn respectively; FU_CL and FUn_CL: the current synthesis layer part of the FU and the current synthesis layer part of the standby functional unit FUn; internal connection relationship: flows from FU_CL (FUn_CL) to FU_TL (FUn_TL).

[0187] See also Figure 8 : Transformation connection diagram.

[0188] Figure 8 (1) Basic FU connection example:

[0189] Take polling dynamic mapping as an example, see " Figure 2 (2) Relationship between VLcore and GS - State Domain (Time Domain) Analysis", the FU connection of VLcore1 is taken as an example.

[0190] Figure 8 (2) Example of FU connection after conversion:

[0191] Combined with Figure 7 : FU and FUn composition diagram", Figure 8 (1) The basic FU connection example is transformed into Figure 8 (2) That is, the time series layer part FU_TL of the previous FU functional unit flows to the current synthesis layer part FU_CL of the next FU functional unit.

[0192] like Fig. 9 As shown, Fig. 9 Model the main implementation methods of the mapping.

[0193] Fig. 9 (1) Core issues that need to be addressed in implementation:

[0194] It mainly solves the problem of connecting FUX_TL (including FUn_TL) to FUY_TL (including FUn_TL), where X and Y can be equal or unequal. In the time domain: Y at the current moment is equal to X at the next moment, that is:

[0195] Y(T)=X(T+1); X represents the present time, and Y represents the next time (future), that is, X is the FU function unit number of the previous time, and Y is the FU function unit number of the next time.

[0196] According to the Figure 7 The "FU and FUn composition diagram" also implies the connection relationship between FUY_CL and FUY_TL; therefore, it becomes a sequential connection relationship between FUX_TL, FUY_CL, and FUY_TL.

[0197] This is a purely internal problem of the FU operation domain. By solving the connection relationship among FUX_TL, FUY_CL and FUY_TL, the system can be connected in series. At the same time, X represents the current moment and Y represents the next moment, thus connecting the progressive relationship in time sequence.

[0198] Fig. 9 (2) Transformation of core issues:

[0199] It is necessary to emphasize the relationship between FU configuration and VLcore. Therefore, the concept of VLcore is introduced in the modeling process, and VLcoreN (VLcore1~VLcore5) information is added to convert the FU operation domain into the GS state domain. The focus is on solving the interlaced transition (conversion) between operation domains.

[0200] like Fig. 9 As shown: FUX_TL (including FUn_TL) connected to VLcoreN_in is the core element, which is the current key information of "FUX mapped to VLcoreN". FUY_CL and FUY_TL need to satisfy "Y(T) = X(T+1)". FUX mapped to VLcoreN may include the following connection relationships:

[0201] FUX_TL—>VLcoreN_in—>FU1_CL—>VLcoreN_out—>FU1_TL(X(T+1)=1)

[0202] FUX_TL—>VLcoreN_in—>FU2_CL—>VLcoreN_out—>FU2_TL(X(T+1)=2)

[0203] …

[0204] FUX_TL—>VLcoreN_in—>FUX_CL—>VLcoreN_out—>FUX_TL

[0205] (X(T+1)=X(T))

[0206] …

[0207] That is, the time series layer part FUX_TL of the FU functional unit at the previous moment flows to the input of the mapped virtual logic core; the input of the virtual logic core flows to the current synthesis layer part FUY_CL of the FU functional unit at the next moment; the current synthesis layer part FUY_CL of the FU functional unit at the next moment flows to the output of the mapped virtual logic core; the output of the mapped virtual logic core flows to the time series layer part FUY_TL of the FU functional unit at the next moment.

[0208] Fig. 9 (3) Implementation modeling:

[0209] 1-FU operation domain: FUX_TL (including FUn_TL); current time series layer array;

[0210] 2-FU operation domain is converted to GS status domain: VLcoreN input mapping multiplexer (Input map crossbar input mapping multiplexer); VLcoreN information introduced by FUX is the key information for mapping FUX to VLcoreN.

[0211] 3-GS state domain is converted to FU operation domain: FUY modem matrix; VLcoreN modulates and demodulates to FUY_CL (including FUn_CL) information;

[0212] 4-FU operation domain: FUY_CL (also includes FUn_CL); the current synthesis layer array, ready for the data needed at the next moment; for example: data_in and data_load, etc., see " Fig.16 "" Figure 17(1)-Figure 17(3) ”;

[0213] 5-FU operation domain is converted to GS state domain: VLcoreN extract matrix; VLcoreN specific requirements are extracted from FUY_CL (including FUn_CL) information;

[0214] 6-GS state domain is converted to FU operation domain: VLcoreN outputs mapping multiplexer (Output mapcrossbar); VLcoreN outputs FUY information to FUY_TL;

[0215] 7-FU operation domain: FUY_TL (including FUn_TL); next moment time series layer array;

[0216] 11-GS status domain: VLcoreN input; represents VLcore1~VLcore5;

[0217] 12-GS status domain: VLcoreN output; represents VLcore1~VLcore5.

[0218] That is, the time series layer partial array is transmitted through the input mapping multiplexer to the input of the virtual logic core; the input of the virtual logic core is transmitted through the modulation and demodulation matrix to the current synthesis layer partial array; the current synthesis layer partial array is transmitted through the extraction matrix to the output of the virtual logic core; the output of the virtual logic core is transmitted through the output mapping multiplexer to the time series layer partial array at the next moment.

[0219] See also Fig.10 : The main process of mapping.

[0220] The main process of mapping FUX to VLcoreN is as follows:

[0221] Step 1: FU_TL array; go to step 2;

[0222] Step 2: VLcoreN Input map crossbar input mapping multiplexer; match FUX information and connect FUX_TL to VLcoreN; go to step 3;

[0223] Step 3: FU modem matrix; match FUY information, modulate and demodulate VLcoreN to FUY_CL information; go to step 4;

[0224] Step 4: Go through the FU_CL array; prepare the FU_CL results data_in and data_load, see " Fig.16 "" Figure 17(1)-Figure 17(3) "; Go to step 5;

[0225] Step 5: VlcoreN extract matrix; match FUY information, extract VLcoreN's dedicated FUY_CL results data_in and data_load; go to step 6;

[0226] Step 6: VLcoreN Output map crossbar output mapping multiplexer; output FUY_CL result from VLcoreN to FUY_TL; go to step 7;

[0227] Step 7: FU_TL array; go to step 1.

[0228] See also Fig.11 , Fig.11 This is a system block diagram of the present invention.

[0229] 1-FU operation domain: FUX_TL (including FUn_TL); current time series layer array;

[0230] 2-FU operation domain is converted to GS status domain: Input map crossbar input mapping multiplexer; VLcoreN information is introduced by FUX, which is the key information for FUX to VLcoreN mapping;

[0231] 3-GS status domain is converted to FU operation domain: FU modem matrix; matching FUY information, modulated and demodulated by VLcoreN to FUY_CL (including FUn_CL) information;

[0232] 4-FU operation domain: FUY_CL (including FUn_CL); current synthesis layer array; prepare the data needed at the next moment; for example: data_in and data_load, etc., see " Fig.16 "" Figure 17(1)-Figure 17(3) ”;

[0233] 5-FU operation domain is converted to GS state domain: VlcoreN extract matrix; extract VLcoreN dedicated requirements from FUY_CL (including FUn_CL) information. Fig. 27 and Fig.28 , the special requirement is to extract the connection relationship of FUY_CL at a certain moment, for example: Fig.28 In switch2_on, FU2_CL to FU2_TL switch control is used. Fig. 27 At T2, T3, T4, T8, T10, T12, T14, T16, T17, T20, and T21, switch2_on is turned on, that is, FU2_CL is extracted; at the same time: at T2, FU2_CL extracts the dedicated requirements of VLcore5; at T3, FU2_CL extracts the dedicated requirements of VLcore5; at T21, FU2_CL extracts the dedicated requirements of VLcore1.

[0234] 6-GS status domain is converted to FU operation domain: Output map crossbar; VLcoreN outputs FUY information to FUY_TL;

[0235] 7-FU operation domain: FUY_TL (including FUn_TL); next moment time series layer array;

[0236] 8-FU mapping refresh controller (FU flush controller), two refresh modes; output signal, as the main basis of the signal channel timing controller (Channel timing controller), refreshes the FUX_TL and FUY_TL time series layer arrays at the same time;

[0237] 9- Channel timing controller; controls the multiplexers and matrices of 2, 3, 4, 5 to ensure the instant connection relationship of: FUX_TL—>VLcoreN_in—>FUY_CL—>VLcoreN_out—>FUY_TL;

[0238] 10-External memory interface (EX_memory IO), including memory interface (memory IO) and local interrupt interface (Local interrupt IO); memory interface includes program memory interface and data memory interface; local interrupt refers to the corresponding interrupt source of the kernel; both memory and local interrupt interfaces are bidirectional data;

[0239] 11-GS status domain: VLcoreN input; represents VLcore1~VLcore5;

[0240] 12-GS status domain: VLcoreN output; represents VLcore1~VLcore5.

[0241] See also Fig.12 :Input map crossbar input mapping multi-way switch structure diagram.

[0242] The main function of the input map crossbar input mapping multiplexer is to convert the FU operation domain to the GS state domain. According to the number of VLcores, the input map crossbar input mapping multiplexer simultaneously maps multiple FUX_TLs to VLcore1_in~VLcore5_in, and each VLcore is assigned to a FUX_TL.

[0243] 1-Channel timing controller; controls the signal channel from FUX_TL to VLcore_in;

[0244] 2-Signal physical path, each physical path has a switch, and all switches are controlled by "1".

[0245] The diagram shows all possible channels from FU1_TL to FU5_TL, FUn_TL to VLcore1_in to VLcore5_in. Depending on actual needs, the specific implementation plan may be a subset of the Input map crossbar input mapping multiplexer shown in the diagram.

[0246] That is, the input mapping multi-way switch or the output mapping multi-way switch includes a signal channel timing controller and a signal physical channel, the signal channel timing controller controls the switching of the signal physical channel, and the physical channel realizes different connections between front and rear inputs and outputs.

[0247] See also Fig.13 :FU modem matrix, schematic diagram of the FU functional unit modulation and demodulation matrix structure.

[0248] The main functions of the FU modem matrix are: converting from the GS state domain to the FU operation domain; according to the number of VLcores, the FU modem matrix simultaneously maps multiple FUY_CLs to VLcore1_in~VLcore5_in, and each VLcore is assigned to a FUY_CL;

[0249] 1-Channel timing controller; controls the signal channel from VLcore_in to FUY_CL;

[0250] 2-Signal physical path, each physical path has a switch, and all switches are controlled by "1".

[0251] The diagram shows all possible channels from VLcore1_in to VLcore5_in to FU1_CL to FU5_CL and FUn_CL. According to actual needs and specific implementation plans, they may be a subset of the FU modem matrix shown in the diagram, that is, the number may be variable.

[0252] See also Fig.14 :Vlcore extract matrix, schematic diagram of the extraction matrix structure.

[0253] The main function of Vlcore extract matrix is ​​to convert the FU operation domain to the GS state domain. According to the number of VLcores, Vlcore extract matrix extracts multiple FUY_CLs at the same time and maps them to VLcore1_out~VLcore5_in_out respectively. Each VLcore will be assigned to a FUY_CL.

[0254] 1-Channel timing controller; controls the signal channel from FUY_CL to VLcore_out;

[0255] 2-Signal physical path, each physical path has a switch, and all switches are controlled by "1".

[0256] The diagram shows all possible channels from FU1_CL to FU5_CL, FUn_CL to VLcore1_out to VLcore5_out. Depending on actual needs, the specific implementation plan may be a subset of the Vlcore extract matrix shown in the diagram.

[0257] See also Fig.15 :Output map crossbar Output mapping multi-way switch structure diagram.

[0258] The main function of the output map crossbar is to convert the GS state domain to the FU operation domain. According to the number of VLcores, the output map crossbar simultaneously maps multiple FUY_TLs to VLcore1_out~VLcore5_out, and each VLcore is assigned to a FUY_TL.

[0259] 1-Channel timing controller; controls the signal channel from VLcore_out to FUY_TL;

[0260] 2-Signal physical channel (signal path), each physical channel has a switch, and all switches are controlled by the 1-Signal channel timing controller.

[0261] The diagram shows all possible channels from VLcore1_out to VLcore5_out to FU1_TL to FU5_TL and FUn_TL. Depending on actual needs and the specific implementation plan, it may be a subset of the Output map crossbar shown.

[0262] See also Fig.16 : The composition and function description of FUX_TL and FUn_TL. The time sequence layer part FU_TL includes a loading stack FU_load and multiple transfer stacks FU_trans. The loading stack FU_load outputs the loaded data according to the processor system working clock, the loading data and the refresh control signal of the refresh controller. The transfer stack FU_trans outputs the transfer data according to the processor system working clock, the transfer data and the refresh control signal of the refresh controller. The specific description is as follows:

[0263] 1-FUX_TL represents FU1_TL~FU5_TL, specifically composed of: FU1_trans (FU1 transfer stack),

[0264] FU2_trans (FU2 transfer stack)...FUX_load (FUX load stack)...FUE_trans (the last FU transfer stack);

[0265] 2- The specific composition of FUn_TL: FU1_trans (FU1 transfer stack), FU2_trans (FU2 transfer stack) ... FUX_trans (FUX transfer stack) ... FUE_trans (the last transfer stack); all are only transfer stacks, and can only be transferred in standby timing;

[0266] 3-FUX load stack (FUX_load), corresponding to FUX_TL, determines the location of FUX_load;

[0267] The inputs of FUX_load are clk, data_load, and flush; among them: clk is the processor system working clock; data_load is the load data, which comes from FUX_CL; flush is the refresh control signal, which comes from the FU flush controller;

[0268] The output of FUX_load is data_out: data is output to FUY_CL.

[0269] 4-FU transfer stack (FU_trans), including: FU1_trans, FU2_trans...FUX_trans...FUE_trans;

[0270] The inputs of FUX_trans are clk, data_in, and flush; among them: clk is the processor system working clock; data_in is the transfer data, which comes from ~FU1_CL, ~FU2_CL...~FUX_CL...~FUE_CL; flush is the refresh control signal, which comes from the FU flush controller;

[0271] The output of FUX_trans is data_out: data is output to all FU_CL or FUn_CL;

[0272] 5-FUX_load core register; see "10" for the specific algorithm;

[0273] 6-FUX_trans core register; see "11" for the specific algorithm;

[0274] 7- Load data (data_load), divided into load refresh data (data_new), load condition 1 (case1), load condition 2 (case2) ... load condition n (casen);

[0275] data_new data width ≥ data_in data width = data_out data width

[0276] 8-FUX_trans refresh timing; the earliest refresh timing is FUX_trans after FUX_load, and the latest refresh timing is FUX_trans before FUX_load. See the diagram on the right for details. Figure 8 : Conversion connection diagram" is taken as an example to discuss the refresh timing of FU1_trans: FU1_TL is the timing of FU1_load. Therefore, the black box part is in accordance with: the earliest refresh timing is FU1_trans (corresponding to FU5_TL) after FU1_load (corresponding to FU1_TL), and the latest refresh timing is FU1_trans (corresponding to FU4_TL) before FU1_load (corresponding to FU1_TL).

[0277] 9-FUX_load refresh timing is always valid, that is, it is always refreshing;

[0278] 10-FUX_load behavior modeling algorithm, clk edge is the clock edge, flush is the refresh indication, case1~case1n are n load operation conditions, data_new[case1] represents the relevant data bits of case1 condition in data_new:

[0279] clk edge&flush&case1=>data_out=data_new[case1]

[0280] clk edge&flush&case2=>data_out=data_new[case2]

[0281] clk edge&flush&case3=>data_out=data_new[case3]

[0282] …

[0283] clk edge&flush&casen=>data_out=data_new[casen]

[0284] 11-FU_trans behavior modeling algorithm, this algorithm is only applicable to mode1 of FU flush controller, data_vld indicates valid data, data_invld indicates invalid data:

[0285] clk edge&! flush=>data_out=data_vld

[0286] clk edge&flush=>data_out=data_invld

[0287] Mode 2 of FU flush controller will cancel the behavior modeling algorithm of FU_trans;

[0288] In mode 1 of the 12-FU flush controller, an example of the application of FUX_load is used for fetching instruction code (ins_code). clk edge is the clock edge, if_op is the operation of fetching instruction code, flush is the refresh indication, ins_new indicates the new instruction code entering the kernel, vld start is the effective starting point of the new instruction code, nf_op is the operation of non-fetching instruction code, ins_trans is the input data from the instruction code transfer stack, and assigninvld indicates the reference connection of the non-valid instruction code from FUX_trans:

[0289] clk edge&if_op&flush=>ins_code=ins_new(vld start&flush)

[0290] clk edge&nf_op&flush=>ins_code=ins_trans(assign invld&flush)

[0291] 13-FU flush controller mode2, FUX_load application example, also about the use case of fetching instruction code (ins_code), clk edge is the clock edge, if_op is the operation of fetching instruction code, flush is the refresh indication, ins_new indicates the new instruction code entering the kernel, vld start is the effective starting point, nf_op is the operation of not fetching instruction code, ins_trans is the input data from the instruction code transfer stack, hold is the hold operation (i.e. no change):

[0292] clk edge&if_op&flush=>ins_code=ins_new(vldstart&flush)

[0293] clk edge&nf_op&flush=>ins_code=ins_code(hold&flush)

[0294] 14-FU flush controller mode1, FU_trans application example, also about the use case of fetching instruction code (ins_code), clk edge is the clock edge, flush is the refresh indication, ins_vld indicates the valid instruction code from FUX_load, assign vld indicates the reference connection of the valid instruction code from FUX_load, invld start is the invalid starting point of the instruction code after FUX_trans processing, and ins_invld is the invalid instruction code after FUX_trans processing:

[0295] clk edge=>ins_code&! flush=ins_vld(assign vld)

[0296] clk edge&flush=>ins_code&flush=ins_invld(invld start&flush)

[0297] 15-In mode 2 of the FU flush controller, FU_trans is released by hardware, that is, there is no entity.

[0298] See also Figure 17(1)-Figure 17(3) :Composition and function description of FUY_CL and FUn_CL.

[0299] Figure 17(1) is an overview of the functions of FUY_CL and FUn_CL.

[0300] As shown in the figure, FUY_CL has four functions, as follows:

[0301] 1-FUX_load-connection-FUX_trans, FUX_trans-connection-FUX_trans, the specific algorithm:

[0302] assignment data_in=data_out

[0303] 2-Ex_memory-connection-FUY_load function, specific algorithm:

[0304] assignment data_load=Ex_memory

[0305] 3-FUX_load-connection-Ex_memory function, specific algorithm:

[0306] assignment Ex_memory=data_out

[0307] 4-FUY_trans-connect-FUY_load, FUY_load-connect-FUY_load, the specific algorithm is:

[0308] assignment data_load=data_out

[0309] FUn_CL must be connected to FUn_TL, so it has only the following two functions:

[0310] 1-FUX_load-connection-FUX_trans, FUX_trans-connection-FUX_trans, the specific algorithm:

[0311] assignment data_in=data_out

[0312] 3-FUX_load-connection-Ex_memory function, specific algorithm:

[0313] assignment Ex_memory=data_out

[0314] The specific method of data_load from Ex_memory (2 above) and data_out (4 above) is as follows:

[0315] Operation method, Ex_memory and data_out are operated and the result is sent to data_new;

[0316] Combination method, Ex_memory and data_out are combined to get the result and send it to data_new;

[0317] Bypass method, Ex_memory generally bypasses data_out and directly sends it to data_new.

[0318] Figure 17(2) Effect after FUY_CL and FUn_CL are connected in series

[0319] The picture shows from upper left to upper right to lower left to lower right;

[0320] FUX_TL------FUY_CL------FUY_TL;

[0321] FUn_TL------FUY_CL------FUY_TL;

[0322] FUX_TL------FUn_CL------FUn_TL;

[0323] FUn_TL------FUn_CL------FUn_TL;

[0324] The connection effects of the four cases, where X still represents the present (current moment), Y represents the future (next moment), FUn represents the insertion of the standby component, and FUE_load and FUE_trans represent the last FU_load and FU_trans. In the figure, Ex_memory is directly connected to FUX_load and FUY_load.

[0325] Figure 17(3) Figure 8 Results The tandem effect after the above transformation.

[0326] The connection relationship between FU_load (FU1_load~FU5_load) and FU_trans (FU1_trans~FU5_trans) in the figure is finally:

[0327] FU1_load and FU1_trans form a loop;

[0328] FU5_load and FU5_trans form a loop;

[0329] FU2_load and FU2_trans form a loop;

[0330] FU3_load and FU3_trans form a loop;

[0331] FU4_load and FU4_trans form a loop;

[0332] In the above loops, the position of FU_load is shifted rightward successively;

[0333] Take FU1 as an example: FU1 becomes effective after FU1_load, and becomes invalid after FU1_trans refresh. The time of failure is controllable, and the earliest failure point of FU1 is generally used. These analyses are similar to " Fig.16 : The configuration and function description of FUX_TL and FUn_TL" and "8-FUX_trans refresh timing" are completely consistent.

[0334] See also Fig.18 :FU flush controller two modes

[0335] The first mode (mode1): with " Figure 2 :Polling dynamic mapping" as an example.

[0336] FUX is refreshed (flush) in both FUX_load and FUX_trans. As shown in the figure: FUX is refreshed by FUX_load or FUX_trans in FU1, FU2...FU5, and the corresponding time may be T1, T2...T5. Among them, FUX_load will make FUX effective, and FUX_trans will make FUX invalid. Among them, X represents the current, after FUX_load (see Fig.16 , Figure 17(1)-Figure 17(3) , FUX_load can only be in FUX_TL), the current data is loaded into FUX_TL, that is, it takes effect. Transition to the next moment, FUX_TL-FUY_CL-FUY_TL, FUX_load (in FUX_TL) will connect to FUX_trans (in FUY_TL), and will generally be updated (flush) at the next moment Y. After the update, the current value is invalid. For the specific connection relationship, see Figure 17 (2) and Figure 17 (3).

[0337] For example: FUX_load occurs at time T1, that is, FUX takes effect at time T1; FUX_trans occurs at time T2~T5, and FUX failure can occur at any time between T2 and T5.

[0338] Therefore, in this mode:

[0339] (1) Both FUX_load and FUX_trans are necessary;

[0340] (2) From the perspective of the FU operation domain alone, no matter what the VLcore needs from the FU, it can be quickly refreshed through FUX_load and FUX_trans;

[0341] (3) The connection between FUX_load and FUX_trans indirectly expresses the system status operation relationship.

[0342] The second mode (mode2): with " Figure 2 :Polling dynamic mapping" as an example.

[0343] FUX is only refreshed (flush) at FUX_load. As shown in the figure: there is a global state counter (GS_cnt), and there will be corresponding logical core 1 state counter (VL1_scnt), logical core 2 state counter (VL2_scnt)...logical core 5 state counter (VL5_scnt), VL1_scnt~VL5_scnt correspond to a specific refresh state SX. After SX, the FUX_load behavior will be triggered, and FUX will take effect. In other states, FUX is in a maintained state and will not fail. VL1_scnt is permanently in operation, and VL2_scnt~VL5_scnt only operate after the corresponding logical core is started.

[0344] Therefore, in this mode:

[0345] (1) FUX_load is necessary, but FUX_trans is not necessary. FUX_trans is released by release.

[0346] (2) Slow refresh can be achieved, for example, the refresh rate when only VL1_scnt is started is one fifth of the refresh rate of all VL1_scnt to VL5_scnt;

[0347] (3) VL1_scnt~VL5_scnt are needed to calibrate the operating status of each logic core;

[0348] (4) GS_cnt can be used to indirectly calibrate VL1_scnt~VL5_scnt, and thus GS_cnt can be used to calibrate the operating status of each logic core.

[0349] See also Fig.19 : Example of FU flush controller mode 2 with polling dynamic mapping.

[0350] Fig.19 (1) shows that: VLcore1~VLcore3 are started normally and are in active state; VLcore4 and VLcore5 are not started and are in idle state.

[0351] Fig.19 (2) shows: the operating status of GS_cnt, VL1_scnt ~ VL5_scnt. GS_cnt is always in the operating state, VL1_scnt ~ VL3_scnt are in the operating state, VL4_scnt, VL5_scnt are in the stagnant state.

[0352] GS_cnt, VL1_scnt~VL3_scnt all have 5 state cycles. Fig.19(1) Correspondence. VL1_scnt to VL3_scnt are staggered by one state, forming a staggered relationship. VL4_scnt and VL5_scnt are in the invalid state (Sinvld) at any time.

[0353] See also Fig. 20 :FU_trans hardware and interface release.

[0354] When the FU flush controller adopts mode 2 implementation strategy, all FU_trans releases are released, that is, FU_trans does not need to exist, which includes:

[0355] (1) FU1_trans, FU2_trans, FUX-1_trans, FUX+1_trans, FUE_trans in FUX are released;

[0356] (2) FU1_trans, FU2_trans, FUX-1_trans, FUX_trans, FUX+1_trans, FUE_trans in FUn are released; that is, the entire FUn is released;

[0357] (3) All interfaces involved in the released parts of (1) and (2) are also released.

[0358] See also Fig.21 : Detailed process of mapping.

[0359] At time T, FUX is mapped to VLcoreN, and at time T+1, FUY is mapped to VLcoreN. Corresponding to the previous text, X represents the present and Y represents the future. According to " Fig. 9 : The main implementation method of mapping is modeled" to obtain FUX_TL→VLcoreN_in→FUY_CL→VLcoreN_out→FUY_TL, and the detailed process is as follows:

[0360] Step 1: Start; Go to step 2;

[0361] Step 2: In the FU operation domain, the only logical core hardware is discretized, and the hardware discretization is divided according to certain rules: for example, as mentioned above, for simple systems, the functions are mutually exclusive; for complex systems, the performance is divided according to the principle of high efficiency. It is divided into FU1~FU5, FUn is the standby function unit, and the timing part is: FU1_TL~FU5_TL, FUn_TL; go to step 3;

[0362] Step 3: The Channel timing controller controls the signal path from FU1_TL to FU5_TL, FUn_TL to VLcore1_in to VLcore5_in, thereby matching the FUX requirement and connecting FUX_TL to VLcoreN. The FU operation domain is switched to the GS state domain, and the process goes to step 4.

[0363] Step 4: In the GS state domain, load the demand information of VLcoreN, and match the FU1_TL~FU5_TL and FUn_TL introduced above for VLcore1~VLcore5 respectively; go to step 5;

[0364] Step 5: The channel timing controller controls the signal path from VLcore1_in to VLcore5_in to FU1_CL to FU5_CL and FUn_CL, thereby matching the FUY requirement and connecting VLcore_in to FUY_CL. The GS state domain is switched to the FU operation domain, and the process goes to step 6.

[0365] Step 6: In the FU operation domain, load the demand information of FUY, and match the VLcore1_in~VLcore5_in introduced above for FU1_CL~FU5_CL and FUn_CL respectively; go to step 7;

[0366] Step 7: In the FU operation domain, pass through the FU_CL array; prepare the FU_CL result data_in and data_load, see " Fig.16 "" Figure 17(1)-Figure 17(3) "; Go to step 8;

[0367] Step 8: The Channel timing controller controls the signal paths from FU1_CL to FU5_CL, FUn_CL to VLcore1_out to VLcore5_out, thereby matching the FUY requirements, extracting the FUY_CL path that meets the requirements, and connecting FUY_CL to VLcoreN_out; the FU operation domain is switched to the GS state domain, and the process goes to step 9;

[0368] Step 9: In the GS state domain, continue to complete the demand information of VLcoreN, and match the FU1_CL~FU5_CL and FUn_CL introduced above for VLcore1~VLcore5 respectively; go to step 10;

[0369] Step 10: The channel timing controller controls the signal path from VLcore1_out to VLcore5_out to FU1_TL to FU5_TL and FUn_TL, thereby matching the FUY requirement and connecting VLcore_out to FUY_TL. The GS state domain is switched to the FU operation domain, and the process goes to step 11.

[0370] Step 11: In the FU operation domain, load the demand information of FUY, and match the VLcore1_out~VLcore5_out introduced above for FU1_TL~FU5_TL and FUn_TL respectively; go to step 12;

[0371] Step 12: In the FU operation domain, pass through the FU_TL array; go to step 13;

[0372] Step 13: Wait for the FU mapping relationship to be refreshed; if yes, go to step 1; if yes, go to step 13.

[0373] It is important to emphasize that:

[0374] (1) The above mapping relationship (process) occurs at time T, and may and often changes at time T+1. After the FU mapping is refreshed, the mapping relationship will change;

[0375] (2) Map multiple FUs to VLcore at the same time; for example:

[0376] FU1_TL→VLcore1_in→FU2_CL→VLcore1_out→FU2_TL

[0377] FU2_TL→VLcore2_in→FU3_CL→VLcore2_out→FU3_TL

[0378] FU3_TL→VLcore3_in→FU4_CL→VLcore3_out→FU4_TL

[0379] FU4_TL→VLcore4_in→FU5_CL→VLcore4_out→FU5_TL

[0380] FU5_TL→VLcore5_in→FU1_CL→VLcore5_out→FU1_TL

[0381] can and often do occur simultaneously;

[0382] (3) Steps 3 and 4 correspond to the Input map crossbar input mapping multi-way switch;

[0383] (4) Steps 5 and 6 correspond to the FU modem matrix;

[0384] (5) Steps 8 and 9 correspond to the Vlcore extract matrix;

[0385] (6) Steps 10 and 11 correspond to the Output map crossbar;

[0386] (7) Step 7 is used to connect to external storage (Ex_memory). The specific external storage interfaces are: memoryIO, Local interrupt IO

[0387] See also Fig. 22 : From behavioral modeling to implementation method of the embodiment of the present invention.

[0388] 1-Demand; Assume that the demands are as follows:

[0389] (1) FUX is mapped to VLcore1 at time T1;

[0390] (2) FUX is mapped to VLcore2 at time T2;

[0391] (3) FUX is mapped to VLcore3 at time T3;

[0392] (4) FUX is mapped to VLcore4 at time T4;

[0393] (5) FUX is mapped to VLcore5 at time T5;

[0394] 2-Behavior Modeling, in response to the above requirements, adopt " Fig. 9 : The main implementation method modeling diagram" method, abstract Figure 5 Model. FUX is demand-specific, therefore, FUX_TL is a model element; VLcore1~VLcore5 are subdivided into VLcore1_in~VLcore5_in, VLcore1_out~VLcore5_out; interleaved transition (conversion) between FU operation domain and GS status domain is realized, for other details, please see "3" and "4";

[0395] 3-FUY_CL&FUY_TL, no matter how much "Y" is equal to, it will not affect the conclusion of FUX mapping to VLcoreN; but it must be satisfied in the time domain: Y at the current moment is equal to X at the next moment, that is:

[0396] Y(T)=X(T+1);

[0397] 4- Two-dimensional physical channel switch array, including " Fig. 9: The main implementation methods of mapping modeling mentioned in "Mapping Modeling":

[0398] Input map crossbar input mapping multiplexer - converted from the FU operation domain to the GS status domain,

[0399] FU modem matrix - converted from the GS state domain to the FU operation domain,

[0400] VlcoreN extract matrix——converted from FU operation domain to GS state domain,

[0401] Output map crossbar——Transformed from GS state domain to FU operation domain,

[0402] That is, the above four switch arrays;

[0403] 5-Specific implementation method: In order to simplify the above behavior modeling for easy implementation, the following ideas are obtained: Fig. 22 , originally there are 5 signal paths in "2", these paths are used to connect FUX_TL, FUY_CL, FUY_TL, for VLcore1 ~ VLcore5, FUX_TL, FUY_CL, FUY_TL through time T1 ~ T5 respectively; 5 physical paths can be changed into 1, and the mapping relationship of VLcore1 ~ VLcore5 can be converted into switch control at T1 ~ T5. Therefore, the following is added:

[0404] 6- One-dimensional time domain switch array. T1~T5 correspond to the mapping relationship of VLcore1~VLcore5 respectively. One-dimensional time domain switch array technology derives and simulates the capture and occupation of FU by each VLcore.

[0405] One of the important functions of VLcore is to realize the operation domain conversion, which is to transition the FU operation domain to the GS state domain. In a system, the mapping behavior of FU functional units with the same or different GS lengths is unified with the reference time scale, which forms the time domain analysis. The time domain is a specific abstract form of the GS state domain. Therefore, the operation domain conversion function of VLcore can be realized by using the time domain switch.

[0406] The flush control will refresh the mapping relationship between FUX and VLcore (VLcore1~VLcore5) at each moment (T1~T5). The one-dimensional time domain switch array already contains all possible connection relationships involved in the flush. The flush may affect the timing of the channel switch control of the one-dimensional time domain switch array. For example, the switch timing is not affected in the "polling dynamic mapping working" state (because it is always open), but it is affected in other working states (not always open).

[0407] After simplification from modeling to implementation, the complexity is reduced and the technical feasibility is enhanced. In this way, a system with multiple threads in parallel is realized, including an FU operation domain, a GS state domain, and a physical channel switch array. The FU operation domain describes the FU mapping state. The FU includes a time series layer part FU_TL and a current synthesis layer part FU_CL. The GS state domain is converted from the VLcore operation domain. The GS state domain can be converted from the VLcore operation domain back to the FU operation domain. The VLcore operation domain conversion is an analysis of the current use state of the FU with VLcore as the medium. The VLcore includes a virtual logic core input VLcore_in and a virtual logic core output VLcore_out. The time series layer part FU_TL is converted to the virtual logic core input VLcore_in through the two-dimensional physical channel switch array. The virtual logic core input VLcore_in is converted to the current synthesis layer part FU_CL through the two-dimensional physical channel switch array. The current synthesis layer part FU_CL is converted to the virtual logic core output VLcore_out through the two-dimensional physical channel switch array. The virtual logic core output VLcore_out is converted to the current synthesis layer part FU_CL at the next moment through the two-dimensional physical channel switch array. It should be noted that: FU operation domain is not an entity, FU is an entity; the GS state domain corresponds to the FU operation domain; there is also VLcore operation domain conversion. FU operation domain + VLcore operation domain conversion = GS state domain; similarly, GS state domain and VLcore operation domain conversion are not entities, VLcore is an entity.

[0408] See also Fig.23 : Polling dynamic mapping workflow.

[0409] According to the method mentioned above, we analyze the Figure 2 : The main process of the "polling dynamic mapping method" is as follows:

[0410] Step 1: Start; Go to step 2;

[0411] Step 2: By " Fig.21 : The detailed process of mapping "gets the following initialization mapping relationship:

[0412] FU1 is mapped to VLcore1 - FU1_TL-connected-FU5_CL-connected-FU5_TL;

[0413] FU4 is mapped to VLcore2 - FU4_TL-connected-FU1_CL-connected-FU1_TL;

[0414] FU3 is mapped to VLcore3 - FU3_TL - connected - FU4_CL - connected - FU4_TL;

[0415] FU2 is mapped to VLcore4 - FU2_TL - connected - FU3_CL - connected - FU3_TL;

[0416] FU5 is mapped to VLcore5 - FU5_TL-connected-FU2_CL-connected-FU2_TL;

[0417] For the above mapping relationship, synchronization occurs in the GS1 state (time), and go to step 3;

[0418] Step 3: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 4, otherwise go to step 3;

[0419] Step 4: Refresh the mapping relationship to obtain the following:

[0420] FU5 is mapped to VLcore1 - FU5_TL-connected-FU2_CL-connected-FU2_TL

[0421] FU1 is mapped to VLcore1 - FU1_TL-connect-FU5_CL-connect-FU5_TL

[0422] FU4 is mapped to VLcore3 - FU4_TL-connected-FU1_CL-connected-FU1_TL

[0423] FU3 is mapped to VLcore4 - FU3_TL-connect-FU4_CL-connect-FU4_TL

[0424] FU2 is mapped to VLcore5 - FU2_TL - Connect - FU3_CL - Connect - FU3_TL

[0425] For the above mapping relationship, synchronization occurs in GS2 state (time), go to step 5;

[0426] Step 5: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 6, otherwise go to step 5; Step 6: Refresh the mapping relationship to obtain the following:

[0427] FU2 is mapped to VLcore1 - FU2_TL - Connect - FU3_CL - Connect - FU3_TL

[0428] FU5 is mapped to VLcore2 - FU5_TL-connect-FU2_CL-connect-FU2_TL

[0429] FU1 is mapped to VLcore3 - FU1_TL-connect-FU5_CL-connect-FU5_TL

[0430] FU4 is mapped to VLcore4 - FU4_TL-connected-FU1_CL-connected-FU1_TL

[0431] FU3 is mapped to VLcore5 - FU3_TL-connect-FU4_CL-connect-FU4_TL

[0432] For the above mapping relationship, synchronization occurs in GS3 state (time), go to step 7;

[0433] Step 7: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 8, otherwise go to step 7; Step 8: Refresh the mapping relationship to obtain the following:

[0434] FU3 is mapped to VLcore1 - FU3_TL - Connect - FU4_CL - Connect - FU4_TL

[0435] FU2 is mapped to VLcore2 - FU2_TL - Connect - FU3_CL - Connect - FU3_TL

[0436] FU5 is mapped to VLcore3 - FU5_TL-connect-FU2_CL-connect-FU2_TL

[0437] FU1 is mapped to VLcore4 - FU1_TL-connect-FU5_CL-connect-FU5_TL

[0438] FU4 is mapped to VLcore5 - FU4_TL-connected-FU1_CL-connected-FU1_TL

[0439] For the above mapping relationship, synchronization occurs in GS4 state (time), go to step 9;

[0440] Step 9: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 10, otherwise go to step 9; Step 10: Refresh the mapping relationship to obtain the following:

[0441] FU4 is mapped to VLcore1 - FU4_TL-connect-FU1_CL-connect-FU1_TL

[0442] FU3 is mapped to VLcore2 - FU3_TL - Connect - FU4_CL - Connect - FU4_TL

[0443] FU2 is mapped to VLcore3 - FU2_TL - Connect - FU3_CL - Connect - FU3_TL

[0444] FU5 is mapped to VLcore4 - FU5_TL-connected-FU2_CL-connected-FU2_TL

[0445] FU1 is mapped to VLcore5 - FU1_TL-connect-FU5_CL-connect-FU5_TL

[0446] For the above mapping relationship, synchronization occurs in the GS5 state (time), and go to step 11;

[0447] Step 11: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 1; otherwise, go to step 11;

[0448] See also Fig.24 : Polling dynamic mapping implementation block diagram.

[0449] According to the previous method, the focus is on " Fig. 9 :Main implementation methods of mapping, modeling, Fig.11 : Patent system block diagram" and " Fig. 22 :From Behavior Modeling to Implementation Methods", analyzing " Figure 2 : Polling dynamic mapping method" to obtain the implementation block diagram;

[0450] After transformation, a diagram connection relationship is formed, in which:

[0451] 1- Combine with " Fig.23 :Polling dynamic mapping process” analyzes the working status of the FU4_TL→FU1_CL connection relationship and defines this switch control signal as switch1 on;

[0452] 2- Combine " Fig.23 :Polling dynamic mapping process” analyzes the working status of the FU1_CL→FU1_TL connection relationship and defines this switch control signal as switch2 on;

[0453] exist" Fig.23 :Polling dynamic mapping process”:

[0454] FU4 is mapped to VLcore2 - FU4_TL - Connect - FU1_CL - Connect - FU1_TL (GS1)

[0455] FU4 is mapped to VLcore3 - FU4_TL - Connect - FU1_CL - Connect - FU1_TL (GS2)

[0456] FU4 is mapped to VLcore4 - FU4_TL-connected-FU1_CL-connected-FU1_TL (GS3)

[0457] FU4 is mapped to VLcore5 - FU4_TL-connected-FU1_CL-connected-FU1_TL (GS4)

[0458] FU4 is mapped to VLcore1 - FU4_TL-connected-FU1_CL-connected-FU1_TL (GS5)

[0459] In the figure, switch1 on and switch2 on are marked with dark boxes. From the above analysis, we can get that in all states (times) of GS1 to GS5, switch1 on and switch2 on are valid, that is, they are in the normally open state. The same conclusion can be obtained for other paths according to the above analysis:

[0460] 3- Left-hand one-dimensional time-domain switch array (“ Fig. 22 :From Behavior Modeling to Implementation Methods”) Normally open;

[0461] 4- One-dimensional time-domain switch array on the right (“ Fig. 22 :From Behavior Modeling to Implementation Methods”) Normally open;

[0462] Flush may refresh the mapping relationship between FU and VLcore for each GS(T). The one-dimensional time domain switch array already contains all possible connection relationships involved in flush. Flush will affect the timing (normally open) of the channel switch control of the one-dimensional time domain switch array.

[0463] Finally there will be a conclusion:

[0464] A.FU1_TL→FU5_CL→FU5_TL; normally open state;

[0465] B.FU2_TL→FU3_CL→FU3_TL; normally open state;

[0466] C.FU3_TL→FU4_CL→FU4_TL; normally open state;

[0467] D.FU4_TL→FU1_CL→FU1_TL; normally open state;

[0468] E.FU5_TL→FU2_CL→FU2_TL; normally open state.

[0469] See also Fig.25 :Advanced dynamic mapping - GS fixed length workflow.

[0470] According to the method mentioned above, we analyze the Figure 3 The main process of "Advanced Dynamic Mapping-GS Fixed Length Method" is as follows:

[0471] Step 1: Start; Go to step 2;

[0472] Step 2: By " Fig.21 : The detailed process of mapping "gets the following initialization mapping relationship:

[0473] FU1 is mapped to VLcore1 - FU1_TL - Connect - FU3_CL - Connect - FU3_TL

[0474] FU5 is mapped to VLcore2 - FU5_TL-connect-FU5_CL-connect-FU5_TL

[0475] FU2 is mapped to VLcore3 - FU2_TL-connect-FU2_CL-connect-FU2_TL

[0476] FU3 is mapped to VLcore4 - FU3_TL-connect-FU4_CL-connect-FU4_TL

[0477] FU4 is mapped to VLcore5 - FU4_TL-connected-FU1_CL-connected-FU1_TL

[0478] For the above mapping relationship, synchronization occurs in the GS1 state (time), and go to step 3;

[0479] Step 3: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 4, otherwise go to step 3;

[0480] Step 4: Refresh the mapping relationship to obtain the following:

[0481] FU3 is mapped to VLcore1 - FU3_TL - Connect - FU3_CL - Connect - FU3_TL

[0482] FU5 is mapped to VLcore2 - FU5_TL-connected-FU4_CL-connected-FU4_TL

[0483] FU2 is mapped to VLcore3 - FU2_TL-connected-FU1_CL-connected-FU1_TL

[0484] FU4 is mapped to VLcore4 - FU4_TL-connect-FU5_CL-connect-FU5_TL

[0485] FU1 is mapped to VLcore5 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0486] For the above mapping relationship, synchronization occurs in GS2 state (time), go to step 5;

[0487] Step 5: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 6, otherwise go to step 5;

[0488] Step 6: Refresh the mapping relationship to obtain the following:

[0489] FU3 is mapped to VLcore1 - FU3_TL - Connect - FU5_CL - Connect - FU5_TL

[0490] FU4 is mapped to VLcore2 - FU4_TL-connected-FU1_CL-connected-FU1_TL

[0491] FU1 is mapped to VLcore3 - FU1_TL-connect-FU4_CL-connect-FU4_TL

[0492] FU5 is mapped to VLcore4 - FU5_TL-connected-FU3_CL-connected-FU3_TL

[0493] FU2 is mapped to VLcore5 - FU2_TL-connect-FU2_CL-connect-FU2_TL

[0494] For the above mapping relationship, synchronization occurs in GS3 state (time), go to step 7;

[0495] Step 7: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 8, otherwise go to step 7;

[0496] Step 8: Refresh the mapping relationship to obtain the following:

[0497] FU5 is mapped to VLcore1 - FU5_TL-connected-FU3_CL-connected-FU3_TL

[0498] FU1 is mapped to VLcore2 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0499] FU4 is mapped to VLcore3 - FU4_TL-connect-FU4_CL-connect-FU4_TL

[0500] FU3 is mapped to VLcore4 - FU3_TL-connected-FU1_CL-connected-FU1_TL

[0501] FU2 is mapped to VLcore5 - FU2_TL-connect-FU5_CL-connect-FU5_TL

[0502] For the above mapping relationship, synchronization occurs in GS4 state (time), go to step 9;

[0503] Step 9: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 10, otherwise go to step 9; Step 10: Refresh the mapping relationship to obtain the following:

[0504] FU3 is mapped to VLcore1 - FU3_TL-connect-FU1_CL-connect-FU1_TL

[0505] FU2 is mapped to VLcore2 - FU2_TL - Connect - FU4_CL - Connect - FU4_TL

[0506] FU4 is mapped to VLcore3 - FU4_TL - Connect - FU3_CL - Connect - FU3_TL

[0507] FU1 is mapped to VLcore4 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0508] FU5 is mapped to VLcore5 - FU5_TL-connect-FU5_CL-connect-FU5_TL

[0509] For the above mapping relationship, synchronization occurs in the GS5 state (time), and go to step 11;

[0510] Step 11: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 12, otherwise go to step 11; Step 12: Refresh the mapping relationship to obtain the following:

[0511] FU1 is mapped to VLcore1 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0512] FU4 is mapped to VLcore2 - FU4_TL-connect-FU5_CL-connect-FU5_TL

[0513] FU3 is mapped to VLcore3 - FU3_TL-connected-FU1_CL-connected-FU1_TL

[0514] FU2 is mapped to VLcore4 - FU2_TL - Connect - FU3_CL - Connect - FU3_TL

[0515] FU5 is mapped to VLcore5 - FU5_TL-connected-FU4_CL-connected-FU4_TL

[0516] For the above mapping relationship, synchronization occurs in the GS6 state (time), and go to step 13;

[0517] Step 13: Wait for the FU mapping relationship to be refreshed, if refreshed, go to step 14, otherwise go to step 13;

[0518] Step 14: Refresh the mapping relationship to obtain the following:

[0519] FU2 is mapped to VLcore1 - FU2_TL-connected-FU1_CL-connected-FU1_TL

[0520] FU5 is mapped to VLcore2 - FU5_TL-connect-FU5_CL-connect-FU5_TL

[0521] FU1 is mapped to VLcore3 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0522] FU3 is mapped to VLcore4 - FU3_TL-connect-FU3_CL-connect-FU3_TL

[0523] FU4 is mapped to VLcore5 - FU4_TL-connect-FU4_CL-connect-FU4_TL

[0524] For the above mapping relationship, synchronization occurs in the GS7 state (time), and go to step 15;

[0525] Step 15: Wait for the FU mapping relationship to be refreshed. If refreshed, go to step 1; otherwise, go to step 15;

[0526] See also Fig.26 :Advanced dynamic mapping - GS fixed-length implementation block diagram.

[0527] According to the previous method, the focus is on " Fig. 9 :Main implementation methods of mapping, modeling, Fig.11 : Patent system block diagram" and " Fig. 22 :From Behavior Modeling to Implementation Methods", analyzing " Figure 3 :Advanced dynamic mapping-GS fixed length method" gets the implementation block diagram;

[0528] After transformation, the diagram connection relationship is obtained, where:

[0529] 1- Combine with " Fig.25 :Advanced Dynamic Mapping - GS Fixed Length Workflow" analyzes the working status of the FU5_TL→FU5_CL connection relationship and defines this switch control signal as switch1 on;

[0530] exist" Fig.25 In "Advanced Dynamic Mapping - GS Fixed Length Workflow", switch1 on is turned on at the following times:

[0531] FU5 is mapped to VLcore2 - FU5_TL-connect-FU5_CL-connect-FU5_TL (GS1)

[0532] FU5 is mapped to VLcore5 - FU5_TL-connect-FU5_CL-connect-FU5_TL (GS5)

[0533] 2- Combine " Fig.25:Advanced Dynamic Mapping - GS Fixed Length Workflow" analyzes the working status of the FU5_CL→FU5_TL connection relationship and defines this switch control signal as switch2 on;

[0534] exist" Fig.25 In "Advanced Dynamic Mapping - GS Fixed Length Workflow", switch2 on is turned on when:

[0535] FU5 is mapped to VLcore2 - FU5_TL-connect-FU5_CL-connect-FU5_TL (GS1)

[0536] FU4 is mapped to VLcore4 - FU4_TL - Connect - FU5_CL - Connect - FU5_TL (GS2)

[0537] FU3 is mapped to VLcore1 - FU3_TL - Connect - FU5_CL - Connect - FU5_TL (GS3)

[0538] FU2 is mapped to VLcore5 - FU2_TL-connected-FU5_CL-connected-FU5_TL (GS4)

[0539] FU5 is mapped to VLcore5 - FU5_TL-connect-FU5_CL-connect-FU5_TL (GS5)

[0540] FU4 is mapped to VLcore2 - FU4_TL - Connect - FU5_CL - Connect - FU5_TL (GS6)

[0541] FU5 is mapped to VLcore2 - FU5_TL-connect-FU5_CL-connect-FU5_TL (GS7)

[0542] In the figure, switch1 on and switch2 on are marked with dark boxes. Switch2 on is normally open, and switch1 on is a controlled switch. Other channels can also be analyzed according to the above to obtain the switching timing of each channel:

[0543] 3- Left-hand one-dimensional time-domain switch array (“ Fig. 22 : From Behavior Modeling to Implementation Methods”) controlled switches, for each path, specific analysis is required, according to “ Fig.25 :Advanced dynamic mapping - GS fixed length workflow" sorts out the switch timing state and writes it into the Channel timing controller state machine for control;

[0544] 4- One-dimensional time-domain switch array on the right (“ Fig. 22 :From Behavior Modeling to Implementation Methods”) Normally open;

[0545] 5-Flush: Each GS(T) may refresh the mapping relationship between FU and VLcore. The one-dimensional time-domain switch array already contains all possible connection relationships involved in flush. Flush will affect the timing of the channel switch control of the one-dimensional time-domain switch array. For example, FU5 is mapped to VLcore2 and FU5 is mapped to VLcore5, which turns switch1 on. FU5 is mapped to VLcore1, FU5 is mapped to VLcore3, and FU5 is mapped to VLcore4, which turns switch1 on and turns on other channels.

[0546] See also Fig. 27 :Advanced dynamic mapping - GS variable length workflow.

[0547] According to the method mentioned above, we analyze the Figure 4 :Advanced Dynamic Mapping-GS Variable Length Method" and " Figure 5 The main process of "Advanced Dynamic Mapping-GS Indefinite Length Time Domain Analysis" is as follows (due to the long process, some non-critical transitional steps are omitted and only the core process is retained):

[0548] Step 1: From the Fig.21 : The detailed process of mapping "gets the following initialization mapping relationship:

[0549] FU1 is mapped to VLcore1 - FU1_TL - Connect - FU3_CL - Connect - FU3_TL

[0550] FU5 is mapped to VLcore2 - FU5_TL-connect-FU5_CL-connect-FU5_TL

[0551] FU2 is mapped to VLcore3 - FU2_TL-connect-FU2_CL-connect-FU2_TL

[0552] FU3 is mapped to VLcore4 - FU3_TL-connect-FU4_CL-connect-FU4_TL

[0553] FU4 is mapped to VLcore5 - FU4_TL-connected-FU1_CL-connected-FU1_TL

[0554] In the above mapping relationship, synchronization occurs at time T1, and after FU flush, go to step 2;

[0555] Step 2: Refresh the mapping relationship to obtain the following:

[0556] FU3 is mapped to VLcore1 - FU3_TL - Connect - FU3_CL - Connect - FU3_TL

[0557] FU5 is mapped to VLcore2 - FU5_TL-connected-FU4_CL-connected-FU4_TL

[0558] FU2 is mapped to VLcore3 - FU2_TL-connected-FU1_CL-connected-FU1_TL

[0559] FU4 is mapped to VLcore4 - FU4_TL-connect-FU5_CL-connect-FU5_TL

[0560] FU1 is mapped to VLcore5 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0561] In the above mapping relationship, synchronization occurs at time T2, and after FU flush, go to step 3;

[0562] Step 3: Refresh the mapping relationship to obtain the following:

[0563] FU3 is mapped to VLcore1 - FU3_TL - Connect - FU5_CL - Connect - FU5_TL

[0564] FU4 is mapped to VLcore2 - FU4_TL-connected-FU1_CL-connected-FU1_TL

[0565] FU1 is mapped to VLcore3 - FU1_TL-connect-FU4_CL-connect-FU4_TL

[0566] FU5 is mapped to VLcore4 - FU5_TL-connected-FU3_CL-connected-FU3_TL

[0567] FU2 is mapped to VLcore5 - FU2_TL-connect-FU2_CL-connect-FU2_TL

[0568] In the above mapping relationship, synchronization occurs at time T3, and after FU flush, go to step 4;

[0569] Step 4: Refresh the mapping relationship to obtain the following:

[0570] FU5 is mapped to VLcore1 - FU5_TL-connected-FU3_CL-connected-FU3_TL

[0571] FU1 is mapped to VLcore2 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0572] FU4 is mapped to VLcore3 - FU4_TL - connection - FU4_CL - connection - FU4_TL FU3 is mapped to VLcore4 - FU3_TL - connection - FU1_CL - connection - FU1_TL FU2 is mapped to VLcore5 - FU2_TL - connection - FU5_CL - connection - FU5_TL The above mapping relationship is synchronized at time T4. After FU flush, go to step 5; Step 5: refresh the mapping relationship to get the following:

[0573] FU3 is mapped to VLcore1 - FU3_TL - connection - FU1_CL - connection - FU1_TL FU2 is mapped to VLcore2 - FU2_TL - connection - FU4_CL - connection - FU4_TL FU4 is mapped to VLcore3 - FU4_TL - connection - FU3_CL - connection - FU3_TL FU1 is mapped to VLcore4 - FU1_TL - connection - FU4_CL - connection - FU4_TL FU5 is mapped to VLcore5 - FU5_TL - connection - FU5_CL - connection - FU5_TL For the above mapping relationship, synchronization occurs at time T5. After FUflush, go to step 6. Step 6: Refresh the mapping relationship to get the following:

[0574] FU1 is mapped to VLcore1 - FU1_TL - connection - FU3_CL - connection - FU3_TL FU4 is mapped to VLcore2 - FU4_TL - connection - FU5_CL - connection - FU5_TL FU3 is mapped to VLcore3 - FU3_TL - connection - FU1_CL - connection - FU1_TL FU4 is mapped to VLcore4 - FU4_TL - connection - FUn1_CL - connection - FUn1_TL FU5 is mapped to VLcore5 - FU5_TL - connection - FU4_CL - connection - FU4_TL The above mapping relationship is synchronized at time T6. After FUflush, go to step 7. Step 7: Refresh the mapping relationship to get the following:

[0575] FU3 is mapped to VLcore1 - FU3_TL - connection - FU3_CL - connection - FU3_TL FU5 is mapped to VLcore2 - FU5_TL - connection - FU1_CL - connection - FU1_TL FU1 is mapped to VLcore3 - FU1_TL - connection - FU4_CL - connection - FU4_TL FUn1 is mapped to VLcore4 - FUn1_TL - connection - FU5_CL - connection - FU5_TL FU4 is mapped to VLcore5 - FU4_TL - connection - FUn1_CL - connection - FUn1_TL The above mapping relationship is synchronized at time T7. After FU flush, go to step 8; Step 8: Refresh the mapping relationship to get the following:

[0576] FU3 is mapped to VLcore1 - FU3_TL - connected - FUn1_CL - connected - FUn1_TL FU1 is mapped to VLcore2 - FU1_TL - connected - FU2_CL - connected - FU2_TL FU4 is mapped to VLcore3 - FU4_TL - connected - FU4_CL - connected - FU4_TL FU5 is mapped to VLcore4 - FU5_TL - connected - FU3_CL - connected - FU3_TL FUn1 is mapped to VLcore5 - FUn1_TL - connected - FU5_CL - connected - FU5_TL The above mapping relationship is synchronized at time T8. After FU flush, go to step 9; Step 9: Refresh the mapping relationship to get the following:

[0577] FUn1 is mapped to VLcore1 - FUn1_TL - connection - FU5_CL - connection - FU5_TL FU2 is mapped to VLcore2 - FU2_TL - connection - FU4_CL - connection - FU4_TL FU4 is mapped to VLcore3 - FU4_TL - connection - FU3_CL - connection - FU3_TL FU3 is mapped to VLcore4 - FU3_TL - connection - FU1_CL - connection - FU1_TL FU5 is mapped to VLcore5 - FU5_TL - connection - FUn1_CL - connection - FUn1_TL For the above mapping relationship, synchronization occurs at time T9. After FUflush, go to step 10. Step 10: Refresh the mapping relationship to get the following:

[0578] FU5 is mapped to VLcore1 - FU5_TL - connection - FU3_CL - connection - FU3_TL FU4 is mapped to VLcore2 - FU4_TL - connection - FUn1_CL - connection - FUn1_TL FU3 is mapped to VLcore3 - FU3_TL - connection - FU1_CL - connection - FU1_TL FU1 is mapped to VLcore4 - FU1_TL - connection - FU2_CL - connection - FU2_TL FUn1 is mapped to VLcore5 - FUn1_TL - connection - FU5_CL - connection - FU5_TL The above mapping relationship is synchronized at time T10. After FU flush, go to step 11; Step 11: Refresh the mapping relationship to get the following:

[0579] FU3 is mapped to VLcore1 - FU3_TL - connection - FU1_CL - connection - FU1_TL FUn1 is mapped to VLcore2 - FUn1_TL - connection - FU5_CL - connection - FU5_TL FU1 is mapped to VLcore3 - FU1_TL - connection - FUn1_CL - connection - FUn1_TL FU2 is mapped to VLcore4 - FU2_TL - connection - FU3_CL - connection - FU3_TL FU5 is mapped to VLcore5 - FU5_TL - connection - FU4_CL - connection - FU4_TL For the above mapping relationships, synchronization occurs at time T11. After FU flush, go to step 12. Step 12: Refresh the mapping relationship to obtain the following:

[0580] FU1 is mapped to VLcore1 - FU1_TL - connection - FU2_CL - connection - FU2_TL FU5 is mapped to VLcore2 - FU5_TL - connection - FUn1_CL - connection - FUn1_TL FUn1 is mapped to VLcore3 - FUn1_TL - connection - FU1_CL - connection - FU1_TL FU3 is mapped to VLcore4 - FU3_TL - connection - FU3_CL - connection - FU3_TL FU4 is mapped to VLcore5 - FU4_TL - connection - FU4_CL - connection - FU4_TL The above mapping relationship is synchronized at time T12. After FU flush, go to step 13; Step 13: Refresh the mapping relationship to get the following:

[0581] FU2 is mapped to VLcore1 - FU2_TL - connected to FUn1_CL - connected to FUn1_TL FUn1 is mapped to VLcore2 - FUn1_TL - connected to FU1_CL - connected to FU1_TL FU1 is mapped to VLcore3 - FU1_TL - connected to FU4_CL - connected to FU4_TL FU3 is mapped to VLcore4 - FU3_TL - connected to FUn2_CL - connected to FUn2_TL FU4 is mapped to VLcore5 - FU4_TL - connected to FUn3_CL - connected to FUn3_TL The above mapping relationship is synchronized at time T13. After FU flush, go to step 14. Step 14: Refresh the mapping relationship to get the following:

[0582] FUn1 is mapped to VLcore1 - FUn1_TL - connected to FU1_CL - connected to FU1_TL FU1 is mapped to VLcore2 - FU1_TL - connected to FU2_CL - connected to FU2_TL FU4 is mapped to VLcore3 - FU4_TL - connected to FUn1_CL - connected to FUn1_TL FUn2 is mapped to VLcore4 - FUn2_TL - connected to FU4_CL - connected to FU4_TL FUn3 is mapped to VLcore5 - FUn3_TL - connected to FUn2_CL - connected to FUn2_TL For the above mapping relationship, synchronization occurs at time T14. After FU flush, go to step 15. Step 15: Refresh the mapping relationship to get the following:

[0583] FU1 is mapped to VLcore1 - FU1_TL - connection - FU3_CL - connection - FU3_TL FU2 is mapped to VLcore2 - FU2_TL - connection - FUn1_CL - connection - FUn1_TL FUn1 is mapped to VLcore3 - FUn1_TL - connection - FU4_CL - connection - FU4_TL FU4 is mapped to VLcore4 - FU4_TL - connection - FU5_CL - connection - FU5_TL FUn2 is mapped to VLcore5 - FUn2_TL - connection - FU1_CL - connection - FU1_TL The above mapping relationship is synchronized at time T15. After FU flush, go to step 16; Step 16: Refresh the mapping relationship to get the following:

[0584] FU3 is mapped to VLcore1 - FU3_TL - connection - FU3_CL - connection - FU3_TL FUn1 is mapped to VLcore2 - FUn1_TL - connection - FU4_CL - connection - FU4_TL FU4 is mapped to VLcore3 - FU4_TL - connection - FUn1_CL - connection - FUn1_TL FU5 is mapped to VLcore4 - FU5_TL - connection - FUn2_CL - connection - FUn2_TL FU1 is mapped to VLcore5 - FU1_TL - connection - FU2_CL - connection - FU2_TL The above mapping relationship is synchronized at time T16. After FU flush, go to step 17; Step 17: Refresh the mapping relationship to get the following:

[0585] FU3 is mapped to VLcore1 - FU3_TL - connection - FU5_CL - connection - FU5_TL FU4 is mapped to VLcore2 - FU4_TL - connection - FUn1_CL - connection - FUn1_TL FUn1 is mapped to VLcore3 - FUn1_TL - connection - FU3_CL - connection - FU3_TL FUn2 is mapped to VLcore4 - FUn2_TL - connection - FUn2_CL - connection - FUn2_TL FU2 is mapped to VLcore5 - FU2_TL - connection - FU2_CL - connection - FU2_TL The above mapping relationship is synchronized at T17. After FU flush, go to step 18. Step 18: Refresh the mapping relationship to get the following:

[0586] FU5 is mapped to VLcore1 -- FU5_TL -- Connected to FUn1_CL -- Connected to FUn1_TL FUn1 is mapped to VLcore2 -- FUn1_TL -- Connected to FU5_CL -- Connected to FU5_TL FU3 is mapped to VLcore3 -- ...

[0587] FUn2 is mapped to VLcore4 - FUn2_TL - connection - FU3_CL - connection - FU3_TL FU2 is mapped to VLcore5 - FU2_TL - connection - FU5_CL - connection - FU5_TL The above mapping relationship is synchronized at time T18. After FUflush, go to step 19; Step 19: Refresh the mapping relationship to get the following:

[0588] FUn1 is mapped to VLcore1 -- FUn1_TL -- Connect -- FU3_CL -- Connect -- FU3_TL FU5 is mapped to VLcore2 -- …

[0589] FU3 is mapped to VLcore4 - FU3_TL-connected-FU1_CL-connected-FU1_TL

[0590] FU5 is mapped to VLcore5 - FU5_TL-connect-FU5_CL-connect-FU5_TL

[0591] In the above mapping relationship, synchronization occurs at time T19, and after FU flush, go to step 20;

[0592] Step 20: Refresh the mapping relationship to obtain the following:

[0593] FU3 is mapped to VLcore1 - FU3_TL-connect-FU1_CL-connect-FU1_TL

[0594] FU1 is mapped to VLcore4 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0595] FU5 is mapped to VLcore5 - FU5_TL-connected-FU4_CL-connected-FU4_TL

[0596] In the above mapping relationship, synchronization occurs at time T20, and after FU flush, go to step 21;

[0597] Step 21: Refresh the mapping relationship to obtain the following:

[0598] FU1 is mapped to VLcore1 - FU1_TL-connect-FU2_CL-connect-FU2_TL

[0599] FU2 is mapped to VLcore4 - FU2_TL - Connect - FU3_CL - Connect - FU3_TL

[0600] FU4 is mapped to VLcore5 ---……

[0601] In the above mapping relationship, synchronization occurs at time T20, and after FU flush, go to step 22;

[0602] Step 21: Refresh the mapping relationship to obtain the following:

[0603] FU2 is mapped to VLcore1——……

[0604] FU3 is mapped to VLcore4 ---……

[0605] See also Fig.28 :Advanced dynamic mapping - GS variable length implementation block diagram.

[0606] According to the previous method, the focus is on " Fig. 9 :Main implementation methods of mapping, modeling, Fig.11 : Patent system block diagram" and " Fig. 22:From Behavior Modeling to Implementation Methods", analyzing " Figure 5 :Advanced dynamic mapping-GS indefinite length time domain analysis" gets the implementation block diagram;

[0607] After transformation, the diagram connection relationship is obtained, where:

[0608] 1- Combine with " Fig. 27 :Advanced Dynamic Mapping - GS Indefinite Length Workflow" analyzes the working status of the FU1_TL→FU2_CL connection relationship and defines this switch control signal as switch1 on;

[0609] exist" Fig. 27 In "Advanced Dynamic Mapping - GS Variable Length Workflow", switch1 on is turned on at the following times:

[0610] FU1 is mapped to VLcore5 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T2)

[0611] FU1 is mapped to VLcore2 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T4)

[0612] FU1 is mapped to VLcore2 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T8)

[0613] FU1 is mapped to VLcore4 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T10)

[0614] FU1 is mapped to VLcore1 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T12)

[0615] FU1 is mapped to VLcore2 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T14)

[0616] FU1 is mapped to VLcore5 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T16)

[0617] FU1 is mapped to VLcore4 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T20)

[0618] FU1 is mapped to VLcore1 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T21)

[0619] 2- Combine " Fig. 27:Advanced Dynamic Mapping - GS Indefinite Length Workflow" analyzes the working status of the FU2_CL→FU2_TL connection relationship and defines this switch control signal as switch2 on;

[0620] exist" Fig. 27 In "Advanced Dynamic Mapping - GS Variable Length Workflow", switch2 on is turned on when:

[0621] FU1 is mapped to VLcore5 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T2)

[0622] FU2 is mapped to VLcore5 - FU2_TL-connect-FU2_CL-connect-FU2_TL (T3)

[0623] FU1 is mapped to VLcore2 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T4)

[0624] FU1 is mapped to VLcore2 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T8)

[0625] FU1 is mapped to VLcore4 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T10)

[0626] FU1 is mapped to VLcore1 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T12)

[0627] FU1 is mapped to VLcore2 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T14)

[0628] FU1 is mapped to VLcore5 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T16)

[0629] FU2 is mapped to VLcore5 - FU2_TL - Connect - FU2_CL - Connect - FU2_TL (T17)

[0630] FU1 is mapped to VLcore4 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T20)

[0631] FU1 is mapped to VLcore1 - FU1_TL-connected-FU2_CL-connected-FU2_TL (T21)

[0632] In the figure, switch1 on and switch2 on are marked with dark boxes. Both switch2 on and switch1 on are controlled switches. Other paths can also be analyzed according to the above to obtain the switching timing of each path:

[0633] 3- Left-hand one-dimensional time-domain switch array (“ Fig. 22 : From Behavior Modeling to Implementation Methods”) controlled switches, for each path, specific analysis is required, according to “ Fig. 27 :Advanced dynamic mapping - GS indefinite length workflow" sorts out the switch timing state and writes it into the Channel timing controller state machine for control;

[0634] 4- One-dimensional time-domain switch array on the right (“ Fig. 22 : From Behavior Modeling to Implementation Methods”) controlled switches, for each path, specific analysis is required, according to “ Fig. 27 :Advanced dynamic mapping - GS indefinite length workflow" sorts out the switch timing state and writes it into the Channel timing controller state machine for control;

[0635] 5-Flush: Each GS(T) may refresh the mapping relationship between FU and VLcore. The one-dimensional time-domain switch array already contains all possible connection relationships involved in flush. Flush will affect the timing of the channel switch control of the one-dimensional time-domain switch array. For example, the steps listed in "1" are all to turn on switch1on, except that the other steps are to turn off switch1on and turn on other channels.

[0636] See also Fig.29 :An example of the application of polling dynamic mapping in a macro perspective.

[0637] The right side is an example of a common processor executing instructions, which has the following corresponding relationships:

[0638] FU1——IF——fetch instruction code unit;

[0639] FU5——DE——decode instruction code unit;

[0640] FU2——EX——Executive unit;

[0641] FU3——MR——Access storage unit;

[0642] FU4 - WB - Write back component;

[0643] As shown in the figure, the five VLcores on the right are executing instructions of their respective threads at the same time. In short: this is the basic effect of multi-threaded parallelism.

[0644] See also Fig.30 :An example of the application of polling dynamic mapping at a micro perspective.

[0645] From the perspective of register resources, for each VLcore (for example, VLcore1), we analyze how the registers work, and there is the following corresponding relationship:

[0646] FU1——CN——VLcore number register (VLcore1~VLcore5);

[0647] FU5——CD——instruction code register;

[0648] FU3——AC——addition result register;

[0649] The figure analyzes the situations in two FU flush modes:

[0650] Mode 1:

[0651] GS1: CN gets the opcode from the external storage area (Ex_memory) and flushes it to the current CNvalid;

[0652] GS2: CN is transferred. You can execute flush here to invalidate CN.

[0653] GS3: CN is transferred, flush can be executed here to invalidate CN;

[0654] GS4: CN is transferred, flush can be executed here to invalidate CN;

[0655] GS5: CN is transferred. Flush can be executed here to ensure that CN is invalid after GS5.

[0656] GS2: CD gets the instruction code from the external storage area (Ex_memory) and flushes it to the current CDvalid;

[0657] GS3: CD transfer, flush can be executed here to make CD invalid;

[0658] GS4: CD is passed, flush can be executed here to make the CD invalid;

[0659] GS5: CD transfer, you can execute flush here to make the CD invalid;

[0660] GS1: CD transfer, flush can be executed here, and CD is invalid after GS1.

[0661] GS4: AC gets the integer addition opcode from the external memory area (Ex_memory) and flushes it to the current ACvalid;

[0662] GS5: AC is transferred, and flush can be executed here to invalidate AC;

[0663] GS1: AC is transferred, and flush can be executed here to invalidate AC;

[0664] GS2: AC transfer, flush can be executed here to invalidate AC;

[0665] GS3: AC transfer, flush can be executed here to ensure that AC is invalid after GS3;

[0666] Mode 2:

[0667] GS1: CN gets the opcode from the external storage area (Ex_memory) and flushes it to the current CN; it implies that the old data is invalid and the new data is valid;

[0668] GS2: CNhold; no entity;

[0669] GS3: CN hold; no entity;

[0670] GS4: CN hold; no entity;

[0671] GS5: CN hold; no entity;

[0672] GS2: CD gets the instruction code from the external storage area (Ex_memory) and flushes it to the current CD; it implies that the old data is invalid and the new data is valid;

[0673] GS3: CD hold; no entity;

[0674] GS4: CD hold; no entity;

[0675] GS5: CD hold; no entity;

[0676] GS1: CD hold; no entity;

[0677] GS4: AC gets the integer addition operation code from the external storage area (Ex_memory) and flushes it to the current AC; it implies that the old data is invalid and the new data is valid;

[0678] GS5: AC hold; no entity;

[0679] GS1: AC hold; no entity;

[0680] GS2: AC hold; no entity;

[0681] GS3: AC hold; no entity;

[0682] The figure shows the situation analysis of VLcore1, and the same applies to VLcore2~VLcore5. Ultimately, through dynamic mapping through polling, the effect of 5 CN, CD, and AC registers is achieved!

[0683] The present invention also provides a system for implementing a hyperthreading architecture for multiple threads in parallel in a processor, including a memory and a processor, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the steps of the method described in any one of the embodiments of the present invention are implemented. The storage medium of this embodiment may be a storage medium provided in an electronic device, and the electronic device may read the content of the storage medium and implement the effects of the present invention. The storage medium may also be a separate storage medium, and the storage medium is connected to an electronic device, so that the electronic device may read the content in the storage medium and implement the steps of the method of the present invention. The system of the present invention has only one set of hardware of a logic core and an operator, which saves resources; by dividing the FU functional unit and dynamically mapping, a multi-core logic core and an operator are virtualized to achieve the effect of synchronous multithreading; the system complexity is reduced to ensure feasibility.

[0684] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A system for implementing a hyperthreading architecture for multiple threads in parallel in a processor, characterized in that: include: FU operation domain, GS status domain, physical channel switch array, the FU operation domain describes the FU mapping state, the FU includes a time sequence layer part FU_TL and a current synthesis layer part FU_CL; the GS status domain is converted from the VLcore operation domain, the GS status domain can be converted from the VLcore operation domain back to the FU operation domain, the VLcore operation domain conversion is an analysis of the current use state of the FU functional unit with VLcore as the medium, the VLcore includes a virtual logic core input VLcore_in and a virtual logic core output VLcore_out, the time sequence layer part FU_TL is converted to the virtual logic core input VLcore_in through the physical channel switch array, the virtual logic core input VLcore_in is converted to the current synthesis layer part FU_CL through the physical channel switch array, the current synthesis layer part FU_CL is converted to the virtual logic core output VLcore_out through the physical channel switch array, and the virtual logic core output VLcore_out is converted to the current synthesis layer part FU_CL at the next moment through the physical channel switch array; FU is a functional unit, FU operation domain is a functional unit operation domain, and VLcore is a virtual logic core; A physical logical core is discretized into multiple logical core FU functional units. The logical core FU functional units are divided according to system requirements. The logical core includes multiple logical core FU functional units. The multiple logical core FU functional units are respectively mapped to multiple virtual logical cores. The FU operation domain analyzes the mapping status of multiple FU functional units, and the VLcore operation domain conversion analyzes the current usage status of multiple virtual logical cores for FU functional units.

2. The system for implementing a hyperthreading architecture for multiple threads in parallel in a processor according to claim 1, characterized in that: The physical channel switch array includes an input mapping multiplexer, a modulation and demodulation matrix, a decimation matrix and an output mapping multiplexer; The time series layer part FU_TL is converted to the virtual logic core input VLcore_in through the input mapping multiplexer, the virtual logic core input VLcore_in is converted to the current synthesis layer part FU_CL through the modulation and demodulation matrix, the current synthesis layer part FU_CL is converted to the virtual logic core output VLcore_out through the extraction matrix, and the virtual logic core output VLcore_out is converted to the current synthesis layer part FU_CL at the next moment through the output mapping multiplexer.

3. The system for implementing a hyperthreading architecture for multiple threads in parallel in a processor according to claim 1, characterized in that: It also includes a one-dimensional time domain switch array, which controls the connection relationship between the FU and the VLcore, and the one-dimensional time domain switch array refreshes the connection relationship between the FU and the VLcore at every moment.

4. The system for implementing a hyperthreading architecture for multiple threads in parallel in a processor according to claim 3, characterized in that: The state of the one-dimensional time domain switch array includes normally open or not normally open.

5. The system for implementing a hyperthreading architecture for multiple threads in parallel in a processor according to claim 2, characterized in that: It includes a switch control signal 1 and a switch control signal 2, wherein the switch control signal 1 is used to control the time series layer part FU_TL to flow to the current synthesis layer part FU_CL, and the switch control signal 2 is used to control the current synthesis layer part FU_CL to flow to the time series layer part FU_TL at the next moment.

6. The system for implementing a hyperthreading architecture for multiple threads in parallel in a processor according to claim 1, characterized in that: The logic core FU functional unit includes an instruction code fetching unit, an instruction code decoding unit, an execution unit, a storage access unit and a write-back unit.

7. A system for implementing a hyperthreading architecture for multiple threads in parallel in a processor according to claim 1 or 6, characterized in that: The physical logic core is replaced by a physical operator, the virtual logic core is replaced by a virtual operator, and the logic core FU functional unit is replaced by an operator FU functional unit.

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