Mass production test method, device, equipment and storage medium for FPGA interconnection resources

Abstract

The present invention relates to the field of FPGA technology, and discloses a mass production test method, device, equipment and storage medium for FPGA interconnection resources. The method includes: obtaining the multiple line type of global interconnection resources and the line type of local interconnection resources in the FPGA chip to be tested, and establishing a full coverage connection between global interconnection resources and local interconnection resources based on the multiple line type of global interconnection resources and the line type of local interconnection resources within the unit block to obtain the unit interconnection result, and extending the unit interconnection result within the unit block to the whole chip to obtain the interconnection result of the FPGA chip to be tested, and performing mass production test on the FPGA chip to be tested based on the interconnection result to obtain the faulty unit block. The present invention simultaneously considers the connection relationship between the global line type and the local line type, introduces a trigger, and realizes fault analysis and fault location with the block as the granularity, so as to reduce the number of configurations of mass production tests, improve test efficiency and improve the accuracy of fault location.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a mass production test method, device, equipment and storage medium for FPGA interconnection resources. Background Art

[0002] As a programmable hardware platform, field programmable gate array (FPGA) is versatile, flexible, reconfigurable and parallel computing, and is widely used in many important fields such as national defense, medical treatment, computing acceleration and communication signal processing. Its unique feature is that it can reconfigure hardware logic circuits through programming to adapt them to different application scenarios and realize specific digital logic functions.

[0003] After the FPGA chip leaves the factory, it must undergo CP mass production testing and FT mass production testing. CP (Circuit Probe) is a wafer-level test of the chip before packaging. FT (Final Test) is a test after packaging is completed, and it is also the test that is closest to actual usage. Whether it is CP mass production testing or FT mass production testing, detailed fault coverage testing of the most critical interconnect resources of the FPGA is required. The length of time for these mass production tests is often an important factor affecting chip costs. During the execution of FPGA mass production testing, the most time is spent on bitstream loading time. Therefore, the most important consideration for mass production design is to test the bitstream configuration as few times as possible to cover as many faults as possible.

[0004] The traditional FPGA interconnection coverage method directly uses an algorithm to test the global interconnection resources of the entire chip. This method takes a long time to run the algorithm and is not convenient for positioning. Alternatively, the global interconnection resource coverage and local interconnection resource coverage are tested separately, which will result in too many mass production test configuration times and low test efficiency. Summary of the invention

[0005] In view of this, the present invention provides a mass production test method, device, equipment and storage medium for FPGA interconnection resources. By simultaneously considering the connection relationship between global linear types and local linear types and introducing triggers, a connection between interconnection resources and logic resources is established, and fault analysis and fault location with block-based granularity are realized to solve the problems of excessive number of configuration times, low test efficiency and inaccurate fault location in traditional mass production tests.

[0006] In a first aspect, the present invention provides a mass production test method for FPGA interconnection resources, the method comprising:

[0007] Obtain the multiple line type of the global interconnection resource and the line type of the local interconnection resource in the FPGA chip to be detected;

[0008] Within the unit block, based on the multiple line type of the global interconnection resource and the line type of the local interconnection resource, a full coverage connection between the global interconnection resource and the local interconnection resource is established to obtain a unit interconnection result. The unit block includes a switch matrix and a programmable logic function block, and the programmable logic function block includes a trigger;

[0009] The unit interconnection results within the unit block are expanded to the whole chip to obtain the interconnection results of the FPGA chip to be tested;

[0010] Based on the interconnection results, the FPGA chip to be tested is mass-produced and tested to obtain the fault unit block.

[0011] The mass production test method of FPGA interconnection resources provided by the embodiment of the present invention simultaneously establishes the connection relationship between global interconnection resources and local interconnection resources in a unit block, introduces triggers, establishes the connection between interconnection resources and logic resources, and realizes fault analysis and fault location with block as the unit granularity, so as to solve the problems of excessive number of configuration times, low test efficiency and inaccurate fault location in traditional mass production test.

[0012] In an optional implementation, within a unit block, based on the multiple line type of the global interconnection resource and the line type of the local interconnection resource, a full coverage connection between the global interconnection resource and the local interconnection resource is established to obtain a unit interconnection result, including:

[0013] Establish the connection relationship of global interconnected resources within the unit block;

[0014] On the basis of the connection relationship of the global interconnection resources, the connection relationship of the local interconnection resources is supplemented.

[0015] The mass production test method of FPGA interconnection resources provided by the embodiment of the present invention establishes connection relationships between global interconnection resources and local interconnection resources in unit blocks, thereby achieving full coverage connection of interconnection resources at the unit block granularity.

[0016] In an optional implementation, establishing a connection relationship of global interconnected resources within a unit block includes:

[0017] Establish connection relationships between multiple lines of the same type of global interconnection resources;

[0018] Establish the connection relationship between different types of multiplexers of global interconnection resources.

[0019] The mass production test method of FPGA interconnection resources provided by the embodiment of the present invention simultaneously establishes the connection relationship between the same type of global interconnection resources and different types of global interconnection resource multiplexers, thereby achieving full coverage of global resources at the unit block granularity.

[0020] In an optional implementation, based on the connection relationship of the global interconnection resources, the connection relationship of the local interconnection resources is supplemented, including:

[0021] Connect the doubled line of the global interconnection resource to the input type line in the local interconnection resource, and then connect it to the input end of the trigger in the programmable logic function block in the unit block;

[0022] The output end of the trigger in the programmable logic function block in the unit block is connected to the output type line in the local interconnection resource, and then connected to the double line of the global interconnection resource.

[0023] The mass production test method of FPGA interconnection resources provided by the embodiment of the present invention connects triggers through local interconnection resources, so that the connection status of global interconnection resources and local interconnection resources in the FPGA chip to be tested can be reflected by observing the number of trigger beats.

[0024] In an optional implementation, the unit interconnection result in the unit block is extended to the whole chip to obtain the interconnection result of the FPGA chip to be tested, including:

[0025] The unit interconnection result in the unit block is copied to the remaining preset number of unit blocks in the FPGA chip to be detected.

[0026] The mass production test method of FPGA interconnection resources provided by the embodiment of the present invention analyzes the connection relationship of a single block, designs the coverage connection of interconnection resources of different line types, and then expands to the entire chip by copying it to the remaining blocks, thereby completing the connection coverage of the interconnection resources of the entire chip.

[0027] In an optional implementation, a mass production test is performed on the FPGA chip to be tested based on the interconnection result to obtain a faulty unit block, including:

[0028] Injecting an excitation signal into the input pin of the FPGA chip to be tested, and recording the output value of the output pin of the FPGA chip to be tested, where the output value of the output pin includes the output result corresponding to the unit block;

[0029] Compare the output value of the output pin with the preset output value, which is obtained based on the stimulus signal injected into the input pin;

[0030] If the output value of the output pin does not match the preset output value, the faulty unit block of the FPGA chip to be detected is determined based on the output value.

[0031] The mass production test method of FPGA interconnection resources provided in an embodiment of the present invention injects an excitation signal into the input pin, observes the output value of the output pin after being transmitted through the interconnection resource, and compares the output value with the expected output value, and performs mass production testing and fault location at the unit block granularity based on the number of abnormal bits that do not meet expectations.

[0032] In an optional implementation, injecting an excitation signal into an input pin of the FPGA chip to be detected and recording an output value of an output pin of the FPGA chip to be detected includes:

[0033] Get the number of pins of the FPGA chip to be tested;

[0034] Set a preset number of pins as input pins and the remaining pins as output pins;

[0035] Injecting excitation signals into a preset number of input pins respectively, the excitation signals being represented by a binary code stream of preset bits;

[0036] Record the output value of the output pin, the output value is determined by the trigger.

[0037] The mass production test method of FPGA interconnection resources provided by the embodiment of the present invention injects an excitation signal into a part of the pins on the chip to be tested as input pins. The excitation signal is a binary code stream composed of 0 or 1 converted from the level signal. The fault position is determined according to the output value of the output pin. The output value is also a binary code stream of preset bits. The specific value is determined by the trigger in each block, so as to realize the interconnection resource fault location in units of blocks.

[0038] In an optional implementation, if the output value of the output pin does not match the preset output value, the faulty unit block of the FPGA chip to be detected is determined based on the output value, including:

[0039] The first digit in the output value that does not match the preset output value is determined as the abnormal digit;

[0040] The unit block where the trigger corresponding to the abnormal bit number is located is determined as the faulty unit block.

[0041] In a second aspect, the present invention provides a mass production test device for FPGA interconnection resources, the device comprising:

[0042] An acquisition module is used to acquire the multiple line type of the global interconnection resource and the line type of the local interconnection resource in the FPGA chip to be detected;

[0043] A connection module is used to establish a full coverage connection between global interconnection resources and local interconnection resources within a unit block based on the multiple line type of the global interconnection resources and the line type of the local interconnection resources to obtain a unit interconnection result. The unit block includes a switch matrix and a programmable logic function block, and the programmable logic function block includes a trigger;

[0044] An expansion module is used to expand the unit interconnection results within the unit block to the whole chip to obtain the interconnection results of the FPGA chip to be tested;

[0045] The test module is used to perform mass production test on the FPGA chip to be tested based on the interconnection results to obtain the fault unit block.

[0046] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute the mass production test method of FPGA interconnection resources of the above-mentioned first aspect or any corresponding embodiment thereof.

[0047] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the mass production test method for FPGA interconnection resources of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 is a flow chart of a mass production test method for FPGA interconnection resources according to an embodiment of the present invention;

[0050] Figure 2 It is a flow chart of a mass production test method of FPGA interconnection resources according to an embodiment of the present invention;

[0051] Figure 3 is another flow chart of a mass production test method for FPGA interconnection resources according to an embodiment of the present invention;

[0052] Figure 4 is a structural block diagram of a mass production test device for FPGA interconnection resources according to an embodiment of the present invention;

[0053] Figure 5It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0055] As a programmable hardware platform, field programmable gate array (FPGA) has the characteristics of general flexibility, reconfiguration and parallel computing. It is widely used in many important fields such as national defense, medical treatment, computing acceleration and communication signal processing. After the FPGA chip leaves the factory, it must undergo CP mass production test and FT mass production test. CP (Circuit Probe) is a wafer-level test of the chip before packaging. FT (Final Test) is the test after the packaging is completed, and it is also the test closest to the actual use. Whether it is CP mass production test or FT mass production test, it is necessary to conduct detailed fault coverage test on the most critical interconnection resources of FPGA. The length of time for these mass production tests is often an important factor affecting chip cost. During the execution of FPGA mass production test, the most time is the bitstream loading time. Therefore, the most important consideration for mass production design is to test the bitstream configuration as few times as possible to cover as many faults as possible.

[0056] The traditional FPGA interconnection coverage method directly uses an algorithm to test the global interconnection resources of the entire chip. This method takes a long time to run the algorithm and is not convenient for positioning. Alternatively, the global interconnection resource coverage and local interconnection resource coverage are tested separately, which will result in too many mass production test configuration times and low test efficiency.

[0057] The present invention provides a mass production test method, device, equipment and storage medium for FPGA interconnection resources. By simultaneously considering the connection relationship between global linear types and local linear types and introducing triggers, the connection between interconnection resources and logic resources is established, and fault analysis and fault location with block-based granularity are realized to solve the problems of excessive number of configuration times, low test efficiency and inaccurate fault location in traditional mass production tests.

[0058] According to an embodiment of the present invention, an embodiment of a mass production test method for FPGA interconnection resources is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0059] In this embodiment, a mass production test method for FPGA interconnection resources is provided. Figure 1 As shown, Figure 1 is a flow chart of a mass production test method for FPGA interconnection resources according to an embodiment of the present invention, such as Figure 1 As shown, the process includes the following steps:

[0060] Step S101, obtaining the line type of the global interconnection resources and the line type of the local interconnection resources in the FPGA chip to be detected.

[0061] Specifically, the multiplier types of global interconnection resources include single-fold lines, double-fold lines, triple-fold lines, and other types of global interconnection lines.

[0062] Furthermore, the local interconnect resource connection types include input type and output type.

[0063] Step S102 : within the unit block, based on the multiple line type of the global interconnection resource and the line type of the local interconnection resource, a full coverage connection between the global interconnection resource and the local interconnection resource is established to obtain a unit interconnection result.

[0064] Specifically, the unit block includes a switch matrix and a programmable logic function block.

[0065] Furthermore, the global interconnection resources and the local interconnection resources realize the connection between the switch matrix and the programmable logic function block and the covering connection of each interconnection switch within the unit block.

[0066] Step S103, expanding the unit interconnection result in the unit block to the whole chip to obtain the interconnection result of the FPGA chip to be tested.

[0067] Specifically, the interconnection result includes the connection relationship between the global interconnection resources and the local interconnection resources of each unit block within the entire chip.

[0068] Step S104, performing mass production testing on the FPGA chip to be tested based on the interconnection result to obtain a faulty unit block.

[0069] Specifically, mass production tests are performed on the interconnection results, and the obtained test results can realize fault location with unit blocks as the granularity.

[0070] The mass production test method of FPGA interconnection resources provided in this embodiment obtains global and local interconnection resources on the FPGA to be tested, first establishes the connection relationship between the global interconnection resources and the local interconnection resources in the unit block, and then expands it to the whole chip on this basis to achieve full coverage connection of interconnection resources in the whole chip range. By introducing triggers, the connection status of the interconnection resources is characterized based on the number of trigger beats, and fault analysis and fault location with the block as the unit granularity are realized, thereby reducing the number of configuration times of mass production tests and improving detection efficiency.

[0071] In some optional implementations, step S102 includes:

[0072] Establish the connection relationship of global interconnected resources within the unit block;

[0073] On the basis of the connection relationship of the global interconnection resources, the connection relationship of the local interconnection resources is supplemented.

[0074] like Figure 2 As shown, it is assumed that the FPGA chip to be tested has three types of global interconnection resource lines, namely: L1, L2, and L3, and two types of local interconnection resource lines, namely input and output types. Some common algorithms, such as greedy algorithms or SMT algorithms, are used to establish coverage connections for each interconnection resource in the unit block according to the types of global interconnection resource lines and local interconnection resource lines.

[0075] In some optional implementations, establishing a connection relationship of global interconnected resources within a unit block includes:

[0076] Establish connection relationships between multiple lines of the same type of global interconnection resources;

[0077] Establish the connection relationship between different types of multiplexers of global interconnection resources.

[0078] like Figure 2 As shown, the multiple lines of the global interconnection resource also include a number of lines. The multiple lines of the same type of global interconnection resource multiple lines can be directly interconnected or interconnected after passing through a first-level multiplexer, such as L1->L1 in the figure. The lines of different types of multiple lines can also be directly interconnected or interconnected after passing through a first-level multiplexer, such as L1->L2, L2->L3 in the figure.

[0079] In some optional implementations, based on the connection relationship of the global interconnection resources, the connection relationship of the local interconnection resources is supplemented, including:

[0080] Connect the doubled line of the global interconnection resource to the input type line in the local interconnection resource, and then connect it to the input end of the trigger in the programmable logic function block in the unit block;

[0081] The output end of the trigger in the programmable logic function block in the unit block is connected to the output type line in the local interconnection resource, and then connected to the double line of the global interconnection resource.

[0082] like Figure 2 As shown, it is assumed that the FPGA chip to be tested has three types of global interconnection resource lines, namely: L1, L2, and L3, and two types of local interconnection resource lines, namely: Local In and Local Out. Within the unit block, the global interconnection resource line can be connected to the D signal end of the D flip-flop in the programmable logic function block through Local In, such as L3->Local In->DFF:D in the figure. In addition, the Q signal of the D flip-flop can be connected to the global interconnection resource line through Local Out, such as DFF:Q->Local Out->L1 in the figure. Some common algorithms, such as greedy algorithms or SMT algorithms, are used to design the connection relationship between global interconnection resources and local interconnection resources using multiple bit streams, so as to achieve full coverage of each connection relationship, namely, line->line, line->Local In, and Local Out->line.

[0083] In some optional implementations, step S103 includes:

[0084] The unit interconnection result in the unit block is copied to the remaining preset number of unit blocks in the FPGA chip to be detected.

[0085] like Figure 2 As shown, by analyzing the connection relationship of a single block, the unit interconnection result is obtained, and the unit interconnection result is copied to the remaining blocks of the chip to be tested. For example, the interconnection method on unit block 1 in the figure is copied and extended to unit block 2 and the remaining number of unit blocks to complete the connection coverage of the interconnection resources of the entire chip.

[0086] In some optional implementations, step S104 includes:

[0087] Injecting an excitation signal into the input pin of the FPGA chip to be tested, and recording the output value of the output pin of the FPGA chip to be tested, where the output value of the output pin includes the output result corresponding to the unit block;

[0088] Compare the output value of the output pin with the preset output value, which is obtained based on the stimulus signal injected into the input pin;

[0089] If the output value of the output pin does not match the preset output value, the faulty unit block of the FPGA chip to be detected is determined based on the output value.

[0090] like Figure 3As shown, a preset excitation signal is input to the input pin, such as "110011001100" in the figure. According to the input excitation signal, if all interconnected resources are normal, the preset output value should also be "110011001100". If they match, it indicates that there is no fault in the interconnected resources of the FPGA to be tested. Otherwise, it indicates that there is a faulty unit block. The faulty unit block is located based on the output value.

[0091] In some optional implementations, injecting an excitation signal into an input pin of the FPGA chip to be detected and recording an output value of an output pin of the FPGA chip to be detected includes:

[0092] Get the number of pins of the FPGA chip to be tested;

[0093] Set a preset number of pins as input pins and the remaining pins as output pins;

[0094] Injecting excitation signals into a preset number of input pins respectively, the excitation signals being represented by a binary code stream of preset bits;

[0095] Record the output value of the output pin, the output value is determined by the trigger.

[0096] like Figure 3 As shown, each input pin is connected to the multiplexer of each global interconnection resource, and a binary code stream of a preset number of bits is input to each input pin, such as "110011001100" in the figure. According to the input excitation signal, if each interconnection resource is normal, the preset output value should also be "110011001100". Each digit in the output value is determined by the trigger in each unit block. If the output value of the output pin is the same as the preset output value, it indicates that there is no fault in the interconnection resources of the FPGA to be tested, otherwise it indicates that there is a faulty unit block, and the faulty unit block is located based on the output value.

[0097] In some optional implementations, if the output value of the output pin does not match the preset output value, the faulty unit block of the FPGA chip to be detected is determined based on the output value, including:

[0098] The first digit in the output value that does not match the preset output value is determined as the abnormal digit;

[0099] The unit block where the trigger corresponding to the abnormal bit number is located is determined as the faulty unit block.

[0100] like Figure 3As shown, assuming that the excitation signal injected into the input pin based on the interconnection result is "110011001100", if the connection relationship of each interconnection resource is normal, the expected output result should also be "110011001100", however, if the output value is "110011100011", which is different from the expected output value, then the number of digits with the wrong first value is determined, that is, the seventh digit on the figure. The unit block corresponding to the seventh digit is the seventh-to-last block, which indicates that the unit block is faulty, resulting in errors in the values ​​of subsequent digits. The unit block corresponding to the seventh digit is a faulty unit block. If the first three digits of the output result are 110 and the following are all 1, then the fourth digit is an abnormal digit, indicating that there may be an open circuit fault in the unit block corresponding to the abnormal digit.

[0101] In this embodiment, a mass production test device for FPGA interconnection resources is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0102] This embodiment provides a mass production test device for FPGA interconnection resources, such as Figure 4 As shown, including:

[0103] The acquisition module 501 is used to acquire the line type of the global interconnection resources and the line type of the local interconnection resources in the FPGA chip to be detected.

[0104] The connection module 502 is used to establish a full coverage connection between global interconnection resources and local interconnection resources within the unit block based on the multiple line type of the global interconnection resources and the line type of the local interconnection resources to obtain a unit interconnection result. The unit block includes a switch matrix and a programmable logic function block, and the programmable logic function block includes a trigger.

[0105] The expansion module 503 is used to expand the unit interconnection results within the unit block to the whole chip to obtain the interconnection results of the FPGA chip to be tested.

[0106] The testing module 504 is used to perform mass production testing on the FPGA chip to be tested based on the interconnection results to obtain the faulty unit block.

[0107] In some optional implementations, the connection module 502 includes:

[0108] A submodule is established to establish the connection relationship of the global interconnected resources within the unit block.

[0109] The supplementary submodule is used to supplement the connection relationship of the local interconnection resources based on the connection relationship of the global interconnection resources.

[0110] In some optional implementations, establishing a submodule includes:

[0111] The same type of unit is used to establish the connection relationship between the same type of multiple lines of the global interconnection resource.

[0112] Different types of units are used to establish connection relationships between different types of multiplexers of global interconnection resources.

[0113] In some optional embodiments, the supplementary submodule includes:

[0114] The input unit connects the doubled line of the global interconnection resource to the input type line in the local interconnection resource, and then connects it to the input end of the trigger in the programmable logic function block in the unit block.

[0115] The output unit is used to connect the output end of the trigger in the programmable logic function block in the unit block to the output type line in the local interconnection resource, and then to the double line of the global interconnection resource.

[0116] In some optional implementations, the expansion module 503 includes:

[0117] The copy submodule is used to copy the unit interconnection result in the unit block to the remaining preset number of unit blocks in the FPGA chip to be detected.

[0118] In some optional implementations, the testing module 504 includes:

[0119] The injection submodule is used to inject an excitation signal into the input pin of the FPGA chip to be detected, and record the output value of the output pin of the FPGA chip to be detected, where the output value of the output pin includes the output result corresponding to the unit block.

[0120] The comparison submodule is used to compare the output value of the output pin with a preset output value, where the preset output value is obtained based on the stimulus signal injected into the input pin.

[0121] The determination submodule is used to determine the faulty unit block of the FPGA chip to be detected based on the output value when the output value of the output pin does not match the preset output value.

[0122] In some optional embodiments, the injection submodule includes:

[0123] Get the pin unit, which is used to obtain the number of pins of the FPGA chip to be detected.

[0124] The selection unit is used to select a preset number of pins as input pins and the remaining pins as output pins.

[0125] The signal injection unit is used to inject excitation signals into a preset number of input pins respectively, and the excitation signals are represented by a binary code stream with a preset number of bits.

[0126] The recording unit is used to record the output value of the output pin. The output value is determined by the trigger.

[0127] In some optional implementations, the determining submodule includes:

[0128] The abnormal digit determination unit is used to determine the first digit in the output value that does not match the preset output value as the abnormal digit.

[0129] The faulty unit block unit is determined to determine the unit block where the trigger corresponding to the abnormal bit number is located as the faulty unit block.

[0130] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0131] The mass production test device of the FPGA interconnection resources in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0132] The embodiment of the present invention also provides a computer device having the above Figure 4 The mass production test setup of the FPGA interconnect resources is shown.

[0133] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0134] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0135] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0136] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0137] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0138] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0139] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0140] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0141] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A mass production test method for FPGA interconnection resources, characterized in that: The method comprises: Obtain the multiple line type of the global interconnection resource and the line type of the local interconnection resource in the FPGA chip to be detected; Within a unit block, based on the multiple line type of the global interconnection resource and the line type of the local interconnection resource, a full coverage connection between the global interconnection resource and the local interconnection resource is established to obtain a unit interconnection result, wherein the unit block includes a switch matrix and a programmable logic function block, and the programmable logic function block includes a trigger; Expanding the unit interconnection result in the unit block to the whole chip to obtain the interconnection result of the FPGA chip to be tested; Based on the interconnection result, a mass production test is performed on the FPGA chip to be tested to obtain a fault unit block; The step of extending the unit interconnection result in the unit block to the entire chip to obtain the interconnection result of the FPGA chip to be tested includes: Copying the unit interconnection result in the unit block to the remaining preset number of unit blocks in the FPGA chip to be detected; The method of performing mass production testing on the FPGA chip to be tested based on the interconnection result to obtain a faulty unit block includes: Injecting an excitation signal into the input pin of the FPGA chip to be detected, and recording the output value of the output pin of the FPGA chip to be detected, wherein the output value of the output pin includes the output result corresponding to the unit block; Comparing the output value of the output pin with a preset output value, wherein the preset output value is obtained based on the excitation signal injected into the input pin; If the output value of the output pin does not match the preset output value, the faulty unit block of the FPGA chip to be detected is determined based on the output value.

2. The method according to claim 1, characterized in that The step of establishing a full coverage connection between global interconnection resources and local interconnection resources based on the multiple line type of the global interconnection resources and the line type of the local interconnection resources within the unit block to obtain a unit interconnection result includes: Establishing a connection relationship between global interconnected resources within the unit block; On the basis of the connection relationship of the global interconnection resources, the connection relationship of the local interconnection resources is supplemented.

3. The method according to claim 2, characterized in that The establishing of the connection relationship of the global interconnected resources within the unit block includes: Establishing a connection relationship between multiple lines of the same type of the global interconnection resource; Establishing connection relationships between different types of multiplexers of the global interconnection resource.

4. The method according to claim 2, characterized in that: The method of supplementing the connection relationship of the local interconnection resources on the basis of the connection relationship of the global interconnection resources includes: Connecting the doubled line of the global interconnection resource to the input type line in the local interconnection resource, and then connecting it to the input end of the trigger in the programmable logic function block in the unit block; The output end of the trigger in the programmable logic function block in the unit block is connected to the output type line in the local interconnection resource, and then connected to the doubled line of the global interconnection resource.

5. The method according to claim 1, characterized in that The step of injecting an excitation signal into an input pin of the FPGA chip to be detected and recording an output value of an output pin of the FPGA chip to be detected comprises: Obtain the number of pins of the FPGA chip to be detected; Using a preset number of the pins as input pins and the remaining pins as output pins; Injecting an excitation signal into each of the preset number of input pins, wherein the excitation signal is represented by a binary code stream of preset bits; The output value of the output pin is recorded, and the output value is determined by the trigger.

6. The method according to claim 1, characterized in that If the output value of the output pin does not match the preset output value, determining the faulty unit block of the FPGA chip to be detected based on the output value includes: Determine the first digit in the output value that does not match the preset output value as an abnormal digit; The unit block where the trigger corresponding to the abnormal bit number is located is determined as a faulty unit block.

7. A mass production test device for FPGA interconnection resources, characterized in that: The device comprises: An acquisition module is used to acquire the multiple line type of the global interconnection resource and the line type of the local interconnection resource in the FPGA chip to be detected; A connection module is used to establish a full coverage connection between global interconnection resources and local interconnection resources within a unit block based on the multiple line type of the global interconnection resources and the line type of the local interconnection resources to obtain a unit interconnection result, wherein the unit block includes a switch matrix and a programmable logic function block, and the programmable logic function block includes a trigger; An expansion module, used to expand the unit interconnection result in the unit block to the whole chip to obtain the interconnection result of the FPGA chip to be tested; A testing module, used for performing a mass production test on the FPGA chip to be tested based on the interconnection result to obtain a faulty unit block; The expansion module is used to copy the unit interconnection result in the unit block to the remaining preset number of unit blocks in the FPGA chip to be detected; The test module is used to copy the unit interconnection result in the unit block to the remaining preset number of unit blocks in the FPGA chip to be tested; the mass production test of the FPGA chip to be tested based on the interconnection result to obtain the faulty unit block includes: injecting an excitation signal into the input pin of the FPGA chip to be tested, recording the output value of the output pin of the FPGA chip to be tested, the output value of the output pin includes the output result corresponding to the unit block; comparing the output value of the output pin with a preset output value, the preset output value is obtained based on the injection of the excitation signal into the input pin; if the output value of the output pin does not match the preset output value, then determining the faulty unit block of the FPGA chip to be tested based on the output value.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 6.

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