Processing device, instruction processing method and electronic equipment

Abstract

The present application discloses a processing device, an instruction processing method, and an electronic device, belonging to the field of electronic technology. The processing device includes a processing unit and a multi-stage pipeline. The processing unit is responsible for executing instructions in the multi-stage pipeline. The first stage of the pipeline in the multi-stage pipeline is used to obtain a first instruction and, upon obtaining a first operand of the first instruction, transmit the first instruction and the first operand to the processing unit. The first stage of the pipeline is any stage of the pipeline in the multi-stage pipeline. The processing unit is used to receive the first instruction and the first operand, process the first instruction and the first operand, and obtain a first processing result. One processing unit is responsible for executing instructions in the multi-stage pipeline, thereby improving the reuse rate of the processing unit and the efficiency of the processing device in processing instructions.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a processing device, an instruction processing method, and an electronic device. Background Art

[0002] In the field of computer technology, processing devices are an important component of computers. Processing devices with different architectures use different instruction processing methods to process instructions and obtain processing results, which are used to support the computer's various functions. Summary of the Invention

[0003] The embodiments of the present application provide a processing device, an instruction processing method, and an electronic device that can improve instruction processing efficiency. The technical solution is as follows:

[0004] On the one hand, an embodiment of the present application provides a processing device, which includes a processing unit and multiple stages; pipeline, the processing unit is responsible for the instruction execution of the multi-stage pipeline; the first stage of the pipeline in the multi-stage pipeline is used to obtain a first instruction, and when the first operand of the first instruction is obtained, the first instruction and the first operand are transmitted to the processing unit, and the first stage of the pipeline is any stage of the pipeline in the multi-stage pipeline; the processing unit is used to receive the first instruction and the first operand, process the first instruction and the first operand, and obtain a first processing result.

[0005] In one possible implementation, the first-stage pipeline is also used to send a first grab request to the processing unit and obtain a grab result for the processing unit when the first-stage pipeline obtains the first operand, and the grab result is used to indicate whether the processing unit can process the first instruction and the first operand; the first-stage pipeline is used to transmit the first instruction and the first operand to the processing unit when the grab result is a successful grab.

[0006] In one possible implementation, the processing unit is also used to determine the contention result based on the first contention request, the second contention request, and the priority of the first-level pipeline and the second-level pipeline in the multi-level pipeline, and transmit the contention result to the first-level pipeline. The second contention request is transmitted to the processing unit by the second-level pipeline when the second operand is obtained.

[0007] In a possible implementation, the priorities of the first-stage pipeline and the second-stage pipeline are determined based on the order in which the first-stage pipeline and the second-stage pipeline fetch instructions.

[0008] In one possible implementation, the processing device also includes a result module, which is connected to the processing unit and is responsible for storing and transmitting the processing results of the instructions of the multi-stage pipeline; the result module is used to receive the second processing result transmitted by the processing unit, and when the second processing result includes the first operand, transmit the first operand to the first stage of the pipeline, and the second processing result is obtained based on the third instruction and third operand transmitted by the third stage of the pipeline in the multi-stage pipeline.

[0009] In one possible implementation, the processing device also includes a transmitting module and a register module, and the transmitting module is connected to the register module and the multi-stage pipeline respectively; the transmitting module is used to read the first operand from the register module and transmit the first operand to the first-stage pipeline; the first-stage pipeline is also used to receive the first operand.

[0010] In a possible implementation, the transmitting module is further configured to transmit the first instruction to the first-stage pipeline; and the first-stage pipeline is configured to receive the first instruction.

[0011] In one possible implementation, the first-stage pipeline is connected to the fourth-stage pipeline, and the fourth-stage pipeline obtains the first instruction before the first-stage pipeline; the fourth-stage pipeline is used to transmit the first instruction to the first-stage pipeline; and the first-stage pipeline is used to receive the first instruction.

[0012] On the other hand, an instruction processing method is provided, which is applied to a processing device, the processing device including a processing unit and a multi-stage pipeline, and the processing unit is directly connected to the multi-stage pipeline; the method includes: obtaining a first instruction through a first-stage pipeline in the multi-stage pipeline, and transmitting the first instruction and the first operand to the processing unit when a first operand of the first instruction is obtained, the first-stage pipeline being any one-stage pipeline in the multi-stage pipeline; receiving the first instruction and the first operand through the processing unit, processing the first instruction and the first operand, and obtaining a first processing result.

[0013] In one possible implementation, when the first operand of the first instruction is obtained, before the first instruction and the first operand are transmitted to the processing unit, it also includes: through the first stage of pipeline, when the first operand is obtained in the first stage of pipeline, sending a first grab request to the processing unit; through the first stage of pipeline, obtaining a grab result for the processing unit, the grab result is used to indicate whether the processing unit can process the first instruction and the first operand; when the first operand of the first instruction is obtained, transmitting the first instruction and the first operand to the processing unit, including: through the first stage of pipeline, when the grab result is a successful grab, transmitting the first instruction and the first operand to the processing unit.

[0014] In one possible implementation, before obtaining the contention result of the processing unit through the first-level pipeline, it also includes: determining the contention result through the processing unit according to the first contention request, the second contention request and the priority of the first-level pipeline and the second-level pipeline in the multi-level pipeline, and transmitting the contention result to the first-level pipeline, and the second contention request is transmitted to the processing unit by the second-level pipeline when the second operand is obtained.

[0015] In a possible implementation, the priorities of the first-stage pipeline and the second-stage pipeline are determined based on the order in which the first-stage pipeline and the second-stage pipeline fetch instructions.

[0016] In one possible implementation, the processing device also includes a result module, which is connected to the processing unit, and the result module is responsible for storing and transmitting the processing results of the instructions of the multi-stage pipeline; when the first operand of the first instruction is obtained, before transmitting the first instruction and the first operand to the processing unit, it also includes: receiving the second processing result transmitted by the processing unit through the result module, and when the second processing result includes the first operand, transmitting the first operand to the first stage of the pipeline, and the second processing result is obtained based on the third instruction and the third operand transmitted by the third stage of the pipeline in the multi-stage pipeline.

[0017] In one possible implementation, the processing device further includes a transmitting module and a register module, and the transmitting module is connected to the register module and the multi-stage pipeline respectively; when the first operand of the first instruction is obtained, before transmitting the first instruction and the first operand to the processing unit, it also includes: reading the first operand from the register module through the transmitting module, transmitting the first operand to the first stage of the pipeline; and receiving the first operand through the first stage of the pipeline.

[0018] In a possible implementation, before obtaining the first instruction, the method further includes: transmitting the first instruction to the first-stage pipeline through the transmitting module; obtaining the first instruction includes: receiving the first instruction through the first-stage pipeline.

[0019] In one possible implementation, the first-stage pipeline is connected to the fourth-stage pipeline, and the fourth-stage pipeline obtains the first instruction before the first-stage pipeline; before obtaining the first instruction, it also includes: transmitting the first instruction to the first-stage pipeline through the fourth-stage pipeline; obtaining the first instruction includes: receiving the first instruction through the first-stage pipeline.

[0020] On the other hand, an electronic device is provided, which includes a processing device and a memory, wherein at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processing device to enable the electronic device to implement any of the above-mentioned instruction processing methods.

[0021] The technical solution provided by the embodiment of the present application brings at least the following beneficial effects: one processing unit is responsible for executing instructions of multiple stages of pipelines, thereby improving the reuse rate of the processing unit and improving the efficiency of the processing device in processing instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 It is a structural diagram of a pipeline processing device provided by the related art;

[0024] Figure 2 This is a schematic structural diagram of a processing device provided in an embodiment of the present application;

[0025] Figure 3 is a structural diagram of another processing device provided in an embodiment of the present application;

[0026] Figure 4 This is a flowchart of an instruction processing method provided in an embodiment of the present application;

[0027] Figure 5 This is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0029] The instruction processing process of a processing device may include stages such as instruction fetch, decoding, execution, memory access, and writeback. During a cycle, a unit within the processing device performs the operations corresponding to each stage. For example, during a cycle, a unit performs the instruction fetch operation corresponding to instruction a. In traditional processing devices, one unit performs operations during a cycle, and the operations corresponding to multiple stages of an instruction are completed by a single unit within multiple cycles. Other units wait for the unit to complete all operations for the instruction before processing other instructions.

[0030] With the development of electronic technology, processing devices need to process more and more instructions, but traditional processing devices have low efficiency in instruction processing and are unable to process the instructions in time. In this case, pipeline-type processing devices have emerged.

[0031] In a pipelined processing device, different processing stages of an instruction are performed by different units. After completing its own processing, each unit pipes the processed instruction to an adjacent unit, allowing multiple units to collaborate to complete the processing of each instruction.

[0032] Furthermore, in a pipelined processing device, each unit can execute operations simultaneously without waiting. For example, in cycle 1, unit 1 executes the instruction fetch operation of instruction a and passes instruction a to unit 2 after the operation is completed. In cycle 2, unit 1 can execute the instruction fetch operation of instruction b, while unit 2 executes the decoding operation of instruction a. After the operation of unit 1 is completed, it passes instruction b to unit 2, and after the operation of unit 2 is completed, it passes instruction a to unit 3. In cycle 3, unit 1 can execute the instruction fetch operation of instruction c, while unit 2 executes the decoding operation of instruction b, and unit 3 executes the operation of instruction a. After the operation of unit 1 is completed, it passes instruction c to unit 2, and after the operation of unit 2 is completed, it passes instruction b to unit 3, and after the operation of unit 3 is completed, it passes instruction a to unit 4. Similarly, each unit in the pipelined processing device processes different instructions in one cycle, and multiple instructions are processed in parallel in one cycle, which improves the efficiency of the processing device in processing instructions.

[0033] In an in-order processor, when implemented as a pipelined microarchitecture, instructions are issued to each unit in the order in which they are stored. For example, during the issue stage, the issue module in the processor reads the instruction and its operands from the register module and issues the instruction and its operands to the pipeline segment (or stage).

[0034] In some cases, the operands required by instruction 0 come from the currently executing instruction 1. In this case, after receiving the processing result of the currently executing instruction 1, the result module in the processing device can transmit the operands required by instruction 0 to the transmitting module through the forward network. If the transmitting module fails to obtain the operands required by instruction 0, instruction 0 stalls in the transmitting module.

[0035] With the development of pipeline processing devices, even if the transmitting module has not yet obtained the operands corresponding to some instructions when some instructions are issued, the processing device can also issue these instructions with unready operands in advance, thereby achieving micro-disordering of instructions in the sequential execution processing device.

[0036] These pre-issued instructions typically use a forward network to retrieve operands, which are then processed in the corresponding unit. For example, the instruction stream processed by a processing device contains a large number of arithmetic and logical operation instructions, which are implemented by the ALU (Arithmetic Logical Unit). The results of the ALU operation can be fed forward to the unit where the subsequent instruction is located through the forward network, so that the unit where the subsequent instruction is located can obtain the required operands. Therefore, accelerating ALU operations can improve the performance of the processing device.

[0037] In the related art, arithmetic and logical operation instructions issued in advance are passed to a fixed ALU in the pipeline for processing after obtaining the operands, resulting in the operation results not being obtained in the corresponding pipeline unit in a timely manner and the ALU reuse rate being low.

[0038] For example, see Figure 1 A schematic diagram of a partial structure of a pipeline processing device is shown. The pipeline processing device includes pipeline stages 0 through 3, each of which is used to process instructions at different stages. In this processing device, the ALU is located in pipeline stage 3 and can only be called from pipeline stage 3.

[0039] In this case, if the arithmetic and logical operation instructions issued in advance obtain the operands corresponding to the instructions when operating in pipeline stage 1, since pipeline stage 1 cannot call the ALU, pipeline stage 1 cannot operate on the operands according to the instruction and cannot complete the processing of the instruction and operands.

[0040] Pipeline stage 1 can only pass the instruction and operand to the following pipeline stage 2, and pipeline stage 2 cannot call ALU, so pipeline stage 2 cannot complete the processing of the instruction and operand. Pipeline stage 2 can only pass the instruction and the operand corresponding to the instruction to the following pipeline stage 3.

[0041] Because pipeline stage 3 can call the ALU, it performs operations on the operands according to the instruction by calling the ALU, completing the processing of the instruction and operands. Therefore, between the time the pipeline stage obtains the operands and the time it completes the processing of the instruction and operands, there are two cycles in which the instruction and operands are not processed at all. Therefore, the fixed ALU used to perform operations on the instruction results in low overall instruction processing efficiency.

[0042] Therefore, the number of ALUs and their location in the processing device have a great impact on the performance of the processing device in processing instructions. The earlier the ALU operation is performed, the earlier the ALU result can be obtained, thereby releasing the stall of instructions that depend on the ALU instruction result in the emission stage.

[0043] The embodiment of the present application provides a processing device that can improve the overall processing efficiency of instructions. Figure 2 , showing a schematic structural diagram of a processing device provided in an embodiment of the present application. The processing device may be a pipeline (or execution pipeline) type processing device, such as a pipeline type CPU (Central Processing Unit). The processing device includes a processing unit 21 and a multi-stage pipeline 22 in the pipeline. The multi-stage pipeline is a multi-layer sequence (sequence of stages) in the processing device. Each layer in the multi-layer sequence can also be called a pipe or each stage of pipeline. The first stage of pipeline includes a register segment and a hardware circuit connected to the register segment. The hardware circuit is used to connect adjacent pipelines, transmit data between adjacent pipelines, and perform logical judgments, etc. For example, the hardware circuit can determine whether the transmitted instruction is valid.

[0044] Because a pipeline stage is a module or unit for executing instructions, it can also be called an execution (EX) unit or an execution module. Each pipeline stage has data transmission, caching, and logical judgment capabilities. In the embodiments of the present application, the operations performed by any pipeline stage are performed by a register segment and hardware circuit in any pipeline stage, either individually or in combination.

[0045] The processing unit 21 is responsible for the execution of instructions of the multi-stage pipeline 22, which is implemented as the processing unit 21 can be directly connected to the multi-stage pipeline 22, that is, one processing unit 21 can be connected to the hardware circuit of the multi-stage pipeline 22, so that the multi-stage pipeline 22 and one processing unit 21 can transmit data. The processing unit 21 can be an ALU or other unit that can perform operations on instructions. Optionally, the processing device may include one or more processing units 21, and each processing unit 21 can be responsible for the execution of instructions of the multi-stage pipeline 22. The first-stage pipeline, the second-stage pipeline... in the multi-stage pipeline in the embodiment of the present application are to distinguish different levels of pipelines in the multi-stage pipeline. The words "first", "second" and so on are used to distinguish different levels of pipelines. It can be understood that the processor pipeline can have other pipelines (segments) before the first-stage pipeline.

[0046] The following is an exemplary description of the composition and function of each part of the processing device.

[0047] The first stage of the multi-stage pipeline is used to obtain the first instruction and, when the first operand of the first instruction is obtained, transmit the first instruction and the first operand to the processing unit. The first stage of the pipeline is any one of the multi-stage pipelines. For example, the first stage of the pipeline can be Figure 2 1-level pipeline, 2-level pipeline or n-level pipeline.

[0048] Since the first instruction may be a sequentially issued instruction or an early-issued instruction with unready operands, the first-stage pipeline may not obtain the corresponding first operand when it obtains the first instruction, and cannot simultaneously transmit the first instruction and the first operand to the processing unit. However, when the first-stage pipeline obtains the first operand, it can transmit the first instruction and the first operand to the processing unit connected to the first-stage pipeline, so that the processing unit can process the first instruction and the first operand.

[0049] The embodiments of the present application do not limit the manner in which the first-stage pipeline obtains the first instruction. For example, since the processing device can be a pipeline-type processing device, the first-stage pipeline can be connected to other-stage pipelines and receive the first instruction transmitted by other-stage pipelines. For example, in the case of the first-stage pipeline being connected to the fourth-stage pipeline, the fourth-stage pipeline can transmit the first instruction to the first-stage pipeline; the first-stage pipeline receives the first instruction. The fourth-stage pipeline obtains the first instruction before the first-stage pipeline.

[0050] If the fourth-stage pipeline obtains the first instruction but does not obtain the first operand, the fourth-stage pipeline cannot call the processing unit connected to the fourth-stage pipeline to process the first instruction. Therefore, the fourth-stage pipeline passes the first instruction backward to the first-stage pipeline. The first-stage pipeline obtains the first instruction by receiving the first instruction.

[0051] In one possible implementation, the processing device further includes a transmitter module, which can be connected to the first-stage pipeline. For example, when the first-stage pipeline is the first stage of a multi-stage pipeline, the first-stage pipeline can be connected to the transmitter module. Thus, after acquiring the first instruction, the transmitter module can transmit the first instruction to the first-stage pipeline; the first-stage pipeline acquires the first instruction by receiving the first instruction.

[0052] The embodiment of the present application does not limit the manner in which the transmitting module obtains the first instruction. For example, the processing device may further include a register module. The register module may be a GPR (General Purpose Register), which stores instructions to be processed by the processing device. Therefore, the transmitting module can read the first instruction from the register module, thereby enabling the transmitting module to obtain the first instruction.

[0053] Accordingly, the embodiment of the present application does not limit the manner in which the first-stage pipeline obtains the first operand. Based on the foregoing, it can be seen that the processing device also includes a transmitter module and a register module. The register module can not only store the various instructions to be processed by the processing device, but also store the operands required for some instructions and information such as the storage address of the operands. Therefore, if the first operand is stored in the register module, the transmitter module can read the first operand from the register module and transmit the first operand to the first-stage pipeline; the first-stage pipeline obtains the first operand by receiving the first operand.

[0054] In one possible implementation, the processing device further includes a result module, which is connected to the processing unit. The result module, which may also be referred to as a result register module, is responsible for storing and transmitting the execution results of instructions in multiple pipelines. Because the processing result of one instruction may be an operand required by another instruction, the result module can feed the processing result of the one instruction forward to the pipeline containing the other instruction, allowing the pipeline containing the other instruction to obtain the required operands and call the processing unit to process the other instruction and its corresponding operands.

[0055] Exemplarily, the result module may receive a second processing result transmitted by the processing unit, and, if the second processing result includes a first operand, transmit the first operand to the first-stage pipeline. The second processing result is obtained based on a third instruction and a third operand transmitted by a third-stage pipeline in the multi-stage pipeline. The third-stage pipeline may be adjacent to the first-stage pipeline or may not be adjacent to the first-stage pipeline.

[0056] Because processing units are directly connected to multiple pipeline stages, they can be called by multiple pipeline stages. However, within a cycle, a processing unit can only process one instruction and its corresponding operands sent by a single pipeline stage. Therefore, if multiple pipeline stages connected to a processing unit obtain the operands they need within the same cycle, the multiple pipeline stages will send a competition request to the processing unit to compete for the processing unit. The competition result determines whether each pipeline stage can call the processing unit within the same cycle.

[0057] For example, when the first stage pipeline obtains the first operand, it sends a first preemption request to the processing unit and obtains a preemption result for the processing unit, wherein the preemption result indicates whether the processing unit can process the first instruction and the first operand.

[0058] The embodiment of the present application does not limit the manner in which the first-stage pipeline obtains the preemption result. For example, the preemption result can be determined and sent by the processing unit that the first-stage pipeline and the other-stage pipelines are preempting. Therefore, before the first-stage pipeline obtains the preemption result, the processing unit can determine the preemption result based on the first preemption request, the second preemption request, and the priority of the first-stage pipeline and the second-stage pipeline. The second-stage pipeline is the pipeline other than the first-stage pipeline in the multi-stage pipeline, and the second preemption request is transmitted by the second-stage pipeline to the processing unit when the second operand is obtained.

[0059] Optionally, the priority of the first-level pipeline and the second-level pipeline can be determined based on the order in which the first-level pipeline and the second-level pipeline obtain instructions. The reason is that the earlier the order in which any one-level pipeline obtains instructions, the longer the time it takes for the instructions to be executed. Instructions that take longer to be executed should be processed first to reduce the execution time of the instructions, thereby improving the efficiency of the processor in executing instructions. In addition, the earlier the order in which any one-level pipeline obtains instructions, the more subsequent instructions may depend on the processing results of the instructions obtained by this level of pipeline. Therefore, giving priority to processing the instructions and operands obtained earlier can more quickly eliminate the dependence of other instructions and accelerate the processing of subsequent instructions.

[0060] From this, we can see that if the time when the first-level pipeline obtains the first instruction is earlier than the time when the second-level pipeline obtains the second instruction, the processing unit can determine that the first-level pipeline can call the processing unit within this cycle, and the corresponding snatch result of the first-level pipeline is a successful snatch, while the corresponding snatch result of the second-level pipeline is a failed snatch.

[0061] In a possible implementation, a mux (multiplexer) circuit may be added to the processing unit to enable the processing unit to determine the contention result.

[0062] After the processing unit determines the competition result, it can transmit the competition result to the first-stage pipeline and the second-stage pipeline so that the first-stage pipeline and the second-stage pipeline can determine whether to compete for the processing unit, and thus determine whether to send processing instructions and operands to the processing unit.

[0063] In another possible implementation, each level of pipeline can send a grab request to other levels of pipeline connected to the processing unit after receiving the required operands. Based on the received grab request and the priority of each level of pipeline that obtains the operand, each level of pipeline can independently determine the grab result of each level of pipeline, and determine whether to transmit instructions and operands to the processing unit based on their respective grab results.

[0064] For example, when the first stage pipeline obtains the first operand, it may send a first grab request to the fifth stage pipeline, wherein the fifth stage pipeline and the first stage pipeline are connected to the same processing unit, and the number of the fifth stage pipelines may be one or more.

[0065] Taking the example of a plurality of fifth-stage pipelines, the first-stage pipeline can also receive a third preemption request sent by the fifth-stage pipeline that has obtained an operand in the fifth-stage pipeline. The first-stage pipeline determines a first preemption result based on the priority of the first-stage pipeline and the fifth-stage pipeline that has obtained the operand. If the priority of the first-stage pipeline is higher than that of the fifth-stage pipeline, the first preemption result is a preemption success, and the first-stage pipeline can transmit the first instruction and the first operand to the processing unit. If the priority of the first-stage pipeline is lower than that of the fifth-stage pipeline, the first preemption result is a preemption failure, and the first-stage pipeline temporarily does not transmit the first instruction and the first operand to the processing unit.

[0066] In addition, any fifth-stage pipeline that obtains an operand can also receive the first grab request transmitted by the first-stage pipeline and the third grab request transmitted by other fifth-stage pipelines that obtain operands. Therefore, any fifth-stage pipeline that obtains an operand can also determine the grab result of any fifth-stage pipeline that obtains an operand based on the priority of the first-stage pipeline and each fifth-stage pipeline that obtains an operand.

[0067] If the contention result of any fifth-stage pipeline that obtains the operand is a success, the obtained instruction and operand are sent to the processing unit; if the contention result is a failure, the obtained instruction and operand are temporarily not sent to the processing unit.

[0068] If the first-stage pipeline's preemption result is a success, the first-stage pipeline can transmit the preemption result to the processing unit at the same time as transmitting the first instruction and the first operand to the processing unit, so that the processing unit can confirm that it can process the first instruction and the first operand. If any fifth-stage pipeline that obtains an operand transmits an instruction and an operand to the processing unit when its preemption result is a failure, the processing unit will not process the instruction and operand to ensure the accuracy of the processing order and processing results.

[0069] Regardless of how the first-stage pipeline obtains the preemption result, when the preemption result obtained by the first-stage pipeline is a successful preemption, the first-stage pipeline can transmit the first instruction and the first operand to the processing unit. The processing unit then receives the first instruction and the first operand, processes the first instruction and the first operand, and obtains a first processing result.

[0070] For example, if the processing unit is an ALU unit and the first instruction is an arithmetic instruction, after receiving the first instruction and the first operand, the processing unit performs the operation on the first operand according to the first instruction, and the operation result is the processing result. For example, if the first instruction is an addition instruction and the first operand includes operand a and operand b, the processing unit may add operand a and operand b, and the resulting sum is the first processing result.

[0071] Next, combine Figure 3 , through a complete example, the functions of the various parts of the processing device provided in the embodiment of the present application are explained. The processing device is a pipeline type processing device, and the instructions are transmitted backward in the pipeline through each level of the pipeline.

[0072] The processing device includes a multi-stage pipeline, an emission module, a register module, a result module, a processing unit 0, a processing unit 1, and a retirement write-back module. Processing unit 0 is responsible for processing instructions and operands of the 0th and 1st stage pipelines, while processing unit 1 is responsible for processing instructions and operands of the 2nd and 3rd stage pipelines.

[0073] The launch module reads data such as instructions and operands from the register module and issues them to each stage of the pipeline during the launch phase. Logic has been added to pipeline stages 0 through 3 to determine whether operands have been retrieved and whether a processing unit has been allocated. When an operand is retrieved at any stage, it determines whether the connected processing unit has been allocated and whether it has been allocated.

[0074] For example, when the 0-level pipeline and the 1-level pipeline simultaneously obtain operands, since the priority of the 1-level pipeline is higher than that of the 0-level pipeline, the processing unit 0 processes the instructions and operands transmitted by the 1-level pipeline. When only one of the 0-level and 1-level pipelines (for example, the 0-level pipeline or the 1-level pipeline) obtains the operand, there is no competition, and the 1-level pipeline that obtains the operand directly calls the processing unit to process the instruction and operand. When the 2-level pipeline and the 3-level pipeline obtain operands at the same time, the instructions and operands are processed in a similar manner, which will not be repeated here.

[0075] In addition, when the processing of an instruction is completed, the processing unit transmits the processing result to the result module. The result module can send the processing result to the retirement write-back module. The processing unit can also send the completed instruction to the retirement write-back module. The retirement write-back module, also known as the retirement write-back unit (RTU), retires the completed instruction and writes back the processing result and other data to the register module.

[0076] Figure 3The illustrated processing device uses two processing units to process instructions and operands obtained through four pipeline stages, from level 0 to level 3. This processing device dynamically adjusts the call relationships between the processing units and the connected pipeline stages to improve the processing unit's reuse rate, obtain processing results in a timely manner, and then forward the processing results through a forward network, thereby improving the processing device's instruction processing performance.

[0077] In some related technologies, the processing efficiency of the processing device for instructions is improved by increasing the number of ALUs, thereby improving the efficiency of the processing device in processing instructions. For example, each stage of the pipeline is directly connected to a separate processing unit, so that the ratio of pipeline to processing unit is 1:1. However, this method will increase the size and power consumption of the processing device. The processing device provided in the embodiments of the present application can improve the processing efficiency of instructions while avoiding excessively increasing the size and power consumption of the processing device, so that the processing device strikes a balance between high efficiency and low power consumption and small size.

[0078] In summary, in the processing device provided in the embodiment of the present application, one processing unit can be responsible for executing instructions in multiple stages of pipelines, thereby improving the multiplexing rate of the processing unit and improving the efficiency of the processing device in processing instructions.

[0079] In an exemplary embodiment, the present application also provides an instruction processing method, which can be applied to the above-mentioned processing device. Figure 4 , shows a flow chart of the instruction processing method. The method includes but is not limited to the following S401 and S402.

[0080] S401, obtaining a first instruction through a first stage of a multi-stage pipeline, and transmitting the first instruction and the first operand to a processing unit when a first operand of the first instruction is obtained. The first stage of the pipeline is any stage of the multi-stage pipeline.

[0081] S402: Receive a first instruction and a first operand through a processing unit, process the first instruction and the first operand, and obtain a first processing result.

[0082] In one possible implementation, when the first operand of the first instruction is obtained, before the first instruction and the first operand are transmitted to the processing unit, it also includes: through the first stage of pipeline, when the first operand is obtained in the first stage of pipeline, sending a first grab request to the processing unit; through the first stage of pipeline, obtaining a grab result for the processing unit, the grab result is used to indicate whether the processing unit can process the first instruction and the first operand; when the first operand of the first instruction is obtained, transmitting the first instruction and the first operand to the processing unit, including: through the first stage of pipeline, when the grab result is a successful grab, transmitting the first instruction and the first operand to the processing unit.

[0083] In one possible implementation, before obtaining the contention result of the processing unit through the first-level pipeline, it also includes: determining the contention result through the processing unit according to the first contention request, the second contention request and the priority of the first-level pipeline and the second-level pipeline in the multi-level pipeline, and transmitting the contention result to the first-level pipeline, and the second contention request is transmitted to the processing unit by the second-level pipeline when the second operand is obtained.

[0084] In a possible implementation, the priorities of the first-stage pipeline and the second-stage pipeline are determined based on the order in which the first-stage pipeline and the second-stage pipeline fetch instructions.

[0085] In one possible implementation, the processing device also includes a result module, which is connected to the processing unit, and the result module is responsible for storing and transmitting the processing results of the instructions of the multi-stage pipeline; when the first operand of the first instruction is obtained, before transmitting the first instruction and the first operand to the processing unit, it also includes: receiving the second processing result transmitted by the processing unit through the result module, and when the second processing result includes the first operand, transmitting the first operand to the first stage of the pipeline, and the second processing result is obtained based on the third instruction and the third operand transmitted by the third stage of the pipeline in the multi-stage pipeline.

[0086] In one possible implementation, the processing device further includes a transmitting module and a register module, and the transmitting module is connected to the register module and the multi-stage pipeline respectively; when the first operand of the first instruction is obtained, before transmitting the first instruction and the first operand to the processing unit, it also includes: reading the first operand from the register module through the transmitting module, transmitting the first operand to the first stage of the pipeline; and receiving the first operand through the first stage of the pipeline.

[0087] In a possible implementation, before obtaining the first instruction, the method further includes: transmitting the first instruction to the first-stage pipeline through the transmitting module; obtaining the first instruction includes: receiving the first instruction through the first-stage pipeline.

[0088] In one possible implementation, the first-stage pipeline is connected to the fourth-stage pipeline, and the fourth-stage pipeline obtains the first instruction before the first-stage pipeline; before obtaining the first instruction, it also includes: transmitting the first instruction to the first-stage pipeline through the fourth-stage pipeline; obtaining the first instruction includes: receiving the first instruction through the first-stage pipeline.

[0089] The instruction processing method provided in the embodiment of the present application can be executed by the processing device described above. The description and beneficial effects of the processing device executing the method can refer to the above description and beneficial effects of the processing device, which will not be repeated here.

[0090] In an exemplary embodiment, the present application also provides an electronic device. Figure 5 As shown, the electronic device includes a processing device and a memory. The memory stores at least one instruction, and the processing device can be the processing device in the above embodiment. The at least one instruction is loaded and executed by the processing device to enable the electronic device to implement any of the above instruction processing methods.

[0091] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, storage, display, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the instructions and operands involved in this application are obtained with full authorization.

[0092] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0093] It should be noted that the terms "first," "second," etc. (if any) in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the application as detailed in the appended claims.

[0094] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A processing device, characterized in that: The processing device includes a processing unit and multiple pipelines in a pipeline, wherein the processing unit is responsible for executing instructions of the multiple pipelines, and one processing unit is responsible for executing instructions of one pipeline in the multiple pipelines in one cycle; A first stage of the multi-stage pipeline is configured to fetch a first instruction and, upon fetching a first operand of the first instruction, transmit the first instruction and the first operand to the processing unit. The first stage of the pipeline is any one stage of the multi-stage pipeline. The processing unit is configured to receive the first instruction and the first operand, process the first instruction and the first operand, and obtain a first processing result.

2. The processing device according to claim 1, characterized in that The first-stage pipeline is further configured to, when the first-stage pipeline obtains the first operand, send a first preemption request to the processing unit and obtain a preemption result for the processing unit, wherein the preemption result is used to indicate whether the processing unit can process the first instruction and the first operand; The first-stage pipeline is configured to transmit the first instruction and the first operand to the processing unit when the contention result is a success.

3. The processing device according to claim 2, characterized in that The processing unit is also used to determine the contention result based on the first contention request, the second contention request and the priority of the first-level pipeline and the second-level pipeline in the multi-level pipeline, and transmit the contention result to the first-level pipeline. The second contention request is transmitted to the processing unit by the second-level pipeline when the second operand is obtained.

4. The processing device according to claim 3, characterized in that The priorities of the first-stage pipeline and the second-stage pipeline are determined based on the order in which the first-stage pipeline and the second-stage pipeline fetch instructions.

5. The processing device according to any one of claims 1 to 4, characterized in that: The processing device further comprises a result module, the result module is connected to the processing unit, and the result module is responsible for storing and transmitting the processing results of the multi-stage pipeline instructions; The result module is used to receive the second processing result transmitted by the processing unit, and when the second processing result includes the first operand, transmit the first operand to the first stage pipeline. The second processing result is obtained based on the third instruction and third operand transmitted by the third stage pipeline in the multi-stage pipeline.

6. The processing device according to any one of claims 1 to 4, characterized in that: The processing device further includes a transmitting module and a register module, wherein the transmitting module is connected to the register module and the multi-stage pipeline respectively; The transmitting module is configured to read the first operand from the register module and transmit the first operand to the first stage pipeline; The first stage pipeline is also used to receive the first operand.

7. The processing device according to claim 6, characterized in that The transmitting module is further configured to transmit the first instruction to the first stage pipeline; The first-stage pipeline is used to receive the first instruction.

8. The processing device according to any one of claims 1 to 4, characterized in that: The first stage pipeline is connected to the fourth stage pipeline, and the fourth stage pipeline obtains the first instruction before the first stage pipeline; The fourth stage pipeline is used to transmit the first instruction to the first stage pipeline; The first-stage pipeline is used to receive the first instruction.

9. A method for processing an instruction, characterized in that: The method is applied to a processing device, the processing device including a processing unit and multiple pipelines in a pipeline, the processing unit being responsible for executing instructions of the multiple pipelines, and one processing unit being responsible for executing instructions of one pipeline in the multiple pipelines in one cycle; the method comprising: fetching a first instruction through a first stage of the multi-stage pipeline, and transmitting the first instruction and the first operand to the processing unit when a first operand of the first instruction is fetched, wherein the first stage of the pipeline is any one stage of the multi-stage pipeline; The processing unit receives the first instruction and the first operand, processes the first instruction and the first operand, and obtains a first processing result.

10. The method according to claim 9, characterized in that In the case where the first operand of the first instruction is obtained, before transmitting the first instruction and the first operand to the processing unit, the method further includes: When the first stage pipeline obtains the first operand, sending a first grab request to the processing unit; Obtaining, through the first stage pipeline, a competition result for the processing unit, wherein the competition result is used to indicate whether the processing unit can process the first instruction and the first operand; The step of transmitting the first instruction and the first operand to the processing unit when the first operand of the first instruction is obtained includes: Through the first stage pipeline, if the contention result is a success, the first instruction and the first operand are transmitted to the processing unit.

11. The method according to claim 10, characterized in that Before obtaining the result of the contention for the processing unit through the first-stage pipeline, the method further includes: Through the processing unit, the preemption result is determined according to the first preemption request, the second preemption request, and the priority of the first-level pipeline and the second-level pipeline in the multi-level pipeline, and the preemption result is transmitted to the first-level pipeline. The second preemption request is transmitted to the processing unit by the second-level pipeline when the second operand is obtained.

12. The method according to claim 11, characterized in that The priorities of the first-stage pipeline and the second-stage pipeline are determined based on the order in which the first-stage pipeline and the second-stage pipeline fetch instructions.

13. The method according to any one of claims 9 to 12, characterized in that: The processing device further comprises a result module, the result module is connected to the processing unit, and the result module is responsible for storing and transmitting the processing results of the multi-stage pipeline instructions; In the case where the first operand of the first instruction is obtained, before transmitting the first instruction and the first operand to the processing unit, the method further includes: The result module receives the second processing result transmitted by the processing unit, and when the second processing result includes the first operand, transmits the first operand to the first stage pipeline. The second processing result is obtained based on the third instruction and third operand transmitted by the third stage pipeline in the multi-stage pipeline.

14. The method according to any one of claims 9 to 12, characterized in that: The processing device further includes a transmitting module and a register module, wherein the transmitting module is connected to the register module and the multi-stage pipeline respectively; In the case where the first operand of the first instruction is obtained, before transmitting the first instruction and the first operand to the processing unit, the method further includes: Reading the first operand from the register module through the transmitting module, and transmitting the first operand to the first stage pipeline; The first operand is received through the first stage pipeline.

15. The method according to claim 14, characterized in that Before obtaining the first instruction, the method further includes: transmitting the first instruction to the first-stage pipeline through the transmitting module; The obtaining of the first instruction includes: The first instruction is received through the first stage pipeline.

16. The method according to any one of claims 9 to 12, characterized in that: The first stage pipeline is connected to the fourth stage pipeline, and the fourth stage pipeline obtains the first instruction before the first stage pipeline; Before obtaining the first instruction, the method further includes: transmitting the first instruction to the first stage pipeline through the fourth stage pipeline; The obtaining of the first instruction includes: The first instruction is received through the first stage pipeline.

17. An electronic device, characterized in that: The electronic device includes a processing device and a memory, wherein the memory stores at least one instruction, and the at least one instruction is loaded and executed by the processing device, so that the electronic device implements the instruction processing method according to any one of claims 9 to 16.

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