A high-side and low-side integrated MOS power switch

Abstract

The present invention belongs to the technical field of power semiconductor devices, and discloses a high-low side integrated MOS type power switch. The present invention first proposes a high-low side integrated MOS type device, which integrates two MOS devices on the same substrate, isolates the two MOS devices through a dielectric isolation region to withstand the lateral withstand voltage between the devices, and connects the source of one MOS to the drain of another MOS through a low resistivity region or a metal trace, and the low resistivity region or the metal trace provides a low impedance channel, which can achieve efficient and compact series connection, and further, the control circuit and the high-low side integrated MOS type device of the present invention can be integrated on the same substrate to form an intelligent power switch, which is conducive to reducing the occupied area of ​​the chip, achieving high power density, reducing temperature fluctuations, reducing transmission delays, reducing electromagnetic interference, etc. The present invention helps to achieve efficient current control and switch management, especially in applications requiring high voltage and current control, such as BUCK circuits, BOOST circuits, and half-bridge circuits.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a high-low side integrated MOS type power switch. Background Art

[0002] Traditional electronic power circuits based on MOS devices, such as BUCK, BOOST and half-bridge circuits, all have power conversion functions. The use of integrated circuits to complete the power conversion function usually requires a control circuit, a DC high-side device electrically coupled to the input voltage, and a DC low-side device electrically coupled to the ground. For example, in a synchronous buck converter, power conversion is performed by alternately operating the high-side device and the low-side device to reduce the voltage, wherein the control circuit performs high-efficiency and low-power switching and control functions, so the high-side and low-side devices can be regarded as a power switch.

[0003] The control circuit usually includes logic circuit, protection circuit and drive circuit, so the control circuit and high-side and low-side devices can be collectively referred to as an intelligent power switch. As the output stage of the intelligent power switch, that is, the high-side and low-side devices, two MOS devices configured in series are often required, where the source of one MOS is connected to the drain of the other MOS, such as Figures 1 to 3 The traditional solution is to use two discrete MOS devices and a driver chip to connect on the PCB board. However, this solution occupies a large PCB board area, has a long wiring length, and has large parasitic inductance, capacitance, and resistance, which affects signal transmission delay and increases electromagnetic interference. At the same time, there are also reliability issues that may be caused by multiple package welding points.

[0004] In order to solve the drawbacks of the traditional solution, two series-connected Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) chips can be integrated into a single package to reduce problems such as area and transmission delay. However, the two MOSFET chips still need to be connected by welding wires, which will bring additional parasitic inductance, capacitance, and resistance, and the chip integration is relatively low. In addition, the two MOSFET chips control their respective gates through external control circuits to switch them alternately. The device temperature will increase when it is turned on and decrease when it is turned off. Although the two MOSFET chips are integrated into a single package, they are still independent of each other, so the temperature propagation may be uneven, resulting in large temperature fluctuations, which may cause the welding wires to fall off, causing reliability problems. Summary of the invention

[0005] In view of the above technical problems, one of the purposes of the present invention is to propose a high-low side integrated MOS type device, which integrates two MOSFETs into a single silicon wafer, not only is the two MOS devices isolated by a dielectric isolation region to withstand the lateral withstand voltage between the devices, but also the source of one MOS is connected to the drain of another MOS through a low resistance region or a metal trace, and the low resistivity region or the metal trace provides a low impedance channel, thereby forming an efficient and compact single-chip solution with series connection, which is beneficial to reducing the area occupied by the chip on the PCB board, achieving high power density, reducing temperature fluctuations, reducing transmission delays, reducing electromagnetic interference, etc.

[0006] In order to achieve the above object, the present invention adopts the following technical scheme:

[0007] A high-low-side integrated MOS type device, whose cell structure includes a third metallized source, a P+ substrate and a P- epitaxial layer stacked in sequence from bottom to top;

[0008] A first trench is provided at a middle position along the left-right direction of the P-epitaxial layer, the first trench is arranged in a longitudinal direction, and extends downward from the upper surface of the P-epitaxial layer to the upper surface of the P+ substrate;

[0009] The first trench is filled with a dielectric material to form a dielectric isolation region;

[0010] A third P+ low resistivity region is provided on the left side of the first trench, and the third P+ low resistivity region is also arranged vertically; the third P+ low resistivity region is in contact with the left side surface of the first trench;

[0011] A first P-type base region, a first N-drift region and a first planar gate structure are disposed on the left side of the third P+ low resistivity region; the first P-type base region and the first N-drift region are both included in the P-epitaxial layer;

[0012] The first P-type base region and the first N-drift region are both located at the top of the left region of the P-epitaxial layer and the sides of the two are in contact with each other, and the first P-type base region is located at the left side of the first N-drift region;

[0013] The first P-type base region includes a first P+ low resistivity region and a first N+ source region; the first P+ low resistivity region and the first N+ source region are both located in the top left region of the first P-type base region and the sides of the two regions are in contact with each other, and the first P+ low resistivity region is located on the left side of the first N+ source region; the top right region of the first P-type base region is located between the right side surface of the first N+ source region and the right side surface of the first P-type base region;

[0014] The first N-drift region includes a first N+ drain region; the first N+ drain region is located in a top right region of the first N-drift region; the top left region of the first N-drift region is located between a left side surface of the first N+ drain region and a left side surface of the first N-drift region;

[0015] The right sides of the first N-drift region and the first N+ drain region are in contact with the left side of the third P+ low-resistivity region;

[0016] The first planar gate structure includes a first gate oxide layer and a first gate electrode;

[0017] The bottom surface of the first gate oxide layer is in contact with a right portion of the top surface of the first N+ source region, a top right region of the first P-type base region, and a top left region of the first N-drift region;

[0018] A first gate electrode is located on a top surface of the first gate oxide layer;

[0019] A second P+ low resistivity region is provided on the right side of the first trench, and the second P+ low resistivity region is also arranged vertically; the second P+ low resistivity region is in contact with the right side surface of the first trench;

[0020] A second P-type base region, a second N-drift region and a second planar gate structure are provided on the right side of the second P+ low resistivity region; the second P-type base region and the second N-drift region are both included in the P-epitaxial layer;

[0021] The second P-type base region and the second N-drift region are both located at the top of the right region of the P-epitaxial layer and the sides of the two are in contact with each other, and the second P-type base region is located on the left side of the second N-drift region;

[0022] The second P-type base region includes a second N+ source region;

[0023] The second N+ source region is located at the top left region of the second P-type base region; the top right region of the second P-type base region is located between the right side surface of the second N+ source region and the right side surface of the second P-type base region;

[0024] The left sides of the second N+ source region and the second P-type base region are both in contact with the right side of the second P+ low resistivity region;

[0025] The second N-drift region includes a second N+ drain region;

[0026] The second N+ drain region is located at the top right region of the second N-drift region; the top left region of the second N-drift region is located between the left side surface of the second N+ drain region and the left side surface of the second N-drift region;

[0027] The second planar gate structure includes a second gate oxide layer and a second gate electrode;

[0028] The bottom surface of the second gate oxide layer is in contact with a right portion of the top surface of the second N+ source region, a right region of the top of the second P-type base region, and a left region of the top of the second N-drift region;

[0029] The second gate electrode is located on the top surface of the second gate oxide layer;

[0030] An insulating layer is provided above the P-epitaxial layer; a first metallized source electrode, a first metallized drain electrode, a second metallized source electrode, and a second metallized drain electrode are provided above the insulating layer;

[0031] A through hole is provided in the insulating layer; wherein the first metallized source electrode is in ohmic contact with the first P+ low resistivity region and the first N+ source region through the through hole; the first metallized drain electrode is in ohmic contact with the first N+ drain region and the third P+ low resistivity region through the through hole; the second metallized source electrode is in ohmic contact with the second P+ low resistivity region and the second N+ source region through the through hole; and the second metallized drain electrode is in ohmic contact with the second N+ drain region through the through hole.

[0032] In addition, based on the above-mentioned high-low side integrated MOS type device structure, the present invention also proposes a new high-low side integrated MOS type device. In the new high-low side integrated MOS type device, the third P+ low resistivity region is removed, the first metallized drain and the second metallized source are merged into a second metallized source, the Source_down structure of the second P+ low resistivity region is changed to a conventional LDMOS structure, and the third metallized source is removed. Other structures can refer to the structure of the above-mentioned high-low side integrated MOS type device.

[0033] In addition, the present invention also proposes a high-low side integrated MOS type device which is different from the above two high-low side integrated MOS type device structures, and adopts the following technical solution:

[0034] A high-low-side integrated MOS type device, whose cell structure includes a first metallized drain, an N+ substrate and a P-deep well region stacked in sequence from bottom to top;

[0035] A first groove is provided in the middle position along the left-right direction of the P-deep well region; the first groove is arranged in a longitudinal direction and extends downward from the upper surface of the P-deep well region to the upper surface of the N+ substrate;

[0036] The first trench is filled with a dielectric material to form a dielectric isolation region;

[0037] A first N+ low resistivity region is provided on the left side of the first trench, the first N+ low resistivity region is also arranged vertically, and the first N+ low resistivity region is in contact with the left side surface of the first trench;

[0038] A first P-type base region, a first N-drift region and a first planar gate structure are provided on the left side of the first N+ low resistivity region; the first P-type base region and the first N-drift region are both included in the P-deep well region;

[0039] The first P-type base region and the first N-drift region are both located at the top of the left region of the P-deep well region and the sides of the two are in contact with each other, and the first P-type base region is located at the left side of the first N-drift region;

[0040] The right side surface of the first N-drift region is in contact with the left side surface of the first N+ low-resistivity region;

[0041] The first P-type base region includes a first P+ low resistivity region and a first N+ source region; the first P+ low resistivity region and the first N+ source region are both located in the top left region of the first P-type base region and the sides of the two regions are in contact with each other, and the first N+ source region is located on the right side of the first P+ low resistivity region; the top right region of the first P-type base region is located between the right side surface of the first N+ source region and the right side surface of the first P-type base region;

[0042] The first planar gate structure includes a first gate oxide layer and a first gate electrode;

[0043] The bottom surface of the first gate oxide layer is in contact with a right portion of the top surface of the first N+ source region, a right portion of the top surface of the first P-type base region, and a left portion of the top surface of the first N-drift region;

[0044] A first gate electrode is located on a top surface of the first gate oxide layer;

[0045] A second N+ low resistivity region is provided on the right side of the first trench, the second N+ low resistivity region is also arranged vertically, and the second N+ low resistivity region is in contact with the right side surface of the first trench;

[0046] A second P-type base region, a second N-drift region and a second planar gate structure are provided on the right side of the second N+ low resistivity region; the second P-type base region and the second N-drift region are both included in the P-deep well region;

[0047] The second P-type base region and the second N-drift region are both located at the top of the right side region of the P-deep well region and the sides of the two regions are in contact with each other, and the second P-type base region is located at the left side of the second N-drift region;

[0048] The second P-type base region includes a second N+ source region and a second P+ low resistivity region; the second N+ source region and the second P+ low resistivity region are both located in the top left region of the second P-type base region and the sides of the two regions are in contact with each other, and the second N+ source region is located on the right side of the second P+ low resistivity region; the top right region of the second P-type base region is located between the right side surface of the second N+ source region and the right side surface of the second P-type base region;

[0049] The left sides of the second P-type base region and the second P+ low-resistivity region are in contact with the right side of the second N+ low-resistivity region;

[0050] The second N-drift region includes a second N+ drain region;

[0051] The second N+ drain region is located at the top right region of the second N-drift region; the top left region of the second N-drift region is located between the left side surface of the second N+ drain region and the left side surface of the second N-drift region;

[0052] The second planar gate structure includes a second gate oxide layer and a second gate electrode;

[0053] The bottom surface of the second gate oxide layer is in contact with a right portion of the top surface of the second N+ source region, a top right region of the second P-type base region, and a top left region of the second N-drift region;

[0054] The second gate electrode is located on the top surface of the second gate oxide layer;

[0055] An insulating layer is provided above the P-deep well region; a first metallized source electrode, a second metallized source electrode, and a second metallized drain electrode are provided above the insulating layer;

[0056] A through hole is provided in the insulating layer; wherein the first metallized source electrode is in ohmic contact with the first P+ low resistivity region and the first N+ source region through the through hole; the second metallized source electrode is in ohmic contact with the second N+ low resistivity region, the second N+ source region and the second P+ low resistivity region through the through hole; and the second metallized drain electrode is in ohmic contact with the second N+ drain region through the through hole.

[0057] In addition, based on the above-mentioned high-low side integrated MOS type device structure, the present invention also proposes a new high-low side integrated MOS type device. In the new high-low side integrated MOS type device, the second N+ low resistivity region is removed, and the Drain_down structure of the first N+ low resistivity region is changed to a conventional LDMOS structure. In addition to making ohmic contact with the second N+ source region and the second P+ low resistivity region through a through hole, the second metallized source also makes ohmic contact with the first N+ low resistivity region through a through hole at the same time, and the first metallized drain is removed. Other structures are the same as those of the above-mentioned high-low side integrated MOS type device.

[0058] In addition, based on the above-mentioned high-side and low-side integrated MOS type devices, the control circuit part can be further integrated with the high-side and low-side integrated MOS type devices to form an intelligent power switch.

[0059] Specifically, the high-side and low-side integrated MOS power switch includes a control circuit and high-side and low-side devices. The high-side and low-side devices and the control circuit are integrated on the same substrate and electrically connected; the control circuit includes a drive circuit for driving the high-side and low-side devices.

[0060] The high-side and low-side devices may be any one of the high-side and low-side integrated MOS devices described above.

[0061] The present invention integrates the control circuit part with the high-side and low-side integrated MOS type devices to form an intelligent power switch, which greatly reduces the area occupied by the PCB board, improves the integration level, and reduces transmission delay and electromagnetic interference.

[0062] The present invention has the following advantages:

[0063] As described above, the present invention provides a high-low side integrated MOS type device, which adopts a single-chip integration scheme, that is, two MOS devices are integrated on the same substrate, not only the two MOS devices are isolated by the dielectric isolation region, thereby resisting the lateral withstand voltage between the devices, but also the source of one MOS is connected to the drain of another MOS by the low resistance region or the metal routing, and the low resistivity region or the metal routing provides a low impedance channel, thereby realizing an efficient and compact series connection. On the basis of the above-mentioned high-low side integrated MOS type device, the control circuit and the low side integrated MOS type device improved by the present invention can be further integrated on the same substrate to form a high-low side integrated MOS type power switch, that is, an intelligent power switch, which reduces the area occupied by the chip on the PCB board, realizes high power density, reduces temperature fluctuations, reduces transmission delays, reduces electromagnetic interference and other problems. The single-chip integration scheme proposed by the present invention helps to realize efficient current control and switch management, especially in applications requiring high voltage and current control, such as BUCK circuits, BOOST circuits, and half-bridge circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 It is the structural diagram of BUCK circuit;

[0065] Figure 2 It is the structural diagram of BOOST circuit;

[0066] Figure 3 It is a structural schematic diagram of a half-bridge circuit;

[0067] Figure 4 This is a schematic diagram of the structure of a high-low side integrated MOS type device in Embodiment 1 of the present invention;

[0068] Figure 5 This is an equivalent structural diagram of the high-low side integrated MOS type device in Example 1 of the present invention;

[0069] Figure 6 It is a schematic diagram of the structure of the high-low side integrated MOS type device in Embodiment 2 of the present invention;

[0070] Figure 7 It is a schematic diagram of the structure of the high-low side integrated MOS type device in Example 3 of the present invention;

[0071] Figure 8 This is an equivalent structural diagram of the high-low side integrated MOS type device in Embodiment 3 of the present invention;

[0072] Fig. 9 It is a schematic diagram of the structure of the high-low side integrated MOS type device in Example 4 of the present invention;

[0073] Fig.10 This is a circuit module diagram of the high- and low-side integrated MOS power switch in Example 5 of the present invention. DETAILED DESCRIPTION

[0074] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0075] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0076] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0077] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0078] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0079] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0080] Example 1

[0081] In traditional MOS device-based electronic power circuits, the solution to achieve two MOS series configurations is to use packaging technology to package two independent MOSFETs into a single housing. The co-packaging technology requires two MOSFETs manufactured on different silicon wafers to be placed in the same package. Although the two devices can be placed together physically, they are still electrically independent and may be subject to electromagnetic interference from each other as well as challenges in thermal management and signal integrity.

[0082] This embodiment 1 proposes a high-low side integrated MOS type device, which integrates two MOS on the same substrate, and the source of LDMOS2 and the drain of LDMOS1 are connected through the P+ low resistivity region, while the traditional package integration is connected through welding wires. The single-chip integration scheme proposed by the present invention not only reduces the area, but also eliminates the welding wires and welding points between MOS, and reduces the additional inductance, capacitance and resistance. Integration can combine the advantages of the two devices, improve the working stability and strength of the device, improve the switching speed, reduce the conduction loss, improve the efficiency, etc., so that the device has better performance under high power, high frequency, high temperature and other working conditions. This structure adopts Source_down technology, and realizes the combination of vertical current and LDMOS lateral power MOSFET through the injection of P+ low resistivity region. The small Qg of the lateral device can enhance the driving ability, improve the conversion speed and response time; the vertical current can provide high current density, and the charge balance principle is used to realize high doping of N-drift region to obtain low on-resistance Ron. At the same time, the lateral device has a higher breakdown voltage and better frequency characteristics, has the excellent impedance performance of trench MOSFET technology, and maintains extremely low charge characteristics, which greatly improves switching loss and driving loss. This structure can improve energy utilization in high-power computing, networks, server systems and power supplies, and can provide a wide operating range on a chip. In addition, there is a dielectric isolation area in the structure, which can make the device cell area smaller. With the same chip area, the unit size is smaller, more units can be made, and the density of unit cells and channel units can be increased, further reducing the on-resistance and current density. If there is no dielectric isolation area, if you want to separate the device characteristics of LDMOS1 and LDMOS2 without affecting each other, there will be a certain distance of P-epitaxial layer between them to block, which will increase the cell area and increase the cost.

[0083] like Figure 4 As shown, the high-low-side integrated MOS device in this embodiment has a cell structure including a third metallized source 110, a P+ substrate 109 and a P- epitaxial layer 108 stacked in sequence from bottom to top.

[0084] A first trench 125 is disposed in the middle of the P-epitaxial layer 108 in the left-right direction. The first trench 125 is arranged longitudinally and extends downward from the upper surface of the P-epitaxial layer 108 to the upper surface of the P+ substrate 109 .

[0085] It should be noted that the left-right and up-down directions defined here are relative to the states shown in the drawings in order to more clearly illustrate the present invention, and the directions may be the same as or different from the actual directions.

[0086] The first trench 125 is filled with a dielectric material 120 to form a dielectric isolation region. In this embodiment, the dielectric material 220 is made of, for example, silicon dioxide, silicon nitride, aluminum oxide, borophosphosilicate glass, sapphire or hafnium oxide.

[0087] A third P+ low resistivity region 121 is disposed on the left side of the first trench 125 . The third P+ low resistivity region 121 is also arranged vertically and extends downward from the upper surface of the P− epitaxial layer 108 to the upper surface of the P+ substrate 109 .

[0088] The right side surface of the third P+ low-resistivity region 121 is in contact with the left side surface of the first trench 125 .

[0089] A first P-type base region 107 , a first N-drift region 123 and a first planar gate structure are disposed on the left side of the third P+ low resistivity region 121 ; the first P-type base region 107 and the first N-drift region 123 are both included in the P-epitaxial layer 108 .

[0090] The first P-type base region 107 and the first N-drift region 123 are both located at the top of the left region of the P-epitaxial layer 108 and the sides of the two are in contact with each other. The first P-type base region 107 is located on the left side of the first N-drift region 123. Figure 4 shown.

[0091] The left region of the P-epitaxial layer 108 refers to a region of the P-epitaxial layer 108 located on the left side of the third P+ low-resistivity region 121 .

[0092] The first P-type base region 107 includes a first P+ low resistivity region 106 and a first N+ source region 103 .

[0093] The first P+ low resistivity region 106 and the first N+ source region 103 are both located at the top left area of ​​the first P-type base region 107 and the sides of the two are in contact with each other. The first N+ source region 103 is located on the right side of the first P+ low resistivity region 106 .

[0094] The top right area of ​​the first P-type base region 107 is located between the right side of the first N+ source region 103 and the right side of the first P-type base region 107 , so that there is a certain distance between the first N+ source region 103 and the right side of the first P-type base region 107 .

[0095] The first N− drift region 123 includes a first N+ drain region 122 .

[0096] The first N+ drain region 122 is located at the top right region of the first N-drift region 123. The top left region of the first N-drift region 123 is located between the left side of the first N+ drain region 122 and the left side of the first N-drift region 123, so that there is a certain distance between the first N+ drain region 122 and the left side of the first N-drift region 123.

[0097] The right sides of the first N− drift region 123 and the first N+ drain region 122 are in contact with the left side of the third P+ low-resistivity region 121 .

[0098] The first planar gate structure is located above the left region of the P-epitaxial layer 108. More specifically, the first planar gate structure is located above the top right region of the first P-type base region 107. Figure 4 shown.

[0099] The first planar gate structure includes a first gate oxide layer 102 and a first gate electrode 101 .

[0100] The bottom surface of the first gate oxide layer 102 contacts the right portion of the top surface of the first N+ source region 103 , the top right region of the first P-type base region 107 , and the top left region of the first N− drift region 123 .

[0101] The first gate electrode 101 is located on the top surface of the first gate oxide layer 102 .

[0102] The first planar gate structure, the first P+ low resistivity region 106, the first N+ source region 103, the first N+ drain region 122, the first P-type base region 107, the first N-drift region 123, the P-epitaxial layer 108 and the P+ substrate 109 can constitute a lateral double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET), which can be referred to as LDMOS1, and in this embodiment refers to an N-channel LDMOS device.

[0103] A second P+ low resistivity region 119 is disposed on the right side of the first trench 125 . The second P+ low resistivity region 119 is also arranged vertically and extends downward from the upper surface of the P− epitaxial layer 108 to the upper surface of the P+ substrate 109 .

[0104] The left side surface of the second P+ low-resistivity region 119 and the right side surface of the first trench 125 are in contact with each other.

[0105] A second P-type base region 117 , a second N-drift region 112 and a second planar gate structure are disposed on the right side of the second P+ low resistivity region 119 . The second P-type base region 117 and the second N-drift region 112 are both included in the P-epitaxial layer 108 .

[0106] The second P-type base region 117 and the second N-drift region 112 are both located at the top of the right region of the P-epitaxial layer 108 and the sides of the two are in contact with each other. The second P-type base region 117 is located on the left side of the second N-drift region 112 .

[0107] The right region of the P-epitaxial layer 108 refers to a region of the P-epitaxial layer 108 located on the right side of the second P+ low-resistivity region 119 .

[0108] The second P-type base region 117 includes a second N+ source region 118 .

[0109] The second N+ source region 118 is located in the top left area of ​​the second P-type base region 117; the top right area of ​​the second P-type base region 117 is located between the right side surface of the second N+ source region 118 and the right side surface of the second P-type base region 117, so that there is a certain distance between the second N+ source region 118 and the right side surface of the second P-type base region 117.

[0110] The left sides of the second P-type base region 117 and the second N+ source region 118 are in contact with the right side of the second P+ low-resistivity region 119 .

[0111] The second N-drift region 112 includes a second N+ drain region 113 .

[0112] The second N+ drain region 113 is located in the top right area of ​​the second N-drift region 112; the top left area of ​​the second N-drift region 112 is located between the left side of the second N+ drain region 113 and the left side of the second N-drift region 112, so that there is a certain distance between the second N+ drain region 113 and the left side of the second N-drift region 112.

[0113] The second planar gate structure is located above the right region of the P-epitaxial layer 108. More specifically, the second planar gate structure is located above the top right region of the second P-type base region 117. Figure 4 shown.

[0114] The second planar gate structure includes a second gate oxide layer 116 and a second gate electrode 115 .

[0115] The bottom surface of the second gate oxide layer 116 contacts the right portion of the top surface of the second N+ source region 118 , the top right region of the second P-type base region 117 , and the top left region of the second N− drift region 112 .

[0116] The second gate electrode 115 is located on the top surface of the second gate oxide layer 116 .

[0117] The second planar gate structure, the second P+ low resistivity region 119, the second N+ source region 118, the second N+ drain region 113, the second P-type base region 117, the second N-drift region 112, the P-epitaxial layer 108 and the P+ substrate 109 can constitute a lateral double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET), which can be abbreviated as LDMOS2, and in this embodiment refers to an N-channel LDMOS device.

[0118] An insulating layer 124 is disposed above the P-epitaxial layer 108. In this embodiment, the insulating layer 124 may be made of, for example, borophosphosilicate glass, silicon dioxide, benzocyclobutene, aluminum oxide, sapphire, or hafnium oxide.

[0119] A first metallized source 104, a first metallized drain 126, a second metallized source 127, and a second metallized drain 114 are provided above the insulating layer 124. The first metallized source 104 is located above the first P+ low resistivity region 106 and the first N+ source region 103; the first metallized drain 126 is located above the first N+ drain region 122 and the third P+ low resistivity region 121; the second metallized source 127 is located above the second P+ low resistivity region 119 and the second N+ source region 118; and the second metallized drain 114 is located above the second N+ drain region 113.

[0120] A through hole 105 is provided in the insulating layer 124. Figure 4 As shown. The first metallized source 104 is in ohmic contact with the first P+ low resistivity region 106 and the first N+ source region 103 through the through hole 105; the first metallized drain 126 is in ohmic contact with the first N+ drain region 122 and the third P+ low resistivity region 121 through the through hole 105; the second metallized source 127 is in ohmic contact with the second P+ low resistivity region 119 and the second N+ source region 118 through the through hole 105; the second metallized drain 114 is in ohmic contact with the second N+ drain region 113 through the through hole 105. It should be noted that the present embodiment does not specifically limit the number of through holes 105.

[0121] For example, the first metallized source 104 can make ohmic contact with the first P+ low resistivity region 106 and the first N+ source region 103 through two through holes 105, such as Figure 4 Of course, the first metallized source 104 can also make ohmic contact with the first P+ low resistivity region 106 and the first N+ source region 103 through a through hole 105 at the same time.

[0122] Similarly, the first metallized drain electrode 126 can make ohmic contact with the first N+ drain region 122 and the third P+ low resistivity region 121 through the two through holes 105, such as Figure 4 Of course, the first metallized drain 126 can also make ohmic contact with the first N+ drain region 122 and the third P+ low resistivity region 121 simultaneously through a through hole 105 .

[0123] Similarly, the second metallized source 127 can also make ohmic contacts with the second P+ low resistivity region 119 and the second N+ source region 118 respectively through the two through holes 105, such as Figure 4 Of course, the second metallized source 127 can also make ohmic contact with the second P+ low resistivity region 119 and the second N+ source region 118 simultaneously through a through hole 105 .

[0124] In this embodiment, the metallized pins, the third metallized source 110 , the first metallized source 104 , the first metallized drain 126 , the second metallized source 127 and the second metallized drain 114 are made of one or more of aluminum, copper, gold or silver.

[0125] like Figure 4 As shown, the left part of the structure in this embodiment is an LDMOS1 structure composed of a first planar gate structure, a first P+ low resistivity region 106, a first N+ source region 103, a first N+ drain region 122, a first P-type base region 107, a first N-drift region 123, a P-epitaxial layer 108 and a P+ substrate 109, and the right part is an LDMOS2 structure composed of a second planar gate structure, a second P+ low resistivity region 119, a second N+ source region 118, a second N+ drain region 113, a second P-type base region 117, a second N-drift region 112, a P-epitaxial layer 108 and a P+ substrate 109. The present invention isolates two MOSs through a dielectric isolation region to withstand lateral withstand voltage between devices. The third P+ low resistivity region 121 and the first N+ drain region 122 are connected by a through hole to form an equipotential. The third P+ low resistivity region 121 and the P+ substrate 109 are in direct ohmic contact. The third P+ low resistivity region 121 provides a low impedance channel to achieve efficient and compact series connection.

[0126] It should be noted that the second P+ low resistivity region 119 and the third P+ low resistivity region 121 have different functions. The second P+ low resistivity region 119 is a part of LDMOS2. In this embodiment, LDMOS2 adopts a Source_down structure to transfer the lateral current to the longitudinal current, which can increase the current density and make it have the advantage of strong current capacity of the longitudinal device. By using the charge balance principle, the N-drift region is highly doped to obtain low Ron.

[0127] The equivalent structure of the high and low side integrated MOS type device in this embodiment is as follows: Figure 5 Wherein, M1 is LDMOS2, M2 is LDMOS1, D1 is the second metallized drain 114, G1 is the second gate electrode 115, S1 (D2) is the third metallized source 110, G2 is the first gate electrode 101, and S2 is the first metallized source 104.

[0128] The working mode of the structure in this embodiment is to control the gates of LDMOS1 and LDMOS2 respectively through an external control circuit so that they are switched alternately to achieve the purpose of power conversion. The output port of the structure is the third metallized source 110 of LDMOS2. At this time, the first metallized drain 126 of LDMOS1 is only used as an electrical connection bridge between the third P+ low resistivity region 121 and the drain region of LDMOS1 (i.e., the first N+ drain region 122). The second metallized source 127 of LDMOS2 is only used as an electrical connection bridge between the second P+ low resistivity region 119 and the source region of LDMOS2 (i.e., the second N+ source region 118), and does not need to be led out.

[0129] A dielectric isolation region is set between LDMOS1 and LDMOS2. When LDMOS2 is turned on and LDMOS1 is turned off, the source region of LDMOS2 is at a high potential, which is potentially harmful to the device of LDMOS1. The dielectric isolation region can withstand lateral voltage to ensure the reliability of the structure. If there is no dielectric isolation region, the two devices need to be separated by a certain distance and use the P-epitaxial layer for lateral voltage withstand, which will result in a larger lateral area of ​​the cell. The presence of the trench dielectric greatly reduces the cell area and achieves high power density. A P+ low resistivity region is set between LDMOS1 and LDMOS2 to provide a low impedance channel, converting the horizontal current of LDMOS1 into a vertical current, which not only enhances the current capacity, but also realizes efficient and compact series connection.

[0130] The formation process of the conduction channel of LDMOS1 in this embodiment is as follows:

[0131] When a voltage with correct polarity and a value greater than the threshold voltage of LDMOS1 is applied to the first gate electrode 101, a conductive channel will be formed under the first gate electrode 101. The conductive channel is located in the top right area of ​​the first P-type base region 107 and contacts the lower surface of the first gate oxide layer 102. The left side of the conductive channel contacts the right side of the first N+ source region 103, and the right side of the conductive channel contacts the right side of the first P-type base region 107. Charge carriers can migrate between the source region and the drain region through the conductive channel, thereby realizing the conduction of LDMOS1.

[0132] The formation process of the conduction channel of LDMOS2 in this embodiment is as follows:

[0133] When a voltage with correct polarity and a value greater than the threshold voltage of LDMOS2 is applied to the second gate electrode 115, a conductive channel will be formed under the second gate electrode 115. The conductive channel is located in the top right area of ​​the second P-type base region 117 and contacts the lower surface of the second gate oxide layer 116. The left side of the conductive channel contacts the right side of the second N+ source region 118, and the right side of the conductive channel contacts the right side of the second P-type base region 117. Charge carriers can migrate between the source region and the drain region through the conductive channel, thereby achieving conduction of LDMOS2.

[0134] The present invention integrates two LDMOS on the same substrate. The LDMOS has a higher breakdown voltage and better frequency characteristics. At the same time, the upper tube LDMOS2 also has the advantage of a strong current capability of a longitudinal device. The on-resistance of the upper tube is lower than that of the lower tube LDMOS1. The LDMOS2 can better withstand the high voltage from the load, thereby improving the withstand voltage and current capability of the entire series structure, more effectively realizing the switching operation, and reducing the conduction loss under high voltage. Both LDMOS1 and LDMOS2 can have a good withstand voltage capability by adopting a surface field reduction technology in an N-drift region, and can better withstand high voltage.

[0135] The present invention is a single-chip integrated solution, which eliminates the welding line between LDMOS1 and LDMOS2, greatly reduces the welding points and wiring length, reduces the parasitic effects caused by parasitic inductance, capacitance, and resistance, improves system reliability, increases switching speed, and reduces signal transmission delay, power loss, electromagnetic interference, etc. When LDMOS1 and LDMOS2 work normally, the temperature of the chip will increase when it is turned on, and the temperature will decrease when it is turned off. Since the present invention adopts a single-chip integrated solution, the two MOSs are very close, the temperature distribution is relatively uniform, and the fluctuation is small, so that the reliability of the chip will be greatly improved.

[0136] Example 2

[0137] This embodiment 2 describes a high-low side integrated MOS type device. Except for the following technical features that are different from the above embodiment 1, the other technical features of the high-low side integrated MOS type device can refer to the above embodiment 1.

[0138] This embodiment 2 provides a new high-low side integrated MOS type device structure. Unlike the above embodiment 1, this structure connects the source of LDMOS2 and the drain of LDMOS1 through metal wiring to realize the series configuration of two MOS. The scheme of realizing the series configuration of two MOSFETs through metal connection in this embodiment 2 is consistent with the structure and working principle of the above embodiment 1, which simplifies the design and manufacturing process and has more specific performance. Because LDMOS is suitable for high voltage and high frequency applications, the two LDMOS are integrated together to focus more on these application areas rather than providing a wide working range. This structure uses a P-type substrate. The LDMOS device of the P substrate performs well in power switch applications, can improve the voltage anti-interference ability of the device, and reduce the sensitivity of the device to interference and noise. With the continuous development and improvement of manufacturing processes, the manufacturing process of P-substrate LDMOS has been strengthened and optimized, making it easier to produce high-performance and stable P-substrate LDMOS devices.

[0139] like Figure 6 As shown, based on the high-low side integrated MOS device structure in the above-mentioned embodiment 1, the present embodiment 2 makes the following improvements to the high-low side integrated MOS device structure: the third P+ low resistivity region 121 is removed, the first metallized drain 126 and the second metallized source 127 are merged into the second metallized source 127, the Source_down structure of the second P+ low resistivity region 119 is changed to a conventional LDMOS structure, the third metallized source 110 is removed, and the other structures are the same as those of the high-low side integrated MOS device in the above-mentioned embodiment 1.

[0140] Specifically, a second P-type base region 117 , a second N-drift region 112 and a second planar gate structure are disposed on the right side of the first trench 125 ; the second P-type base region 117 and the second N-drift region 112 are both included in the P-epitaxial layer 108 .

[0141] The second P-type base region 117 and the second N-drift region 112 are both located at the top of the right region of the P-epitaxial layer 108 and the sides of the two are in contact with each other. The second P-type base region 117 is located on the left side of the second N-drift region 112 .

[0142] The second P-type base region 117 includes a second N+ source region 118 and a second P+ low resistivity region 119 .

[0143] The second N+ source region 118 and the second P+ low resistivity region 119 are both located at the top left area of ​​the second P-type base region 117 and the sides of the two are in contact with each other. The second N+ source region 118 is located on the right side of the second P+ low resistivity region 119 .

[0144] The top right area of ​​the second P-type base region 117 is located between the right side surface of the second N+ source region 118 and the right side surface of the second P-type base region 117 , so that there is a certain distance between the second N+ source region 118 and the right side surface of the second P-type base region 117 .

[0145] The second metallized source 127 is located above the first N+ drain region 122, the second P+ low resistivity region 119 and the second N+ source region 118, and the second metallized source 127 simultaneously makes ohmic contact with the first N+ drain region 122, the second P+ low resistivity region 119 and the second N+ source region 118 through the through hole 105. Similarly, the present embodiment does not specifically limit the number of through holes 105.

[0146] The right side surface of the first N-drift region 123 contacts the left side surface of the first trench 125. The left side surface of the second P-type base region 117 contacts the right side surface of the first trench 125.

[0147] It should be noted here that the process of forming the conduction channels of LDMOS1 and LDMOS2 in the second embodiment is the same as the process of forming the conduction channels of LDMOS1 and LDMOS2 in the first embodiment, and will not be described in detail here.

[0148] In the present embodiment 2, the drain region of LDMOS1 (i.e., the first N+ drain region 122) and the source region of LDMOS2 (the second N+ source region 118 and the second P+ low resistivity region 119) are electrically connected through metal wiring, and the third P+ low resistivity region 121 and the third metallized source 110 that can provide vertical current are removed. The output port of the structure is the second metallized source 127 of LDMOS2, so that the cell area is further reduced, the manufacturing process is simpler, and the cost is lower when certain conditions can be met.

[0149] Example 3

[0150] In traditional MOS device-based electronic power circuits, the solution to achieve two MOS series configurations is to use packaging technology to package two independent MOSFETs into a single housing. The co-packaging technology requires two MOSFETs manufactured on different silicon wafers to be placed in the same package. Although the two devices can be placed together physically, they are still electrically independent and may be subject to electromagnetic interference from each other as well as challenges in thermal management and signal integrity.

[0151] This embodiment 3 proposes a high-low side integrated MOS type device, which integrates two MOS on the same substrate. In this structure, the source of LDMOS2 and the drain of LDMOS1 are connected through the N+ low resistivity region to realize the series configuration of the two MOS, and the package integration is connected through welding wires. The single chip integration proposed by the present invention not only reduces the area, but also eliminates the welding wires and welding points between MOS, reducing the additional inductance, capacitance and resistance. Integration can combine the advantages of the two devices, improve the working stability and strength of the device, improve the switching speed, reduce the conduction loss, improve the efficiency, etc., so that the device has better performance under high power, high frequency, high temperature and other working conditions. The combination of vertical current and LDMOS lateral power MOSFET is realized by the injection of N+ low resistivity region. The small Qg of the lateral device can enhance the driving ability, improve the conversion speed and response time; the vertical current can provide high current density, and the charge balance principle is used to realize high doping of N-drift region to obtain low on-resistance Ron. At the same time, the lateral device has a higher breakdown voltage and better frequency characteristics, has the excellent impedance performance of trench MOSFET technology, and maintains extremely low charge characteristics, which greatly improves switching loss and driving loss. This structure can improve energy utilization in high-power computing, networks, server systems and power supplies, and can provide a wide operating range on a chip. In addition, the structure has a dielectric isolation area, which can make the device cell area smaller. With the same chip area, the unit size is smaller, more units can be made, and the unit cell and channel unit density can be increased, further reducing the on-resistance and current density. If there is no dielectric isolation area, if you want to separate the device characteristics of LDMOS1 and LDMOS2 without affecting each other, there will be a certain distance between them. The P-deep well area will block it, which will increase the cell area and increase the cost.

[0152] like Figure 7 As shown, in the high-low-side integrated MOS device in this embodiment, its cell structure includes a first metallized drain 210, an N+ substrate 209 and a P-deep well region 208 stacked in sequence from bottom to top.

[0153] A first trench 225 is disposed in the middle of the P-deep well region 208 in the left-right direction. The first trench 225 is arranged longitudinally and extends downward from the upper surface of the P-deep well region 208 to the upper surface of the N+ substrate 209 .

[0154] It should be noted that the left-right and up-down directions defined here are relative to the states shown in the drawings in order to more clearly illustrate the present invention, and the directions may be the same as or different from the actual directions.

[0155] The first trench 225 is filled with a dielectric material 220 to form a dielectric isolation region. In this embodiment, the dielectric material 220 is made of, for example, silicon dioxide, silicon nitride, aluminum oxide, borophosphosilicate glass, sapphire or hafnium oxide.

[0156] A first N+ low resistivity region 222 is disposed on the left side of the first trench 225 . The first N+ low resistivity region 222 is also arranged vertically and extends downward from the upper surface of the P-deep well region 208 to the upper surface of the N+ substrate 209 .

[0157] The right side surface of the first N+ low-resistivity region 222 is in contact with the left side surface of the first trench 225 .

[0158] The first P-type base region 207 , the first N− drift region 223 and the first planar gate structure are disposed on the left side of the first N+ low resistivity region 222 ; the first P-type base region 207 and the first N− drift region 223 are both contained in the P− deep well region 208 .

[0159] The first P-type base region 207 and the first N-drift region 223 are both located at the top of the left area of ​​the P-deep well region 208 and their sides are in contact with each other. The first P-type base region 207 is located on the left side of the first N-drift region 223 .

[0160] The right side surface of the first N − drift region 223 and the left side surface of the first N + low-resistivity region 222 are in contact with each other.

[0161] The left region of the P-deep well region 208 refers to the region of the P-deep well region 208 located on the left side of the first N+ low resistivity region 222 .

[0162] The first P-type base region 207 includes a first P+ low resistivity region 206 and a first N+ source region 203 .

[0163] The first P+ low resistivity region 206 and the first N+ source region 203 are both located at the top left area of ​​the first P-type base region 207 and the sides of the two are in contact with each other. The first P+ low resistivity region 206 is located on the left side of the first N+ source region 203 .

[0164] The top right area of ​​the first P-type base region 207 is located between the right side of the first N+ source region 203 and the right side of the first P-type base region 207 , so that there is a certain distance between the first N+ source region 203 and the right side of the first P-type base region 207 .

[0165] The first planar gate structure is located above the left region of the P-deep well region 208 . More specifically, the first planar gate structure is located above the top right region of the first P-type base region 207 .

[0166] The first planar gate structure includes a first gate oxide layer 202 and a first gate electrode 201 .

[0167] The bottom surface of the first gate oxide layer 202 contacts the right portion of the top surface of the first N+ source region 203 , the top right region of the first P-type base region 207 , and the left portion of the top surface of the first N− drift region 223 .

[0168] The first gate electrode 201 is located on the top surface of the first gate oxide layer 202 .

[0169] The first planar gate structure, the first P+ low resistivity region 206, the first N+ source region 203, the first N+ low resistivity region 222, the first P-type base region 207, the first N-drift region 223, the P-deep well region 208 and the N+ substrate 209 can constitute a lateral double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET), which can be referred to as LDMOS1, and in this embodiment refers to an N-channel LDMOS device.

[0170] A second N+ low resistivity region 221 is disposed on the right side of the first trench 225 . The second N+ low resistivity region 221 is also arranged vertically and extends downward from the upper surface of the P-deep well region 208 to the upper surface of the N+ substrate 209 .

[0171] The left side surface of the second N+ low-resistivity region 221 is in contact with the right side surface of the first trench 225 .

[0172] A second P-type base region 217 , a second N− drift region 212 and a second planar gate structure are disposed on the right side of the second N+ low resistivity region 221 ; the second P-type base region 217 and the second N− drift region 212 are both included in the P− deep well region 208 .

[0173] The second P-type base region 217 and the second N-drift region 212 are both located at the top of the right area of ​​the P-deep well region 208 and the sides of the two are in contact with each other. The second P-type base region 217 is located on the left side of the second N-drift region 212 .

[0174] The right region of the P-deep well region 208 refers to the region of the P-deep well region 208 located on the right side of the second N+ low resistivity region 221 .

[0175] The second P-type base region 217 includes a second N+ source region 218 and a second P+ low resistivity region 219 .

[0176] The second N+ source region 218 and the second P+ low resistivity region 219 are both located at the top left area of ​​the second P-type base region 217 and the sides of the two are in contact with each other. The second N+ source region 218 is located on the right side of the second P+ low resistivity region 219 .

[0177] The left sides of the second P+ low-resistivity region 219 and the second P-type base region 217 are in contact with the right side of the second N+ low-resistivity region 221 .

[0178] The top right area of ​​the second P-type base region 217 is located between the right side surface of the second N+ source region 218 and the right side surface of the second P-type base region 217 , so that there is a certain distance between the second N+ source region 218 and the right side surface of the second P-type base region 217 .

[0179] The second N-drift region 212 includes a second N+ drain region 213 .

[0180] The second N+ drain region 213 is located in the top right area of ​​the second N-drift region 212; the top left area of ​​the second N-drift region 212 is located between the left side of the second N+ drain region 213 and the left side of the second N-drift region 212, so that there is a certain distance between the second N+ drain region 213 and the left side of the second N-drift region 212.

[0181] The second planar gate structure is located above the right region of the P-deep well region 208 . More specifically, the second planar gate structure is located above the top right region of the second P-type base region 217 .

[0182] The second planar gate structure includes a second gate oxide layer 216 and a second gate electrode 215 .

[0183] The bottom surface of the second gate oxide layer 216 contacts the right portion of the top surface of the second N+ source region 218 , the top right region of the second P-type base region 217 , and the top left region of the second N− drift region 212 .

[0184] The second gate electrode 215 is located on the top surface of the second gate oxide layer 216 .

[0185] The second planar gate structure, the second P+ low resistivity region 219, the second N+ source region 218, the second N+ drain region 213, the second P-type base region 217, the second N-drift region 212, the P-deep well region 208 and the N+ substrate 209 can constitute a lateral double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET), which can be abbreviated as LDMOS2, and in this embodiment refers to an N-channel LDMOS device.

[0186] An insulating layer 224 is disposed above the P-deep well region 208. The insulating layer 224 in this embodiment is made of, for example, borophosphosilicate glass, silicon dioxide, benzocyclobutene, aluminum oxide, sapphire or hafnium oxide.

[0187] like Figure 7 As shown, a first metallized source 204, a second metallized source 226, and a second metallized drain 214 are provided above the insulating layer 224. The first metallized source 204 is located above the first P+ low resistivity region 206 and the first N+ source region 203, the second metallized source 226 is located above the second N+ low resistivity region 221, the second N+ source region 218, and the second P+ low resistivity region 219, and the second metallized drain 214 is located above the second N+ drain region 213.

[0188] A through hole 205 is provided in the insulating layer 224. The first metallized source 204 is in ohmic contact with the first P+ low resistivity region 206 and the first N+ source region 203 through the through hole 205; the second metallized source 226 is in ohmic contact with the second N+ low resistivity region 221, the second N+ source region 218 and the second P+ low resistivity region 219 through the through hole 205; the second metallized drain 214 is in ohmic contact with the second N+ drain region 213 through the through hole 205. The number of the through holes 205 is not specifically limited in this embodiment.

[0189] For example, the first metallized source 204 makes ohmic contact with the first P+ low resistivity region 206 and the first N+ source region 203 respectively through two through holes 205. Figure 7 Of course, the first metallized source 204 can also make ohmic contact with the first P+ low resistivity region 206 and the first N+ source region 203 through a through hole 205 at the same time.

[0190] Similarly, the second metallized source 226 makes ohmic contact with the second N+ low resistivity region 221, the second N+ source region 218 and the second P+ low resistivity region 219 respectively through the three through holes 205. Figure 7 Of course, the second metallized source 226 can also simultaneously make ohmic contact with the second N+ low resistivity region 221 , the second N+ source region 218 and the second P+ low resistivity region 219 through a through hole 205 .

[0191] In this embodiment, the metallized pins, the first metallized drain 210 , the first metallized source 204 , the second metallized source 226 , and the second metallized drain 214 are made of one or more of aluminum, copper, gold, or silver.

[0192] like Figure 7As shown, the left part of the structure in this embodiment is an LDMOS1 structure composed of a first planar gate structure, a first P+ low resistivity region 206, a first N+ source region 203, a first N+ low resistivity region 222, a first P-type base region 207, a first N-drift region 223, a P-deep well region 208 and an N+ substrate 209, and the right part is an LDMOS2 structure composed of a second planar gate structure, a second P+ low resistivity region 219, a second N+ source region 218, a second N+ drain region 213, a second P-type base region 217, a second N-drift region 212, a P-deep well region 208 and an N+ substrate 209. The present invention isolates two MOSs through a dielectric isolation region to withstand lateral withstand voltage between devices. The second N+ low resistivity region 221, the second P+ low resistivity region 219, and the second N+ source region 218 are connected by through holes to form equipotential. The second N+ low resistivity region 221 and the N+ substrate 209 are in direct ohmic contact. The second N+ low resistivity region 221 provides a low impedance channel to achieve efficient and compact series connection.

[0193] It should be noted here that the first N+ low resistivity region 222 and the second N+ low resistivity region 221 have different functions. The first N+ low resistivity region 222 is a part of LDMOS1. LDMOS1 adopts a Drain_down structure to transfer the lateral current to the longitudinal current, which can increase the current density and make it have the advantage of strong current capacity of the longitudinal device. By using the charge balance principle, the N-drift region is highly doped to obtain low Ron.

[0194] The equivalent structure of the high and low side integrated MOS type device in this embodiment is as follows: Figure 8 Wherein, M1 is LDMOS2, M2 is LDMOS1, D1 is the second metallized drain 214, G1 is the second gate electrode 215, S1 (D2) is the first metallized drain 210, G2 is the first gate electrode 201, and S2 is the first metallized source 204.

[0195] The working mode of the structure in this embodiment is to control the gates of LDMOS1 and LDMOS2 respectively through an external control circuit so that they are switched alternately to achieve the purpose of power conversion. The output port of the structure is the first metallized drain 210 of LDMOS1. At this time, the second metallized source 226 of LDMOS2 is only used as an electrical connection bridge between the second N+ low resistivity region 221 and the source region of LDMOS2 (i.e., the second N+ source region 218 and the second P+ low resistivity region 219), and no lead is required. A dielectric isolation region is set between LDMOS1 and LDMOS2. When LDMOS2 is turned on and LDMOS1 is turned off, the source region of LDMOS2 is at a high potential, which is potentially harmful to the device of LDMOS1. The dielectric isolation region can withstand lateral pressure to ensure the reliability of the structure. If there is no dielectric isolation region, the two devices need to be separated by a certain distance and use the P-deep well region for lateral pressure resistance, which will result in a larger lateral area of ​​the cell. The presence of the trench dielectric greatly reduces the cell area and achieves high power density. In addition, a second N+ low resistivity region 221 is provided between LDMOS1 and LDMOS2 to provide a low impedance channel and convert the horizontal current of LDMOS2 into a vertical current, which not only enhances the current capability but also realizes an efficient and compact series connection.

[0196] The formation process of the conduction channel of LDMOS1 in this embodiment is as follows:

[0197] When a voltage with correct polarity and a value greater than the threshold voltage of LDMOS1 is applied to the first gate electrode 201, a conductive channel will be formed under the first gate electrode 201. The conductive channel is located in the top right area of ​​the first P-type base region 207 and contacts the lower surface of the first gate oxide layer 202. The left side of the conductive channel contacts the right side of the first N+ source region 203, and the right side of the conductive channel contacts the right side of the first P-type base region 207. Charge carriers can migrate between the source region and the drain region through the conductive channel, thereby achieving conduction of LDMOS1.

[0198] The formation process of the conduction channel of LDMOS2 in this embodiment is as follows:

[0199] When a voltage with correct polarity and a value greater than the threshold voltage of LDMOS2 is applied to the second gate electrode 215, a conductive channel will be formed under the second gate electrode 215. The conductive channel is located in the top right area of ​​the second P-type base region 217 and contacts the lower surface of the second gate oxide layer 216. The left side of the conductive channel contacts the right side of the second N+ source region 218, and the right side of the conductive channel contacts the right side of the second P-type base region 217. Charge carriers can migrate between the source region and the drain region through the conductive channel, thereby achieving conduction of LDMOS2.

[0200] The present invention integrates two LDMOS on the same substrate. The LDMOS has a higher breakdown voltage and better frequency characteristics. Meanwhile, the lower tube LDMOS1 also has the advantage of a strong current capability of a longitudinal device. Therefore, the on-resistance of the lower tube is lower than that of the upper tube LDMOS2. The LDMOS1 has a better discharge capability and reduces the conduction loss. Both the LDMOS1 and the LDMOS2 can have a good withstand voltage capability by adopting a surface field reduction technology in an N-drift region, and can better withstand high voltage.

[0201] The present invention is a single-chip integrated solution, which eliminates the welding line between LDMOS1 and LDMOS2, greatly reduces the welding points and wiring length, reduces the parasitic effects caused by parasitic inductance, capacitance, and resistance, improves system reliability, increases switching speed, and reduces signal transmission delay, power loss, electromagnetic interference, etc. When LDMOS1 and LDMOS2 work normally, the temperature of the chip will increase when it is turned on, and the temperature will decrease when it is turned off. Since the present invention adopts a single-chip integrated solution, the two MOSs are very close, the temperature distribution is relatively uniform, the fluctuation is small, and the reliability of the chip will be greatly improved.

[0202] The single-chip integration solution proposed in the present invention integrates two MOS devices on the same substrate, isolates the two MOS through a dielectric isolation region to withstand lateral voltage between the devices, and connects the source of one MOS to the drain of the other through a second N+ low resistivity region 221. The second N+ low resistivity region 221 provides a low impedance channel to achieve efficient and compact series connection, thereby reducing the chip's occupied area, achieving high power density, reducing temperature fluctuations, reducing transmission delays, reducing electromagnetic interference, etc.

[0203] Example 4

[0204] This embodiment 4 describes a high-low side integrated MOS type device. Except for the following technical features that are different from those of the above embodiment 3, the remaining technical features of the high-low side integrated MOS type device can refer to those of the above embodiment 3.

[0205] This embodiment 4 provides a new high-low side integrated MOS device structure. Different from the above embodiment 3, the structure connects the source of LDMOS2 and the drain of LDMOS1 through metal wiring, and realizes the series configuration of two MOSFETs through metal connection. Their structures and working principles are consistent, simplifying the design and manufacturing process, and the performance is more specific. Because LDMOS is suitable for high voltage and high frequency applications, the two LDMOS are integrated together to focus more on these application areas, rather than providing a wide range of working conditions. The structure uses an N-type substrate. N-substrate LDMOS shows good stability and reliability under some conditions, especially under high temperature and radiation environments, and can also improve the current transmission capacity of the device, increase the response speed and working efficiency of the device.

[0206] like Fig. 9 As shown, based on the high-low side integrated MOS device structure in the above-mentioned embodiment 3, the present embodiment 4 makes the following improvements to the high-low side integrated MOS device structure: the second N+ low resistivity region 221 is removed, the Drain_down structure of the first N+ low resistivity region 222 is changed to a conventional LDMOS structure, the second metallized source 226 makes ohmic contact with the second N+ source region 218 and the second P+ low resistivity region 219 through the through hole, and also makes ohmic contact with the first N+ low resistivity region 222 through the through hole, the first metallized drain 210 is removed, and other structures can refer to the structure of the high-low side integrated MOS device in the above-mentioned embodiment 3.

[0207] Specifically, a first P-type base region 207 , a first N-drift region 223 and a first planar gate structure are disposed on the left side of the first trench 225 ; the first P-type base region 207 and the first N-drift region 223 are both included in the P-deep well region 208 .

[0208] The first P-type base region 207 and the first N-drift region 223 are both located at the top of the left region of the P-deep well region 208 and their sides are in contact with each other. The first P-type base region 207 is located at the left side of the first N-drift region 223 .

[0209] The first N− drift region 223 includes a first N+ low resistivity region 222 .

[0210] The first N+ low resistivity region 222 is located in the top right area of ​​the first N-drift region 223, and the top left area of ​​the first N-drift region 223 is located between the left side of the first N+ low resistivity region 222 and the left side of the first N-drift region 223, so that there is a certain distance between the first N+ low resistivity region 222 and the left side of the first N-drift region 223.

[0211] The right side surface of the first N-drift region 223 and the left side surface of the first trench 225 are in contact with each other.

[0212] The first planar gate structure includes a first gate oxide layer 202 and a first gate electrode 201 .

[0213] The bottom surface of the first gate oxide layer 202 contacts the right portion of the top surface of the first N+ source region 203 , the top right region of the first P-type base region 207 , and the top left region of the first N− drift region 223 .

[0214] The left side surface of the second P-type base region 217 is in contact with the right side surface of the first trench 225 .

[0215] The second metallized source 226 is located above the second N+ source region 218, the second P+ low resistivity region 219 and the first N+ low resistivity region 222, and the second metallized source 226 simultaneously makes ohmic contact with the second N+ source region 218, the second P+ low resistivity region 219 and the first N+ low resistivity region 222 through the through hole 205.

[0216] Similarly, this embodiment does not impose any specific limitation on the number of through holes 205 .

[0217] It should be noted that the process of forming the conduction channels of LDMOS1 and LDMOS2 in the fourth embodiment is the same as the process of forming the conduction channels of LDMOS1 and LDMOS2 in the third embodiment, and will not be described in detail here.

[0218] The drain region of LDMOS1 (i.e., the first N+ low resistivity region 222) and the source region of LDMOS2 (i.e., the second N+ source region 218 and the second P+ low resistivity region 219) are electrically connected through metal wiring, and the second N+ low resistivity region 221 and the first metallized drain 210 that can provide vertical current are removed. The output port of this structure is the second metallized source 226 of LDMOS2, which further reduces the cell area, simplifies the manufacturing process, and reduces the cost when certain conditions are met.

[0219] although Figure 4 , Figure 6 , Figure 7 , Fig. 9 , the manufactured semiconductor device is shown as an N-channel LDMOS device, but the semiconductor device can also be manufactured as a P-channel LDMOS device, which will not be repeated here.

[0220] The single-chip integrated structure proposed by the present invention aims at some problems caused by two power MOSFET switches in traditional electronic power circuits based on MOS devices such as BUCK, BOOST and half-bridge. Compared with traditional package integration, it has the following advantages:

[0221] 1. Small size helps save PCB space, improve system integration and power density. At the same time, single-chip integration allows two LDMOS to be very close, and the temperature distribution during alternating operation is more uniform, the temperature fluctuation will be relatively small, and the chip reliability will be improved.

[0222] 2. The welding lines and welding points between MOS are eliminated, and the drain of LDMOS1 and the source of LDMOS2 are connected by low resistivity area or metal routing, which reduces the additional inductance, capacitance and resistance, not only improving the reliability and stability of the system, but also reducing transmission delay and power loss. In addition, since the entire power MOSFET circuit is integrated on a chip, it can also reduce the defects and damage that may occur during the packaging process.

[0223] 3. Performance matching: Integrating two LDMOS together can ensure that their performance is very close, which is very important in push-pull or bridge-tied load configurations, because such configurations require the performance of the two transistors to match as much as possible.

[0224] 4. Simplified design: Integrating two LDMOS transistors onto a single chip can simplify the circuit design and assembly process. Designers do not need to select and match two separate transistors, which can reduce design complexity and speed up the development process.

[0225] 5. Integrated LDMOS can more easily work with other system-level components, such as control logic, drive circuits, and protection circuits, thereby improving the performance and reliability of the overall circuit.

[0226] The present invention integrates two MOSFETs into a single silicon chip to form a compact single-chip solution. The two MOSFETs are configured in series in the circuit, which helps to achieve efficient current control and switch management, especially in applications requiring high voltage and current control, such as BUCK circuits, BOOST circuits, and half-bridge circuits.

[0227] Example 5

[0228] This embodiment 5 describes a high-side and low-side integrated MOS power switch, which includes a control circuit and high-side and low-side devices. The high-side and low-side devices and the control circuit are integrated on the same substrate and electrically connected to form an intelligent power switch.

[0229] The high-side and low-side devices are high-side and low-side integrated MOS devices as in the above embodiments 1, 2 or 3.

[0230] The control circuit of the high-side and low-side integrated MOS power switch described in this embodiment includes a logic circuit, a protection circuit and a drive circuit, wherein the drive circuit is a high-side and low-side device drive circuit for driving high-side and low-side devices.

[0231] like Fig.10 A circuit module diagram of a high-low-side integrated MOS power switch is described, wherein the output devices described are high- and low-side devices, including a high-side device 42 and a low-side device 43 .

[0232] This device schematic depicts a pair of N-channel MOSFET devices used as output devices.

[0233] In one embodiment of the device of the present invention, in the high-low-side integrated MOS power switch circuit, the high-side device 42 is, for example, an LDMOS MOSFET, and the low-side device 43 is also an LDMOS MOSFET.

[0234] The logic circuit includes a Schmitt trigger 30 and a logic and interlock circuit 32 .

[0235] The Schmitt trigger 30 is used to be compatible with a 3.3V or 5V input signal provided by a CPU or a DSP.

[0236] The logic and interlock circuit 32 is used to prevent the two MOS from being turned on at the same time and causing a shoot-through phenomenon, thereby damaging the transistor. It also performs logical judgment on the output signals of the remaining protection modules. If a fault occurs, the MOS tube will be turned off and a fault signal FO will be output.

[0237] The protection circuit includes a low-side undervoltage protection circuit 31 , an overtemperature protection circuit 35 , an overcurrent protection circuit 36 ​​, an open circuit protection circuit 37 and a high-side undervoltage protection circuit 39 .

[0238] The over-temperature protection circuit 35 is used to prevent the chip temperature from being too high and damaging the device. If it exceeds the set threshold, the transistor will be turned off.

[0239] The overcurrent protection circuit 36 ​​is used to prevent the transistor from being damaged by excessive current. If the current exceeds the set threshold, the threshold current will be maintained or the transistor will be turned off. The open circuit protection circuit 37 is used to detect whether the load is working properly.

[0240] The low-side undervoltage protection circuit 31 and the high-side undervoltage protection circuit 39 are used to detect whether the VCC voltage and the BOOT voltage are lower than the threshold value of normal operation to prevent functional errors caused by undervoltage.

[0241] The driving circuit includes a high-side driving circuit 40 and a low-side driving circuit 41. The high-side driving circuit 40 and the low-side driving circuit 41 are used to provide a large driving capability to drive the subsequent power MOS (ie, the high-side device 42 and the low-side device 43).

[0242] In addition, the control circuit further includes, for example, a bandgap reference source 33 , a low voltage level shift 34 and a high voltage level shift 38 .

[0243] The bandgap reference source 33 is used to provide a reference voltage for the protection module, while the low voltage level shift 34 and the high voltage level shift 38 are used to convert the front-stage power rail into the rear-stage power rail to ensure the normal operation of the circuit.

[0244] The intelligent power switch of the present invention has high-side and low-side devices and a control circuit integrated on the same substrate and electrically connected, which greatly reduces the area occupied by the PCB board, improves the integration level, and reduces transmission delay, electromagnetic interference, power loss, etc.

[0245] Of course, the above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It should be noted that all equivalent substitutions and obvious deformation forms made by any technician familiar with the field under the guidance of this specification fall within the essential scope of this specification and should be protected by the present invention.

Claims

1. A high-low side integrated MOS type device, characterized in that: The cell structure comprises a third metallized source (110), a P+ substrate (109) and a P- epitaxial layer (108) which are stacked in sequence from bottom to top; A first groove (125) is provided at a middle position along the left-right direction of the P-epitaxial layer (108), the first groove (125) is arranged in a longitudinal direction, and extends downward from the upper surface of the P-epitaxial layer (108) to the upper surface of the P+ substrate (109); The first trench (125) is filled with a dielectric material (120) to form a dielectric isolation region; A third P+ low resistivity region (121) is provided on the left side of the first trench (125), and the third P+ low resistivity region (121) is also arranged vertically; the third P+ low resistivity region (121) is in contact with the left side surface of the first trench (125); A first P-type base region (107), a first N-drift region (123) and a first planar gate structure are provided on the left side of the third P+ low resistivity region (121); the first P-type base region (107) and the first N-drift region (123) are both included in the P-epitaxial layer (108); The first P-type base region (107) and the first N-drift region (123) are both located at the top of the left region of the P-epitaxial layer (108) and the sides of the two are in contact with each other, and the first P-type base region (107) is located on the left side of the first N-drift region (123); The first P-type base region (107) comprises a first P+ low resistivity region (106) and a first N+ source region (103); the first P+ low resistivity region (106) and the first N+ source region (103) are both located at the top left region of the first P-type base region (107) and the sides of the two regions are in contact with each other, and the first N+ source region (103) is located at the right side of the first P+ low resistivity region (106); the top right region of the first P-type base region (107) is located between the right side surface of the first N+ source region (103) and the right side surface of the first P-type base region (107); The first N-drift region (123) includes a first N+ drain region (122); the first N+ drain region (122) is located in the top right region of the first N-drift region (123); the top left region of the first N-drift region (123) is located between the left side surface of the first N+ drain region (122) and the left side surface of the first N-drift region (123); The right sides of the first N-drift region (123) and the first N+ drain region (122) are in contact with the left side of the third P+ low resistivity region (121); The first planar gate structure comprises a first gate oxide layer (102) and a first gate electrode (101); The bottom surface of the first gate oxide layer (102) is in contact with a right portion of the top surface of the first N+ source region (103), a top right region of the first P-type base region (107), and a top left region of the first N-drift region (123); The first gate electrode (101) is located on the top surface of the first gate oxide layer (102); A second P+ low resistivity region (119) is provided on the right side of the first trench (125), and the second P+ low resistivity region (119) is also arranged vertically; the second P+ low resistivity region (119) is in contact with the right side surface of the first trench (125); A second P-type base region (117), a second N-drift region (112) and a second planar gate structure are provided on the right side of the second P+ low resistivity region (119); the second P-type base region (117) and the second N-drift region (112) are both contained in the P-epitaxial layer (108); The second P-type base region (117) and the second N-drift region (112) are both located at the top of the right region of the P-epitaxial layer (108) and the sides of the two are in contact with each other, and the second P-type base region (117) is located on the left side of the second N-drift region (112); The second P-type base region (117) includes a second N+ source region (118); the second N+ source region (118) is located at the top left region of the second P-type base region (117); the top right region of the second P-type base region (117) is located between the right side surface of the second N+ source region (118) and the right side surface of the second P-type base region (117); The left sides of the second P-type base region (117) and the second N+ source region (118) are in contact with the right side of the second P+ low resistivity region (119); The second N-drift region (112) includes a second N+ drain region (113); The second N+ drain region (113) is located at the top right region of the second N-drift region (112); the top left region of the second N-drift region (112) is located between the left side surface of the second N+ drain region (113) and the left side surface of the second N-drift region (112); The second planar gate structure comprises a second gate oxide layer (116) and a second gate electrode (115); The bottom surface of the second gate oxide layer (116) is in contact with a right portion of the top surface of the second N+ source region (118), a top right region of the second P-type base region (117), and a top left region of the second N-drift region (112); The second gate electrode (115) is located on the top surface of the second gate oxide layer (116); An insulating layer (124) is provided above the P-epitaxial layer (108); a first metallized source (104), a first metallized drain (126), a second metallized source (127) and a second metallized drain (114) are provided above the insulating layer (124); A through hole (105) is provided in the insulating layer (124); wherein the first metallized source electrode (104) is in ohmic contact with the first P+ low resistivity region (106) and the first N+ source region (103) through the through hole (105); the first metallized drain electrode (126) is in ohmic contact with the first N+ drain region (122) and the third P+ low resistivity region (121) through the through hole (105); the second metallized source electrode (127) is in ohmic contact with the second P+ low resistivity region (119) and the second N+ source region (118) through the through hole (105); and the second metallized drain electrode (114) is in ohmic contact with the second N+ drain region (113) through the through hole (105).

2. A high-low side integrated MOS type device, characterized in that: The cell structure includes a P+ substrate (109) and a P- epitaxial layer (108) stacked in sequence from bottom to top; A first groove (125) is provided at a middle position along the left-right direction of the P-epitaxial layer (108), the first groove (125) is arranged in a longitudinal direction, and extends downward from the upper surface of the P-epitaxial layer (108) to the upper surface of the P+ substrate (109); The first trench (125) is filled with a dielectric material (120) to form a dielectric isolation region; A first P-type base region (107), a first N-drift region (123) and a first planar gate structure are provided on the left side of the first trench (125); the first P-type base region (107) and the first N-drift region (123) are both contained in the P-epitaxial layer (108); The first P-type base region (107) and the first N-drift region (123) are both located at the top of the left region of the P-epitaxial layer (108) and the sides of the two are in contact with each other, and the first P-type base region (107) is located on the left side of the first N-drift region (123); The right side surface of the first N-drift region (123) and the left side surface of the first trench (125) are in contact with each other; The first P-type base region (107) comprises a first P+ low resistivity region (106) and a first N+ source region (103); the first P+ low resistivity region (106) and the first N+ source region (103) are both located at the top left region of the first P-type base region (107) and the sides of the two regions are in contact with each other, and the first N+ source region (103) is located at the right side of the first P+ low resistivity region (106); the top right region of the first P-type base region (107) is located between the right side surface of the first N+ source region (103) and the right side surface of the first P-type base region (107); The first N-drift region (123) includes a first N+ drain region (122); the first N+ drain region (122) is located in the top right region of the first N-drift region (123); the top left region of the first N-drift region (123) is located between the left side surface of the first N+ drain region (122) and the left side surface of the first N-drift region (123); The first planar gate structure comprises a first gate oxide layer (102) and a first gate electrode (101); The bottom surface of the first gate oxide layer (102) is in contact with a right portion of the top surface of the first N+ source region (103), a top right region of the first P-type base region (107), and a top left region of the first N-drift region (123); The first gate electrode (101) is located on the top surface of the first gate oxide layer (102); A second P-type base region (117), a second N-drift region (112) and a second planar gate structure are provided on the right side of the first trench (125); the second P-type base region (117) and the second N-drift region (112) are both contained in the P-epitaxial layer (108); The second P-type base region (117) and the second N-drift region (112) are both located at the top of the right region of the P-epitaxial layer (108) and the sides of the two are in contact with each other, and the second P-type base region (117) is located on the left side of the second N-drift region (112); The left side surface of the second P-type base region (117) is in contact with the right side surface of the first trench (125); The second P-type base region (117) includes a second N+ source region (118) and a second P+ low resistivity region (119); the second N+ source region (118) and the second P+ low resistivity region (119) are both located at the top left region of the second P-type base region (117) and the sides of the two regions are in contact with each other, and the second N+ source region (118) is located at the right side of the second P+ low resistivity region (119); the top right region of the second P-type base region (117) is located between the right side surface of the second N+ source region (118) and the right side surface of the second P-type base region (117); The second N-drift region (112) includes a second N+ drain region (113); The second N+ drain region (113) is located at the top right region of the second N-drift region (112); the top left region of the second N-drift region (112) is located between the left side surface of the second N+ drain region (113) and the left side surface of the second N-drift region (112); The second planar gate structure comprises a second gate oxide layer (116) and a second gate electrode (115); The bottom surface of the second gate oxide layer (116) is in contact with a right portion of the top surface of the second N+ source region (118), a top right region of the second P-type base region (117), and a top left region of the second N-drift region (112); The second gate electrode (115) is located on the top surface of the second gate oxide layer (116); An insulating layer (124) is provided above the P-epitaxial layer (108); a first metallized source electrode (104), a second metallized source electrode (127) and a second metallized drain electrode (114) are provided above the insulating layer (124); A through hole (105) is provided in the insulating layer (124); wherein the first metallized source electrode (104) is in ohmic contact with the first P+ low resistivity region (106) and the first N+ source region (103) through the through hole (105); the second metallized source electrode (127) is in ohmic contact with the first N+ drain region (122), the second P+ low resistivity region (119) and the second N+ source region (118) through the through hole (105); and the second metallized drain electrode (114) is in ohmic contact with the second N+ drain region (113) through the through hole (105).

3. The high-low side integrated MOS type device according to claim 1 or 2, characterized in that: The dielectric material (120) is made of silicon dioxide, silicon nitride, aluminum oxide, borophosphosilicate glass, sapphire or hafnium oxide.

4. The high-low side integrated MOS type device according to claim 1 or 2, characterized in that: The insulating layer (124) is made of borophosphosilicate glass, silicon dioxide, benzocyclobutene, aluminum oxide, sapphire or hafnium oxide.

5. The high-low side integrated MOS type device according to claim 1, characterized in that: The third metallized source (110), the first metallized source (104), the first metallized drain (126), the second metallized source (127) and the second metallized drain (114) are made of one or more of aluminum, copper, gold or silver.

6. A high-low side integrated MOS type device, characterized in that: The cell structure includes a first metallized drain (210), an N+ substrate (209) and a P-deep well region (208) which are stacked in sequence from bottom to top; A first groove (225) is provided at a middle position along the left-right direction of the P-deep well region (208); the first groove (225) is arranged in a longitudinal direction and extends downward from the upper surface of the P-deep well region (208) to the upper surface of the N+ substrate (209); The first trench (225) is filled with a dielectric material (220) to form a dielectric isolation region; A first N+ low resistivity region (222) is provided on the left side of the first trench (225), the first N+ low resistivity region (222) is also arranged vertically, and the first N+ low resistivity region (222) is in contact with the left side surface of the first trench (225); A first P-type base region (207), a first N-drift region (223) and a first planar gate structure are provided on the left side of the first N+ low resistivity region (222); the first P-type base region (207) and the first N-drift region (223) are both contained in the P-deep well region (208); The first P-type base region (207) and the first N-drift region (223) are both located at the top of the left region of the P-deep well region (208) and the sides of the two regions are in contact with each other, and the first P-type base region (207) is located at the left side of the first N-drift region (223); The right side surface of the first N-drift region (223) and the left side surface of the first N+ low resistivity region (222) are in contact with each other; The first P-type base region (207) includes a first P+ low resistivity region (206) and a first N+ source region (203); the first P+ low resistivity region (206) and the first N+ source region (203) are both located at the top left region of the first P-type base region (207) and the sides of the two regions are in contact with each other, and the first N+ source region (203) is located at the right side of the first P+ low resistivity region (206); the top right region of the first P-type base region (207) is located between the right side surface of the first N+ source region (203) and the right side surface of the first P-type base region (207); The first planar gate structure comprises a first gate oxide layer (202) and a first gate electrode (201); The bottom surface of the first gate oxide layer (202) is in contact with a right portion of the top surface of the first N+ source region (203), a top right portion of the first P-type base region (207), and a left portion of the top surface of the first N-drift region (223); The first gate electrode (201) is located on the top surface of the first gate oxide layer (202); A second N+ low resistivity region (221) is provided on the right side of the first trench (225), the second N+ low resistivity region (221) is also arranged vertically, and the second N+ low resistivity region (221) is in contact with the right side surface of the first trench (225); A second P-type base region (217), a second N-drift region (212) and a second planar gate structure are provided on the right side of the second N+ low resistivity region (221); the second P-type base region (217) and the second N-drift region (212) are both included in the P-deep well region (208); The second P-type base region (217) and the second N-drift region (212) are both located at the top of the right region of the P-deep well region (208) and the sides of the two are in contact with each other, and the second P-type base region (217) is located on the left side of the second N-drift region (212); The second P-type base region (217) includes a second N+ source region (218) and a second P+ low resistivity region (219); the second N+ source region (218) and the second P+ low resistivity region (219) are both located at the top left region of the second P-type base region (217) and the sides of the two regions are in contact with each other, and the second N+ source region (218) is located at the right side of the second P+ low resistivity region (219); the top right region of the second P-type base region (217) is located between the right side surface of the second N+ source region (218) and the right side surface of the second P-type base region (217); The left sides of the second P-type base region (217) and the second P+ low-resistivity region (219) are in contact with the right side of the second N+ low-resistivity region (221); The second N-drift region (212) includes a second N+ drain region (213); The second N+ drain region (213) is located at the top right region of the second N-drift region (212); the top left region of the second N-drift region (212) is located between the left side surface of the second N+ drain region (213) and the left side surface of the second N-drift region (212); The second planar gate structure comprises a second gate oxide layer (216) and a second gate electrode (215); The bottom surface of the second gate oxide layer (216) is in contact with a right portion of the top surface of the second N+ source region (218), a top right region of the second P-type base region (217), and a top left region of the second N-drift region (212); The second gate electrode (215) is located on the top surface of the second gate oxide layer (216); An insulating layer (224) is provided above the P-deep well region (208); a first metallized source electrode (204), a second metallized source electrode (226) and a second metallized drain electrode (214) are provided above the insulating layer (224); A through hole (205) is provided in the insulating layer (224); wherein the first metallized source electrode (204) is in ohmic contact with the first P+ low resistivity region (206) and the first N+ source region (203) through the through hole (205); the second metallized source electrode (226) is in ohmic contact with the second N+ low resistivity region (221), the second N+ source region (218) and the second P+ low resistivity region (219) through the through hole (205); and the second metallized drain electrode (214) is in ohmic contact with the second N+ drain region (213) through the through hole (205).

7. A high-low side integrated MOS type device, characterized in that: The cell structure includes an N+ substrate (209) and a P-deep well region (208) stacked in sequence from bottom to top; A first groove (225) is provided at a middle position along the left-right direction of the P-deep well region (208); the first groove (225) is arranged in a longitudinal direction and extends downward from the upper surface of the P-deep well region (208) to the upper surface of the N+ substrate (209); The first trench (225) is filled with a dielectric material (220) to form a dielectric isolation region; A first P-type base region (207), a first N-drift region (223) and a first planar gate structure are provided on the left side of the first trench (225); the first P-type base region (207) and the first N-drift region (223) are both contained in the P-deep well region (208); The first P-type base region (207) and the first N-drift region (223) are both located at the top of the left region of the P-deep well region (208) and the sides of the two regions are in contact with each other, and the first P-type base region (207) is located at the left side of the first N-drift region (223); The right side surface of the first N-drift region (223) and the left side surface of the first trench (225) are in contact with each other; The first P-type base region (207) includes a first P+ low resistivity region (206) and a first N+ source region (203); the first P+ low resistivity region (206) and the first N+ source region (203) are both located at the top left region of the first P-type base region (207) and the sides of the two regions are in contact with each other, and the first N+ source region (203) is located at the right side of the first P+ low resistivity region (206); the top right region of the first P-type base region (207) is located between the right side surface of the first N+ source region (203) and the right side surface of the first P-type base region (207); The first N-drift region (223) includes a first N+ low resistivity region (222); the first N+ low resistivity region (222) is located in the top right region of the first N-drift region (223); and the top left region of the first N-drift region (223) is located between the left side surface of the first N+ low resistivity region (222) and the left side surface of the first N-drift region (223); The first planar gate structure comprises a first gate oxide layer (202) and a first gate electrode (201); The bottom surface of the first gate oxide layer (202) is in contact with a right portion of the top surface of the first N+ source region (203), a top right region of the first P-type base region (207), and a top left region of the first N-drift region (223); The first gate electrode (201) is located on the top surface of the first gate oxide layer (202); A second P-type base region (217), a second N-drift region (212) and a second planar gate structure are provided on the right side of the first trench (225); the second P-type base region (217) and the second N-drift region (212) are both contained in the P-deep well region (208); The second P-type base region (217) and the second N-drift region (212) are both located at the top of the right region of the P-deep well region (208) and the sides of the two are in contact with each other, and the second P-type base region (217) is located on the left side of the second N-drift region (212); The left side surface of the second P-type base region (217) is in contact with the right side surface of the first trench (225); The second P-type base region (217) includes a second N+ source region (218) and a second P+ low resistivity region (219); the second N+ source region (218) and the second P+ low resistivity region (219) are both located at the top left region of the second P-type base region (217) and the sides of the two regions are in contact with each other, and the second N+ source region (218) is located at the right side of the second P+ low resistivity region (219); the top right region of the second P-type base region (217) is located between the right side surface of the second N+ source region (218) and the right side surface of the second P-type base region (217); The second N-drift region (212) includes a second N+ drain region (213); The second N+ drain region (213) is located at the top right region of the second N-drift region (212); the top left region of the second N-drift region (212) is located between the left side surface of the second N+ drain region (213) and the left side surface of the second N-drift region (212); The second planar gate structure comprises a second gate oxide layer (216) and a second gate electrode (215); The bottom surface of the second gate oxide layer (216) is in contact with a right portion of the top surface of the second N+ source region (218), a top right region of the second P-type base region (217), and a top left region of the second N-drift region (212); The second gate electrode (215) is located on the top surface of the second gate oxide layer (216); An insulating layer (224) is provided above the P-deep well region (208); a first metallized source electrode (204), a second metallized source electrode (226) and a second metallized drain electrode (214) are provided above the insulating layer (224); A through hole (205) is provided in the insulating layer (224); wherein the first metallized source electrode (204) is in ohmic contact with the first P+ low resistivity region (206) and the first N+ source region (203) through the through hole (205); the second metallized source electrode (226) is in ohmic contact with the first N+ low resistivity region (222), the second N+ source region (218) and the second P+ low resistivity region (219) through the through hole (205); and the second metallized drain electrode (214) is in ohmic contact with the second N+ drain region (213) through the through hole (205).

8. The high-low side integrated MOS type device according to claim 6 or 7, characterized in that: The dielectric material (220) is made of silicon dioxide, silicon nitride, aluminum oxide, borophosphosilicate glass, sapphire or hafnium oxide.

9. The high-low side integrated MOS type device according to claim 6 or 7, characterized in that: The insulating layer (224) is made of borophosphosilicate glass, silicon dioxide, benzocyclobutene, aluminum oxide, sapphire or hafnium oxide.

10. The high-low side integrated MOS type device according to claim 6, characterized in that: The first metallized drain (210), the first metallized source (204), the second metallized source (226) and the second metallized drain (214) are made of one or more of aluminum, copper, gold or silver.

11. A high-side and low-side integrated MOS power switch, comprising a control circuit and high-side and low-side devices, wherein the high-side and low-side devices and the control circuit are integrated on the same substrate and electrically connected; characterized in that: The control circuit includes a driving circuit for driving the high-side and low-side devices; The high-side and low-side devices are high-side and low-side integrated MOS devices as described in any one of claims 1 to 10.

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