A SiC UMOSFET device and preparation method thereof

Abstract

A SiC UMOSFET device and a preparation method thereof, relating to the field of semiconductor technology. By forming a first trench region and a second trench region in the SiC UMOSFET device, and by forming a P+Shield region at the bottom of the first trench region, the gate oxide at the bottom of the first trench region and the second trench region are protected at the same time, and channel regions are formed on both sides of the first trench region and the second trench region, thereby increasing the number of channel regions of the chip and improving the current carrying capacity of the device. In addition, the present invention forms a body diode at the bottom of the first trench region, so that the P+Shield region at the bottom is grounded, further improving its protection capability, and because the body diode is transferred from the original drift layer above to the inside, the resistance of the body diode during the freewheeling process is also reduced, reducing the freewheeling loss.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC UMOSFET device and a preparation method thereof. Background Art

[0002] With the rapid development of new energy vehicles, photovoltaic energy storage, charging piles and other industries, traditional silicon-based power devices have become increasingly unable to meet more stringent use requirements. Although Si-based MOSFET devices have fast switching frequency and low switching loss, they cannot be used in high-voltage and high-power applications. Although Si-based IGBT devices have the advantages of high voltage and low loss, they cannot be used in fields with fast switching frequencies. As a third-generation semiconductor material, SiC has excellent characteristics such as large bandgap width, high critical breakdown field strength, low intrinsic carrier concentration, and high thermal conductivity. Therefore, MOSFET devices made of SiC materials can meet the strict requirements of high-voltage, high-temperature, and high-frequency application environments due to the excellent characteristics of the material itself and the structural characteristics of MOSFET unipolar devices.

[0003] Compared with DMOSFET devices, SiC UMOSFET devices are favored by manufacturers in the industry because of their smaller chip source cell size, which leads to smaller overall chip size and lower cost. However, due to the characteristics of SiC materials themselves, the long-term use of SiC UMOSFET devices is challenged. For example, the dielectric constant of SiC is lower than that of SiO 2 This results in a larger electric field strength in the gate oxide layer than in SiC, and the quality of the gate oxide layer grown on the SiC material is also poor. The trench gate oxide structure of the UMOSFET device also makes the gate oxide layer at the bottom corner more susceptible to electric field concentration. Summary of the invention

[0004] The present invention designs a SiC UMOSFET device, which increases the number of device channel regions while protecting trench gate oxide, thereby improving the current conduction capacity of the device, and forms a body diode in the trench region, transfers the body diode from above the drift layer to the inside, reduces the resistance of the body diode in the freewheeling process, and thus reduces the freewheeling loss.

[0005] The technical solution of the present invention is:

[0006] A method for preparing a SiC UMOSFET device comprises the following steps:

[0007] S100, epitaxially growing an N-Drift layer on the N+Sub layer;

[0008] S200, forming a current spreading layer CSL on the N-Drift layer by ion implantation in the source region;

[0009] S300, forming a P-base region on the current spreading layer CSL by Al ion implantation;

[0010] S400, forming an NP region on the P-base region by N ion implantation;

[0011] S500, forming a first trench region extending to below the current spreading layer CSL on the NP region by etching;

[0012] S600, forming a P+ Shield region extending downward at the bottom of the first trench region by Al ion implantation;

[0013] S700, forming a second trench region extending downward into the current spreading layer CSL on the top surface of the NP region by etching;

[0014] S800, growing a gate oxide layer in the first trench region and the second trench region respectively by dry oxygen;

[0015] S900, etching away the gate oxide layer in the middle of the bottom in the first trench region by etching to reserve a window for the ohmic contact alloy layer;

[0016] S1000, forming a polysilicon layer (11) on the gate oxide layer by deposition in the first trench region and the second trench region to serve as a gate electrode of the device;

[0017] S1100, forming an isolation dielectric layer on the first trench region and the second trench region by deposition to prevent the gate and source of the device from being short-circuited;

[0018] S1200, forming an ohmic contact alloy layer by metal sputtering at the bottom window in the first trench region and at the top surface of the NP region by alloy annealing;

[0019] S1300, forming a front electrode metal layer on the isolation dielectric layer and the ohmic contact alloy layer by Al metal sputtering to serve as a source electrode of the device.

[0020] Specifically, in step S200, the current spreading layer CSL is formed by N ion implantation with a concentration greater than 1E17 cm -2 , reducing the internal resistance of the device and improving the current-carrying capacity of the device.

[0021] Specifically, in step S800, the thickness of the gate oxide layer is 60nm-70nm.

[0022] A SiC UMOSFET device, prepared by the method for preparing a SiC UMOSFET device according to claim 1, characterized in that it comprises an N+Sub layer, an N-Drift layer, a current spreading layer CSL, a P-base region, an NP region, an ohmic contact alloy layer and a front electrode metal arranged in sequence from bottom to top;

[0023] The top surface of the NP region is provided with a first trench region extending downward to the N-Drift layer;

[0024] A P+Shield region extending downward is provided at the bottom of the first trench region;

[0025] A first gate oxide layer is provided inside the first trench region, and an ohmic contact alloy layer connected to the P+Shield region is provided in the middle of the trench bottom; a first isolation dielectric layer extending upward to the top surface of the NP region is provided between the sidewall of the ohmic contact alloy layer and the first gate oxide layer; a first polysilicon Poly layer is provided between the first isolation dielectric layer and the first gate oxide layer;

[0026] The front electrode metal extends downward from the middle of the first isolation dielectric layer and is connected to the ohmic contact alloy layer in the bottom of the groove;

[0027] A second trench region extending downward to the current spreading layer CSL is provided in the middle of the top surface of the NP region;

[0028] A second gate oxide layer is provided along the inner wall of the second trench region, and the second gate oxide layer is filled with a second polysilicon Poly layer; a second isolation dielectric layer connected to the NP region is provided on the top of the second trench region;

[0029] Specifically, the gate oxide layer is located on the inner sidewalls and bottom corners of the first trench region.

[0030] Specifically, the bottom of the second trench region is in the current spreading layer CSL.

[0031] The present invention forms a first trench region and a second trench region in a SiC UMOSFET device, forms a P+Shield region at the bottom of the first trench region, and simultaneously protects the gate oxide at the bottom of the first trench region and the second trench region, and simultaneously forms a channel region on both sides of the first trench region and the second trench region, thereby increasing the number of channel regions of the chip and improving the current carrying capacity of the device. In addition, the present invention forms a body diode at the bottom of the first trench region, so that the P+Shield region at the bottom is grounded, further improving its protection capability, and because the body diode is transferred from the original drift layer above to the inside, the resistance of the body diode during the freewheeling process is also reduced, reducing the freewheeling loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1is a structural schematic diagram of step S100 of the present invention;

[0033] Figure 2 is a structural schematic diagram of step S200 of the present invention;

[0034] Figure 3 is a schematic structural diagram of step S300 of the present invention;

[0035] Figure 4 is a schematic structural diagram of step S400 of the present invention;

[0036] Figure 5 is a schematic structural diagram of step S500 of the present invention;

[0037] Figure 6 is a schematic diagram of the structure of step S600 of the present invention;

[0038] Figure 7 is a schematic structural diagram of step S700 of the present invention;

[0039] Figure 8 is a structural schematic diagram of step S800 of the present invention;

[0040] Fig. 9 is a structural schematic diagram of step S900 of the present invention;

[0041] Fig.10 is a structural schematic diagram of step S1000 of the present invention;

[0042] Fig.11 is a structural schematic diagram of step S1100 of the present invention;

[0043] Fig.12 is a schematic diagram of the structure of step S1200 of the present invention;

[0044] Fig.13 is a schematic diagram of the structure of step S1300 of the present invention;

[0045] In the figure, 1 is the N+Sub layer, 2 is the N-Drift layer, 3 is the current spreading layer CSL, 4 is the P-base region, 5 is the NP region, 6 is the first trench region, 7 is the P+Shield region, 8 is the second trench region, 9 is the gate oxide layer, 10 is the etching region at the bottom of the gate oxide layer, 11 is the Poly layer, 12 is the isolation dielectric layer, 13 is the ohmic contact alloy layer, and 14 is the front electrode metal layer. DETAILED DESCRIPTION

[0046] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0047] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0048] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0049] A method for preparing a SiC UMOSFET device comprises the following steps:

[0050] S100, refer to Figure 1 As shown, an N-Drift layer 2 is formed by epitaxial growth on the N+Sub layer 1;

[0051] S200, refer to Figure 2 As shown, a current spreading layer CSL3 is formed on the N-Drift layer 2 by ion implantation in the source region;

[0052] In step S200, the current spreading layer CSL3 is formed by N ion implantation with a concentration greater than 1E17 cm -2 , reducing the internal resistance of the device and improving the current-carrying capacity of the device.

[0053] S300, refer to Figure 3 As shown, a P-base region 4 is formed on the current spreading layer CSL3 by Al ion implantation;

[0054] S400, refer to Figure 4 As shown, an NP region 5 is formed on the P-base region 4 by N ion implantation;

[0055] S500, refer to Figure 5 As shown, a first trench region 6 extending to below the current spreading layer CSL3 is formed on the NP region 5 by etching;

[0056] S600, refer to Figure 6 As shown, a P+ Shield region 7 extending downward is formed at the bottom of the first trench region 6 by Al ion implantation;

[0057] Since the P+Shield region 7 in step S600 is at the bottom of the first trench region 6, it needs to be formed by two opposite oblique injections;

[0058] S700, reference Figure 7 As shown, a second trench region 8 extending downward into the current spreading layer CSL3 is formed on the top surface of the NP region 5 by etching;

[0059] S800, reference Figure 8 As shown, a gate oxide layer 9 is grown in the first trench region 6 and the second trench region 8 respectively by dry oxygen growth;

[0060] In step S800 , the thickness of the gate oxide layer 9 is 60 nm to 70 nm, thereby improving the robustness of the gate oxide layer.

[0061] S900, refer to Fig. 9 As shown, the gate oxide layer 9 in the middle of the bottom of the first trench region 6 is etched away by etching to reserve a window for the ohmic contact alloy layer 13, that is, Fig. 9 An etched region 10 at the bottom of the middle gate oxide layer;

[0062] S1000, refer to Fig.10 As shown, a polysilicon layer 11 is formed on the gate oxide layer 9 by deposition in the first trench region 6 and the second trench region 8 to serve as the gate of the device;

[0063] S1100, reference Fig.11 As shown, an isolation dielectric layer 12 is formed on the first trench region 6 and the second trench region 8 by deposition to prevent the gate and source of the device from being short-circuited;

[0064] S1200, refer to Fig.12 As shown, an ohmic contact alloy layer 13 is formed by metal sputtering at the bottom window in the first trench region 6 and the top surface of the NP region 5 through alloy annealing;

[0065] S1300, refer to Fig.13 As shown, a front electrode metal layer 14 is formed on the isolation dielectric layer 12 and the ohmic contact alloy layer 13 by Al metal sputtering to serve as the source electrode of the device.

[0066] A SiC UMOSFET device comprises an N+Sub layer 1, an N-Drift layer 2, a current spreading layer CSL3, a P-base region 4, an NP region 5, an ohmic contact alloy layer 13 and a front electrode metal layer 14 arranged in sequence from bottom to top;

[0067] The top surface of the NP region 5 is provided with a first trench region 6 extending downward to the N-Drift layer 2;

[0068] A P+ Shield region 7 extending downward is provided at the bottom of the first trench region 6;

[0069] A first gate oxide layer is provided inside the first trench region 6, and an ohmic contact alloy layer 13 connected to the P+Shield region 7 is provided in the middle of the trench bottom; a first isolation dielectric layer extending upward to the top surface of the NP region 5 is provided between the sidewall of the ohmic contact alloy layer 13 and the first gate oxide layer; a first polysilicon Poly layer is provided between the first isolation dielectric layer and the first gate oxide layer;

[0070] The front electrode metal layer 14 extends downward from the middle of the first isolation dielectric layer and is connected to the ohmic contact alloy layer 13 in the bottom of the groove; the top of the first isolation dielectric layer is connected to the ohmic contact alloy layer 13 on the NP region 5;

[0071] A second trench region 8 extending downward to the current spreading layer CSL3 is provided in the middle of the top surface of the NP region 5;

[0072] A second gate oxide layer is provided along the inner wall of the second trench region 8, and the second gate oxide layer is filled with a second polysilicon Poly layer; a second isolation dielectric layer connected to the NP region 5 is provided on the top of the second trench region 8;

[0073] It is further defined that the gate oxide layer is located on the inner sidewalls and bottom corners of the first trench region 6 .

[0074] It is further defined that the bottom of the second trench region 8 is in the current spreading layer CSL3.

[0075] Beneficial effects of the present invention:

[0076] 1. Improve the current flow capacity of the device: When the SiC UMOSFET is turned on, the channel region through the sidewall of the trench is used as the current path. The present invention forms a P+Shield region at the bottom of the first trench region 6, and wraps the bottom of the first trench region 6 with a P+Shield region 7 to protect the bottom of the trench gate oxide of the first trench region 6, and when the device is turned off, the space charge region formed by the P+Shield region 7 and the N-Drift layer 2 also extends to the bottom corner of the second trench region 8 to protect the bottom corner of the trench gate oxide of the second trench region 8. At the same time, the present invention also designs channel regions on both side walls of the first trench region 6, so that the number of channel regions of the chip source cell is increased by 1 times, thereby further improving the current flow capacity of the SiC UMOSFET.

[0077] 2. Reduce the body diode freewheeling loss of the device: The parasitic PN junction body diode of the conventional SiC UMOSFET is above the N-Drift layer 2, and its total resistance is composed of contact resistance, material resistance, etc. The present invention designs the parasitic PN junction body diode at the bottom of the first trench region 6, so that the body diode is transferred from above the N-Drift layer 2 to the inside, which reduces the thickness of the material passed by the body diode during the freewheeling process, thereby reducing the material resistance, and ultimately reducing the total resistance during the freewheeling process and reducing the freewheeling loss.

[0078] Regarding the contents disclosed in this case, there are a few points that need to be explained:

[0079] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0080] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;

[0081] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a SiC UMOSFET device, characterized in that: The steps include: S100, epitaxially growing an N-Drift layer (2) on the N+Sub layer (1); S200, forming a current spreading layer CSL (3) on the N-Drift layer (2) by ion implantation in the source region; S300, forming a P-base region (4) on the current spreading layer CSL (3) by Al ion implantation; S400, forming an NP region (5) on the P-base region (4) by N ion implantation; S500, forming a first trench region (6) extending to below the current spreading layer CSL (3) on the NP region (5) by etching; S600, forming a P+ Shield region (7) extending downward at the bottom of the first trench region (6) by Al ion implantation; S700, forming a second trench region (8) extending downward into the current spreading layer CSL (3) on the top surface of the NP region (5) by etching; S800, growing a gate oxide layer (9) in the first trench region (6) and the second trench region (8) respectively by dry oxygen; S900, etching away the gate oxide layer (9) in the middle of the bottom in the first trench region (6) by etching, so as to reserve a window for the ohmic contact alloy layer (13); S1000, forming a polysilicon layer (11) on the gate oxide layer (9) by deposition in the first trench region (6) and the second trench region (8) to serve as a gate electrode of the device; S1100, forming an isolation dielectric layer (12) on the first trench region (6) and the second trench region (8) by deposition to prevent the gate and source of the device from being short-circuited; S1200, forming an ohmic contact alloy layer (13) by alloy annealing at the bottom window in the first trench region (6) and the top surface of the NP region (5) by metal sputtering; S1300, forming a front electrode metal layer (14) on the isolation dielectric layer (12) and the ohmic contact alloy layer (13) by Al metal sputtering to serve as a source electrode of the device; A P+Shield region (7) is formed at the bottom of the first trench region (6), and the bottom of the first trench region (6) is wrapped by the P+Shield region (7) to protect the bottom of the trench gate oxide of the first trench region (6). When the device is turned off, the space charge region formed by the P+Shield region (7) and the N-Drift layer (2) also extends to the bottom corner of the second trench region (8), so as to protect the bottom corner of the trench gate oxide of the second trench region (8).

2. The method for preparing a SiC UMOSFET device according to claim 1, characterized in that: In step S200, the current spreading layer CSL (3) is formed by N ion implantation with a concentration greater than 1E17 cm -2 , reducing the internal resistance of the device and improving the current-carrying capacity of the device.

3. The method for preparing a SiC UMOSFET device according to claim 1, characterized in that: In step S800, the thickness of the gate oxide layer (9) is 60nm-70nm.

4. A SiC UMOSFET device, prepared by the method for preparing a SiC UMOSFET device according to claim 1, characterized in that: It includes an N+Sub layer (1), an N-Drift layer (2), a current spreading layer CSL (3), a P-base region (4), an NP region (5), an ohmic contact alloy layer (13) and a front electrode metal layer (14) arranged in sequence from bottom to top; The top surface of the NP region (5) is provided with a first groove region (6) extending downward to the N-Drift layer (2); A P+ Shield region (7) extending downward is provided at the bottom of the first trench region (6); A first gate oxide layer is provided inside the first trench region (6), and an ohmic contact alloy layer (13) connected to the P+ Shield region (7) is provided in the middle of the trench bottom; a first isolation dielectric layer extending upward to the top surface of the NP region (5) is provided between the side wall of the ohmic contact alloy layer (13) and the first gate oxide layer; and a first polysilicon Poly layer is provided between the first isolation dielectric layer and the first gate oxide layer; The front electrode metal layer (14) extends downward from the middle of the first isolation dielectric layer and is connected to the ohmic contact alloy layer (13) in the bottom of the groove; A second trench region (8) extending downward to the current spreading layer CSL (3) is provided in the middle of the top surface of the NP region (5); A second gate oxide layer is provided along the inner wall of the second trench region (8), and the second gate oxide layer is filled with a second polysilicon Poly layer; a second isolation dielectric layer connected to the NP region (5) is provided on the top of the second trench region (8); A P+Shield region (7) is formed at the bottom of the first trench region (6), and the P+Shield region (7) wraps the bottom of the first trench region (6), thereby protecting the bottom of the trench gate oxide of the first trench region (6); and when the device is turned off, a space charge region formed by the P+Shield region (7) and the N-Drift layer (2) extends to the bottom corner of the second trench region (8), thereby protecting the bottom corner of the trench gate oxide of the second trench region (8).

5. A SiC UMOSFET device according to claim 4, characterized in that: The gate oxide layer is located on the inner side walls and bottom corners of the first trench region (6).

6. A SiC UMOSFET device according to claim 4, characterized in that: The bottom of the second trench region (8) is in the current spreading layer CSL (3).

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