A high-speed receiver circuit for CAN bus

Abstract

The present invention discloses a high-speed receiver circuit applied to a CAN bus, comprising: a voltage reduction protection module, a hysteresis control module and a high-speed comparator module; the voltage reduction protection module reduces the voltage of the CANH terminal and the CANL terminal of the CAN bus and inputs it into the hysteresis control module; when the CANH terminal and the CANL terminal of the CAN bus are disturbed and produce a small fluctuation, the hysteresis control module adopts hysteresis for control, and sends the output of the hysteresis control to the high-speed comparator module; the high-speed comparator module compares the dominant state or the recessive state according to the output of the hysteresis control module, and controls the output size of the current source in the hysteresis control module with the output result of the comparison. The present invention overcomes the problem of the imbalance between the common mode potential VCM and the preset potential caused by the high-speed receiver in the recessive state, and improves the EMI and EME characteristics of the high-speed receiver.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuit design, and in particular to a high-speed receiver circuit applied to a CAN bus. Background Art

[0002] Currently, there are many types of field buses in industrial electronic systems and automotive electronic systems to solve the problem that the control core of modern industrial scenarios lies in data communication between field devices. The Controller Area Network (CAN) is one of the most widely used and mature field buses, especially in the automotive field. In automotive applications, the electromagnetic interference (EMI) and electromagnetic emissions (EME) of CAN bus communication are very high to avoid data transmission on the CAN bus interfering with surrounding systems.

[0003] In the prior art, since the voltage operating range on the CAN bus is very large, a step-down protection module is required to reduce the voltage on CANH and CANL to a voltage level that the high-speed receiver can withstand, and use a current mirror to further adjust the level sent to the receiver input terminal, and adjust the bias voltage of the current mirror according to the visible and invisible state of the CAN bus level to achieve the hysteresis function. However, in the recessive working state, there is a DC path from the common mode potential through the voltage divider resistor to the current mirror, and the current mirror has a shunt effect, which will cause the level on the bus to deviate from the preset common mode potential VCM, resulting in a difference in the common mode potential between the dominant and recessive. This causes high-frequency electromagnetic interference on the CAN bus when the visible and invisible jumps during the signal transmission process, which may affect the signal transmission of other communication systems.

[0004] Specifically, Figure 1 This is a traditional hysteresis control module applied to the CAN bus high-speed receiver. Since there is a high level on the CAN BUS, a resistor is used to divide the potential on the BUS. After the bus voltage is divided by the resistor, the level is adjusted through the current mirror to ensure that the high-speed comparator can make a comparison when CANH and CANL are the same. Therefore, the level signal at the input end of the high-speed comparator is as follows: Figure 3As shown; however, this structure has a disadvantage. After the recessive state is stable, there is a DC path from the common-mode level through the voltage divider resistor to the current mirror. CANH and CANL are connected through an external load, and the external load RL is much smaller than Rdiv1, so VCANH≈VCANL. Due to the requirement for voltage reduction, Rdiv1 is much larger than Rdiv2, so the current flowing through Rdiv1 is very small, about 0. Therefore, the current on the current mirror basically flows through Rdiv2, which will generate I*Rdiv2 on Rdiv2. Therefore, VCANH=VCANL=VCM-I*Rdiv2, so CANH+CANL=2VCM-2*I*Rdiv2, Vcm(step)≈2*I*Rdiv2. If the difference Vcom(dom) between the dominant and recessive common-mode levels of the CANH and CANL ends in the CAN bus is reduced by reducing Rdiv2 or reducing I, the common-mode level Vcom(rec) of the CANH and CANL ends in the invisible state will be reduced, which will increase the requirements for the offset of the high-speed comparator. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a high-speed receiver circuit applied to a CAN transceiver, which overcomes the problem of imbalance between the common mode potential VCM and the preset potential caused by the high-speed receiver in the recessive state, and improves the EMI and EME characteristics of the high-speed receiver.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solutions: A high-speed receiver circuit applied to a CAN bus, comprising: a voltage drop protection module, a hysteresis control module and a high-speed comparator module;

[0007] The voltage reduction protection module reduces the voltage of the CANH terminal and the CANL terminal of the CAN bus and inputs the voltage into the hysteresis control module;

[0008] When the CANH and CANL terminals of the CAN bus are disturbed and produce slight fluctuations, the hysteresis control module uses hysteresis to perform control, and sends the output of the hysteresis control to the high-speed comparator module;

[0009] The high-speed comparator module performs a comparison of the dominant state or the recessive state according to the output of the hysteresis control module, and controls the output size of the current source in the hysteresis control module with the output result of the comparison.

[0010] Furthermore, the hysteresis control module includes: a current source, a current replication module, a current mirror isolation module, a bias module and a voltage regulation module, the current source is used to generate a constant current, the current replication module is used to copy the constant current generated by the current source to the hysteresis control module, the current mirror isolation module is used to control the opening or closing of the CAN bus signal channel, the bias module is used to convert the constant current into a bias voltage, and the voltage regulation module is used to adjust the voltage sent to the input end of the high-speed comparator.

[0011] Further, the current replication module includes: a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a second PMOS tube PM2 and a third PMOS tube PM3, the gate of the second NMOS tube NM2, the gate of the third NMOS tube NM3 and the gate of the fourth NMOS tube NM4 are all connected to the output end of the current source, the source of the second NMOS tube NM2, the source of the third NMOS tube NM3 and the source of the fourth NMOS tube NM4 are all grounded, the drain of the second NMOS tube NM2, the gate of the second PMOS tube PM2 and the gate of the third PMOS tube PM3 are all connected to the bias module, the source of the second PMOS tube PM2 and the source of the third PMOS tube PM3 are all connected to the power supply voltage, and the drain of the third PMOS tube PM3 is connected to the current mirror isolation module; the input end of the current source is connected to the output end of the high-speed comparator module.

[0012] Further, the bias module includes: a first NMOS tube NM1 and a first PMOS tube PM1, the source of the first PMOS tube PM1 is connected to the power supply voltage, the drain of the first PMOS tube PM1 and the gate of the first PMOS tube PM1 are connected to the gate of the second PMOS tube PM2, the gate of the third PMOS tube PM3, and the drain of the second NMOS tube NM2; the gate of the first NMOS tube NM1 and the drain of the first NMOS tube NM1 are connected to the output end of the current source, and the source of the first NMOS tube NM1 is grounded.

[0013] Further, the current mirror isolation module includes: a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15, a sixteenth NMOS tube NM16 and a seventeenth NMOS tube NM17, the gate of the fourteenth NMOS tube NM14, the gate of the fifteenth NMOS tube NM15, the gate of the sixteenth NMOS tube NM16 and the gate of the seventeenth NMOS tube NM17 are all connected to the external control signal EN, and the source of the fourteenth NMOS tube NM14, the source of the fifteenth NMOS tube NM15, the source of the sixteenth NMOS tube NM16 and the source of the seventeenth NMOS tube NM17 are all connected to the output end of the step-down protection module.

[0014] Furthermore, the voltage regulating module includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is respectively connected to the drain of the second PMOS tube PM2 and the inverting input terminal of the high-speed comparator module, and the other end of the first resistor R1 is connected to the drain of the sixteenth NMOS tube NM16; one end of the second resistor R2 is respectively connected to the drain of the third PMOS tube PM3 and the drain of the seventeenth NMOS tube NM17, and the other end of the second resistor R2 is connected to the non-inverting input terminal of the high-speed comparator module.

[0015] Further, the drain of the fourteenth NMOS tube NM14 is connected to the drain of the third NMOS tube NM3 , and the drain of the fifteenth NMOS tube NM15 is connected to the drain of the fourth NMOS tube NM4 .

[0016] Further, the voltage regulating module includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the drain of the fourteenth NMOS tube NM14, and the other end of the first resistor R1 is respectively connected to the drain of the third NMOS tube NM3 and the inverting input end of the high-speed comparator module; one end of the second resistor R2 is respectively connected to the drain of the fifteenth NMOS tube NM15 and the drain of the fourth NMOS tube NM4, and the other end of the second resistor R2 is connected to the non-inverting input end of the high-speed comparator module.

[0017] Further, the drain of the sixteenth NMOS transistor NM16 is connected to the drain of the second PMOS transistor PM2 , and the drain of the seventeenth NMOS transistor NM17 is connected to the drain of the third PMOS transistor PM3 .

[0018] Further, the voltage drop protection module includes: a first voltage drop resistor Rdiv11, a second voltage drop resistor Rdiv12, a third voltage drop resistor Rdiv21 and a fourth voltage drop resistor Rdiv22, one end of the first voltage drop resistor Rdiv11 is connected to the CANH end of the CAN bus, and the other end of the first voltage drop resistor Rdiv11 is respectively connected to one end of the third voltage drop resistor Rdiv21, one end of the fifteenth NMOS tube NM15 and one end of the seventeenth NMOS tube NM17; one end of the second voltage drop resistor Rdiv12 is connected to the CANL end of the CAN bus, and the other end of the second voltage drop resistor Rdiv12 is respectively connected to one end of the fourth voltage drop resistor Rdiv22, one end of the fourteenth NMOS tube NM14 and one end of the sixteenth NMOS tube NM16; the other end of the third voltage drop resistor Rdiv21 and the other end of the fourth voltage drop resistor Rdiv22 are both connected to the common mode potential VCM.

[0019] Compared with the prior art, the present invention has the following beneficial effects: the hysteresis control module in the high-speed receiver circuit of the CAN transceiver used in the present invention mainly makes the high and low level flip thresholds of the high-speed receiver different. Since the current of the branch where the first resistor R1 in the voltage regulation module is located is determined by the current in the current replication module and the current mirror isolation module, this part of the current is determined by the output of the current source, and the output of the current source is determined by the output of the high-speed comparator module. When the output of the high-speed comparator module is low or high, the generated current is different, so that the voltage generated on the first resistor R1 is different, so that the output of the high-speed comparator module after the hysteresis control module jumps. The CANH terminal and The difference at the CANL end is different, thereby generating hysteresis, filtering smaller interference, and improving the EMI performance of the high-speed receiver; at the same time, the present invention eliminates the DC path from the common mode level to the current mirror when the recessive state is stable, thereby reducing the common mode potential VCM between the CANH end and the CANL end between the dominant and recessive states, and improving the EME characteristics of the high-speed receiver; on the basis of improving the EME and EMI performance, the present invention does not need to increase the requirements for the comparator offset in the high-speed receiver; the present invention adds a current mirror isolation module in the hysteresis control module to isolate the CAN bus and the input end of the high-speed comparator module, thereby avoiding the influence of the DC characteristics of the input BJT of the high-speed comparator module on the CAN bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of a conventional hysteresis control module applied to a CAN bus high-speed receiver;

[0021] Figure 2 A schematic diagram of a high-speed receiver circuit applied to a CAN transceiver according to the present invention;

[0022] Figure 3 A schematic diagram of the input voltage of the high-speed comparator module in the present invention;

[0023] Figure 4 for Figure 2 A schematic diagram of a hysteresis control module in eliminating a DC path in a hidden state;

[0024] Figure 5 To adopt Figure 2 Schematic diagram of the solution to improve the CAN bus signal;

[0025] Figure 6 This is another schematic diagram of a high-speed receiver circuit applied to a CAN transceiver in the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0027] The invention provides a high-speed receiver circuit applied to a CAN bus, comprising: a voltage reduction protection module, a hysteresis control module and a high-speed comparator module; the voltage reduction protection module reduces the voltage of the CANH terminal and the CANL terminal of the CAN bus and inputs the voltage into the hysteresis control module; when the CANH terminal and the CANL terminal of the CAN bus are interfered and produce a small fluctuation, the hysteresis control module adopts hysteresis to perform control, and sends the output of the hysteresis control into the high-speed comparator module; the hysteresis control module of the invention is to produce a certain deviation before the CANH terminal and the CANL terminal of the CAN transceiver reach the input terminal of the high-speed comparator module after the voltage is divided by the voltage reduction protection module, so as to facilitate the high-speed comparator module to compare; the hysteresis control module can avoid the problem that the output jumps back and forth to generate an error signal when the difference between CANH and CANL is near the threshold of the high-speed receiver when interference exists, and realizes filtering of relatively small interference; the high-speed comparator module compares the dominant state or the recessive state according to the output of the hysteresis control module, and controls the output size of the current source in the hysteresis control module with the output result of the comparison, so that the hysteresis control module produces hysteresis, and improves the anti-interference ability of the high-speed receiver.

[0028] The hysteresis control module of the present invention comprises: a current source, a current replication module, a current mirror isolation module, a bias module and a voltage regulation module, wherein the current source is used to generate a constant current, the current replication module is used to replicate the constant current generated by the current source to the hysteresis control module, the current mirror isolation module is used to control the opening or closing of the CAN bus signal channel, the bias module is used to convert the constant current into a bias voltage, and the voltage regulation module is used to regulate the input terminal voltage sent to the high-speed comparator module, so that the input terminal voltage of the high-speed comparator module is as follows: Figure 3 As shown, among which, CANH COM and CANL COM The signal waveforms of the base of the first BJT transistor Q1 and the base of the second BJT transistor Q2 in the high-speed comparator module are shown respectively. It can be seen that CANH COM and CANL COM The CANH and CANL terminals of the CAN bus are divided by voltage, and a DC offset is added to the divided signal. By adopting the high-speed receiver structure adopted in the present invention, the DC path introduced by the voltage divider circuit in the traditional structure can be eliminated, thereby reducing the difference between Vcm(dom) and Vcm(rec). At the same time, the hysteresis control module in the present invention uses the product of resistance and current to introduce a deviation on the voltage after the CANH and CANL terminals are divided, and an offset is created at the input end of the high-speed comparator, thereby reducing the requirement for the high-speed comparator offset.

[0029] like Figure 2The current replication module of the present invention provides a bias current for a signal channel of a CAN bus. The current replication module includes: a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a second PMOS tube PM2 and a third PMOS tube PM3. The gate of the second NMOS tube NM2, the gate of the third NMOS tube NM3 and the gate of the fourth NMOS tube NM4 are all connected to the output end of the current source, the source of the second NMOS tube NM2, the source of the third NMOS tube NM3 and the source of the fourth NMOS tube NM4 are all grounded, the drain of the second NMOS tube NM2, the gate of the second PMOS tube PM2 and the gate of the third PMOS tube PM3 are all connected to the bias module, the source of the second PMOS tube PM2 and the source of the third PMOS tube PM3 are all connected to the power supply voltage, and the drain of the third PMOS tube PM3 is connected to the current mirror isolation module; the input end of the current source is connected to the output end of the high-speed comparator module. The CAN bus signal channel is triggered from the CANH terminal and the CANL terminal to generate CANH_div and CANL_div through the resistor of the step-down protection module, and is transmitted to the base of the first BJT transistor Q1 and the base of the second BJT transistor Q2 in the high-speed comparator module through the signal channel composed of the second NMOS tube NM2 to the fourth NMOS tube NM4 and the second PMOS tube PM2 to the third PMOS tube PM3.

[0030] The bias module in the present invention comprises: a first NMOS tube NM1 and a first PMOS tube PM1, wherein the source of the first PMOS tube PM1 is connected to a power supply voltage, the drain of the first PMOS tube PM1 and the gate of the first PMOS tube PM1 are connected to the gate of the second PMOS tube PM2, the gate of the third PMOS tube PM3, and the drain of the second NMOS tube NM2; the gate of the first NMOS tube NM1 and the drain of the first NMOS tube NM1 are connected to the output end of the current source, and the source of the first NMOS tube NM1 is grounded. The first NMOS transistor NM1 provides a bias voltage for the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4. The first PMOS transistor PM1 converts the current of the second NMOS transistor NM2 into a bias voltage, and provides it to the second PMOS transistor PM2 and the third PMOS transistor PM3, so that the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 in the hysteresis control module provide the same bias current.

[0031] The current mirror isolation module of the present invention comprises: a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15, a sixteenth NMOS tube NM16 and a seventeenth NMOS tube NM17, the gate of the fourteenth NMOS tube NM14, the gate of the fifteenth NMOS tube NM15, the gate of the sixteenth NMOS tube NM16 and the gate of the seventeenth NMOS tube NM17 are all connected to the external control signal EN, the source of the fourteenth NMOS tube NM14, the source of the fifteenth NMOS tube NM15, the source of the sixteenth NMOS tube NM16 and the source of the seventeenth NMOS tube NM17 are all connected to the output end of the step-down protection module. The current mirror isolation module inputs an enable signal through the external control signal EN, and the enable signal determines whether the high-speed receiver works by controlling the gates of the four NMOS tubes in the current mirror isolation module.

[0032] The voltage drop protection module in the present invention includes: a first voltage drop resistor Rdiv11, a second voltage drop resistor Rdiv12, a third voltage drop resistor Rdiv21 and a fourth voltage drop resistor Rdiv22, one end of the first voltage drop resistor Rdiv11 is connected to the CANH end of the CAN bus, and the other end of the first voltage drop resistor Rdiv11 is respectively connected to one end of the third voltage drop resistor Rdiv21 and one end connected to the fifteenth NMOS tube NM15 and the seventeenth NMOS tube NM17; one end of the second voltage drop resistor Rdiv12 is connected to the CANL end of the CAN bus, and the other end of the second voltage drop resistor Rdiv12 is respectively connected to one end of the fourth voltage drop resistor Rdiv22 and one end connected to the fourteenth NMOS tube NM14 and the sixteenth NMOS tube NM16; the other end of the third voltage drop resistor Rdiv21 and the other end of the fourth voltage drop resistor Rdiv22 are both connected to the common mode potential VCM. Through the action of current replication of two groups of current mirrors of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4, the current flowing through the second PMOS transistor PM2 and the third PMOS transistor PM3 is I, and the current flowing through the third NMOS transistor NM3 and the fourth NMOS transistor NM4 is I, so that the current on the third drop resistor Rdiv21 and the fourth drop resistor Rdiv22 is approximately 0, therefore, the CANH terminal voltage and the CANL terminal voltage on the CAN bus are equal to the common mode point VCM, so that the voltage sum of the CANH terminal and the CANL terminal on the CAN bus is equal to the power supply voltage VCC, thereby eliminating the DC path from the common mode level to the current mirror when the recessive state is stable.

[0033] The high-speed comparator module of the present invention comprises a first-stage amplification module, a second-stage amplification module and a comparison module connected in sequence, wherein the first-stage amplification module comprises: a first BJT transistor Q1, a second BJT transistor Q2, a third BJT transistor Q3, a fourth BJT transistor Q4, a third resistor R3, a fourth resistor R4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7, one end of the third resistor R3, one end of the fourth resistor R4, the collector of the third BJT transistor Q3 and the collector of the fourth BJT transistor Q4 are all connected to the power supply voltage VCC, the other end of the third resistor R3 is respectively connected to the collector of the first BJT transistor Q1 and the base of the third BJT transistor Q3, the other end of the fourth resistor R4 is respectively connected to the collector of the second BJT transistor Q2 and the base of the fourth BJT transistor The base of the first BJT transistor Q1 and the emitter of the second BJT transistor Q2 are connected to the drain of the fifth NMOS transistor NM5, the base of the first BJT transistor Q1 and the base of the second BJT transistor Q2 are connected to the hysteresis control module, the emitter of the third BJT transistor Q3 is respectively connected to the input end of the second-stage amplification module and the drain of the sixth NMOS transistor NM6, the emitter of the fourth BJT transistor Q4 is respectively connected to the input end of the second-stage amplification module and the drain of the seventh NMOS transistor NM7, the source of the fifth NMOS transistor NM5, the source of the sixth NMOS transistor NM6, and the source of the seventh NMOS transistor NM7 are all grounded, and the gate of the fifth NMOS transistor NM5, the gate of the sixth NMOS transistor NM6, and the gate of the seventh NMOS transistor NM7 are all connected to the output end of the current source;The second-stage amplification module includes: a fifth BJT transistor Q5, a sixth BJT transistor Q6, a seventh BJT transistor Q7, an eighth BJT transistor Q8, a fifth resistor R5, a sixth resistor R6, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9 and a tenth NMOS transistor NM10, one end of the fifth resistor R5, one end of the sixth resistor R6, the collector of the seventh BJT transistor Q7 and the collector of the eighth BJT transistor Q8 are all connected to the power supply voltage VCC, the other end of the fifth resistor R5 is respectively connected to the collector of the fifth BJT transistor Q5 and the base of the seventh BJT transistor Q7, the other end of the sixth resistor R6 is respectively connected to the collector of the sixth BJT transistor Q6 and the base of the eighth BJT transistor Q8, the base of the fifth BJT transistor Q5 is connected to the third BJT transistor The emitter of the sixth BJT transistor Q6 is connected to the emitter of the fourth BJT transistor Q4, the emitter of the fifth BJT transistor Q5 and the emitter of the sixth BJT transistor Q6 are both connected to the drain of the eighth NMOS tube NM8, the emitter of the seventh BJT transistor Q7 is respectively connected to the drain of the ninth NMOS tube NM9 and the input end of the comparison module, the emitter of the eighth BJT transistor Q8 is respectively connected to the drain of the tenth NMOS tube NM10 and the input end of the comparison module, the source of the eighth NMOS tube NM8, the source of the ninth NMOS tube NM9, and the source of the tenth NMOS tube NM10 are all grounded, and the gate of the eighth NMOS tube NM8, the gate of the ninth NMOS tube NM9, and the gate of the tenth NMOS tube NM10 are all connected to the output end of the current source;The comparison module includes: a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eleventh NMOS tube NM11, a twelfth NMOS tube NM12, a thirteenth NMOS tube NM13, an eighteenth NMOS tube NM18 and a nineteenth NMOS tube NM19, a source of the fourth PMOS tube PM4, a source of the fifth PMOS tube PM5, a source of the sixth PMOS tube PM6 and a source of the seventh PMOS tube PM7 are all connected to the power supply voltage VCC, a gate of the fourth PMOS tube PM4 is respectively connected to the gate of the fifth PMOS tube PM5, a drain of the fifth PMOS tube PM5 and a drain of the eighteenth NMOS tube NM18, a drain of the fourth PMOS tube PM4 is respectively connected to the drain of the twelfth NMOS tube NM12, a gate of the twelfth NMOS tube NM13 and a drain of the twelfth NMOS tube NM14. The gate of the 18th NMOS tube NM18 is connected to the emitter of the eighth BJT transistor Q8, the gate of the 19th NMOS tube NM19 is connected to the emitter of the seventh BJT transistor Q7, the drain of the 19th NMOS tube NM19 is respectively connected to the drain of the sixth PMOS tube PM6, the gate of the sixth PMOS tube PM6, and the gate of the seventh PMOS tube PM7, the source of the 18th NMOS tube NM18 and the source of the 19th NMOS tube NM6 are both connected to the drain of the 11th NMOS tube NM11, the gate of the 11th NMOS tube NM11 is connected to the output end of the current source, the drain of the seventh PMOS tube PM7 is connected to the drain of the 13th NMOS tube NM13 as the output end of the high-speed comparator module, and the output end of the high-speed comparator module is connected to the input end of the current source. The source of the eleventh NMOS tube NM11, the source of the twelfth NMOS tube NM12, and the source of the thirteenth NMOS tube NM13 are all grounded. ;

[0034] In a technical solution of the present invention, the voltage regulating module includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is respectively connected to the drain of the second PMOS tube PM2 and the inverting input end of the high-speed comparator module, the inverting input end of the high-speed comparator module refers to the base of the second BJT transistor Q2, and the other end of the first resistor R1 is connected to the drain of the sixteenth NMOS tube NM16; one end of the second resistor R2 is respectively connected to the drain of the third PMOS tube PM3 and the drain of the seventeenth NMOS tube NM17, the other end of the second resistor R2 is connected to the non-inverting input end of the high-speed comparator module, and the non-inverting input end of the high-speed comparator module refers to the base of the first BJT transistor Q1; the drain of the fourteenth NMOS tube NM14 is connected to the drain of the third NMOS tube NM3, and the drain of the fifteenth NMOS tube NM15 is connected to the drain of the fourth NMOS tube NM4. The current in the branch where the first resistor R1 in the voltage regulation module is located is determined by the current in the current replication module and the current mirror isolation module. This part of the current is determined by the output of the current source, and the output of the current source is determined by the output of the high-speed comparator module. When the output VOUT of the high-speed comparator module is low or high, the current generated is different, so that the voltage generated on the first resistor R1 is different. Therefore, the difference between the CANH end and the CANL end on the CAN bus required for the output of the high-speed comparator after the hysteresis control module to jump is different, thereby generating hysteresis. The EIM performance of the CAN bus is mainly determined by the common mode difference of CANH and CANL in the visible and invisible jump, because the CANH and CANL signals are transmitted through twisted pair cables. In the visible and invisible jump, the changing current will generate a magnetic field to be emitted to the outside. If it can be ensured that the common mode value does not change during the visible and invisible jump, then the magnetic fields generated by CANH and CANL will cancel each other, so that no interference is generated to the outside or the interference generated to the outside is small, such as Figure 4 In the recessive stable state, the present invention uses the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3 and the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3, and the fourth NMOS tube NM4 to copy the current through two current mirrors, so that the current flowing through the second PMOS tube PM2 and the third PMOS tube PM3 is I, and the current flowing through the third NMOS tube NM3 and the fourth NMOS tube NM4 is I, so that the current on the third drop resistor Rdiv21 and the fourth drop resistor Rdiv22 is approximately 0. Therefore, if Figure 5, the CANH terminal voltage and CANL terminal voltage on the CAN bus are equal to the common mode point VCM, so that the voltage sum of the CANH terminal and CANL terminal on the CAN bus is equal to the power supply voltage VCC, thereby eliminating the DC path from the common mode level to the current mirror when the recessive state is stable, that is, eliminating the difference between the CANH terminal voltage and the CANL terminal voltage on the CAN bus between the dominant and recessive states, thereby achieving the purpose of improving the EMI and EME performance on the CAN bus.

[0035] like Figure 6 In another technical solution of the present invention, the voltage regulating module includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the drain of the fourteenth NMOS tube NM14, and the other end of the first resistor R1 is respectively connected to the drain of the third NMOS tube NM3 and the inverting input end of the high-speed comparator module; one end of the second resistor R2 is respectively connected to the drain of the fifteenth NMOS tube NM15 and the drain of the fourth NMOS tube NM4, and the other end of the second resistor R2 is connected to the non-inverting input end of the high-speed comparator module; the drain of the sixteenth NMOS tube NM16 is connected to the drain of the second PMOS tube PM2, and the drain of the seventeenth NMOS tube NM17 is connected to the drain of the third PMOS tube PM3. The main function of the first resistor R1 is to generate hysteresis. The function of hysteresis is to make the high and low level thresholds of the high-speed receiver different, so as to avoid the output of the high-speed receiver being affected by interference. If the high and low level thresholds are the same, then when the input signal of the high-speed receiver is near the threshold, when there is external interference, it will cause the high-speed receiver to flip back and forth, causing the output signal to be affected by interference. After introducing hysteresis, it can resist interference, thereby improving the EMI and EME performance on the CAN bus.

[0036] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A high-speed receiver circuit for CAN bus, characterized in that: include: Buck protection module, hysteresis control module and high-speed comparator module; The voltage reduction protection module reduces the voltage of the CANH terminal and the CANL terminal of the CAN bus and inputs the voltage into the hysteresis control module; The hysteresis control module uses hysteresis to control when the CANH and CANL ends of the CAN bus are disturbed and produce small fluctuations, and sends the output of the hysteresis control to the high-speed comparator module; wherein the small fluctuation refers to: the interference existing when the difference between CANH and CANL is at the high-speed receiver threshold; The high-speed comparator module compares the dominant state or the recessive state according to the output of the hysteresis control module, and controls the output size of the current source in the hysteresis control module with the output result of the comparison; The hysteresis control module includes: a current source, a current copy module, a current mirror isolation module, a bias module and a voltage regulation module, wherein the current source is used to generate a constant current, the current copy module is used to copy the constant current generated by the current source to the hysteresis control module, the current mirror isolation module is used to control the opening or closing of the CAN bus signal channel, the bias module is used to convert the constant current into a bias voltage, and the voltage regulation module is used to regulate the voltage sent to the input end of the high-speed comparator; The voltage drop protection module includes: a first voltage drop resistor Rdiv11, a second voltage drop resistor Rdiv12, a third voltage drop resistor Rdiv21 and a fourth voltage drop resistor Rdiv22, one end of the first voltage drop resistor Rdiv11 is connected to the CANH end of the CAN bus, and the other end of the first voltage drop resistor Rdiv11 is respectively connected to one end of the third voltage drop resistor Rdiv21, one end of the fifteenth NMOS tube NM15 and one end of the seventeenth NMOS tube NM17; one end of the second voltage drop resistor Rdiv12 is connected to the CANL end of the CAN bus, and the other end of the second voltage drop resistor Rdiv12 is respectively connected to one end of the fourth voltage drop resistor Rdiv22, one end of the fourteenth NMOS tube NM14 and one end of the sixteenth NMOS tube NM16; the other end of the third voltage drop resistor Rdiv21 and the other end of the fourth voltage drop resistor Rdiv22 are both connected to the common mode potential VCM; The high-speed comparator module includes a first-stage amplification module, a second-stage amplification module and a comparison module connected in sequence. The first-stage amplification module includes: a first BJT transistor Q1, a second BJT transistor Q2, a third BJT transistor Q3, a fourth BJT transistor Q4, a third resistor R3, a fourth resistor R4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7. One end of the third resistor R3, one end of the fourth resistor R4, the collector of the third BJT transistor Q3 and the collector of the fourth BJT transistor Q4 are all connected to the power supply voltage VCC, the other end of the third resistor R3 is respectively connected to the collector of the first BJT transistor Q1 and the base of the third BJT transistor Q3, the other end of the fourth resistor R4 is respectively connected to the collector of the second BJT transistor Q2 and the base of the fourth BJT transistor Q4. The emitter of the first BJT transistor Q1 and the emitter of the second BJT transistor Q2 are both connected to the drain of the fifth NMOS tube NM5, the base of the first BJT transistor Q1 and the base of the second BJT transistor Q2 are both connected to the hysteresis control module, the emitter of the third BJT transistor Q3 is respectively connected to the input end of the second-stage amplification module and the drain of the sixth NMOS tube NM6, the emitter of the fourth BJT transistor Q4 is respectively connected to the input end of the second-stage amplification module and the drain of the seventh NMOS tube NM7, the source of the fifth NMOS tube NM5, the source of the sixth NMOS tube NM6, and the source of the seventh NMOS tube NM7 are all grounded, and the gate of the fifth NMOS tube NM5, the gate of the sixth NMOS tube NM6, and the gate of the seventh NMOS tube NM7 are all connected to the output end of the current source;The second-stage amplification module includes: a fifth BJT transistor Q5, a sixth BJT transistor Q6, a seventh BJT transistor Q7, an eighth BJT transistor Q8, a fifth resistor R5, a sixth resistor R6, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9 and a tenth NMOS transistor NM10, one end of the fifth resistor R5, one end of the sixth resistor R6, the collector of the seventh BJT transistor Q7 and the collector of the eighth BJT transistor Q8 are all connected to the power supply voltage VCC, the other end of the fifth resistor R5 is respectively connected to the collector of the fifth BJT transistor Q5 and the base of the seventh BJT transistor Q7, the other end of the sixth resistor R6 is respectively connected to the collector of the sixth BJT transistor Q6 and the base of the eighth BJT transistor Q8, the base of the fifth BJT transistor Q5 is connected to the third BJT transistor The emitter of the sixth BJT transistor Q6 is connected to the emitter of the fourth BJT transistor Q4, the emitter of the fifth BJT transistor Q5 and the emitter of the sixth BJT transistor Q6 are both connected to the drain of the eighth NMOS tube NM8, the emitter of the seventh BJT transistor Q7 is respectively connected to the drain of the ninth NMOS tube NM9 and the input end of the comparison module, the emitter of the eighth BJT transistor Q8 is respectively connected to the drain of the tenth NMOS tube NM10 and the input end of the comparison module, the source of the eighth NMOS tube NM8, the source of the ninth NMOS tube NM9, and the source of the tenth NMOS tube NM10 are all grounded, and the gate of the eighth NMOS tube NM8, the gate of the ninth NMOS tube NM9, and the gate of the tenth NMOS tube NM10 are all connected to the output end of the current source;The comparison module includes: a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eleventh NMOS tube NM11, a twelfth NMOS tube NM12, a thirteenth NMOS tube NM13, an eighteenth NMOS tube NM18 and a nineteenth NMOS tube NM19, a source of the fourth PMOS tube PM4, a source of the fifth PMOS tube PM5, a source of the sixth PMOS tube PM6 and a source of the seventh PMOS tube PM7 are all connected to the power supply voltage VCC, a gate of the fourth PMOS tube PM4 is respectively connected to the gate of the fifth PMOS tube PM5, a drain of the fifth PMOS tube PM5 and a drain of the eighteenth NMOS tube NM18, a drain of the fourth PMOS tube PM4 is respectively connected to the drain of the twelfth NMOS tube NM12, a gate of the twelfth NMOS tube NM12 and a gate of the thirteenth NMOS tube NM13, and a gate of the eighteenth NMOS tube NM18 is respectively connected. The gate of the OS transistor NM18 is connected to the emitter of the eighth BJT transistor Q8, the gate of the nineteenth NMOS transistor NM19 is connected to the emitter of the seventh BJT transistor Q7, the drain of the nineteenth NMOS transistor NM19 is respectively connected to the drain of the sixth PMOS transistor PM6, the gate of the sixth PMOS transistor PM6, and the gate of the seventh PMOS transistor PM7, the source of the eighteenth NMOS transistor NM18 and the source of the nineteenth NMOS transistor NM6 are both connected to the drain of the eleventh NMOS transistor NM11, the gate of the eleventh NMOS transistor NM11 is connected to the output end of the current source, the drain of the seventh PMOS transistor PM7 is connected to the drain of the thirteenth NMOS transistor NM13 as the output end of the high-speed comparator module, and the output end of the high-speed comparator module is connected to the input end of the current source; the source of the eleventh NMOS transistor NM11, the source of the twelfth NMOS transistor NM12, and the source of the thirteenth NMOS transistor NM13 are all grounded.; 2. A high-speed receiver circuit applied to a CAN bus according to claim 1, characterized in that: The current replication module includes: a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a second PMOS tube PM2 and a third PMOS tube PM3, the gate of the second NMOS tube NM2, the gate of the third NMOS tube NM3 and the gate of the fourth NMOS tube NM4 are all connected to the output end of the current source, the source of the second NMOS tube NM2, the source of the third NMOS tube NM3 and the source of the fourth NMOS tube NM4 are all grounded, the drain of the second NMOS tube NM2, the gate of the second PMOS tube PM2 and the gate of the third PMOS tube PM3 are all connected to the bias module, the source of the second PMOS tube PM2 and the source of the third PMOS tube PM3 are all connected to the power supply voltage, and the drain of the third PMOS tube PM3 is connected to the current mirror isolation module; the input end of the current source is connected to the output end of the high-speed comparator module.

3. A high-speed receiver circuit applied to a CAN bus according to claim 2, characterized in that: The bias module includes: a first NMOS tube NM1 and a first PMOS tube PM1, wherein the source of the first PMOS tube PM1 is connected to a power supply voltage, the drain of the first PMOS tube PM1 and the gate of the first PMOS tube PM1 are connected to the gate of the second PMOS tube PM2, the gate of the third PMOS tube PM3, and the drain of the second NMOS tube NM2; the gate of the first NMOS tube NM1 and the drain of the first NMOS tube NM1 are connected to the output end of the current source, and the source of the first NMOS tube NM1 is grounded.

4. A high-speed receiver circuit applied to a CAN bus according to claim 3, characterized in that: The current mirror isolation module includes: a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15, a sixteenth NMOS tube NM16 and a seventeenth NMOS tube NM17, the gate of the fourteenth NMOS tube NM14, the gate of the fifteenth NMOS tube NM15, the gate of the sixteenth NMOS tube NM16 and the gate of the seventeenth NMOS tube NM17 are all connected to the external control signal EN, and the source of the fourteenth NMOS tube NM14, the source of the fifteenth NMOS tube NM15, the source of the sixteenth NMOS tube NM16 and the source of the seventeenth NMOS tube NM17 are all connected to the output end of the step-down protection module.

5. A high-speed receiver circuit applied to a CAN bus according to claim 4, characterized in that: The voltage regulating module includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is respectively connected to the drain of the second PMOS tube PM2 and the inverting input end of the high-speed comparator module, and the other end of the first resistor R1 is connected to the drain of the sixteenth NMOS tube NM16; one end of the second resistor R2 is respectively connected to the drain of the third PMOS tube PM3 and the drain of the seventeenth NMOS tube NM17, and the other end of the second resistor R2 is connected to the non-inverting input end of the high-speed comparator module.

6. A high-speed receiver circuit applied to a CAN bus according to claim 5, characterized in that: The drain of the fourteenth NMOS tube NM14 is connected to the drain of the third NMOS tube NM3 , and the drain of the fifteenth NMOS tube NM15 is connected to the drain of the fourth NMOS tube NM4 .

7. A high-speed receiver circuit applied to a CAN bus according to claim 6, characterized in that: The voltage regulating module includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the drain of the fourteenth NMOS tube NM14, and the other end of the first resistor R1 is respectively connected to the drain of the third NMOS tube NM3 and the inverting input end of the high-speed comparator module; one end of the second resistor R2 is respectively connected to the drain of the fifteenth NMOS tube NM15 and the drain of the fourth NMOS tube NM4, and the other end of the second resistor R2 is connected to the non-inverting input end of the high-speed comparator module.

8. The high-speed receiver circuit applied to the CAN bus according to claim 7, characterized in that: The drain of the sixteenth NMOS transistor NM16 is connected to the drain of the second PMOS transistor PM2 , and the drain of the seventeenth NMOS transistor NM17 is connected to the drain of the third PMOS transistor PM3 .

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