A level converter and digital logic circuit

Abstract

The present application discloses a level converter and a digital logic circuit. The level converter includes: a level converter circuit for performing level conversion according to an input voltage signal; a switch circuit symmetrically arranged around the level converter circuit, for outputting a corresponding switch signal according to the voltage magnitude of the voltage signal; a control circuit symmetrically arranged around the level converter circuit, including a first control module and a second control module, coupled between the level converter circuit and the switch circuit, for controlling the conduction of the first control module or the second control module according to the switch signal, and generating a control signal corresponding to the voltage signal according to the conduction state, so as to control the level converter circuit to perform the level conversion through the control signal. The technical solution of the present application can output a corresponding switch signal based on the voltage magnitude of the voltage signal, so as to instruct the corresponding control module to conduct according to the switch signal, thereby realizing the multi-mode compatibility of the level converter.

Description

Technical Field

[0001] The present application relates to the technical field of communication circuit design, and in particular to a level converter and a digital logic circuit. Background Art

[0002] Level conversion usually occurs when two devices need to communicate, but their voltage specifications (such as VOH, VOL, VIH, VIL) are different. Due to the difference in voltage specifications between different devices, different devices cannot be directly connected for communication, so a level converter is needed to convert the level to ensure that the signal can be transmitted and processed correctly.

[0003] At the same time, due to the differences in voltage specifications between different devices, there are also different specifications to choose from when using the level converter. For example, in the level conversion technology solutions existing in the prior art, the level converter corresponding to the high voltage mode and the level converter corresponding to the normal voltage mode are often not interchangeable, which brings inconvenience to the use of the level converter.

[0004] Therefore, there is an urgent need for a level converter that is compatible with multiple modes to solve the above problems. Summary of the invention

[0005] In order to solve the above technical problems, an embodiment of the present application provides a level converter and a digital logic circuit.

[0006] According to one aspect of an embodiment of the present application, a level converter is provided, comprising: a level conversion circuit, for performing level conversion according to an input voltage signal; a switch circuit symmetrically arranged around the level conversion circuit, for outputting a corresponding switch signal according to the voltage magnitude of the voltage signal; a control circuit symmetrically arranged around the level conversion circuit, comprising a first control module and a second control module, coupled between the level conversion circuit and the switch circuit, for controlling the conduction status of the first control module or the second control module according to the switch signal, and generating a control signal corresponding to the voltage signal according to the conduction status, so as to control the level conversion circuit to perform the level conversion through the control signal.

[0007] In some embodiments of the present application, based on the above technical solution, the level conversion circuit includes an input circuit, a protection circuit, a voltage holding circuit and a latch circuit coupled in sequence; the input circuit includes a first NMOS tube and a second NMOS tube arranged in a pair, and the gate of the first NMOS tube is coupled to the gate of the second NMOS tube; the protection circuit includes a third NMOS tube and a fourth NMOS tube arranged in a pair, and a first PMOS tube and a second PMOS tube arranged in a pair, the drain of the third NMOS tube is coupled to the drain of the first PMOS tube, and the drain of the fourth NMOS tube is coupled to the drain of the second PMOS tube; the voltage holding circuit includes a third PMOS tube and a fourth PMOS tube arranged in a pair, and the gate of the third PMOS tube is coupled to the gate of the fourth PMOS tube; the latch circuit includes a cross-coupled fifth PMOS tube and a sixth PMOS tube.

[0008] In some embodiments of the present application, based on the above technical solution, the control signal includes a corresponding relationship between a preset voltage signal and a gate voltage of a third PMOS tube, and the level conversion circuit is controlled by the control signal to perform the level conversion, including: the gate voltage of the third PMOS tube is switched according to the corresponding relationship so that the operating voltages of the fifth PMOS tube and the sixth PMOS tube are within a preset threshold voltage range.

[0009] In some embodiments of the present application, based on the above technical solution, the first control module includes a first submodule coupled to the gate of the first PMOS tube, and a second submodule coupled to the gate of the third PMOS tube; the second control module includes a third submodule coupled to the first submodule, and a fourth submodule coupled to the second submodule; the control of the conduction of the first control module or the second control module according to the switch signal includes: when the switch signal is a signal output according to a preset high-voltage signal, controlling the first submodule and the second submodule to be turned on, and controlling the third submodule and the fourth submodule to be turned off; when the switch signal is a signal output according to a preset normal voltage signal, controlling the third submodule and the fourth submodule to be turned on, and controlling the first submodule and the second submodule to be turned off.

[0010] In some embodiments of the present application, based on the above technical solution, the first submodule includes a cross-coupled fifth NMOS tube and a sixth NMOS tube; the second submodule includes a cross-coupled ninth PMOS tube and a tenth PMOS tube.

[0011] In some embodiments of the present application, based on the above technical solution, the third submodule includes a ninth NMOS tube coupled to the sixth NMOS tube; the fourth submodule includes an eleventh PMOS tube coupled to the ninth PMOS tube.

[0012] In some embodiments of the present application, based on the above technical solution, the switching circuit includes a first sub-switch coupled to the first control module, and a second sub-switch coupled to the second control module; according to the voltage size of the voltage signal, a corresponding switching signal is output, including: when the voltage signal is a preset high voltage signal, the first sub-switch outputs a switching signal for indicating that the first sub-module is turned on and the third sub-module is turned off according to the voltage signal; the second sub-switch outputs a switching signal for indicating that the second sub-module is turned on and the fourth sub-module is turned off according to the voltage signal; when the voltage signal is a preset normal voltage signal, the first sub-switch outputs a switching signal for indicating that the first sub-module is turned off and the third sub-module is turned on according to the voltage signal; the second sub-switch outputs a switching signal for indicating that the second sub-module is turned off and the fourth sub-module is turned on according to the voltage signal.

[0013] In some embodiments of the present application, based on the above technical solution, the first sub-switch includes a seventeenth PMOS tube, a thirteenth NMOS tube and a fifteenth PMOS tube coupled one by one, and a transmission gate coupled to the seventeenth PMOS tube, the thirteenth NMOS tube and the fifteenth PMOS tube respectively; the transmission gate includes an eleventh NMOS tube and a seventh PMOS tube coupled to each other.

[0014] In some embodiments of the present application, based on the above technical solution, the second sub-switch includes a nineteenth PMOS tube and a fifteenth NMOS tube coupled to each other.

[0015] According to one aspect of an embodiment of the present application, a level converter and a digital logic circuit are provided, including the level converter described in the above embodiment.

[0016] In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects:

[0017] The level converter provided in the embodiment of the present application, based on the level conversion circuit, also includes a switching circuit and a control circuit including two control modules. The switching circuit outputs a corresponding switching signal by identifying the voltage magnitude of the voltage signal input to the level conversion circuit to indicate the conduction of different control modules in the control circuit, so that when the level converter converts the levels of different specification modes, the level conversion of the level conversion circuit can be controlled by the control signals output by different control modules in the control circuit, thereby improving the compatibility of the level converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 The block diagram of the overall circuit of a level converter is shown in an exemplary embodiment of the present application.

[0020] Figure 2 This is a schematic diagram of the overall circuit structure of a level conversion circuit shown in an exemplary embodiment of the present application.

[0021] Figure 3 The block diagram of the overall circuit of a level converter is shown as another exemplary embodiment of the present application.

[0022] Figure 4 The block diagram of the overall circuit of a level converter is shown as another exemplary embodiment of the present application.

[0023] Figure 5 This is a schematic diagram of the connection relationship between the switch circuit and the control circuit shown in an exemplary embodiment of the present application.

[0024] Figure 6 This is a schematic diagram of the connection relationship between a switch circuit and a control circuit according to another exemplary embodiment of the present application.

[0025] Figure 7 The block diagram of the overall circuit of a level converter is shown as another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0027] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0028] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0029] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0030] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0031] Figure 1 FIG. 1 is a block diagram of an overall circuit of a level converter shown in an exemplary embodiment of the present application. Figure 1 As shown, the level converter includes a level conversion circuit 100 , a control circuit 200 and a switch circuit 300 , wherein the control circuit 200 is coupled between the level conversion circuit 100 and the switch circuit 300 .

[0032] The level conversion circuit 100 is used to perform level conversion according to an input voltage signal.

[0033] The switch circuits 300 are arranged in pairs, and the pair of switch circuits 300 are symmetrically arranged around the level conversion circuit 100 . The switch circuits 300 are used to output corresponding switch signals according to the voltage magnitude of the voltage signal.

[0034] The control circuits 200 are also arranged in pairs, and the pair of control circuits 200 are symmetrically arranged around the level conversion circuit 100. The control circuit 200 includes a first control module and a second control module, which are used to control the conduction of the first control module or the second control module according to the switch signal, and generate a control signal corresponding to the voltage signal according to the conduction condition, so as to control the level conversion circuit 100 to perform level conversion through the control signal.

[0035] Specifically, in actual use, after the level conversion circuit 100 receives the input voltage signal, the switching circuit 300 outputs a corresponding switching signal according to the voltage size of its voltage signal, wherein different switching signals correspond to the conduction or shutdown of the first control module or the second control module, respectively, so as to realize level conversion of different specifications by switching different control modules.

[0036] The description is given by way of example, with 3.3V being the high voltage mode and 1.8V being the normal voltage mode.

[0037] When the level conversion circuit 100 receives an input voltage signal of 3.3V, the level conversion circuit 100 is in high-voltage mode, and the switch signal is used to instruct the first control module to turn on and the second control module to turn off, so that the level conversion circuit 100 can achieve level conversion corresponding to the high-voltage mode.

[0038] When the level conversion circuit 100 receives an input voltage signal of 1.8V, the level conversion circuit 100 is in the normal voltage mode, and the switch signal is used to instruct the second control module to turn on and the first control module to turn off, so that the level conversion circuit 100 can achieve level conversion corresponding to the normal voltage mode.

[0039] The level converter provided by the above-mentioned embodiment, on the basis of the level conversion circuit, further includes a switching circuit and a control circuit including two control modules. The switching circuit outputs a corresponding switching signal by identifying the voltage magnitude of the voltage signal input to the level conversion circuit to indicate the conduction of different control modules in the control circuit. In this way, when the level converter performs level conversion of different specification modes, the level conversion of the level conversion circuit can be controlled by the control signals output by different control modules in the control circuit, thereby improving the compatibility of the level converter.

[0040] In some embodiments of the present application, based on the above embodiments, Figure 2 FIG. 1 is a schematic diagram of the overall circuit structure of a level conversion circuit according to an exemplary embodiment of the present application. Figure 2 As shown, the level conversion circuit 100 includes an input circuit 101, a protection circuit 102, a voltage holding circuit 103 and a latch circuit 104 which are coupled in sequence.

[0041] In order to facilitate the understanding of the technical solution of the present application, it should be noted that, for each embodiment of the present application, the numerical values ​​corresponding to the names of different NMOS tubes are marked in the form of abbreviations in the accompanying drawings. For example, the first NMOS tube is marked as MN1 in the accompanying drawings, and the second NMOS tube is marked as MN2 in the accompanying drawings. Similarly, the numerical values ​​corresponding to the names of different PMOS tubes are also marked in the form of abbreviations in the accompanying drawings. For example, the first PMOS tube is marked as MP1 in the accompanying drawings, and the second PMOS tube is marked as MP2 in the accompanying drawings.

[0042] The input circuit 101 includes a first NMOS transistor and a second NMOS transistor arranged in pair, and the gate of the first NMOS transistor is coupled to the gate of the second NMOS transistor;

[0043] The protection circuit 102 includes a third NMOS tube and a fourth NMOS tube arranged in pairs, and a first PMOS tube and a second PMOS tube arranged in pairs, the drain of the third NMOS tube is coupled to the drain of the first PMOS tube, and the drain of the fourth NMOS tube is coupled to the drain of the second PMOS tube;

[0044] The voltage-maintaining circuit 103 includes a third PMOS tube and a fourth PMOS tube arranged in a pair, and the gate of the third PMOS tube is coupled to the gate of the fourth PMOS tube;

[0045] The latch circuit 104 includes a fifth PMOS transistor and a sixth PMOS transistor which are cross-coupled.

[0046] Specifically, the source of the first NMOS tube and the source of the second NMOS tube are used to input differential signals, so that the first NMOS tube and the second NMOS tube form an input circuit 101, which is used to clamp the source terminal voltage of the first NMOS tube and the second NMOS tube so that the voltage does not exceed the gate voltage of the first NMOS tube and the second NMOS tube, and protect other MOS tubes (not shown in the figure) connected to the corresponding ports of the source of the first NMOS tube and the source of the second NMOS tube, so that the input end of the differential signal works within a safe voltage range.

[0047] The drain of the first NMOS tube is coupled to the source of the third NMOS tube, and the drain of the second NMOS tube is coupled to the source of the fourth NMOS tube.

[0048] The drain of the third NMOS tube is coupled to the drain of the first PMOS tube, and the drain of the fourth NMOS tube is coupled to the drain of the second PMOS tube.

[0049] The third NMOS tube and the fourth NMOS tube form a first protection circuit, and the first PMOS tube and the second PMOS tube form a second protection circuit, which are used to cause a voltage drop according to the voltage difference between the input end and the output end, and adjust the voltage relationship between the output end and the input end to avoid an excessively high voltage difference between the output end and the input end, thereby playing a certain protective role for the level conversion circuit 100.

[0050] The source of the first PMOS tube is coupled to the drain of the third PMOS tube, and the source of the second PMOS tube is coupled to the drain of the fourth PMOS tube.

[0051] The source of the third PMOS tube is coupled to the drain of the fifth PMOS tube, and the source of the fourth PMOS tube is coupled to the drain of the sixth PMOS tube, so that the third PMOS tube and the fourth PMOS tube form a voltage-maintaining circuit 103, which is used to clamp the source voltage of the third PMOS tube and the fourth PMOS tube, so that the voltage is not lower than the gate voltage of the first NMOS tube and the second NMOS tube, thereby playing a certain protective role on the fifth PMOS tube and the sixth PMOS tube, so that the fifth PMOS tube and the sixth PMOS tube work within a safe voltage range.

[0052] The source of the fifth PMOS tube is coupled to the source of the sixth PMOS tube, the gate of the fifth PMOS tube is coupled to the drain of the sixth PMOS tube, and the gate of the sixth PMOS tube is coupled to the drain of the fifth PMOS tube, so that the fifth PMOS tube and the sixth PMOS tube form a latch circuit 104, whose two output nodes are cross-coupled to form negative feedback, so as to accelerate the flipping of the output signal and latch it to a stable state.

[0053] Through the above-mentioned embodiment, by setting the protection circuit 102 and the voltage holding circuit 103 between the input circuit 101 and the latch circuit 104, the protection circuit 102 reduces the voltage drop between the input end and the output end while clamping its source end voltage through the voltage holding circuit 103, so that the latch circuit 104 can better operate within a safe voltage range, so that the level converter can ensure its conversion effect when being compatible with different specifications.

[0054] It should be noted that in the structural description of the level conversion circuit 100 of the present application, the orientation or position relationship indicated by the terms vertical, up, down, horizontal, etc. is based on the orientation or position relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation and be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present application.

[0055] In addition, in the structural description of the level conversion circuit 100 of the present application, it is also necessary to explain that, unless otherwise clearly specified and limited, the coupling of the circuit structure in the above terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0056] In some embodiments of the present application, based on the above embodiments, the control signal includes a correspondence between a preset voltage signal and a gate voltage of the third PMOS tube, and the level conversion circuit 100 is controlled by the control signal to perform the level conversion, including:

[0057] The gate voltage of the third PMOS tube is switched according to the corresponding relationship, so that the operating voltages of the fifth PMOS tube and the sixth PMOS tube are within a preset threshold voltage range.

[0058] For example, if the current level converter mode is the high-voltage mode in the above example, the gate voltage signals of the first NMOS tube and the second NMOS tube can be the same as the gate voltage signals of the third PMOS tube and the fourth PMOS tube. However, when the high-voltage mode is switched to the normal-voltage mode in the above example, the gate voltage signals of the third PMOS tube and the fourth PMOS tube are switched to voltage signals different from the gate voltages of the first NMOS tube and the second NMOS tube, so that the technical solution of the present application can achieve normal operation of the level conversion in both modes. For example, in the high-voltage mode, the gate voltages of the first NMOS tube and the second NMOS tube, and the gate voltage signals of the third PMOS tube and the fourth PMOS tube are all 1.8V, but in the normal-voltage mode, the gate voltages of the first NMOS tube and the second NMOS tube are 1.8V, while the gate voltage signals of the third PMOS tube and the fourth PMOS tube are 0V.

[0059] In some embodiments of the present application, based on the above embodiments, Figure 3 FIG. 1 is a block diagram of an overall circuit of a level converter shown in another exemplary embodiment of the present application. Figure 3 As shown, the first control module includes a first submodule 201 coupled to the gate of the first PMOS tube, and a second submodule 202 coupled to the gate of the third PMOS tube; the second control module includes a third submodule 203 coupled to the first submodule 201, and a fourth submodule 204 coupled to the second submodule 202;

[0060] Controlling the conduction status of the first control module or the second control module according to the switch signal includes:

[0061] When the switch signal is a signal output according to a preset high voltage signal, the first submodule 201 and the second submodule 202 are controlled to be turned on, and the third submodule 203 and the fourth submodule 204 are controlled to be turned off;

[0062] When the switch signal is a signal output according to a preset normal voltage signal, the third submodule 203 and the fourth submodule 204 are controlled to be turned on, and the first submodule 201 and the second submodule 202 are controlled to be turned off.

[0063] Specifically, in actual use, if the level converter is in the high-voltage mode in the above example, the first submodule 201 and the second submodule 202 of the first control module are turned on, and the third submodule 203 and the fourth submodule 204 of the second control module are turned off. At the same time, since the circuits on both sides of the level conversion circuit 100 are symmetrical, the same control is also performed on the side that is symmetrical to the first control module and the second control module.

[0064] If the level converter is in the normal voltage mode in the above example, the first submodule 201 and the second submodule 202 of the first control module are turned off, and the third submodule 203 and the fourth submodule 204 of the second subcontrol module are turned on. Similarly, since the circuits on both sides of the level conversion circuit 100 are symmetrical, the same control is also performed on the side that is symmetrical to the first control module and the second control module.

[0065] Through the above implementation, during actual use, the level converter can switch the effective circuit structure in the corresponding mode according to the on and off of different submodules in the control circuit 200, so that the level converter can be compatible with more modes.

[0066] In some embodiments of the present application, based on the above embodiments, Figure 4 FIG. 1 is a block diagram of an overall circuit of a level converter according to another exemplary embodiment of the present application. Figure 4 As shown, the first submodule 201 includes a fifth NMOS transistor and a sixth NMOS transistor that are cross-coupled; the second submodule 202 includes a ninth PMOS transistor and a tenth PMOS transistor that are cross-coupled.

[0067] In some embodiments of the present application, based on the above embodiments, the third submodule 203 includes a ninth NMOS transistor coupled to the sixth NMOS transistor; and the fourth submodule 204 includes an eleventh PMOS transistor coupled to the ninth PMOS transistor.

[0068] The description is made in combination with the above two embodiments, and the first submodule 201 , the second submodule 202 , the third submodule 203 and the fourth submodule 204 are described in detail.

[0069] Specifically, the gate of the fifth NMOS tube is coupled to the drain of the ninth NMOS tube, the gate of the fifth NMOS tube is also coupled to the drain of the sixth NMOS tube, the source of the ninth NMOS tube is coupled to the source of the sixth NMOS tube, the source of the ninth NMOS tube is also coupled to the source of the fifth NMOS tube, and the source of the fifth NMOS tube is coupled to the gate of the first PMOS tube.

[0070] The gate of the tenth PMOS tube is coupled to the source of the ninth PMOS tube and the source of the eleventh PMOS tube respectively, the drain of the ninth PMOS tube is coupled to the drain of the eleventh PMOS tube and the drain of the tenth PMOS tube respectively, and the drain of the tenth PMOS tube is also coupled to the gate of the third NMOS tube.

[0071] The source of the tenth PMOS tube is respectively coupled to the gate of the fifth NMOS tube and the drain of the third NMOS tube.

[0072] It should be noted that the circuit structures of the first submodule 201, the second submodule 202, the third submodule 203 and the fourth submodule 204, which are symmetrical with the level conversion circuit 100 as the center, are the same as the above-mentioned first submodule 201, the second submodule 202, the third submodule 203 and the fourth submodule 204, and are not repeated here.

[0073] During the use of the level converter of the present application, the gate voltage of the first PMOS tube, that is, B1 shown in the figure, is controlled by the first submodule 201 and the third submodule 203. By controlling the voltage of the node B1, the first PMOS tube can work safely and normally.

[0074] For example, in the high voltage mode corresponding to 3.3V, the first submodule 201 is effective and the third submodule 203 is turned off, and the voltage of the node B1 is controlled to be the lower one between the drain voltage of the first PMOS tube and the gate voltage of the third PMOS tube, so that the first PMOS tube operates within a safe voltage range.

[0075] For another example, in the normal voltage mode corresponding to 1.8V, the first submodule 201 is turned off and the third submodule 203 is enabled, so that the voltage of the node B1 is the gate voltage of the third PMOS tube, thereby keeping the first PMOS tube in a normally open state.

[0076] At the same time, since the circuits on both sides of the level conversion circuit 100 are symmetrical, the side symmetrical to the first submodule 201 and the third submodule 203 also has the same control process.

[0077] In the use of the level converter of the present application, the gate voltage of the third NMOS tube, that is, A1 shown in the figure, is controlled by the second submodule 202 and the fourth submodule 204. By controlling the voltage of the node A1, the third NMOS tube can work safely and normally.

[0078] For example, in the high voltage mode corresponding to 3.3V, the second submodule 202 is effective, and the fourth submodule 204 is turned off, and the voltage of the node A1 is controlled to be the higher one between the drain voltage of the first PMOS tube and the gate voltage of the first NMOS tube, so that the third NMOS tube operates within a safe voltage range.

[0079] For another example, in the normal voltage mode corresponding to 1.8V, the second submodule 202 is turned off and the fourth submodule 204 is enabled, so that the voltage of the node A1 is the gate voltage of the first NMOS transistor, thereby keeping the third NMOS transistor in a normally open state.

[0080] Similarly, since the circuits on both sides of the level conversion circuit 100 are symmetrical, the side symmetrical to the second submodule 202 and the fourth submodule 204 also has the same control process.

[0081] In some embodiments of the present application, based on the above embodiments, Figure 5 FIG. 1 is a schematic diagram showing the connection relationship between the switch circuit and the control circuit according to an exemplary embodiment of the present application. Figure 5 As shown, the switch circuit 300 includes a first sub-switch 301 coupled to a first control module, and a second sub-switch 302 coupled to a second control module;

[0082] According to the voltage of the voltage signal, the corresponding switch signal is output, including:

[0083] When the voltage signal is a preset high voltage signal, the first sub-switch 301 outputs a switch signal for indicating that the first sub-module 201 is turned on and the third sub-module 203 is turned off according to the voltage signal; the second sub-switch 302 outputs a switch signal for indicating that the second sub-module 202 is turned on and the fourth sub-module 204 is turned off according to the voltage signal;

[0084] When the voltage signal is a preset constant voltage signal, the first sub-switch 301 outputs a switch signal for indicating that the first sub-module 201 is turned off and the third sub-module 203 is turned on according to the voltage signal; the second sub-switch 302 outputs a switch signal for indicating that the second sub-module 202 is turned off and the fourth sub-module 204 is turned on according to the voltage signal.

[0085] Specifically, in actual use, if the level converter is in the high-voltage mode in the above example, the voltage signal of the node C1 is the gate voltage of the third PMOS tube, so that the eleventh NMOS tube is always in a closed state within a safe voltage range, and after being combined with the seventh PMOS tube, the output can indicate that the first submodule 201 and the second submodule 202 of the first control module are turned on, and the third submodule 203 and the fourth submodule 204 of the second control module are turned off. At the same time, since the circuits on both sides of the level conversion circuit 100 are symmetrical, the same control is also performed on the side that is symmetrical to the first sub-switch 301 and the second sub-switch 302.

[0086] If the level converter is in the constant voltage mode in the above example, the voltage signal of the node C1 changes with the differential signal input to the source of the first NMOS tube, so that when the differential signal input to the source of the first NMOS tube is high, the differential signal output from the drain of the fifth PMOS tube is pulled down to 0, so that the differential signal output from the drain of the fifth PMOS tube is full swing. At the same time, after combining with the seventh PMOS tube, the output can indicate that the first submodule 201 and the second submodule 202 of the first control module are turned off, and the third submodule 203 and the fourth submodule 204 of the second control module are turned on. Similarly, since the circuits on both sides of the level conversion circuit 100 are symmetrical, the same control is performed on the side that is symmetrical to the first sub-switch 301 and the second sub-switch 302.

[0087] Through the above implementation, during actual use, the level converter can generate different sub-switch signals according to the switch circuit 300 to achieve the control effect of the corresponding control module, so that the level converter can be compatible with more modes.

[0088] In some embodiments of the present application, based on the above embodiments, Figure 6 FIG. 1 is a schematic diagram showing the connection relationship between the switch circuit and the control circuit of another exemplary embodiment of the present application. Figure 6 As shown, the first sub-switch 301 includes a seventeenth PMOS tube, a thirteenth NMOS tube and a fifteenth PMOS tube coupled one by one, and a transmission gate coupled to the seventeenth PMOS tube, the thirteenth NMOS tube and the fifteenth PMOS tube respectively;

[0089] The transmission gate includes an eleventh NMOS transistor and a seventh PMOS transistor coupled to each other.

[0090] Specifically, the drain of the seventeenth PMOS tube is coupled to the source of the thirteenth NMOS tube, the source of the thirteenth NMOS tube is also coupled to the drain of the fifteenth PMOS tube, the gate of the seventeenth PMOS tube is coupled to the gate of the thirteenth NMOS tube, and the drain of the thirteenth NMOS tube is coupled to the source of the fifteenth PMOS tube.

[0091] The drain of the seventeenth PMOS tube is coupled to the gate of the eleventh NMOS tube for outputting a C1 signal.

[0092] The drain of the eleventh NMOS tube is coupled to an output terminal for outputting a differential signal, the source of the eleventh NMOS tube is coupled to the drain of the seventh PMOS tube, the source of the eleventh NMOS tube is also connected to the gate of the fifth NMOS tube, the source of the seventh PMOS tube is coupled to the same output terminal for outputting a differential signal as the eleventh NMOS tube, and the gate of the seventh PMOS tube is coupled to the drain of the third NMOS tube.

[0093] It should be noted that the circuit symmetrical about the first sub-switch 301 and the level conversion circuit 100 is the same as the first sub-switch 301 described above, and will not be described in detail here.

[0094] By way of example, when the level converter is in use, the source voltage of the seventeenth PMOS tube is the same as the source voltage of the eleventh NMOS tube, the gate voltage of the thirteenth NMOS tube is the same as the gate voltage of the ninth NMOS tube, the source voltage of the fifteenth PMOS tube is the same as the differential signal input to the source of the first NMOS tube, and the gate voltage of the fifteenth PMOS tube is the same as the source voltage of the eleventh NMOS tube. In this way, generation of different switch signals on the first sub-switch 301 is achieved.

[0095] It should be noted that the NMOS tube substrate in the transmission gate is connected to the lowest potential point, and the PMOS tube substrate is connected to the highest potential point (VDD). The purpose is to make the PN junction between the substrate and the drain-source electrode reverse biased to prevent the current from flowing directly from the drain electrode into the substrate.

[0096] In some embodiments of the present application, based on the above embodiments, the second sub-switch 302 includes a nineteenth PMOS transistor and a fifteenth NMOS transistor coupled to each other.

[0097] Specifically, the gate of the nineteenth PMOS tube is coupled to the gate of the fifteenth NMOS tube, the drain of the nineteenth PMOS tube is coupled to the drain of the fifteenth NMOS tube, and the drain of the nineteenth PMOS tube is also coupled to the gate of the eleventh PMOS tube.

[0098] It should be noted that the circuit symmetrical about the second sub-switch 302 and the level conversion circuit 100 is the same as the second sub-switch 302 described above, and will not be described in detail here.

[0099] By way of example, when the level converter is in use, the source voltage of the nineteenth PMOS tube is the same as the source voltage of the fifth PMOS tube, the gate voltage of the nineteenth PMOS tube and the gate voltage of the fifteenth NMOS tube are respectively the same as the gate voltage of the first NMOS tube, and the source voltage of the fifteenth NMOS tube is the same as the gate voltage of the third PMOS tube, thereby realizing the generation of different switch signals on the second sub-switch 302.

[0100] In order to more clearly illustrate the relevant examples of the above-mentioned embodiments, a comprehensive description is given below based on the high pressure mode and the normal pressure mode in the above-mentioned examples to better disclose the technical solution of the present application.

[0101] Figure 7 FIG. 1 is a block diagram of an overall circuit of a level converter according to another exemplary embodiment of the present application. Figure 7 As shown, in the normal voltage mode, VDDH2 and VDDH1 are the same voltage, which can be 1.8V / 1.5V / 1.2V. This embodiment takes 1.8V as an example for explanation. In the high voltage mode, VDDH2 is 3.3V and VDDH1 is 1.8V. This embodiment takes VDDH2 as 3.3V and VDDH1 as 1.8V as an example.

[0102] In order to make the various PMOS tubes and NMOS tubes in the present application easier to understand, in the following examples, each MOS tube is briefly described by the corresponding numbers shown in the drawings, with specific reference to the connection relationship and position relationship in the drawings.

[0103] Specifically, in the high voltage mode of the present application: VDDH2 is 3.3V, VDDH1 is 1.8V, VCTRL_1 is 1.8V, and VCTRL_2 is 0V.

[0104] Among them, the voltage signal corresponding to C1 and C2 is 1.8V, and the MOS tubes MN11, MN12, MN13, MN14, MP15, and MP16 are turned off; the voltage signal corresponding to D1 and D2 is 3.3V, and the MOS tubes MP11, MP14, MN9, and MN10 are turned off.

[0105] When the input signal VIP jumps from 1.8V to 0V and VIN jumps from 0V to 1.8V, P1 jumps from 3.3V to 0V, A1 jumps from 3.3V to 1.8V, B1 jumps from 1.8V to 0V, and point Z is pulled down from 3.3V to 1.8V by MP7; ZN is pulled up from 1.8V to 3.3V by MP6, P2 jumps from 0V to 3.3V, A2 jumps from 1.8V to 3.3V, and B2 jumps from 0V to 1.8V.

[0106] Since the two sides of the level conversion circuit 100 are symmetrical, when the input signal VIP jumps from 0V to 1.8V and VIN jumps from 1.8V to 0V, there are similar processes.

[0107] In the normal voltage mode of the present application: VDDH2 is 1.8V, VDDH1 is 1.8V, VCTRL_1 is 0V, and VCTRL_2 is 1.8V.

[0108] Among them, D1 and D2 are 0V, MP11, MP14, MN9, and MN10 are turned on, A1 and A2 nodes remain unchanged at 1.8V, and B1 and B2 nodes remain unchanged at 0V.

[0109] MP17 and MP18 are closed, and C1 and C2 change with the signal input, so that Z and ZN can be pulled down to 0V.

[0110] When the input signal VIP jumps from 1.8V to 0V and VIN jumps from 0V to 1.8V, P1 jumps from 1.8V to 0V, C1 jumps from 0V to 1.8V, and node Z is pulled down from 1.8V to 0V through MN11 and MP7; ZN is pulled up from 0V to 1.8V by MP6, P2 jumps from 0V to 1.8V, and MP8 and MN12 are closed.

[0111] Since the two sides of the level conversion circuit 100 are symmetrical, when the input signal VIP jumps from 0V to 1.8V and VIN jumps from 1.8V to 0V, there are similar processes.

[0112] It can be seen that through the circuit structure design of the level converter of the present application, the level converter can be compatible with the high-voltage mode and the normal-voltage mode. Of course, the high-voltage mode does not only correspond to 3.3V, and the normal-voltage mode does not only correspond to 1.8V. The above examples are for illustration only and are not limiting.

[0113] Through the above example content, the VDDH2 power supply supported by this application can be 3.3V or 1.8V, so that the ODIO (Optical Digital Input / Output card) in 3.3V mode can be reused as the GPIO (General Purpose Input Output) in 1.8V mode, making the application range of the level converter of this application wider, thereby saving additional design costs.

[0114] In some embodiments of the present application, based on the above embodiments, the present application further discloses a digital logic circuit, which is applied with the level converter in any of the above embodiments.

[0115] At the same time, for the drawings of the above-mentioned embodiments of the present application, it should be noted that the block diagrams in the drawings illustrate the electronic components, circuit structures, and corresponding connection relationships according to the various embodiments of the present application, but do not limit their positional relationships. At the same time, the inclusion relationship of modules or electronic components is only explained through the above-mentioned embodiments, and no specific restrictions are made in the drawings.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0117] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A level converter, characterized in that: include: A level conversion circuit, used for performing level conversion according to an input voltage signal; A switch circuit symmetrically arranged around the level conversion circuit, used for outputting a corresponding switch signal according to the voltage magnitude of the voltage signal; A control circuit symmetrically arranged around the level conversion circuit, comprising a first control module and a second control module, coupled between the level conversion circuit and the switch circuit, and used to control the conduction status of the first control module or the second control module according to the switch signal, so as to control the first control module to be turned on and the second control module to be turned off when the switch signal is a signal output by a preset high voltage signal, and to control the second control module to be turned on and the first control module to be turned off when the switch signal is a signal output by a preset low voltage signal, and to generate a control signal corresponding to the voltage signal according to the conduction status, so as to control the level conversion circuit to perform the level conversion through the control signal; The level conversion circuit includes an input circuit, a protection circuit, a voltage holding circuit and a latch circuit coupled in sequence; The input circuit includes a first NMOS transistor and a second NMOS transistor arranged in pair, and the gate of the first NMOS transistor is coupled to the gate of the second NMOS transistor; The protection circuit includes a third NMOS tube and a fourth NMOS tube arranged in pairs, and a first PMOS tube and a second PMOS tube arranged in pairs, the drain of the third NMOS tube is coupled to the drain of the first PMOS tube, and the drain of the fourth NMOS tube is coupled to the drain of the second PMOS tube; The voltage-maintaining circuit includes a third PMOS tube and a fourth PMOS tube arranged in pair, and the gate of the third PMOS tube is coupled to the gate of the fourth PMOS tube; The latch circuit includes a fifth PMOS tube and a sixth PMOS tube which are cross-coupled; Among them, the drain of the first NMOS tube is coupled to the source of the third NMOS tube, the drain of the second NMOS tube is coupled to the source of the fourth NMOS tube, the source of the first PMOS tube is coupled to the drain of the third PMOS tube, the source of the second PMOS tube is coupled to the drain of the fourth PMOS tube, the source of the third PMOS tube is coupled to the drain of the fifth PMOS tube, and the source of the fourth PMOS tube is coupled to the drain of the sixth PMOS tube; the source of the first NMOS tube and the source of the second NMOS tube are used to input differential signals; the source of the fifth PMOS tube is coupled to the source of the sixth PMOS tube; the gates of the first PMOS tube, the second PMOS tube, the third NMOS tube and the fourth NMOS tube are respectively coupled to the control circuit; the gate of the fifth PMOS tube is coupled to the drain of the sixth PMOS tube, and the drain of the fifth PMOS tube is coupled to the gate of the sixth PMOS tube.

2. The level converter according to claim 1, characterized in that: The control signal includes a correspondence between a preset voltage signal and a gate voltage of the third PMOS tube, and controlling the level conversion circuit to perform the level conversion through the control signal includes: The gate voltage of the third PMOS tube is switched according to the corresponding relationship, so that the operating voltages of the fifth PMOS tube and the sixth PMOS tube are within a preset threshold voltage range.

3. The level converter according to claim 1, characterized in that: The first control module includes a first submodule coupled to the gate of the first PMOS tube, and a second submodule coupled to the gate of the third NMOS tube; the second control module includes a third submodule coupled to the first submodule, and a fourth submodule coupled to the second submodule; The controlling the conduction status of the first control module or the second control module according to the switch signal includes: When the switch signal is a signal output according to a preset high-voltage signal, the first submodule and the second submodule are controlled to be turned on, and the third submodule and the fourth submodule are controlled to be turned off; When the switch signal is a signal output according to a preset normal voltage signal, the third submodule and the fourth submodule are controlled to be turned on, and the first submodule and the second submodule are controlled to be turned off.

4. The level converter according to claim 3, characterized in that: The first submodule includes a cross-coupled fifth NMOS tube and a sixth NMOS tube; The second submodule includes a ninth PMOS transistor and a tenth PMOS transistor which are cross-coupled.

5. The level converter according to claim 4, characterized in that: The third submodule includes a ninth NMOS tube coupled to the sixth NMOS tube; The fourth submodule includes an eleventh PMOS transistor coupled to the ninth PMOS transistor.

6. The level converter according to claim 3, characterized in that: The switch circuit includes a first sub-switch coupled to the first control module, and a second sub-switch coupled to the second control module; Outputting a corresponding switch signal according to the voltage magnitude of the voltage signal includes: When the voltage signal is a preset high voltage signal, the first sub-switch outputs a switch signal for indicating that the first sub-module is turned on and the third sub-module is turned off according to the voltage signal; the second sub-switch outputs a switch signal for indicating that the second sub-module is turned on and the fourth sub-module is turned off according to the voltage signal; When the voltage signal is a preset constant voltage signal, the first sub-switch outputs a switch signal for indicating that the first sub-module is turned off and the third sub-module is turned on according to the voltage signal; the second sub-switch outputs a switch signal for indicating that the second sub-module is turned off and the fourth sub-module is turned on according to the voltage signal.

7. The level converter according to claim 6, characterized in that: The first sub-switch includes a seventeenth PMOS tube, a thirteenth NMOS tube and a fifteenth PMOS tube coupled one by one, and a transmission gate coupled to the seventeenth PMOS tube, the thirteenth NMOS tube and the fifteenth PMOS tube respectively; The transmission gate includes an eleventh NMOS transistor and a seventh PMOS transistor coupled to each other.

8. The level converter according to claim 6, characterized in that: The second sub-switch includes a nineteenth PMOS transistor and a fifteenth NMOS transistor coupled to each other.

9. A digital logic circuit, characterized in that: The method comprises a level converter as claimed in any one of claims 1 to 8.

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