Dual-frequency high-efficiency power amplifier with two controllable transmission zeros and its design method

Abstract

The invention relates to the technical field of power amplifiers, and discloses a dual-frequency high-efficiency power amplifier with two controllable transmission zeros and a design method thereof. The dual-frequency high-efficiency power amplifier comprises a transistor and a dual-frequency impedance conversion circuit, wherein the dual-frequency impedance conversion circuit comprises a first circuit, a second circuit and a third circuit. The dual-frequency high-efficiency power amplifier with two controllable transmission zeros and a design method thereof can be designed by using a dual-frequency impedance conversion circuit composed of the first circuit, the second circuit and the third circuit, and in combination with the design method of the circuit, so that a dual-frequency high-efficiency power amplifier with two controllable transmission zeros can be designed, which can effectively suppress more out-of-band frequency signals, and can design a dual-frequency high-efficiency power amplifier with good out-of-band frequency suppression for a multi-frequency wireless terminal in a mine, and at the same time, a second harmonic control circuit and two transmission zero generating circuits are integrated into the dual-frequency fundamental impedance conversion circuit, thereby greatly reducing the circuit size.

Description

Technical Field

[0001] The present invention relates to the technical field of power amplifiers, and in particular to a dual-frequency high-efficiency power amplifier with two controllable transmission zeros and a design method thereof. Background Art

[0002] With the advent of the Internet of Everything (IoE) era, the underground Internet of Things (IoT) is developing rapidly. Building underground communication infrastructure can provide mining companies with a network for remote underground sensing, monitoring, and communication, laying the foundation for future smart mines. Since my country has not yet issued communication standards for wireless terminals in underground mine environments and for M2M (Machine-to-Machine) equipment, various devices in mines typically communicate wirelessly using a variety of communication standards, such as WiFi, LoRa, ZigBee, and NB-IoT. Therefore, wireless access terminals in underground mine backbone networks must possess multi-frequency communication capabilities. However, within the confined space of a mine, multi-frequency wireless terminals can interfere with other wireless terminals. This is primarily due to the insufficient suppression of out-of-band signals by the dual-band, high-efficiency power amplifiers used. Therefore, a dual-band impedance conversion circuit with out-of-band suppression characteristics is key to solving this problem.

[0003] Currently, reconfigurable and synchronous dual-band impedance conversion circuits are commonly used to design dual-band high-efficiency power amplifiers. However, the use of PIN diodes or other RF switches in reconfigurable dual-band impedance conversion circuits significantly increases losses, resulting in insufficient efficiency in reconfigurable dual-band high-efficiency power amplifiers.

[0004] A synchronous dual-band impedance conversion circuit using harmonic tuning can solve the problem of insufficient efficiency in dual-band high-efficiency power amplifiers. However, in these dual-band high-efficiency power amplifiers, the harmonic control circuit and the dual-band fundamental impedance conversion circuit are designed separately, which makes the dual-band impedance conversion circuit larger in size.

[0005] Existing dual-band high-efficiency power amplifiers can flexibly construct a transmission zero within a certain frequency range to suppress out-of-band signals when designing a dual-band impedance conversion circuit. However, they cannot construct more controllable transmission zeros and therefore cannot suppress more out-of-band frequency signals. At the same time, the size of the dual-band impedance conversion circuit needs to be further reduced. Summary of the Invention

[0006] To address the problem in existing dual-band high-efficiency power amplifiers described above, in which a dual-band impedance conversion circuit can flexibly construct a transmission zero within a certain frequency range to suppress out-of-band signals, but cannot construct more controllable transmission zeros and suppress more out-of-band frequency signals, the present invention achieves this problem through the following technical solution: a dual-band high-efficiency power amplifier with two controllable transmission zeros, comprising a transistor and a dual-band impedance conversion circuit, wherein the dual-band impedance conversion circuit comprises a first circuit, a second circuit, and a third circuit, wherein the first circuit is used to implement a second harmonic control circuit for frequencies 2f1 and 2f2, and the second circuit and the third circuit are respectively used to eliminate the imaginary parts of two corresponding admittances at frequencies f1 and f2 looking toward the transistor end;

[0007] The first circuit includes microstrip lines TL1, TL2, and TL3, one end of the microstrip line TL1 is connected to the drain of the transistor, and the microstrip lines TL1, TL2, and TL3 are connected in series in sequence;

[0008] The second circuit includes microstrip lines TL2, TL3, and TL4, wherein the microstrip lines TL4, TL2, and TL3 are sequentially connected in series, and one end of the microstrip line TL1 is connected to the connection point of the microstrip lines TL2 and TL4. The first circuit and the second circuit share the microstrip lines TL2 and TL3, which can reduce the size of the dual-band impedance conversion circuit and simultaneously achieve dual-band second harmonic control and eliminate the imaginary part of the admittance;

[0009] The third circuit includes microstrip lines TL6, TL7, and TL8, wherein the microstrip lines TL8, TL6, and TL7 are connected in series in sequence, and the connection point between the microstrip lines TL8 and TL6 is connected to a 50Ω load resistor at the output end of the dual-frequency impedance conversion circuit;

[0010] One end of the microstrip line TL5 is connected to the connection point of the microstrip lines TL2 and TL4 , and the other end is connected to the connection point of the microstrip lines TL8 and TL6 .

[0011] The design method of a dual-band high-efficiency power amplifier with two controllable transmission zeros includes the following specific steps:

[0012] S1. Determine the operating frequencies f1 and f2 of the power amplifier, as well as the optimal fundamental impedance Z L1，f1 , Z L1，f2 and the second harmonic impedance Z L2，2f1 , Z L2，2f2 , and Z L1，f1 , Z L1，f2 is plural, Z L2，2f1 , Z L2，2f2 is a pure imaginary number, where f1<f2, f2=kf1, where k is a positive real number;

[0013] S2, select the characteristic impedance Z2 of the microstrip line TL2;

[0014] S3, calculating and obtaining the electrical lengths θ2 and θ3 of the microstrip lines TL2 and TL3 at the operating frequency f1 and the characteristic impedance Z3 of the microstrip line TL3, and calculating and obtaining the electrical length θ1 of the microstrip line TL1 at the operating frequency f1 and the characteristic impedance Z1 of the microstrip line TL1;

[0015] S4, calculating and obtaining the electrical lengths θ4, θ5 of the microstrip lines TL4, TL5 at the operating frequency f1 and the characteristic impedances Z4, Z5 of the microstrip lines TL4, TL5;

[0016] S5. Based on the calculation results of S3 and S4, determine whether Z3 and Z4 are within the feasibility parameter range, and determine whether θ4 is within the feasibility parameter range;

[0017] If Z3, Z4 or θ4 is not within the feasibility parameter range, return to S2 and reselect the characteristic impedance Z2 of the microstrip line TL2. If Z3, Z4 or θ4 is within the feasibility parameter range, proceed to the next step.

[0018] S6. Construct two controllable transmission zeros at two frequencies f3 and f4, where f3 < f4, f3 = mf1, f3 = nf1, and m and n are both positive real numbers other than 1;

[0019] S7, select the characteristic impedance Z6 of the microstrip line TL6;

[0020] S8, calculating and obtaining the electrical lengths θ6 and θ7 of the microstrip lines TL6 and TL7 at the operating frequency f1 and the characteristic impedance Z7 of the microstrip line TL7, and calculating and obtaining the electrical length θ8 of the microstrip line TL8 at the operating frequency f1 and the characteristic impedance Z8 of the microstrip line TL8;

[0021] S9. Based on the calculation results of S7 and S8, determine whether Z7 and Z8 are within the feasibility parameter range, and determine whether θ8 is within the feasibility parameter range;

[0022] If Z7, Z8 or θ8 is not within the feasibility parameter range, return to S7 and reselect the characteristic impedance Z6 of the microstrip line TL6. If Z7, Z8 or θ8 is within the feasibility parameter range, the design is completed.

[0023] Furthermore, the characteristic impedance Z2 of the microstrip line TL2 is selected in the range of 20-140Ω;

[0024] The characteristic impedance Z6 of the microstrip line TL6 is selected in the range of 20-140Ω.

[0025] Furthermore, the feasibility parameter range of Z3 and Z4 is 20-140Ω, and the feasibility parameter range of θ4 is 30-90°. An appropriate value of the characteristic impedance Z2 is selected to ensure that the calculated values ​​of Z3 and Z4 are within the range of 20-140Ω, and the value of θ4 is within the range of 30-90°.

[0026] The feasibility parameter range of Z5 is 20-140Ω, and the feasibility parameter range of θ5 is 20-40°.

[0027] Furthermore, the feasibility parameter range of Z7 and Z8 is 20-140Ω, and the feasibility parameter range of θ8 is 10-90°. An appropriate value of the characteristic impedance Z6 is selected to ensure that the calculated values ​​of Z7 and Z8 are within the range of 20-140Ω and the value of θ8 is within the range of 10-90°.

[0028] Furthermore, the microstrip lines TL1 and TL2 are cascaded to form a parallel branch of the dual-frequency impedance conversion circuit, and the input impedance of the parallel branch at 2f1 and 2f2 is Z b1 (Z b1，2f1 and Z b1，2f2 ):

[0029]

[0030] Where j is the imaginary unit in the complex number;

[0031] Since the parallel branch must generate two short-circuit points at 2f1 and 2f2, Z b1 The input impedance at the corresponding frequency must be zero, so the design parameters of the electrical length θ2 of the microstrip line TL2 and the characteristic impedance Z3 and electrical length θ3 of the microstrip line TL3 can be derived and calculated, namely:

[0032] The characteristic impedance Z3 is:

[0033] Z3=Z2tan2θ2tan2θ3=Z2tan2kθ2tan2kθ3;

[0034] The electrical lengths θ2 and θ3 are:

[0035]

[0036] Looking at the second best harmonic impedance Z on the transistor package surface at the load end L2，2f1 and Z L2，2f2 The required design value is usually a pure imaginary number, so only a microstrip line TL1 is needed to control the two second harmonic impedances to the target area. The impedance characteristic Z1 and electrical length θ1 of the microstrip line TL1 are calculated by the following formula:

[0037]

[0038] Among them, X L2，2f1 and X L2，2f2 The impedance Z L2，2f1 and Z L2，2f2 The imaginary part of the impedance Z L2，2f1 and Z L2，2f2 is a pure imaginary number, Z L2，2f1 and Z L2，2f2 Obtained by load-pull on the transistor.

[0039] Furthermore, the impedance characteristic Z4 and electrical length θ4 of the microstrip line TL4 are calculated by the following formula:

[0040]

[0041] Among them, j is the imaginary unit in the complex number, k ranges from 1.6 to 7.6, B 1，f1 、B 1，f2 They are admittance Y 1，f1 and Y 1，f2 The imaginary part of the admittance Y 1，f1 and Y 1，f2 is a complex number, and the admittance Y of the microstrip line TL1 in the direction of the transistor end at f1 and f2 is 1，f1 and Y 1，f2 According to the transmission line theory, at f1 and f2 Under the premise that the value of and the design parameters of the microstrip line TL1 are known, according to the transmission line theory (impedance equation), the admittance Y of the microstrip line TL1 in the direction of the transistor end at f1 and f2 is obtained. 1，f1 and Y 1，f2 , and the admittance Y is eliminated by the second circuit 1，f1 and Y 1，f2 The imaginary part of Y 2，f1 and Y 2，f2 , and Represents Z L1 and Z L2 The conjugate of Z L1 is the optimal fundamental impedance, Z L2 For optimal second harmonic impedance, choose Z2 between 20 and 140 Ω, ensure that the values ​​of Z3 and Z4 are also between 20 and 140 Ω, and that θ4 is between 30° and 90°.

[0042] The admittance Y is converted to 2，f1 and Y 2，f2 Transformed into Y with the same conductance G0 3，f1 and Y 3，f2 , the impedance characteristic Z5 and electrical length θ5 of the microstrip line TL5 are calculated by the following formula:

[0043]

[0044] Among them, G0 is the admittance of the 50Ω load resistor at the output end of the dual-frequency impedance transformation circuit, G 1，f1 , G 1，f2 are respectively the real parts of the admittances Y 1，f1 and Y 1，f2 , and are also the real parts of the admittances Y 2，f1 and Y 2，f2 .

[0045] Furthermore, use the third circuit to cancel the imaginary parts of the admittances Y 3，f1 and Y 3，f2 ; among them, cascade TL6 and TL7 as well, and construct two transmission zeros at f3 and f4 respectively (f3 < f4, f3 = mf1, f3 = nf1), and the two frequencies f3 and f4 can be arbitrarily selected.

[0046] Cascade the microstrip lines TL6 and TL7 to form the parallel branch of the dual-frequency impedance transformation circuit, and the characteristic impedance Z7 is:

[0047] Z7 = Z6tanmθ6tanmθ7 = Z6tannθ6tannθ7;

[0048] The electrical lengths θ6 and θ7 are:

[0049]

[0050] The impedance characteristic Z8 and the electrical length θ8 of the microstrip line TL8 are calculated by the following formulas:

[0051]

[0052] Among them,

[0053]

[0054] Among them, j is the imaginary unit in complex numbers, the value range of k is 1.6 - 7.6, B 2，f1 , B 2，f2 are respectively the imaginary parts of the admittances Y 3，f1 and Y 3，f2 , and the admittances Y 3，f1 and Y 3，f2 seen by the microstrip line TL5 in the direction of the transistor end at f1 and f2 are calculated according to the transmission line theory. Reasonably select Z6 between 20 and 140Ω to ensure that the values of Z7 and Z8 are also within the range of 20 to 140Ω, and θ8 is between 10° and 90°.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] The dual-frequency high-efficiency power amplifier with two controllable transmission zeros and the design method thereof can be designed by using a dual-frequency impedance conversion circuit composed of a first circuit, a second circuit, and a third circuit, in combination with the design method of the circuit. The dual-frequency high-efficiency power amplifier with two controllable transmission zeros can flexibly select two out-of-band frequency signals for effective suppression, and can be used to design a dual-frequency high-efficiency power amplifier with good out-of-band frequency suppression for multi-frequency wireless terminals in mines. At the same time, the second harmonic control circuit and the two transmission zero generation circuits are integrated into the dual-frequency fundamental impedance conversion circuit, thereby greatly reducing the circuit size. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 Schematic diagram of the dual-frequency impedance conversion circuit structure of the transistor output end of the present invention;

[0058] Figure 2 A schematic diagram of a dual-frequency impedance conversion circuit at the output end of a transistor according to an embodiment of the present invention and a simulated impedance trajectory of the circuit when viewed from the transistor package surface toward the load end;

[0059] Figure 3 A schematic diagram of a dual-frequency impedance conversion circuit at a transistor input end and a simulated impedance trajectory of the circuit when viewed from a specified end face toward a source end in an embodiment of the present invention;

[0060] Figure 4 Schematic diagram of the relationship between the simulation results of the gain and power added efficiency and the output power of the dual-band high-efficiency power amplifier in an embodiment of the present invention;

[0061] Figure 5 Schematic diagram of the relationship between the gain, output power and power-added efficiency simulation results and frequency of the dual-band high-efficiency power amplifier in an embodiment of the present invention;

[0062] Figure 6 Schematic diagram of the relationship between output power simulation results and frequency of a dual-band high-efficiency power amplifier according to an embodiment of the present invention;

[0063] Figure 7 The circuit layout and physical schematic diagram of the dual-band high-efficiency power amplifier in an embodiment of the present invention;

[0064] Figure 8 P is the test result of the dual-band high-efficiency power amplifier in the embodiment of the present invention. out , a diagram showing the relationship between Gain and PAE and frequency;

[0065] Figure 9 The P values ​​of the dual-band high-efficiency power amplifier tested at 0.7 GHz and 2.64 GHz in the embodiment of the present invention are respectively out, Gain and PAE and P in Schematic diagram of the relationship between

[0066] Figure 10 This is a flow chart for designing a dual-frequency impedance conversion circuit at the transistor output end of the present invention. DETAILED DESCRIPTION

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0068] The embodiments of the dual-band high-efficiency power amplifier with two controllable transmission zeros and the design method thereof are as follows:

[0069] See also Figure 1 、 Figure 10 A dual-frequency high-efficiency power amplifier with two controllable transmission zeros includes a transistor and a dual-frequency impedance conversion circuit. The dual-frequency impedance conversion circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is used to implement a second harmonic control circuit for frequencies 2f1 and 2f2. The second circuit and the third circuit are used to eliminate the imaginary parts of two corresponding admittances viewed toward the transistor end at frequencies f1 and f2, respectively.

[0070] The first circuit includes microstrip lines TL1, TL2, and TL3, one end of which is connected to the drain of the transistor, and the microstrip lines TL1, TL2, and TL3 are connected in series in sequence. The second circuit includes microstrip lines TL2, TL3, and TL4, and the microstrip lines TL4, TL2, and TL3 are connected in series in sequence. One end of the microstrip line TL1 is connected to the connection point of the microstrip lines TL2 and TL4. The first circuit and the second circuit share the microstrip lines TL2 and TL3, which can reduce the size of the dual-band impedance conversion circuit while achieving dual-band second harmonic control and eliminating the imaginary part of the admittance.

[0071] The third circuit includes microstrip lines TL6, TL7, and TL8, which are connected in series in sequence. The connection between microstrip lines TL8 and TL6 is connected to a 50Ω load resistor at the output end of the dual-frequency impedance conversion circuit; one end of microstrip line TL5 is connected to the connection between microstrip lines TL2 and TL4, and the other end is connected to the connection between microstrip lines TL8 and TL6.

[0072] The design method of a dual-band high-efficiency power amplifier with two controllable transmission zeros includes the following specific steps:

[0073] S1. Determine the operating frequencies f1 and f2 of the power amplifier, as well as the optimal fundamental impedance ZL1，f1 , Z L1，f2 and the optimal second harmonic impedance Z L2，2f1 , Z L2，2f2 , and Z L1，f1 , Z L1，f2 is plural, Z L2，2f1 , Z L2，2f2 is a pure imaginary number, where f1<f2, f2=kf1, where k is a positive real number;

[0074] S2, select the characteristic impedance Z2 of the microstrip line TL2, the selection range of the characteristic impedance Z2 of the microstrip line TL2 is 20-140Ω;

[0075] S3, calculating and obtaining the electrical lengths θ2 and θ3 of the microstrip lines TL2 and TL3 at the operating frequency f1 and the characteristic impedance Z3 of the microstrip line TL3, and calculating and obtaining the electrical length θ1 of the microstrip line TL1 at the operating frequency f1 and the characteristic impedance Z1 of the microstrip line TL1;

[0076] The microstrip lines TL1 and TL2 are cascaded to form a parallel branch of the dual-frequency impedance conversion circuit. The input impedance of the parallel branch at 2f1 and 2f2 is Z b1 (Z b1，2f1 and Z b1，2f2 ):

[0077]

[0078] Where j is the imaginary unit in the complex number;

[0079] Since the parallel branch must generate two short-circuit points at 2f1 and 2f2, Z b1 The input impedance at the corresponding frequency must be zero, so the design parameters of the electrical length θ2 of the microstrip line TL2 and the characteristic impedance Z3 and electrical length θ3 of the microstrip line TL3 can be derived and calculated, namely:

[0080] The characteristic impedance Z3 is:

[0081] Z3=Z2tan2θ2tan2θ3=Z2tan2kθ2tan2kθ3;

[0082] The electrical lengths θ2 and θ3 are:

[0083]

[0084] The second harmonic impedance Z viewed from the transistor package surface to the load end L2，2f1 and Z L2，2f2 The required design value is usually a pure imaginary number, so only a microstrip line TL1 is needed to control the two second harmonic impedances to the target area. The impedance characteristic Z1 and electrical length θ1 of the microstrip line TL1 are calculated by the following formula:

[0085]

[0086] Among them, X L2，2f1 and X L2，2f2 The impedance Z L2，2f1 and Z L2，2f2 The imaginary part of the impedance Z L2，2f1 and Z L2，2f2 By performing load pulling on the transistor, we can get X L2，2f1 and X L2，2f2 .

[0087] S4, calculating and obtaining the electrical lengths θ4, θ5 of the microstrip lines TL4, TL5 at the operating frequency f1 and the characteristic impedances Z4, Z5 of the microstrip lines TL4, TL5;

[0088] The impedance characteristic Z4 and electrical length θ4 of the microstrip line TL4 are calculated by the following formula:

[0089]

[0090] Among them, j is the imaginary unit in the complex number, k ranges from 1.6 to 7.6, B 1，f1 、B 1，f2 They are admittance Y 1，f1 and Y 1，f2 The imaginary part of the admittance Y 1，f1 and Y 1，f2 is a complex number, and the admittance Y of the microstrip line TL1 in the direction of the transistor end at f1 and f2 is 1，f1 and Y 1，f2 According to the transmission line theory, at f1 and f2 Under the premise that the value of and the design parameters of the microstrip line TL1 are known, according to the transmission line theory (impedance equation), the admittance Y in the direction of the transistor end at f1 and f2 is obtained. 1，f1 and Y 1，f2 , and the admittance Y is eliminated by the second circuit 1，f1 and Y 1，f2 The imaginary part of Y 2，f1 and Y 2，f2 , and Represents Z L1 and Z L2 The conjugate of Z L1 is the optimal fundamental impedance, Z L2 For optimal second harmonic impedance, choose Z2 between 20 and 140 Ω, ensure that the values ​​of Z3 and Z4 are also between 20 and 140 Ω, and that θ4 is between 30° and 90°.

[0091] The admittance Y is converted to 2，f1and Y 2，f2 Transformed into Y with the same conductance G0 3，f1 and Y 3，f2 , the impedance characteristic Z5 and electrical length θ5 of the microstrip line TL5 are calculated by the following formula:

[0092]

[0093] Among them, G0 is the admittance of the 50Ω load resistor at the output end of the dual-frequency impedance conversion circuit, G 1，f1 , G 1，f2 Y 1，f1 and Y 1，f2 The real part of the admittance Y 2，f1 and Y 2，f2 The feasibility parameter range of Z5 is 20-140Ω, and the feasibility parameter range of θ5 is 20-40°.

[0094] S5. Based on the calculation results of S3 and S4, determine whether Z3 and Z4 are within the feasibility parameter range, and determine whether θ4 is within the feasibility parameter range. The feasibility parameter range of Z3 and Z4 is 20-140Ω, and the feasibility parameter range of θ4 is 30-90°;

[0095] If Z3, Z4, or θ4 is not within the feasibility parameter range, return to S2 and reselect the characteristic impedance Z2 of the microstrip line TL2. Select an appropriate value of the characteristic impedance Z2 to ensure that the calculated values ​​of Z3 and Z4 are within the range of 20-140Ω and the value of θ4 is within the range of 30-90°. If Z3, Z4, or θ4 is within the feasibility parameter range, proceed to the next step.

[0096] S6. Determine two controllable transmission zeros at two frequencies f3 and f4, where f3 < f4, f3 = mf1, f3 = nf1, and m and n are both non-1 positive real numbers;

[0097] S7, selecting a characteristic impedance Z6 of the microstrip line TL6, wherein the characteristic impedance Z6 of the microstrip line TL6 is selected in a range of 20-140Ω;

[0098] S8, calculating and obtaining the electrical lengths θ6 and θ7 of the microstrip lines TL6 and TL7 at the operating frequency f1 and the characteristic impedance Z7 of the microstrip line TL7, and calculating and obtaining the electrical length θ8 of the microstrip line TL8 at the operating frequency f1 and the characteristic impedance Z8 of the microstrip line TL8;

[0099] Use the third circuit to cancel the admittance Y 3，f1 and Y 3，f2The imaginary part; where TL6 and TL7 are also cascaded, and two transmission zeros are constructed at f3 and f4 respectively (f3 < f4, f3 = mf1, f3 = nf1), and these two frequencies f3 and f4 can be arbitrarily selected.

[0100] Cascade the microstrip lines TL6 and TL7 to form the parallel branch of the dual - frequency impedance transformation circuit. The characteristic impedance Z7 is:

[0101] Z7 = Z6tanmθ6tanmθ7 = Z6tannθ6tannθ7;

[0102] The electrical lengths θ6 and θ7 are:

[0103]

[0104] The impedance characteristic Z8 and the electrical length θ8 of the microstrip line TL8 are calculated by the following formulas:

[0105]

[0106]

[0107] Where,

[0108]

[0109] Where j is the imaginary unit in complex numbers, the value range of k is 1.6 - 7.6, B 2，f1 、B 2，f2 are respectively the imaginary parts of the admittances Y 3，f1 and Y 3，f2 The admittances Y 3，f1 and Y 3，f2 seen by the microstrip line TL5 at f1 and f2 in the direction of the transistor terminal are obtained according to the transmission line theory. Reasonably select Z6 within 20 to 140Ω to ensure that the values of Z7 and Z8 are also within the range of 20 to 140Ω, and θ8 is between 10° and 90°.

[0110] S9. Based on the calculation results of S7 and S8, judge whether Z7 and Z8 are within the feasible parameter range, and judge whether θ8 is within the feasible parameter range. The feasible parameter range of Z7 and Z8 is 20 - 140Ω, and the feasible parameter range of θ8 is 10 - 90°;

[0111] If Z7, Z8 or θ8 is not within the feasible parameter range, return to S7 and re - select the characteristic impedance Z6 of the microstrip line TL6. If Z7, Z8 or θ8 is within the feasible parameter range, the design is completed. Select an appropriate value of the characteristic impedance Z6 to ensure that the calculated values of Z7 and Z8 are within the range of 20 - 140Ω, and the value of θ8 is within the range of 10 - 90°.

[0112] Dual-band high-efficiency power amplifier design example:

[0113] The transistor used is a dual-band high-efficiency power amplifier with an operating frequency of 0.7 and 2.6 GHz, and the gate voltage V GS = -2.9V and drain voltage V DS = 28V. A dual-frequency impedance conversion circuit transforms the 50Ω load resistance into the optimal fundamental and second harmonic impedances at the transistor package surface at both 0.7 and 2.6GHz operating frequencies. To further improve efficiency, the second harmonic source impedance is controlled in the input matching network. In the Advanced Design System (ADS) electromagnetic simulation tool, source-pull and load-pull techniques are used to obtain the optimal fundamental and second harmonic load impedances, as well as the optimal fundamental and second harmonic source impedances, at 0.7 and 2.6GHz, as shown in the following table:

[0114]

[0115] Figure 2 The designed dual-frequency impedance conversion circuit at the output of the transistor and the impedance trajectory of the circuit looking at the load end are given. By reasonably selecting the values ​​of Z2 and Z6 to minimize the difference in characteristic impedance between adjacent cross-linked microstrip lines, the discontinuity of adjacent microstrip lines can be effectively reduced, which is beneficial to the accuracy of electromagnetic simulation. Figure 2 From the designed circuit, it can be seen that the characteristic impedance of each microstrip line is between 30 and 85Ω, and the impedances at 0.7, 1.4, 2.6, and 5.2 GHz obtained by circuit simulation almost overlap with the optimal target impedance.

[0116] In order to improve the working efficiency of dual-frequency, the second harmonic source impedance control design is carried out at the two working frequencies of 0.7 and 2.6 GHz. The designed input end dual-frequency impedance conversion circuit is as follows: Figure 3 As shown. Figure 3 As can be seen, a parallel circuit consisting of a 2.2pF capacitor and an 8.2Ω resistor, along with a microstrip line, forms a stable circuit, ensuring full-band stability over the 0.7-2.6GHz range. Furthermore, the second harmonic source impedance control circuit was designed using the same circuit structure as the second harmonic load impedance control. The final simulation results show that the impedance at the specified end face looking toward the source end is essentially consistent with the target source impedance.

[0117] The performance of the designed dual-band high-efficiency power amplifier is verified by simulation. Figure 4 and Figure 5 The relationship between gain and power added efficiency with output power and the relationship between gain, output power and power added efficiency with frequency are given respectively. Figure 5It can be seen that at 0.7 and 2.6 GHz, when the maximum power increase efficiency is 81% and 71.5% respectively, the gain is 16.7 and 12.4 dB respectively, and the output power is 42.2 and 41.9 dBm respectively. Figure 6 It shows that in the 0.6-0.8GHz and 2.5-2.7GHz frequency bands, when the input power is 25.5 and 29.5dBm respectively, the maximum gain, output power and power added efficiency of the corresponding frequency band are reached at 0.7 and 2.6GHz respectively, and the gain, output power and power added efficiency of the power amplifier are significantly greater when operating in the low frequency band of 0.7GHz than in the high frequency band of 2.6GHz.

[0118] In order to further determine the out-of-band suppression performance of the transmission zero designed at 0.9 and 2.1 GHz, the output power variation characteristics of the two frequency bands of 0.3-1 GHz and 2-3 GHz are simulated, and the input power P of the two frequency bands is in They are 25.5 and 29.5dBm respectively. The simulation results are as follows Figure 6 As shown. Figure 6 It can be seen that the output powers at 0.7 and 2.6 GHz are 42.2 and 41.9 dBm respectively, while the output powers at 0.9 and 2.1 GHz are only -0.9 and -22.9 dBm. It can be intuitively observed that two obvious high suppression points are formed at 0.9 and 2.1 GHz in the two corresponding frequency bands.

[0119] Dual-band high-efficiency power amplifier performance test:

[0120] Select high frequency circuit F4BM-220 plate (ε r =2.2, H = 0.762mm, tanδ = 0.0011) for circuit design, the designed circuit layout and the actual object are as follows Figure 7 As shown in the figure, all the required capacitors are high-Q capacitors of the ATC600F series from AVX. Figure 2 and Figure 3 In the input-output dual-frequency impedance conversion circuit given in [1], the terminals of the four parallel short-circuited branches must be short-circuited at 0.7 and 2.6 GHz respectively. Four 68pF bypass capacitors are used in the low-frequency band of 0.7 GHz to achieve a good short-circuit effect, while parallel lumped capacitors are also used in the high-frequency band of 2.6 GHz. Simulation results show that the efficiency of the dual-frequency high-efficiency power amplifier at 2.6 GHz is somewhat lower than that of the short-circuited four-segment microstrip fan-out line. Therefore, high-Q capacitors and microstrip fan-out lines are connected in parallel at the terminals of the four parallel short-circuited branches to achieve the purpose of short-circuiting at the two operating frequencies.

[0121] The dual-band high-efficiency power amplifier was tested for a single-carrier large signal. The input power in the frequency range of 0.5 to 1 GHz and the frequency range of 2 to 3 GHz were 24.7 and 29.7 dBm respectively. The output power P out , Gain and Power Added Efficiency PAE Figure 8 As shown. Figure 8 It can be seen that in the 0.5-1 GHz and 2-3 GHz frequency bands, the maximum power-added efficiency (PAE) reaches 83.2% and 71.9% at 0.7 and 2.64 GHz, respectively, with output powers of 41.9 and 40.9 dBm, respectively. High suppression is observed at 0.9 and 2.08 GHz, with output powers of only 1.9 and -8.1 dBm, respectively. Comparison between testing and simulation revealed that the operating frequency in the high-frequency band has shifted from 2.6 GHz to 2.64 GHz, and the transmission zero in the high-frequency band has shifted from 2.1 GHz to 2.08 GHz. This frequency shift is primarily due to circuit processing errors, and therefore the impact is more pronounced in the high-frequency band.

[0122] Figure 9 The output power P tested at 0.7 and 2.64 GHz is given. out , Gain and power added efficiency PAE and input power P in The relationship between the input power P in Continuously increasing, the output power P out The power added efficiency (PAE) increases and gradually approaches saturation, while the gain decreases. When the maximum power added efficiency (PAE) reaches 83.2% and 71.9%, respectively, the gains are 17.2 and 11.2 dB, respectively. The table below lists the performance of dual-band high-efficiency power amplifiers reported in recent years. By comparison with some existing dual-band high-efficiency power amplifiers, the designed dual-band high-efficiency power amplifier has the highest power added efficiency and gain in both operating frequency bands, and its output power is also higher than the indicators listed in Comparative Examples 1 and 4. More importantly, the designed dual-band high-efficiency power amplifier has two controllable transmission zeros, which can suppress two out-of-band frequencies and have better out-of-band suppression characteristics.

[0123]

[0124] As can be seen from the above, a high-efficiency dual-band power amplifier operating at 0.7 and 2.6 GHz was designed using the circuit proposed in this invention. Two transmission zeros were designed at 0.9 and 2.1 GHz. Testing verified that the dual-band high-efficiency power amplifier achieved maximum power-added efficiencies of 83.2% and 71.9% at output powers of 41.9 and 40.9 dBm at 0.7 and 2.64 GHz, respectively. Furthermore, the output powers at 0.9 and 2.08 GHz were only 1.9 and -8.1 dBm, respectively, demonstrating excellent rejection characteristics. Simulation and test results confirm the effectiveness of the proposed design method, enabling the design of a high-efficiency dual-band power amplifier with excellent out-of-band frequency rejection for multi-band wireless terminals in underground mines.

[0125] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A design method for a dual-frequency high-efficiency power amplifier with two controllable transmission zeros, characterized in that: It includes a transistor and a dual-frequency impedance conversion circuit, wherein the dual-frequency impedance conversion circuit includes a first circuit, a second circuit and a third circuit; The first circuit includes microstrip lines TL1, TL2, and TL3, one end of the microstrip line TL1 is connected to the drain of the transistor, and the microstrip lines TL1, TL2, and TL3 are connected in series in sequence; The second circuit includes microstrip lines TL2, TL3, and TL4, wherein the microstrip lines TL4, TL2, and TL3 are connected in series in sequence, and one end of the microstrip line TL1 is connected to the connection point of the microstrip lines TL2 and TL4; The third circuit includes microstrip lines TL6, TL7, and TL8, wherein the microstrip lines TL8, TL6, and TL7 are connected in series in sequence, and the connection point between the microstrip lines TL8 and TL6 is connected to the load resistor at the output end of the dual-frequency impedance conversion circuit; One end of the microstrip line TL5 is connected to the connection point of the microstrip lines TL2 and TL4, and the other end is connected to the connection point of the microstrip lines TL8 and TL6; The design method includes the following specific steps: S1. Determine the operating frequencies f1 and f2 of the power amplifier and the optimal fundamental impedance Z on the transistor package surface L1，f1 , Z L1，f2 and the optimal second harmonic impedance Z L2，2f1 , Z L2，2f2 , and Z L1，f1 , Z L1，f2 is a plural number, Z L2，2f1 , Z L2，2f2 is a pure imaginary number, where f1<f2, f2=kf1, where k is a positive real number; S2, select the characteristic impedance Z2 of the microstrip line TL2; S3, calculating and obtaining the electrical lengths θ2 and θ3 of the microstrip lines TL2 and TL3 at the operating frequency f1 and the characteristic impedance Z3 of the microstrip line TL3, and calculating and obtaining the electrical length θ1 of the microstrip line TL1 at the operating frequency f1 and the characteristic impedance Z1 of the microstrip line TL1; S4, calculating and obtaining the electrical lengths θ4, θ5 of the microstrip lines TL4, TL5 at the operating frequency f1 and the characteristic impedances Z4, Z5 of the microstrip lines TL4, TL5; S5. Based on the calculation results of S3 and S4, determine whether Z3 and Z4 are within the feasibility parameter range, and determine whether θ4 is within the feasibility parameter range; If Z3, Z4 or θ4 is not within the feasibility parameter range, return to S2 and reselect the characteristic impedance Z2 of the microstrip line TL2. If Z3, Z4 or θ4 is within the feasibility parameter range, proceed to the next step; S6. Construct two controllable transmission zeros at two frequencies f3 and f4, where f3 < f4, f3 = mf1, f3 = nf1, and m and n are both positive real numbers other than 1; S7, select the characteristic impedance Z6 of the microstrip line TL6; S8, calculating and obtaining the electrical lengths θ6 and θ7 of the microstrip lines TL6 and TL7 at the operating frequency f1 and the characteristic impedance Z7 of the microstrip line TL7, and calculating and obtaining the electrical length θ8 of the microstrip line TL8 at the operating frequency f1 and the characteristic impedance Z8 of the microstrip line TL8; S9, based on the calculation results of S7 and S8, determine whether Z7 and Z8 are within the feasibility parameter range, and determine whether θ8 is within the feasibility parameter range; If Z7, Z8 or θ8 is not within the feasibility parameter range, return to S7 and reselect the characteristic impedance Z6 of the microstrip line TL6. If Z7, Z8 or θ8 is within the feasibility parameter range, the design is completed.

2. The design method of a dual-frequency high-efficiency power amplifier with two controllable transmission zeros according to claim 1, characterized in that: The characteristic impedance Z2 of the microstrip line TL2 is selected in the range of 20-140Ω; The characteristic impedance Z6 of the microstrip line TL6 is selected in the range of 20-140Ω.

3. The design method of a dual-frequency high-efficiency power amplifier with two controllable transmission zeros according to claim 2, characterized in that: The feasibility parameter range of Z3 and Z4 is 20-140Ω, and the feasibility parameter range of θ4 is 30-90°; The feasibility parameter range of Z5 is 20-140Ω, and the feasibility parameter range of θ5 is 20-40°.

4. The design method of a dual-frequency high-efficiency power amplifier with two controllable transmission zeros according to claim 3, characterized in that: The feasibility parameter range of Z7 and Z8 is 20-140Ω, and the feasibility parameter range of θ8 is 10-90°.

5. The design method of a dual-frequency high-efficiency power amplifier with two controllable transmission zeros according to claim 4, characterized in that: The microstrip lines TL1 and TL2 are cascaded to form a parallel branch of the dual-frequency impedance conversion circuit. The input impedance of the parallel branch at 2f1 and 2f2 is Z b1 , Z b1 Including Z b1，2f1 and Z b1，2f2 : Where j is the imaginary unit in the complex number; The characteristic impedance Z3 is: Z3=Z2 tan2θ2tan2θ3=Z2 tan2kθ2tan2kθ3; The electrical lengths θ2 and θ3 are: The characteristic impedance Z1 and electrical length θ1 of the microstrip line TL1 are calculated by the following formula: Among them, X L2，2f1 and X L2，2f2 The optimal second harmonic impedance Z is L2，2f1 and Z L2，2f2 The imaginary part, Z L2，2f1 and Z L2，2f2 Obtained by load-pulling the transistor.

6. The design method of a dual-frequency high-efficiency power amplifier with two controllable transmission zeros according to claim 5, characterized in that: The characteristic impedance Z4 and electrical length θ4 of the microstrip line TL4 are calculated by the following formula: Where j is the imaginary unit in the complex number, k ranges from 1.6 to 7.6, and B 1，f1 , B 1，f2 They are respectively the admittance Y 1，f1 and Y 1，f2 The imaginary part of the admittance Y 1，f1 and Y 1，f2 is a complex number, and the admittance Y of the microstrip line TL1 in the direction of the transistor end at f1 and f2 is 1，f1 and Y 1，f2 Obtained from calculations based on transmission line theory; The impedance characteristic Z5 and electrical length θ5 of the microstrip line TL5 are calculated by the following formula: Where G0 is the admittance of the 50Ω load resistor at the output of the dual-frequency impedance conversion circuit, G 1，f1 , G 1，f2 They are respectively the admittance Y 1，f1 and Y 1，f2 The real part of the admittance Y 2，f1 and Y 2，f2 The real part of .

7. The design method of a dual-frequency high-efficiency power amplifier with two controllable transmission zeros according to claim 6, characterized in that: The microstrip lines TL6 and TL7 are cascaded to form parallel branches of the dual-frequency impedance conversion circuit, and the characteristic impedance Z7 is: Z7=Z6 tanmθ6tanmθ7=Z6 tannθ6tannθ7; The electrical lengths θ6 and θ7 are: The impedance characteristic Z8 and electrical length θ8 of the microstrip line TL8 are calculated by the following formula: in, Where j is the imaginary unit in the complex number, k ranges from 1.6 to 7.6, and B 2，f1 , B 2，f2 They are respectively the admittance Y 3，f1 and Y 3，f2 The imaginary part of the microstrip line TL5 sees the admittance Y of the transistor end at f1 and f2. 3，f1 and Y 3，f2 It is calculated based on transmission line theory.

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