A current detection circuit for a high-side switch

Abstract

The invention relates to the technical field of current detection, and discloses a current detection circuit of a high-side switch, comprising a chopping demodulation unit, an auto-zero unit and a current feedback unit; the chopping demodulation unit comprises a chopping unit, an offset voltage source VOS1 and a demodulation amplifier unit; in actual use, the invention detects an output signal of the chopping demodulation unit through the auto-zero unit, generates a feedback current input to the chopping demodulation unit through the current feedback unit, adjusts the output of the chopping demodulation unit through the feedback current, thereby eliminating high-frequency offset voltage ripple in the signal output by the chopping demodulation unit through current feedback; and a low-pass filter is removed from the chopping demodulation unit, so that the bandwidth of an operational amplifier and the response speed of a circuit can be improved; in addition, a small-area feedback current generating circuit is used to replace a large-area filter circuit, so that the chip area can be saved.

Description

Technical Field

[0001] The present invention relates to the technical field of current detection, and in particular to a current detection circuit of a high-side switch. Background Art

[0002] High-side switches are a common circuit used in manufacturing, especially in the automotive electronics field as load switches, or as hot-swap controllers and surge suppressors with protection functions. When a high-side switch is used as a load switch, in order to diagnose whether the load is working properly and provide feedback to the microcontroller, it is necessary to accurately measure the output current and control the output power.

[0003] Currently, current sampling of high-side switches is mostly achieved through the following two methods:

[0004] Method 1: Through Figure 1 The resistor sampling method shown in the figure is implemented by detecting the voltage through the sampling resistor Rsense in the load current path, and then applying the detection voltage to the resistor R1 by using the virtual short and virtual break of the amplifier to form a sampling current on the PMOS tube, the size of which is (Rsense ILoad) / R1, and then the sampling current is given to the resistor Rout to form a voltage Vout;

[0005] In actual use, although this sampling method has a simple structure, it has strict restrictions on the load power level. When the load current is large, a large power consumption will be generated on the resistor Rsense. In addition, there are strict requirements for the resistance value and accuracy of Rsense.

[0006] Method 2: Through Figure 2 The principle of the SenseFET sampling shown is to use the original cell ratio of the main power tube and the sampling mirror tube of the VDMOS power tube, and control the source voltage through the op amp loop to make the port voltage of the main power tube and the sampling mirror tube exactly the same, forming a sampling current proportional to the load current. This ratio is the original cell ratio of the sampling mirror tube to the main power tube. However, this method needs to strictly control the offset voltage of the op amp in actual use to avoid the current sampling error caused by the op amp offset.

[0007] Currently, calibration or pre-setting of the adjustment amount is generally used to reduce the offset, but this method of reducing the offset will often produce deviations with the use time or temperature changes. The dynamic elimination technology of the offset solves this problem well. It can not only eliminate the offset within the entire system service life, but also dynamically eliminate the changing offset amount.

[0008] The traditional method of eliminating offset dynamically in op amps is to use chopping or auto-zeroing technology. The chopping offset elimination technology uses chopping to modulate the input signal, modulate the frequency of the input signal to the chopping switching frequency, and amplify the high-frequency input signal and the low-frequency offset voltage at the same time when passing through the op amp. After chopping demodulation, the amplified input signal frequency is restored to low frequency, and the amplified offset voltage frequency is modulated to high frequency. Finally, the high-frequency offset voltage signal is eliminated through a low-pass filter, retaining the low-frequency effective output signal. The principle is as follows: Figure 3 shown.

[0009] The principle of the auto-zero technology is to sample and offset the offset voltage in two clock cycles to eliminate the offset voltage. The schematic diagram is as follows: Figure 4 As shown, the offset voltage is V OS In the F1 cycle, switches S2 and S3 are closed, switches S1 and S4 are open, and a voltage drop V is formed on capacitor C1. C =V OS ; In the F2 cycle, switches S1 and S4 are closed, switches S2 and S3 are open, Vin is input, and V on the capacitor C =V OS , to offset the offset voltage V at the positive input of the op amp OS , output voltage Vout = Vin A, the op amp output is formed after the offset voltage is eliminated during the F2 cycle.

[0010] Although they can reduce the offset voltage, chopper amplifiers and auto-zero amplifiers have their own obvious defects. Chopper amplifiers will introduce chopper switching noise at the chopping frequency, and considering the recovery characteristics of the MOS switch, the chopping frequency cannot be too high. At the same time, the signal must pass through a low-pass filter with a frequency lower than the chopping frequency before output, so the overall bandwidth of the chopper amplifier is narrow and the response speed is low when it is put into the system. The defect of the auto-zero amplifier is that it is difficult to achieve signal amplification in continuous time through a simple structure, and sampling will cause noise to fold back to the baseband, causing in-band noise aliasing and generating large noise interference. Summary of the invention

[0011] In view of the shortcomings of the background technology, the present invention provides a current detection circuit for a high-side switch. The technical problem to be solved is that when the current detection circuit of the existing high-side switch uses chopping and auto-zeroing to reduce the offset voltage of the operational amplifier, there are problems such as the need for a low-pass filter, narrow bandwidth, and inability to achieve signal amplification in continuous time.

[0012] In order to solve the above technical problems, the present invention provides the following technical solutions: a current detection circuit of a high-side switch, comprising a chopping demodulation unit, an auto-zero unit and a current feedback unit;

[0013] The chopping demodulation unit includes a chopping unit, an offset voltage source VOS1 and a demodulation amplifier unit; the auto-zero unit includes a first operational amplifier unit, a second operational amplifier unit, a switch S1, a switch S2, a switch S3, a capacitor C1, a capacitor C2, an offset voltage source VOS2 and an offset voltage source VOS3;

[0014] The chopping unit is used to perform chopping processing on the input signal, the first output end of the chopping unit is electrically connected to the negative input end of the demodulation and amplification unit through the offset voltage source VOS1, and the second output end of the chopping unit is electrically connected to the positive input end of the demodulation and amplification unit;

[0015] The output end of the demodulation amplifier unit is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to one end of the switch S1, and is electrically connected to the positive input end of the second operational amplifier unit through the offset voltage source VOS3; the negative input end of the second operational amplifier unit is electrically connected to one end of the switch S2, and is electrically connected to the power supply VCC through the capacitor C2; the other end of the switch S1 is electrically connected to the negative output end of the second operational amplifier unit, and is electrically connected to the positive input end of the first operational amplifier unit through the offset low voltage source VOS2; the other end of the switch S2 is electrically connected to the positive output end of the second operational amplifier unit and the negative input end of the first operational amplifier unit respectively; the positive output end of the first operational amplifier unit is electrically connected to the negative output end of the first operational amplifier unit through the switch S3;

[0016] The current feedback unit is electrically connected to the positive output terminal and the negative output terminal of the first operational amplifier unit, and adjusts the feedback current input to the positive input terminal and the negative input terminal of the demodulation amplifier unit based on the voltage difference between the positive output terminal and the negative output terminal of the first operational amplifier unit. The feedback current is used to adjust the output of the demodulation amplifier unit.

[0017] In a certain implementation manner, the demodulation and amplification unit includes MOS transistor N1, MOS transistor N2, MOS transistor N3, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, demodulator CP1, demodulator CP2 and resistor R1;

[0018] The source of the MOS transistor P1 is electrically connected to the source of the MOS transistor P2, and is also electrically connected to the power supply VCC; the gate of the MOS transistor P1 and the gate of the MOS transistor P2 are used to input the bias voltage Vbias2, the drain of the MOS transistor P1 and the drain of the MOS transistor P2 are electrically connected to the source of the MOS transistor P3 and the source of the MOS transistor P4 through the demodulator CP1, the gate of the MOS transistor P3 and the gate of the MOS transistor P4 are used to input the bias voltage Vbias3, the drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N7, the gate of the MOS transistor N5 and the gate of the MOS transistor N6 respectively, the drain of the MOS transistor P4 is electrically connected to the drain of the MOS transistor N8, the gate of the MOS transistor N7 and the gate of the MOS transistor N8 are used to input the bias voltage Vbias4, the source of the MOS transistor N7 and the source of the MOS transistor N8 are electrically connected to the drain of the MOS transistor N5 and the drain of the MOS transistor N6 through the demodulator CP2, and the source of the MOS transistor N5 and the source of the MOS transistor N6 are both grounded;

[0019] The drain of the MOS tube P1 is also electrically connected to the drain of the MOS tube N1, the drain of the MOS tube P2 is also electrically connected to the drain of the MOS tube N2, the gate of the MOS tube N1 is the positive input terminal of the demodulation and amplification unit, the gate of the MOS tube N2 is the negative input terminal of the demodulation and amplification unit, the source of the MOS tube N1 is respectively electrically connected to one end of the resistor R1 and the drain of the MOS tube N3, the source of the MOS tube N2 is respectively electrically connected to the other end of the resistor R1 and the drain of the MOS tube N4, the gate of the MOS tube N3 and the gate of the MOS tube N4 are used to input the bias voltage Vbias1; the source of the MOS tube N3 and the source of the MOS tube N4 are both grounded.

[0020] In a certain embodiment, the current feedback unit includes an analog-to-digital conversion unit, a clock signal generating unit and a feedback current generating unit, the analog-to-digital conversion unit generates a digital signal based on the voltage difference between the positive output terminal and the negative output terminal of the first operational amplifier unit, the clock signal generating unit generates a clock control signal based on the digital signal, and the feedback current generating unit generates the feedback current based on the clock control signal.

[0021] In a certain implementation manner, the analog-to-digital conversion unit includes a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a MOS transistor P10, a MOS transistor P11, a MOS transistor P12, a MOS transistor N10, a MOS transistor N11, and a MOS transistor N12;

[0022] The source of the MOS transistor P10 is used to be electrically connected to the power supply VCC, the gate of the MOS transistor P10 is used to access the clock signal CP, the drain of the MOS transistor P10 is electrically connected to the source of the MOS transistor P11 and the source of the MOS transistor P12 respectively, the gate of the MOS transistor P11 is electrically connected to the drain of the MOS transistor P12, the drain of the MOS transistor N12, the gate of the MOS transistor N11, the input end of the transmission gate TG3 and the output end of the transmission gate TG2 respectively, the gate of the MOS transistor P12 is electrically connected to the drain of the MOS transistor P11, the drain of the MOS transistor N11, the gate of the MOS transistor N12 and the output end of the transmission gate TG1 respectively, the input end of the transmission gate TG1 is electrically connected to the positive output end of the first operational amplifier unit, the input end of the transmission gate TG2 is electrically connected to the negative output end of the first operational amplifier unit, and the source of the MOS transistor N12 and the source of the MOS transistor N11 are grounded through the MOS transistor N10;

[0023] The first control end of the transmission gate TG1 and the first control end of the transmission gate TG2 are respectively used to input a first clock signal, the second control end of the transmission gate TG1 and the second control end of the transmission gate TG2 are respectively used to input a second clock signal, the first clock signal and the second clock signal are two opposite clock signals, and the gate of the MOS tube N10 is used to input the second clock signal;

[0024] The first control end of the transmission gate TG3 is used to input a third clock signal, and the second control end of the transmission gate TG3 is used to input a fourth clock signal. The third clock signal and the fourth clock signal are two opposite clock signals. The third clock signal has the same frequency as the first clock signal, and the high level interval of the third clock signal is within the low level interval of the first clock signal. The output end of the transmission gate TG3 outputs the digital signal.

[0025] In some implementations, control terminals of the switch S1 , the switch S2 , and the switch S3 are respectively input with switch control signals, and the switch control signals are the same as the first clock signal.

[0026] In a certain embodiment, the feedback current generating unit includes a MOS tube N20 and a MOS tube N21, the drain of the MOS tube N20 is electrically connected to the current source IREF2 and the gate of the MOS tube N20 respectively, the source of the MOS tube N20 is electrically connected to the drains of eight MOS tubes N22, the gates of eight MOS tubes N23 and the gates of eight MOS tubes N24 respectively, and the sources of the eight MOS tubes N23 and the eight MOS tubes N24 are grounded;

[0027] The drain of the MOS tube N21 is electrically connected to the current source IREF1, the gate of the MOS tube N21, the gates of the eight MOS tubes N22, and the gates of the eight MOS tubes N25, respectively; the source of the MOS tube N21 is grounded; the sources of the eight MOS tubes N22 are correspondingly connected to the drains of the eight MOS tubes N23; the sources of the eight MOS tubes N25 are correspondingly connected to the drains of the eight MOS tubes N24;

[0028] The drains of the eight MOS tubes N25 are respectively connected to the sources of the eight MOS tubes N26 and the sources of the eight MOS tubes N27, the gates of the eight MOS tubes N26 are respectively electrically connected to the input end of the inverter INV6, and the gates of the eight MOS tubes N27 are respectively electrically connected to the output end of the inverter INV6;

[0029] The drains of the four MOS tubes N26 are electrically connected to the gate of the MOS tube N36, the drain of the MOS tube N36, the drain of the MOS tube N37, the drain of the MOS tube N38, the drain of the MOS tube N39 and the source of the MOS tube N1 respectively, and the drains of the remaining four MOS tubes N26 are correspondingly connected to the sources of the four MOS tubes N28, the gates of the four MOS tubes N28 are respectively electrically connected to the output end of the inverter INV5, and the drains of the two MOS tubes N28 are respectively electrically connected to the source of the MOS tube N1. The drains of the remaining two MOS tubes N28 are electrically connected to the sources of the two MOS tubes N30. The gates of the two MOS tubes N30 are electrically connected to the output ends of the inverter INV4 respectively. The drain of one MOS tube N30 is electrically connected to the source of the MOS tube N1. The drain of the other MOS tube N30 is electrically connected to the source of the MOS tube N32, the source of the MOS tube N33, the source of the MOS tube N34 and the source of the MOS tube N35 respectively. The gate of the MOS tube N32, the source of the MOS tube N33, the source of the MOS tube N34 and the source of the MOS tube N35 are electrically connected. The gate of MOS tube N33, the gate of MOS tube N34 and the gate of MOS tube N35 are electrically connected to the gate of MOS tube N20 respectively; the drain of MOS tube N32 is electrically connected to the source of MOS tube N36, the drain of MOS tube N33 is electrically connected to the source of MOS tube N37 and the source of MOS tube N40 respectively, the drain of MOS tube N34 is electrically connected to the source of MOS tube N38 and the source of MOS tube N41 respectively, the drain of MOS tube N35 is electrically connected to the source of MOS tube N39 and the source of MOS tube N41 respectively. The source of the MOS tube N42 is electrically connected; the gate of the MOS tube N37 is electrically connected to the output end of the inverter INV1, the gate of the MOS tube N38 is electrically connected to the output end of the inverter INV2, the gate of the MOS tube N39 is electrically connected to the output end of the inverter INV3, the gate of the MOS tube N40 is electrically connected to the input end of the inverter INV1, the gate of the MOS tube N41 is electrically connected to the input end of the inverter INV2, and the gate of the MOS tube N42 is electrically connected to the input end of the inverter INV3;

[0030] The drain of the MOS tube N40 is electrically connected to the drain of the MOS tube N41, the drain of the MOS tube N42, the source of the MOS tube N2, and the drains of the four MOS tubes N27 respectively; the drains of the remaining four MOS tubes N27 are connected to the sources of the four MOS tubes N29 correspondingly; the gates of the four MOS tubes N29 are electrically connected to the input end of the inverter INV5; the drains of the two MOS tubes N29 are electrically connected to the drain of the MOS tube N40; the drains of the other two MOS tubes N29 are electrically connected to the sources of the two MOS tubes N31; the gates of the two MOS tubes N31 are electrically connected to the input end of the inverter INV4; the drain of one MOS tube N31 is electrically connected to the drain of the MOS tube N40; and the drain of the other MOS tube N31 is electrically connected to the drain of the MOS tube N30;

[0031] Input terminals of the inverters INV1 to INV6 are respectively used to input clock control signals generated by the clock signal generating unit.

[0032] Compared with the prior art, the present invention has the following beneficial effects: in actual use, the present invention detects the output signal of the chopping demodulation unit through the auto-zero unit, generates a feedback current input to the chopping demodulation unit through the current feedback unit, adjusts the output of the chopping demodulation unit through the feedback current, thereby eliminating the high-frequency offset voltage ripple in the signal output by the chopping demodulation unit through the current feedback method; and the low-pass filter is removed from the chopping demodulation unit, which can improve the bandwidth of the operational amplifier and the response speed of the circuit; in addition, by replacing the large-area filter circuit with a small-area feedback current generating circuit, the chip area can be saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of current detection through the existing sampling resistor Rsense;

[0034] Figure 2 This is a schematic diagram of the existing current detection through SenseFET

[0035] Figure 3 It is a structural schematic diagram of an existing chopper circuit for eliminating offset;

[0036] Figure 4 It is a structural schematic diagram of an existing auto-zero circuit for eliminating offset;

[0037] Figure 5 It is a schematic diagram of the structure of the present invention in the embodiment;

[0038] Figure 6 is a circuit diagram of a demodulation and amplification unit in an embodiment;

[0039] Figure 7 is a circuit diagram of an analog-to-digital conversion unit in an embodiment;

[0040] Figure 8 is a circuit diagram of a clock signal generating unit in an embodiment;

[0041] Fig. 9 for Figure 8 A waveform diagram of the clock signal generated by the circuit;

[0042] Fig.10 is a partial circuit diagram of a feedback current generating unit in an embodiment;

[0043] Fig.11 FIG. 4 is a partial circuit diagram of a feedback current generating unit in an embodiment. DETAILED DESCRIPTION

[0044] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0045] like Figure 5 As shown, a current detection circuit of a high-side switch includes a chopping demodulation unit 1, an auto-zero unit 2 and a current feedback unit 3;

[0046] The chopping demodulation unit 1 includes a chopping unit 10, an offset voltage source VOS1 and a demodulation amplifier unit 11; the auto-zero unit 2 includes a first operational amplifier unit 20, a second operational amplifier unit 21, a switch S1, a switch S2, a switch S3, a capacitor C1, a capacitor C2, an offset voltage source VOS2 and an offset voltage source VOS3;

[0047] The chopping unit 10 is used to perform chopping processing on the input signal, the first output end of the chopping unit 10 is electrically connected to the negative input end of the demodulation and amplification unit 11 through the offset voltage source VOS1, and the second output end of the chopping unit 10 is electrically connected to the positive input end of the demodulation and amplification unit 11;

[0048] The output end of the demodulation amplifier unit 11 is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to one end of the switch S1, and is electrically connected to the positive input end of the second operational amplifier unit 21 through the offset voltage source VOS3; the negative input end of the second operational amplifier unit 21 is electrically connected to one end of the switch S2, and is electrically connected to the power supply VCC through the capacitor C2; the other end of the switch S1 is electrically connected to the negative output end of the second operational amplifier unit 21, and is electrically connected to the positive input end of the first operational amplifier unit 20 through the offset low voltage source VOS2; the other end of the switch S2 is electrically connected to the positive output end of the second operational amplifier unit 21 and the negative input end of the first operational amplifier unit 20 respectively; the positive output end of the first operational amplifier unit 20 is electrically connected to the negative output end of the first operational amplifier unit 20 through the switch S3;

[0049] The current feedback unit 3 is electrically connected to the positive output terminal and the negative output terminal of the first operational amplifier unit 20, and adjusts the feedback current input to the positive input terminal and the negative input terminal of the demodulation amplifier unit 11 based on the voltage difference between the positive output terminal and the negative output terminal of the first operational amplifier unit 20. The feedback current is used to adjust the output of the demodulation amplifier unit 11.

[0050] In actual use, the present invention detects the output signal of the chopper demodulation unit 11 through the auto-zero unit, generates a feedback current input to the chopper demodulation unit 11 through the current feedback unit 3, and adjusts the output of the chopper demodulation unit 11 through the feedback current, thereby eliminating the high-frequency offset voltage ripple in the signal output by the chopper demodulation unit 1 through current feedback; and the low-pass filter is removed from the chopper demodulation unit 1, which can increase the bandwidth of the operational amplifier and improve the response speed of the circuit; in addition, by replacing the large-area filter circuit with a small-area feedback current generating circuit, the chip area can be saved.

[0051] Specifically, in this embodiment, the circuit of the demodulation and amplification unit 11 is as follows: Figure 6 As shown, it includes MOS tube N1, MOS tube N2, MOS tube N3, MOS tube N4, MOS tube N5, MOS tube N6, MOS tube N7, MOS tube N8, MOS tube P1, MOS tube P2, MOS tube P3, MOS tube P4, demodulator CP1, demodulator CP2 and resistor R1;

[0052] The source of the MOS transistor P1 is electrically connected to the source of the MOS transistor P2, and is also electrically connected to the power supply VCC; the gate of the MOS transistor P1 and the gate of the MOS transistor P2 are used to input the bias voltage Vbias2, the drain of the MOS transistor P1 and the drain of the MOS transistor P2 are electrically connected to the source of the MOS transistor P3 and the source of the MOS transistor P4 through the demodulator CP1, the gate of the MOS transistor P3 and the gate of the MOS transistor P4 are used to input the bias voltage Vbias3, the drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N7, the gate of the MOS transistor N5 and the gate of the MOS transistor N6 respectively, the drain of the MOS transistor P4 is electrically connected to the drain of the MOS transistor N8, the gate of the MOS transistor N7 and the gate of the MOS transistor N8 are used to input the bias voltage Vbias4, the source of the MOS transistor N7 and the source of the MOS transistor N8 are electrically connected to the drain of the MOS transistor N5 and the drain of the MOS transistor N6 through the demodulator CP2, and the source of the MOS transistor N5 and the source of the MOS transistor N6 are both grounded;

[0053] The drain of the MOS tube P1 is also electrically connected to the drain of the MOS tube N1, the drain of the MOS tube P2 is also electrically connected to the drain of the MOS tube N2, the gate of the MOS tube N1 is the positive input terminal of the demodulation amplifier unit, the gate of the MOS tube N2 is the negative input terminal of the demodulation amplifier unit, the source of the MOS tube N1 is respectively electrically connected to one end of the resistor R1 and the drain of the MOS tube N3, the source of the MOS tube N2 is respectively electrically connected to the other end of the resistor R1 and the drain of the MOS tube N4, the gate of the MOS tube N3 and the gate of the MOS tube N4 are used to input the bias voltage Vbias1; the source of the MOS tube N3 and the source of the MOS tube N4 are both grounded.

[0054] for Figure 6 As shown in the figure, I1 and I2 are access channels for feedback current. The signal output by the chopper unit 10 generates a current signal after passing through the input pair consisting of MOS tube N1 and MOS tube N2. The current signal is amplified and chopped and demodulated to form an output signal VOUT. In addition, the bias voltage Vbias1 and the bias voltage Vbias2 are used to provide the required bias current. The bias voltage Vbias3 and the bias voltage Vbias4 can isolate the noise interference of the chopper switch while providing the bias current.

[0055] Specifically, in this embodiment, the working process of the auto-zero unit 2 is as follows. First, it is necessary to know that the switch S1, the switch S2 and the switch S3 are turned on and off at the same time. At the same time, it is assumed that the gain of the first operational amplifier unit 20 is Av2 and the gain of the second operational amplifier unit 21 is Av3;

[0056] When the switch S1, the switch S2 and the switch S3 are closed at the same time, since the input and the output of the second operational amplifier unit 21 are short-circuited, the voltage difference between the node A and the node B is:

[0057] V AB =V A -V B = ;

[0058] When the switches S1, S2 and S3 are turned off at the same time, the auto-zero unit 2 enters the amplification state. At this time, the output voltage of the first operational amplifier unit 20 is:

[0059] ;

[0060] Its equivalent input offset voltage is:

[0061] ;

[0062] This is equivalent to reducing the offset voltage to the original times.

[0063] Specifically, in this embodiment, the current feedback unit 3 includes an analog-to-digital conversion unit, a clock signal generating unit and a feedback current generating unit. The analog-to-digital conversion unit generates a digital signal based on the voltage difference between the positive output terminal and the negative output terminal of the first operational amplifier unit, the clock signal generating unit generates a clock control signal based on the digital signal, and the feedback current generating unit generates a feedback current based on the clock control signal.

[0064] Specifically, Figure 7 As shown, the analog-to-digital conversion unit includes a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a MOS transistor P10, a MOS transistor P11, a MOS transistor P12, a MOS transistor N10, a MOS transistor N11 and a MOS transistor N12;

[0065] The source of the MOS transistor P10 is used to be electrically connected to the power supply VCC, the gate of the MOS transistor P10 is used to access the clock signal CP, the drain of the MOS transistor P10 is electrically connected to the source of the MOS transistor P11 and the source of the MOS transistor P12 respectively, the gate of the MOS transistor P11 is electrically connected to the drain of the MOS transistor P12, the drain of the MOS transistor N12, the gate of the MOS transistor N11, the input end of the transmission gate TG3 and the output end of the transmission gate TG2 respectively, the gate of the MOS transistor P12 is electrically connected to the drain of the MOS transistor P11, the drain of the MOS transistor N11, the gate of the MOS transistor N12 and the output end of the transmission gate TG1 respectively, the input end of the transmission gate TG1 is electrically connected to the positive output end of the first operational amplifier unit, the input end of the transmission gate TG2 is electrically connected to the negative output end of the first operational amplifier unit, and the source of the MOS transistor N12 and the source of the MOS transistor N11 are grounded through the MOS transistor N10;

[0066] The first control end of the transmission gate TG1 and the first control end of the transmission gate TG2 are respectively used to input the first clock signal CP11, the second control end of the transmission gate TG1 and the second control end of the transmission gate TG2 are respectively used to input the second clock signal, the first clock signal CP11 and the second clock signal are two opposite clock signals, and the gate of the MOS tube N10 is used to input the second clock signal;

[0067] The first control end of the transmission gate TG3 is used to input the third clock signal CP12, and the second control end of the transmission gate TG3 is used to input the fourth clock signal. The third clock signal and the fourth clock signal are two opposite clock signals. The third clock signal CP12 has the same frequency as the first clock signal CP11, and the high level interval CP12 of the third clock signal is within the low level interval of the first clock signal CP11; the output end of the transmission gate TG3 outputs a digital signal.

[0068] Specifically, in this embodiment, the control terminals of the switch S1 , the switch S2 , and the switch S3 are respectively input with a switch control signal, and the switch control signal is the same as the first clock signal.

[0069] for Figure 7 In the circuit shown, when the first clock signal CP1 is at a high level, the auto-zero unit 2 enters the amplification state, that is, the switches S1, S2 and S3 are all disconnected. At this time, the transmission gates TG1 and TG2 of the analog-to-digital conversion unit are turned on, and the differential signal output by the first operational amplifier unit 20 is transmitted to the gates of the MOS transistors P11, P12, MN11 and MN12. At this time, the transmission gate TG3 is closed, and the OUT terminal maintains the previous level;

[0070] When the auto-zero unit 2 enters the sampling state, that is, the switches S1, S2 and S3 are all closed, the transmission gates TG1 and TG2 are closed, the MOS transistors P10 and N10 are turned on, and the differential voltage originally applied to the gates of the MOS transistors P11, P12, MN11 and MN12 quickly pulls down or pulls up the output voltage of the node C. At this time, the transmission gate TG3 is turned on under a temporary pulse voltage, and the output voltage of the node C is transmitted to the node OUT. Finally, the output level of the node OUT depends on the positive or negative of the differential signal amplified by the first operational amplifier unit 20 in the previous stage, that is, the position where the overall operational amplifier output deviates from the equilibrium state.

[0071] Specifically, in this embodiment, the circuit of the clock signal generating unit is as follows: Fig. 9 As shown, it includes a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, an inverter INV50, an inverter INV51, a NOR gate NOR1 and six clock generation branches;

[0072] The output end of the NAND gate NAND1 is electrically connected to the first input end of the NAND gate NAND2, the second input end of the NAND gate NAND2 and the first input end of the NOR gate NOR1 are electrically connected to the digital signal output end of the analog-to-digital conversion unit respectively, the output end of the NAND gate NAND3 is electrically connected to the second input end of the NOR gate NOR1 through the inverter INV50, and the output end of the NAND gate NAND2 is electrically connected to the input end of the inverter INV51;

[0073] The six clock generation branches are respectively the first to the sixth clock generation branches, and the clock generation branches include. NAND gate NAND10, XOR gate XOR10, D flip-flop, inverter INV10 and inverter INV11, the output end of NAND gate NAND10 is electrically connected to the first input end of XOR gate XOR10, the output end of XOR gate XOR10 is electrically connected to the D input end of D flip-flop, the clock end of D flip-flop is used to input clock signal CLK, the SET end of D flip-flop is used to input enable signal EN, the Q output end of D flip-flop is electrically connected to the input end of inverter INV10, the output end of inverter INV10 is electrically connected to the input end of inverter INV11, the output end of inverter INV11 is electrically connected to the second input end of XOR gate XOR10, used to output current generation clock signal, the output end of inverter INV11 of six clock generation branches outputs current generation clock signal CP1, current generation clock signal CP2, current generation clock signal CP3, current generation clock signal CP4, current generation clock signal CP5 and current generation clock signal CP6 respectively;

[0074] The output end of the inverter INV51 is electrically connected to the second input end of the NOT gate NAND10 of the first clock generating branch through the inverter INV41, and the output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND10 of the first clock generating branch through the inverter INV40;

[0075] The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND40, the second input end of the NAND gate NAND40 is electrically connected to the input end of the inverter INV11 of the first clock generating branch, and the output end of the NAND gate NAND40 is electrically connected to the first input end of the NAND gate NAND10 of the second clock generating branch; the output end of the inverter INV51 is electrically connected to the second input end of the NAND gate NAND41, the first input end of the NAND gate NAND41 is electrically connected to the output end of the inverter INV11 of the first clock generating branch, and the output end of the NAND gate NAND41 is electrically connected to the second input end of the NAND gate NAND10 of the second clock generating branch;

[0076] The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND42, the second input end of the NAND gate NAND42 is electrically connected to the output end of the NAND gate NAND30, the two input ends of the NAND gate NAND30 are electrically connected to the output end of the inverter INV11 of the first clock generating branch and the output end of the inverter INV11 of the second clock generating branch, respectively, and the output end of the NAND gate NAND42 is electrically connected to the first input end of the NAND gate NAND10 of the third clock generating branch; the output end of the inverter INV51 is electrically connected to the second input end of the NAND gate NAND42, the first input end of the NAND gate NAND43 is electrically connected to the output end of the NAND gate NAND31, the two input ends of the NAND gate NAND43 are electrically connected to the input end of the inverter INV11 of the first clock generating branch and the input end of the inverter INV11 of the second clock generating branch, and the output end of the NAND gate NAND43 is electrically connected to the second input end of the NAND gate NAND10 of the third clock generating branch;

[0077] The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND44, the second input end of the NAND gate NAND44 is electrically connected to the output end of the inverter INV30, the input end of the inverter INV30 is electrically connected to the output end of the NAND gate NAND20, the three input ends of the NAND gate NAND20 are electrically connected to the input end of the inverter INV11 of the first clock generating branch, the input end of the inverter INV11 of the second clock generating branch, and the input end of the inverter INV11 of the third clock generating branch, respectively, and the output end of the NAND gate NAND44 is electrically connected to the first input end of the NAND gate NAND10 of the fourth clock generating branch; The output end of the phase detector INV51 is electrically connected to the second input end of the NAND gate NAND45, the first input end of the NAND gate NAND45 is electrically connected to the output end of the inverter INV31, the input end of the inverter INV31 is electrically connected to the output end of the NAND gate NAND21, the three input ends of the NAND gate NAND21 are respectively electrically connected to the output end of the inverter INV11 of the first clock generating branch, the output end of the inverter INV11 of the second clock generating branch, and the output end of the inverter INV11 of the third clock generating branch, and the output end of the NAND gate NAND45 is electrically connected to the second input end of the NAND gate NAND10 of the fourth clock generating branch;

[0078] The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND46, the second input end of the NAND gate NAND46 is electrically connected to the output end of the inverter INV32, the input end of the inverter INV32 is electrically connected to the output end of the NAND gate NAND22, the two input ends of the NAND gate NAND22 are electrically connected to the output end of the inverter INV30 and the input end of the inverter INV11 of the fourth clock generating branch respectively, and the output end of the NAND gate NAND46 is electrically connected to the first input end of the NAND gate NAND10 of the fifth clock generating branch; The output end of the phase detector INV51 is electrically connected to the second input end of the NAND gate NAND47, the first input end of the NAND gate NAND47 is electrically connected to the output end of the inverter INV33, the input end of the inverter INV33 is electrically connected to the output end of the NAND gate NAND23, the two input ends of the NAND gate NAND23 are respectively electrically connected to the output end of the inverter INV31 and the output end of the inverter INV11 of the fourth clock generating branch, and the output end of the NAND gate NAND47 is electrically connected to the second input end of the NAND gate NAND10 of the fifth clock generating branch;

[0079] The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND48, the second input end of the NAND gate NAND48 is electrically connected to the output end of the inverter INV34, the input end of the inverter INV34 is electrically connected to the output end of the NAND gate NAND24, the three input ends of the NAND gate NAND24 are electrically connected to the output end of the inverter INV30, the input end of the inverter INV11 of the fourth clock generating branch and the input end of the inverter INV11 of the fifth clock generating branch, respectively, the output end of the NAND gate NAND48 is electrically connected to the first input end of the NAND gate NAND10 of the sixth clock generating branch; The output end of the phase detector INV51 is electrically connected to the second input end of the NAND gate NAND49, the first input end of the NAND gate NAND49 is electrically connected to the output end of the inverter INV35, the input end of the inverter INV35 is electrically connected to the output end of the NAND gate NAND25, the three input ends of the NAND gate NAND25 are respectively electrically connected to the output end of the inverter INV31, the output end of the inverter INV11 of the fourth clock generating branch and the output end of the inverter INV11 of the fifth clock generating branch, and the output end of the NAND gate NAND49 is electrically connected to the second input end of the NAND gate NAND10 of the sixth clock generating branch;

[0080] The two input ends of the NAND gate NAND1 are electrically connected to the input end of the inverter INV11 of the sixth clock generating branch and the output end of the inverter INV35, and the two input ends of the NAND gate NAND3 are electrically connected to the output end of the inverter INV11 of the sixth clock generating branch and the output end of the inverter INV34.

[0081] In actual use, the waveforms of the clock control signals CP1 to CP6 are transformed as follows: Fig. 9 As shown, Fig. 9 The upper waveform change in the figure is the state during adjustment, and the lower waveform change is the state when dynamic balance is reached.

[0082] for Figure 8 The circuit shown in the figure ensures that the output of the D flip-flop is cleared when in use, and the D flip-flop is triggered by the rising edge. The output of the operational amplifier of the auto-zero unit 2 is input to the Figure 8 The DAC_OUT terminal in the clock control signal generation can adjust the flip mode according to the output result. When the current sampling is started and the output result of the entire op amp is high, the DAC_OUT input is high, the I2+ port is high, and the I1+ port is low, thereby controlling the clock control signal to flip in the direction of increasing the I2 channel current.

[0083] When the clock control signal CP1 is generated, the I1+ and I2+ port clocks are one high and one low level, and the signal input to the XOR gate through the NAND gate is always high, that is, CP1 keeps periodically flipping, and the frequency is 1 / 2 of CLK. When the flip mode is to add a circuit to channel I2, CP1 is high and CP2 triggers flipping when CLK rises, and then triggers subsequent CP signal flips in sequence. When CP1-CP5 are all flipped to a high level, the current in all paths is added to the I2 channel. At this time, the I1+ and I2+ ports are both set to a low level, the CP1 signal no longer reverses periodically, the I2 channel current is fixed, and the offset error is adjusted as much as possible. The above situation applies to the case where DAC_OUT maintains a low level, and the final path current is added to the I1 channel.

[0084] Before all path currents are biased to a single channel, if the overall op amp output offset causes the DAC_OUT signal to flip, CP1 continues to maintain periodic flipping, I1+ and I2+ are inverted, and CP changes the flipping mode of the bias current until DAC_OUT flips again. Finally, the system will reach dynamic balance, the overall op amp output fluctuates around the equilibrium state, DAC_OUT is a periodic signal, and the path current on the I1 and I2 channels fluctuates periodically in a small range, reducing the offset error.

[0085] Specifically, in this embodiment, the circuit of the feedback current generating unit is as follows: Fig.10 and Fig.11As shown, it includes a MOS tube N20 and a MOS tube N21, the drain of the MOS tube N20 is electrically connected to the current source IREF2 and the gate of the MOS tube N20 respectively, the source of the MOS tube N20 is electrically connected to the drains of eight MOS tubes N22, the gates of eight MOS tubes N23 and the gates of eight MOS tubes N24 respectively, and the sources of the eight MOS tubes N23 and the eight MOS tubes N24 are grounded;

[0086] The drain of the MOS tube N21 is electrically connected to the current source IREF1, the gate of the MOS tube N21, the gates of the eight MOS tubes N22, and the gates of the eight MOS tubes N25, respectively; the source of the MOS tube N21 is grounded; the sources of the eight MOS tubes N22 are correspondingly connected to the drains of the eight MOS tubes N23; the sources of the eight MOS tubes N25 are correspondingly connected to the drains of the eight MOS tubes N24;

[0087] The drains of the eight MOS tubes N25 are respectively connected to the sources of the eight MOS tubes N26 and the sources of the eight MOS tubes N27, the gates of the eight MOS tubes N26 are respectively electrically connected to the input end of the inverter INV6, and the gates of the eight MOS tubes N27 are respectively electrically connected to the output end of the inverter INV6;

[0088] The drains of the four MOS tubes N26 are electrically connected to the gate of the MOS tube N36, the drain of the MOS tube N36, the drain of the MOS tube N37, the drain of the MOS tube N38, the drain of the MOS tube N39 and the source of the MOS tube N1 respectively, the drains of the remaining four MOS tubes N26 are correspondingly connected to the sources of the four MOS tubes N28, the gates of the four MOS tubes N28 are respectively electrically connected to the output end of the inverter INV5, the drains of the two MOS tubes N28 are respectively electrically connected to the source of the MOS tube N1 The drains of the remaining two MOS tubes N28 are electrically connected to the sources of the two MOS tubes N30. The gates of the two MOS tubes N30 are electrically connected to the output end of the inverter INV4 respectively. The drain of one MOS tube N30 is electrically connected to the source of the MOS tube N1. The drain of the other MOS tube N30 is electrically connected to the source of the MOS tube N32, the source of the MOS tube N33, the source of the MOS tube N34 and the source of the MOS tube N35 respectively. The gates of the MOS tube N32 and the MOS tube N33 are electrically connected to the source of the MOS tube N34. The gate of MOS tube N33, the gate of MOS tube N34 and the gate of MOS tube N35 are electrically connected to the gate of MOS tube N20 respectively; the drain of MOS tube N32 is electrically connected to the source of MOS tube N36, the drain of MOS tube N33 is electrically connected to the source of MOS tube N37 and the source of MOS tube N40 respectively, the drain of MOS tube N34 is electrically connected to the source of MOS tube N38 and the source of MOS tube N41 respectively, the drain of MOS tube N35 is electrically connected to the source of MOS tube N39 and the source of MOS tube N41 respectively. The source of the MOS tube N42 is electrically connected; the gate of the MOS tube N37 is electrically connected to the output end of the inverter INV1, the gate of the MOS tube N38 is electrically connected to the output end of the inverter INV2, the gate of the MOS tube N39 is electrically connected to the output end of the inverter INV3, the gate of the MOS tube N40 is electrically connected to the input end of the inverter INV1, the gate of the MOS tube N41 is electrically connected to the input end of the inverter INV2, and the gate of the MOS tube N42 is electrically connected to the input end of the inverter INV3;

[0089] The drain of the MOS tube N40 is electrically connected to the drain of the MOS tube N41, the drain of the MOS tube N42, the source of the MOS tube N2 and the drains of the four MOS tubes N27 respectively, the drains of the remaining four MOS tubes N27 are connected to the sources of the four MOS tubes N29 correspondingly, the gates of the four MOS tubes N29 are electrically connected to the input end of the inverter INV5, the drains of two MOS tubes N29 are electrically connected to the drain of the MOS tube N40, the drains of the other two MOS tubes N29 are electrically connected to the sources of the two MOS tubes N31, the gates of the two MOS tubes N31 are electrically connected to the input end of the inverter INV4, the drain of one MOS tube N31 is electrically connected to the drain of the MOS tube N40, and the drain of the other MOS tube N31 is electrically connected to the drain of the MOS tube N30.

[0090] for Figure 8 , Fig.10 and Fig.11 In the circuit shown in the figure, in actual use, the total current of the I1 or I2 current channel is divided into 8 paths, which are biased by the e current source, CP6 controls 4 current paths, CP5 controls 2 current paths, CP4 controls 1 current path, and the last current path flows through the four MOS tubes M32, M33, M34, and M35, and the current I is proportionally controlled by the current mirror. M32 :I M33 :I M34 : I M35 =1:1:2:4, one current can be divided into 8 parts, the M1 current is always applied to the I1 channel, the clock control signal CP1 controls 1 / 8 of the current, the clock control signal CP2 controls 1 / 4 of the current, and the clock control signal CP3 controls 1 / 2 of the current. When the op amp is just turned on, all clock control signals are at a low level. At this time, the clock control signal CP6 controls 4 currents to enter the I1 channel, and the remaining clock signals control 3+7 / 8 currents to enter the I2 channel, and the M1 tube current is always added to I1. At this time, if the offset is not considered, the output end of the overall op amp will produce a voltage that is offset from the equilibrium state. After being amplified by the op amp of the self-zeroing unit, a digital control signal is generated to trigger the clock control signal CP1 to enter the cycle. When the clock control signal CP1 flips, the I2 channel has 1 / 4 more feedback current than the I1 channel, causing the overall op amp output to shift to the other side of the equilibrium state, causing the digital control signal to flip, and the clock control signal CP1 maintains the periodic change without triggering the clock control signal CP2 to enter the cycle. Finally, the clock control signal CP1 controls the current feedback to be periodically added to the I1 and I2 paths, and the output reaches dynamic balance.

[0091] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A current detection circuit for a high-side switch, characterized in that: It includes a chopping demodulation unit, an auto-zero unit and a current feedback unit; The chopping demodulation unit includes a chopping unit, an offset voltage source VOS1 and a demodulation amplifier unit; the auto-zero unit includes a first operational amplifier unit, a second operational amplifier unit, a switch S1, a switch S2, a switch S3, a capacitor C1, a capacitor C2, an offset voltage source VOS2 and an offset voltage source VOS3; The chopping unit is used to perform chopping processing on the input signal, the first output end of the chopping unit is electrically connected to the negative input end of the demodulation and amplification unit through the offset voltage source VOS1, and the second output end of the chopping unit is electrically connected to the positive input end of the demodulation and amplification unit; The output end of the demodulation amplifier unit is electrically connected to one end of the capacitor C1, the other end of the capacitor C1 is electrically connected to one end of the switch S1, and is electrically connected to the positive input end of the second operational amplifier unit through the offset voltage source VOS3; the negative input end of the second operational amplifier unit is electrically connected to one end of the switch S2, and is electrically connected to the power supply VCC through the capacitor C2; the other end of the switch S1 is electrically connected to the negative output end of the second operational amplifier unit, and is electrically connected to the positive input end of the first operational amplifier unit through the offset low voltage source VOS2; the other end of the switch S2 is electrically connected to the positive output end of the second operational amplifier unit and the negative input end of the first operational amplifier unit respectively; the positive output end of the first operational amplifier unit is electrically connected to the negative output end of the first operational amplifier unit through the switch S3; The current feedback unit is electrically connected to the positive output terminal and the negative output terminal of the first operational amplifier unit, and adjusts the magnitude of the feedback current input to the positive input terminal and the negative input terminal of the demodulation amplifier unit based on the voltage difference between the positive output terminal and the negative output terminal of the first operational amplifier unit, and the feedback current is used to adjust the output of the demodulation amplifier unit; The current feedback unit includes an analog-to-digital conversion unit, a clock signal generating unit and a feedback current generating unit. The analog-to-digital conversion unit generates a digital signal based on the voltage difference between the positive output terminal and the negative output terminal of the first operational amplifier unit, the clock signal generating unit generates a clock control signal based on the digital signal, and the feedback current generating unit generates the feedback current based on the clock control signal.

2. The current detection circuit of a high side switch according to claim 1, characterized in that: The demodulation and amplification unit includes MOS tube N1, MOS tube N2, MOS tube N3, MOS tube N4, MOS tube N5, MOS tube N6, MOS tube N7, MOS tube N8, MOS tube P1, MOS tube P2, MOS tube P3, MOS tube P4, demodulator CP1, demodulator CP2 and resistor R1; The source of the MOS transistor P1 is electrically connected to the source of the MOS transistor P2, and is also electrically connected to the power supply VCC; the gate of the MOS transistor P1 and the gate of the MOS transistor P2 are used to input the bias voltage Vbias2, the drain of the MOS transistor P1 and the drain of the MOS transistor P2 are electrically connected to the source of the MOS transistor P3 and the source of the MOS transistor P4 through the demodulator CP1, the gate of the MOS transistor P3 and the gate of the MOS transistor P4 are used to input the bias voltage Vbias3, the drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N7, the gate of the MOS transistor N5 and the gate of the MOS transistor N6 respectively, the drain of the MOS transistor P4 is electrically connected to the drain of the MOS transistor N8, the gate of the MOS transistor N7 and the gate of the MOS transistor N8 are used to input the bias voltage Vbias4, the source of the MOS transistor N7 and the source of the MOS transistor N8 are electrically connected to the drain of the MOS transistor N5 and the drain of the MOS transistor N6 through the demodulator CP2, and the source of the MOS transistor N5 and the source of the MOS transistor N6 are both grounded; The drain of the MOS tube P1 is also electrically connected to the drain of the MOS tube N1, the drain of the MOS tube P2 is also electrically connected to the drain of the MOS tube N2, the gate of the MOS tube N1 is the positive input terminal of the demodulation and amplification unit, the gate of the MOS tube N2 is the negative input terminal of the demodulation and amplification unit, the source of the MOS tube N1 is respectively electrically connected to one end of the resistor R1 and the drain of the MOS tube N3, the source of the MOS tube N2 is respectively electrically connected to the other end of the resistor R1 and the drain of the MOS tube N4, the gate of the MOS tube N3 and the gate of the MOS tube N4 are used to input the bias voltage Vbias1; the source of the MOS tube N3 and the source of the MOS tube N4 are both grounded.

3. The current detection circuit of a high side switch according to claim 1, characterized in that: The analog-to-digital conversion unit includes a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a MOS transistor P10, a MOS transistor P11, a MOS transistor P12, a MOS transistor N10, a MOS transistor N11 and a MOS transistor N12; The source of the MOS transistor P10 is used to be electrically connected to the power supply VCC, the gate of the MOS transistor P10 is used to access the clock signal CP, the drain of the MOS transistor P10 is electrically connected to the source of the MOS transistor P11 and the source of the MOS transistor P12 respectively, the gate of the MOS transistor P11 is electrically connected to the drain of the MOS transistor P12, the drain of the MOS transistor N12, the gate of the MOS transistor N11, the input end of the transmission gate TG3 and the output end of the transmission gate TG2 respectively, the gate of the MOS transistor P12 is electrically connected to the drain of the MOS transistor P11, the drain of the MOS transistor N11, the gate of the MOS transistor N12 and the output end of the transmission gate TG1 respectively, the input end of the transmission gate TG1 is electrically connected to the positive output end of the first operational amplifier unit, the input end of the transmission gate TG2 is electrically connected to the negative output end of the first operational amplifier unit, and the source of the MOS transistor N12 and the source of the MOS transistor N11 are grounded through the MOS transistor N10; The first control end of the transmission gate TG1 and the first control end of the transmission gate TG2 are respectively used to input a first clock signal, the second control end of the transmission gate TG1 and the second control end of the transmission gate TG2 are respectively used to input a second clock signal, the first clock signal and the second clock signal are two opposite clock signals, and the gate of the MOS tube N10 is used to input the second clock signal; The first control end of the transmission gate TG3 is used to input a third clock signal, and the second control end of the transmission gate TG3 is used to input a fourth clock signal. The third clock signal and the fourth clock signal are two opposite clock signals. The third clock signal has the same frequency as the first clock signal, and the high level interval of the third clock signal is within the low level interval of the first clock signal. The output end of the transmission gate TG3 outputs the digital signal.

4. The current detection circuit of a high side switch according to claim 3, characterized in that: The control ends of the switch S1 , the switch S2 and the switch S3 are respectively input with switch control signals, and the switch control signals are the same as the first clock signal.

5. The current detection circuit of a high side switch according to claim 1, characterized in that: The clock signal generating unit includes a NAND gate NAND1, a NAND gate NAND2, a NAND gate NAND3, an inverter INV50, an inverter INV51, a NOR gate NOR1 and six clock generating branches; The output end of the NAND gate NAND1 is electrically connected to the first input end of the NAND gate NAND2, the second input end of the NAND gate NAND2 and the first input end of the NOR gate NOR1 are electrically connected to the digital signal output end of the analog-to-digital conversion unit respectively, the output end of the NAND gate NAND3 is electrically connected to the second input end of the NOR gate NOR1 through the inverter INV50, and the output end of the NAND gate NAND2 is electrically connected to the input end of the inverter INV51; The six clock generation branches are respectively the first to the sixth clock generation branches, and the clock generation branches include a NAND gate NAND10, an XOR gate XOR10, a D flip-flop, an inverter INV10 and an inverter INV11. The output end of the NAND gate NAND10 is electrically connected to the first input end of the XOR gate XOR10, the output end of the XOR gate XOR10 is electrically connected to the D input end of the D flip-flop, the clock end of the D flip-flop is used to input a clock signal CLK, the SET end of the D flip-flop is used to input an enable signal EN, and the D flip-flop The Q output terminal is electrically connected to the input terminal of the inverter INV10, the output terminal of the inverter INV10 is electrically connected to the input terminal of the inverter INV11, the output terminal of the inverter INV11 is electrically connected to the second input terminal of the XOR gate XOR10, and is used to output a current to generate a clock signal, and the output terminals of the inverter INV11 of the six clock generation branches output clock control signals CP1, CP2, CP3, CP4, CP5 and CP6 respectively; The output end of the inverter INV51 is electrically connected to the second input end of the NOT gate NAND10 of the first clock generating branch through the inverter INV41, and the output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND10 of the first clock generating branch through the inverter INV40; The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND40, the second input end of the NAND gate NAND40 is electrically connected to the input end of the inverter INV11 of the first clock generating branch, and the output end of the NAND gate NAND40 is electrically connected to the first input end of the NAND gate NAND10 of the second clock generating branch; the output end of the inverter INV51 is electrically connected to the second input end of the NAND gate NAND41, the first input end of the NAND gate NAND41 is electrically connected to the output end of the inverter INV11 of the first clock generating branch, and the output end of the NAND gate NAND41 is electrically connected to the second input end of the NAND gate NAND10 of the second clock generating branch; The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND42, the second input end of the NAND gate NAND42 is electrically connected to the output end of the NAND gate NAND30, the two input ends of the NAND gate NAND30 are electrically connected to the output end of the inverter INV11 of the first clock generating branch and the output end of the inverter INV11 of the second clock generating branch, respectively, and the output end of the NAND gate NAND42 is electrically connected to the first input end of the NAND gate NAND10 of the third clock generating branch; the output end of the inverter INV51 is electrically connected to the second input end of the NAND gate NAND42, the first input end of the NAND gate NAND43 is electrically connected to the output end of the NAND gate NAND31, the two input ends of the NAND gate NAND43 are electrically connected to the input end of the inverter INV11 of the first clock generating branch and the input end of the inverter INV11 of the second clock generating branch, and the output end of the NAND gate NAND43 is electrically connected to the second input end of the NAND gate NAND10 of the third clock generating branch; The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND44, the second input end of the NAND gate NAND44 is electrically connected to the output end of the inverter INV30, the input end of the inverter INV30 is electrically connected to the output end of the NAND gate NAND20, the three input ends of the NAND gate NAND20 are electrically connected to the input end of the inverter INV11 of the first clock generating branch, the input end of the inverter INV11 of the second clock generating branch, and the input end of the inverter INV11 of the third clock generating branch, respectively, and the output end of the NAND gate NAND44 is electrically connected to the first input end of the NAND gate NAND10 of the fourth clock generating branch; The output end of the phase detector INV51 is electrically connected to the second input end of the NAND gate NAND45, the first input end of the NAND gate NAND45 is electrically connected to the output end of the inverter INV31, the input end of the inverter INV31 is electrically connected to the output end of the NAND gate NAND21, the three input ends of the NAND gate NAND21 are respectively electrically connected to the output end of the inverter INV11 of the first clock generating branch, the output end of the inverter INV11 of the second clock generating branch, and the output end of the inverter INV11 of the third clock generating branch, and the output end of the NAND gate NAND45 is electrically connected to the second input end of the NAND gate NAND10 of the fourth clock generating branch; The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND46, the second input end of the NAND gate NAND46 is electrically connected to the output end of the inverter INV32, the input end of the inverter INV32 is electrically connected to the output end of the NAND gate NAND22, the two input ends of the NAND gate NAND22 are electrically connected to the output end of the inverter INV30 and the input end of the inverter INV11 of the fourth clock generating branch respectively, and the output end of the NAND gate NAND46 is electrically connected to the first input end of the NAND gate NAND10 of the fifth clock generating branch; The output end of the phase detector INV51 is electrically connected to the second input end of the NAND gate NAND47, the first input end of the NAND gate NAND47 is electrically connected to the output end of the inverter INV33, the input end of the inverter INV33 is electrically connected to the output end of the NAND gate NAND23, the two input ends of the NAND gate NAND23 are respectively electrically connected to the output end of the inverter INV31 and the output end of the inverter INV11 of the fourth clock generating branch, and the output end of the NAND gate NAND47 is electrically connected to the second input end of the NAND gate NAND10 of the fifth clock generating branch; The output end of the NOR gate NOR1 is electrically connected to the first input end of the NAND gate NAND48, the second input end of the NAND gate NAND48 is electrically connected to the output end of the inverter INV34, the input end of the inverter INV34 is electrically connected to the output end of the NAND gate NAND24, the three input ends of the NAND gate NAND24 are electrically connected to the output end of the inverter INV30, the input end of the inverter INV11 of the fourth clock generating branch and the input end of the inverter INV11 of the fifth clock generating branch, respectively, the output end of the NAND gate NAND48 is electrically connected to the first input end of the NAND gate NAND10 of the sixth clock generating branch; The output end of the phase detector INV51 is electrically connected to the second input end of the NAND gate NAND49, the first input end of the NAND gate NAND49 is electrically connected to the output end of the inverter INV35, the input end of the inverter INV35 is electrically connected to the output end of the NAND gate NAND25, the three input ends of the NAND gate NAND25 are respectively electrically connected to the output end of the inverter INV31, the output end of the inverter INV11 of the fourth clock generating branch and the output end of the inverter INV11 of the fifth clock generating branch, and the output end of the NAND gate NAND49 is electrically connected to the second input end of the NAND gate NAND10 of the sixth clock generating branch; The two input ends of the NAND gate NAND1 are electrically connected to the input end of the inverter INV11 of the sixth clock generating branch and the output end of the inverter INV35, and the two input ends of the NAND gate NAND3 are electrically connected to the output end of the inverter INV11 of the sixth clock generating branch and the output end of the inverter INV34.

6. The current detection circuit of a high side switch according to claim 5, characterized in that: The feedback current generating unit includes a MOS tube N20 and a MOS tube N21, the drain of the MOS tube N20 is electrically connected to the current source IREF2 and the gate of the MOS tube N20 respectively, the source of the MOS tube N20 is electrically connected to the drains of eight MOS tubes N22, the gates of eight MOS tubes N23 and the gates of eight MOS tubes N24 respectively, and the sources of the eight MOS tubes N23 and the eight MOS tubes N24 are grounded; The drain of the MOS tube N21 is electrically connected to the current source IREF1, the gate of the MOS tube N21, the gates of the eight MOS tubes N22, and the gates of the eight MOS tubes N25, respectively; the source of the MOS tube N21 is grounded; the sources of the eight MOS tubes N22 are correspondingly connected to the drains of the eight MOS tubes N23; the sources of the eight MOS tubes N25 are correspondingly connected to the drains of the eight MOS tubes N24; The drains of the eight MOS tubes N25 are respectively connected to the sources of the eight MOS tubes N26 and the sources of the eight MOS tubes N27, the gates of the eight MOS tubes N26 are respectively electrically connected to the input end of the inverter INV6, and the gates of the eight MOS tubes N27 are respectively electrically connected to the output end of the inverter INV6; The drains of the four MOS tubes N26 are electrically connected to the gate of the MOS tube N36, the drain of the MOS tube N36, the drain of the MOS tube N37, the drain of the MOS tube N38, the drain of the MOS tube N39 and the source of the MOS tube N1 respectively, and the drains of the remaining four MOS tubes N26 are correspondingly connected to the sources of the four MOS tubes N28, the gates of the four MOS tubes N28 are respectively electrically connected to the output end of the inverter INV5, and the drains of the two MOS tubes N28 are respectively electrically connected to the source of the MOS tube N1. The drains of the remaining two MOS tubes N28 are electrically connected to the sources of the two MOS tubes N30. The gates of the two MOS tubes N30 are electrically connected to the output ends of the inverter INV4 respectively. The drain of one MOS tube N30 is electrically connected to the source of the MOS tube N1. The drain of the other MOS tube N30 is electrically connected to the source of the MOS tube N32, the source of the MOS tube N33, the source of the MOS tube N34 and the source of the MOS tube N35 respectively. The gate of the MOS tube N32, the source of the MOS tube N33, the source of the MOS tube N34 and the source of the MOS tube N35 are electrically connected. The gate of MOS tube N33, the gate of MOS tube N34 and the gate of MOS tube N35 are electrically connected to the gate of MOS tube N20 respectively; the drain of MOS tube N32 is electrically connected to the source of MOS tube N36, the drain of MOS tube N33 is electrically connected to the source of MOS tube N37 and the source of MOS tube N40 respectively, the drain of MOS tube N34 is electrically connected to the source of MOS tube N38 and the source of MOS tube N41 respectively, the drain of MOS tube N35 is electrically connected to the source of MOS tube N39 and the source of MOS tube N41 respectively. The source of the MOS tube N42 is electrically connected; the gate of the MOS tube N37 is electrically connected to the output end of the inverter INV1, the gate of the MOS tube N38 is electrically connected to the output end of the inverter INV2, the gate of the MOS tube N39 is electrically connected to the output end of the inverter INV3, the gate of the MOS tube N40 is electrically connected to the input end of the inverter INV1, the gate of the MOS tube N41 is electrically connected to the input end of the inverter INV2, and the gate of the MOS tube N42 is electrically connected to the input end of the inverter INV3; The drain of the MOS tube N40 is electrically connected to the drain of the MOS tube N41, the drain of the MOS tube N42, the source of the MOS tube N2, and the drains of the four MOS tubes N27 respectively; the drains of the remaining four MOS tubes N27 are connected to the sources of the four MOS tubes N29 correspondingly; the gates of the four MOS tubes N29 are electrically connected to the input end of the inverter INV5; the drains of the two MOS tubes N29 are electrically connected to the drain of the MOS tube N40; the drains of the other two MOS tubes N29 are electrically connected to the sources of the two MOS tubes N31; the gates of the two MOS tubes N31 are electrically connected to the input end of the inverter INV4; the drain of one MOS tube N31 is electrically connected to the drain of the MOS tube N40; and the drain of the other MOS tube N31 is electrically connected to the drain of the MOS tube N30; Input terminals of the inverters INV1 to INV6 are respectively used to input clock control signals generated by the clock signal generating unit.

7. The current detection circuit of a high side switch according to claim 6, characterized in that:The input end of the inverter INV1 is used to input the clock control signal CP1, and the input end of the inverter INV2 is used to input the clock control signal CP2.

8. The current detection circuit of a high side switch according to claim 6, characterized in that: The input terminal of the inverter INV3 is used to input the clock control signal CP3, and the input terminal of the inverter INV4 is used to input the clock control signal CP4.

9. The current detection circuit of a high side switch according to claim 6, characterized in that: The input terminal of the inverter INV5 is used to input the clock control signal CP5, and the input terminal of the inverter INV6 is used to input the clock control signal CP6.

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