High noise immunity, low latency level shift circuit for GaN half-bridge driver IC

Abstract

The present invention relates to a high noise-resistant, low-delay level shift circuit for a GaN half-bridge driver chip, and belongs to the technical field of power management in integrated circuits. The circuit adds an additional path from a floating power rail VDDH to the ground to simulate the influence of noise caused by a sudden change in the floating power rail voltage in the level shift circuit. Theoretically, this solution can achieve very good noise resistance, and only adds six PMOS tubes, one NLDMOS, and one inverter, with a simple structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management in integrated circuits, and relates to a high-noise-resistance, low-delay level shifting circuit for a GaN half-bridge driver chip. Background Art

[0002] Since the on-off output voltage of the power tube of the half-bridge topology works in a floating state, the power supply voltage of the high-voltage side drive circuit will also work in a floating state. Generally speaking, an external bootstrap capacitor is often used to obtain the floating power supply of the high-voltage side drive circuit. Since the power supply of the high-voltage side drive circuit is floating, when the floating power supply voltage changes, very high dv / dt noise will be generated. Due to the large parasitic capacitance of the LDMOS drain, the potential of the LDMOS drain cannot closely follow the change of the floating voltage, which will produce a certain voltage drop. Once the voltage drop reaches the threshold voltage of the subsequent circuit, it is very likely to cause the drive circuit to trigger incorrectly or even burn the circuit. Compared with traditional Si-based devices, the switching frequency of GaN devices is at the MHZ level, the turn-on and turn-off time is extremely fast, and the dv / dt noise generated by the floating power rail is greater. Therefore, the level shift circuit required requires higher noise resistance and lower delay.

[0003] In order to eliminate dv / dt noise, the traditional solution is to connect a narrow pulse filter circuit after the level shift circuit, such as Figure 1 As shown. When there is a large dv / dt noise, the required narrow pulse filter circuit delay will be larger, which will cause a large delay in the driver chip. In addition, many scholars have increased the noise resistance by shunting without increasing the circuit delay, but the noise resistance can be further improved. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a GaN level shift circuit with ultra-high dv / dt noise suppression. The present invention effectively blocks the influence of noise on the output without affecting the normal signal transmission of the circuit, thereby improving the stability and reliability of the circuit.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A high noise immunity, low delay level shift circuit for GaN half-bridge driver chip, by adding an additional floating power rail VDDH to ground path, to simulate the noise impact caused by the sudden change of floating power rail voltage in the level shift circuit. Theoretically, this solution can achieve very good noise immunity, only adding six PMOS tubes (MP9 ~ MP14), one NLDMOS (LD3), and one inverter (INV5), with a simple structure.

[0007] The circuit specifically includes first to fourteenth PMOS transistors MP1 to MP14, first to seventh NMOS transistors MN1 to MN7, a first resistor R1, a second resistor R2, first to third NLDMOS transistors LD1 to LD3, and first to fifth inverters INV1 to INV5.

[0008] The gates of the first NLDMOS transistor LD1 and the second NLDMOS transistor LD2 are respectively connected to the low-voltage narrow pulse signal, their sources are grounded, and their drains are respectively connected to the drains of the first PMOS transistor MP1 and the seventh PMOS transistor MP7; the gate and source of the third NLDMOS transistor LD3 are grounded, and its drain is connected to the drain of the thirteenth PMOS transistor MP13.

[0009] The gate and source of the first NMOS transistor MN1 are connected to the floating ground VSW, and the drain is connected to the drain of the first NLDMOS transistor LD1; the source of the second NMOS transistor MN2 is connected to the floating ground VSW, the gate and the drain are short-circuited, and are connected to the floating ground VSW through the first resistor R1; the gate of the third NMOS transistor MN3 is connected to the gate of the second NMOS transistor MN2, the source is connected to the floating ground VSW, and the drain is connected to the drain of the eleventh PMOS transistor MP11; the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, the source is connected to the floating ground VSW, and the drain is connected to the drain of the tenth PMOS transistor MP10; the gate and the drain of the fifth NMOS transistor MN5 are short-circuited, and are connected to the floating ground VSW through the second resistor R2, and the source is connected to the floating ground VSW; the gate and the source of the sixth NMOS transistor MN6 are connected to the floating ground VSW, and the drain is connected to the drain of the second NLDMOS transistor LD2; the gate and the source of the seventh NMOS transistor MN7 are connected to the floating ground VSW, and the drain is connected to the drain of the third NLDMOS transistor LD3.

[0010] The gate and drain of the first PMOS tube MP1 are short-circuited, connected to the drain of the first NLDMOS tube LD1, and its source is connected to the floating power rail VDDH; the gate of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1, the source is connected to the floating power rail VDDH, and the drain is connected to the source of the ninth PMOS tube MP9; the gate of the third PMOS tube MP3 is connected to the gate of the first PMOS tube MP1, the source is connected to the floating power rail VDDH, and the drain is connected to the source of the tenth PMOS tube MP10; the gate and source of the fourth PMOS tube MP4 are short-circuited, connected to the floating power rail VDDH, and the drain is connected to the gate of the first PMOS tube MP1; the source of the fifth PMOS tube MP5 is connected to the floating power rail VDDH, the gate is connected to the drain of the second NLDMOS tube LD2, and the drain is connected to the source of the eleventh PMOS tube MP11; the source of the sixth PMOS tube MP6 is connected to the floating power rail VDDH, the gate is connected to the gate of the fifth PMOS tube MP5, and the drain is connected to the twelfth PMOS tube MP The gate and drain of the seventh PMOS tube MP7 are short-circuited, connected to the gate of the fifth PMOS tube MP5, and the source is connected to the floating power rail VDDH; the source and gate of the eighth PMOS tube MP8 are short-circuited, and connected to the floating power rail VDDH, and the drain is connected to the gate of the fifth PMOS tube MP5; the drain of the ninth PMOS tube MP9 is connected to the drain of the second NMOS tube MN2; the drain of the twelfth PMOS tube MP12 is connected to the drain of the fifth NMOS tube MN5; the gates of the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11, and the twelfth PMOS tube MP12 are connected to the output end of the fifth inverter INV5; the source of the thirteenth PMOS tube MP13 is connected to the floating power rail VDDH, the gate and the drain are short-circuited, and connected to the drain of the third NLDMOS tube LD3; the gate and the source of the fourteenth PMOS tube PM14 are short-circuited, connected to the floating power rail VDDH, and the drain is connected to the drain of the third NLDMOS tube LD3.

[0011] The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 are all connected between the floating power rail VDDH and the floating ground VSW; the input of the first inverter INV1 is connected to the drain of the third NMOS tube MN3, and the output is connected to the drain of the fourth NMOS tube MN4; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the output is connected to the input of the first inverter INV1; the input of the third inverter INV3 is connected to the input of the first inverter INV1, and the output is connected to OUT+; the input of the fourth inverter INV4 is connected to the output of the first inverter INV1, and the output is connected to OUT-.

[0012] Furthermore, when positive dVSW / dt noise comes, a timely response is made and the ninth PMOS transistor MP9 , the tenth PMOS transistor MP10 , the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are used to block the noise, thereby ensuring stable operation of the circuit.

[0013] Further, when positive dVSW / dt comes, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 are turned off, so that the noise cannot be transmitted to the output end. Ideally, the ability to eliminate noise is infinite, which depends on the tolerance of the devices connected to the nodes G1, G2, and G3 (that is, the gate-source and source-drain breakdown voltages of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fifth PMOS tube PM5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, and the thirteenth PMOS tube MP13, and the source-drain breakdown voltages of the fourth PMOS tube MP4, the eighth PMOS tube MP8, and the fourteenth PMOS tube MP14), thereby ensuring the stability of the circuit operation; when negative dVSW / dt comes, the second PMOS tube MP2, the third PMOS tube MP3, the fifth PMOS tube MP5, and the sixth PMOS tube MP6 are turned off, and the output is not affected.

[0014] The beneficial effect of the present invention is that the circuit of the present invention can effectively isolate the influence of dv / dt noise on the output without substantially increasing the circuit delay, has a strong anti-noise capability, and can be effectively applied to GaN half-bridge driver chips.

[0015] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, except for the input signal IN, the other node signals are voltage changes relative to the floating ground VSW. Among them:

[0017] Figure 1 It is a traditional level shift circuit;

[0018] Figure 2 The level shift circuit diagram of the present invention is applicable to the GaN half-bridge driver chip;

[0019] Figure 3This is the working waveform diagram when there is no noise interference;

[0020] Figure 4 is the delay waveform of the level shift circuit;

[0021] Figure 5 This is the working waveform diagram when there is noise interference;

[0022] Figure 6 This is the working waveform when the noise interference is 3500V / ns. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0024] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0025] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0026] See also Figure 2 to Figure 6 ,like Figure 2As shown, the level shift circuit of the present invention is composed of the first PMOS tube MP1 to the fourteenth PMOS tube MP14, the first NMOS tube MN1 to the seventh NMOS tube MN7, the first resistor R1, the second resistor R2, the first NLDMOS tube LD1 to the third NLDMOS tube LD3, and the first inverter INV1 to the fifth inverter INV5. VDDH is the floating power rail voltage, and VSW is the floating ground. The role of the resistors R1 and R2 is to prevent MN3 and MN4 from being mis-conducted during the non-working period.

[0027] When there is no noise, the waveform is like Figure 3 As shown. After the input square wave signal passes through the narrow pulse generator, a narrow pulse signal is formed, and LD1 and LD2 are turned on at the rising edge and falling edge of the input square wave respectively. When LD1 is turned on, the pull-down current generated will pull down the potential of node G1 to turn on MP2 and MP3. MN1 adopts a diode connection method, which acts to clamp the potential of node G1 to prevent the voltage drop from being too large and breaking down MP1, MP2, and MP3. After MP2 and MP3 are turned on, since the gates of MP9 and MP10 are at a low level, the pull-down current generated will pull node F1 to a high level, and then pull node H1 to a low level through the current mirror formed by MN2 and MN3; at the same time, node H2 will be maintained at a high level, and finally the output OUT+ will be pulled to a high level by the inverter INV3. When LD2 is turned on, the pull-down current generated will pull down the potential of node G2 to turn on MP5 and MP6. MN6 is connected in a diode manner, which acts to clamp the potential of node G2 to prevent excessive voltage drop and breakdown of MP5, MP6, and MP7. After MP5 and MP6 are turned on, since the gates of MP11 and MP12 are at a low level, the pull-down current generated will pull node F2 to a high level, and then pull node H2 to a low level through the current mirror formed by MN4 and MN5; at the same time, node H1 will be maintained at a high level, and finally the inverter INV4 will pull the output OUT- to a high level. The role of INV1 and INV2 is to generate positive feedback and accelerate the transmission of signals. Figure 4 It can be seen that the rising edge delay is 2.72ns and the falling edge delay is 2.72ns.

[0028] However, when actually applied to the GaN half-bridge driver chip, the upper tube of the half-bridge structure is turned on, which will quickly raise the voltage of the floating ground VSW. Since the high-voltage area of ​​the GaN half-bridge driver chip is powered by a bootstrap capacitor, the voltage of the floating power rail VDDH will also be raised. However, the parasitic capacitance of the NLDMOS drain to the ground is very large, resulting in the failure of its drain voltage to follow the change of the floating power rail in time, forming a voltage drop and turning on MP2, MP3, MP5, and MP6, transferring noise to the output, causing logic function disorder.

[0029] In the present invention, an additional path from the floating power supply VDDH to the ground is introduced. The on-resistance of MP13 is about 3 times greater than that of MP1 and MP7. When positive dVSW / dt comes, the potential of node G3 changes more slowly than that of nodes G1 and G2. When the potential of nodes G1 and G2 drops relative to the floating power rail to turn on MP2, MP3, MP5, and MP6, node G3 has already triggered the inverter to output a high level, turning off MP9, MP10, MP11, and MP12, so that the noise cannot be transmitted to the output end. Ideally, the ability to eliminate noise is infinite, which depends on the tolerance of the devices connected to nodes G1, G2, and G3 (i.e., the gate-source and source-drain breakdown voltages of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fifth PMOS tube PM5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, and the thirteenth PMOS tube MP13, and the source-drain breakdown voltages of the fourth PMOS tube MP4, the eighth PMOS tube MP8, and the fourteenth PMOS tube MP14), ensuring the stability of the circuit operation. When negative dVSW / dt comes, MP2, MP3, MP5, and MP6 are turned off, which will not affect the output. The functions of MP4, MP8 and MP14 are to clamp the voltages of nodes G1, G2 and G3 to protect the circuit. Figure 5 , Figure 6 This is the working waveform when there is noise. It can be seen that when dVSW / dt=3500V / ns, it will not affect the working stability.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A high noise immunity, low delay level shift circuit for a GaN half-bridge driver chip, characterized in that: The transistors include a first PMOS transistor MP1 to a fourteenth PMOS transistor MP14, a first NMOS transistor MN1 to a seventh NMOS transistor MN7, a first resistor R1, a second resistor R2, a first NLDMOS transistor LD1 to a third NLDMOS transistor LD3, and a first inverter INV1 to a fifth inverter INV5; The gates of the first NLDMOS transistor LD1 and the second NLDMOS transistor LD2 are connected to the low-voltage narrow pulse signal respectively, the sources thereof are grounded, and the drains thereof are connected to the drains of the first PMOS transistor MP1 and the seventh PMOS transistor MP7 respectively; the gate and source of the third NLDMOS transistor LD3 are grounded, and the drain thereof is connected to the drain of the thirteenth PMOS transistor MP13; The gate and source of the first NMOS transistor MN1 are connected to the floating ground VSW, and the drain is connected to the drain of the first NLDMOS transistor LD1; the source of the second NMOS transistor MN2 is connected to the floating ground VSW, the gate and the drain are short-circuited, and connected to the floating ground VSW through the first resistor R1; the gate of the third NMOS transistor MN3 is connected to the gate of the second NMOS transistor MN2, the source is connected to the floating ground VSW, and the drain is connected to the drain of the eleventh PMOS transistor MP11; the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, the source is connected to the floating ground VSW, and the drain is connected to the drain of the tenth PMOS transistor MP10; the gate and the drain of the fifth NMOS transistor MN5 are short-circuited, and connected to the floating ground VSW through the second resistor R2, and the source is connected to the floating ground VSW; the gate and the source of the sixth NMOS transistor MN6 are connected to the floating ground VSW, and the drain is connected to the drain of the second NLDMOS transistor LD2; the gate and the source of the seventh NMOS transistor MN7 are connected to the floating ground VSW, and the drain is connected to the drain of the third NLDMOS transistor LD3; The gate and drain of the first PMOS tube MP1 are short-circuited, connected to the drain of the first NLDMOS tube LD1, and its source is connected to the floating power rail VDDH; the gate of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1, the source is connected to the floating power rail VDDH, and the drain is connected to the source of the ninth PMOS tube MP9; the gate of the third PMOS tube MP3 is connected to the gate of the first PMOS tube MP1, the source is connected to the floating power rail VDDH, and the drain is connected to the source of the tenth PMOS tube MP10; the gate and source of the fourth PMOS tube MP4 are short-circuited, connected to the floating power rail VDDH, and the drain is connected to the gate of the first PMOS tube MP1; the source of the fifth PMOS tube MP5 is connected to the floating power rail VDDH, the gate is connected to the drain of the second NLDMOS tube LD2, and the drain is connected to the source of the eleventh PMOS tube MP11; the source of the sixth PMOS tube MP6 is connected to the floating power rail VDDH, the gate is connected to the gate of the fifth PMOS tube MP5, and the drain is connected to the twelfth PMOS tube MP The gate and drain of the seventh PMOS tube MP7 are short-circuited, connected to the gate of the fifth PMOS tube MP5, and the source is connected to the floating power rail VDDH; the source and gate of the eighth PMOS tube MP8 are short-circuited, and connected to the floating power rail VDDH, and the drain is connected to the gate of the fifth PMOS tube MP5; the drain of the ninth PMOS tube MP9 is connected to the drain of the second NMOS tube MN2; the drain of the twelfth PMOS tube MP12 is connected to the drain of the fifth NMOS tube MN5; the gates of the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11, and the twelfth PMOS tube MP12 are connected to the output end of the fifth inverter INV5; the source of the thirteenth PMOS tube MP13 is connected to the floating power rail VDDH, the gate and the drain are short-circuited, and connected to the drain of the third NLDMOS tube LD3; the gate and the source of the fourteenth PMOS tube PM14 are short-circuited, connected to the floating power rail VDDH, and the drain is connected to the drain of the third NLDMOS tube LD3; The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 are all connected between the floating power rail VDDH and the floating ground VSW; the input of the first inverter INV1 is connected to the drain of the third NMOS tube MN3, and the output is connected to the drain of the fourth NMOS tube MN4; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the output is connected to the input of the first inverter INV1; the input of the third inverter INV3 is connected to the input of the first inverter INV1, and the output is connected to OUT+; the input of the fourth inverter INV4 is connected to the output of the first inverter INV1, and the output is connected to OUT-.

2. The high noise immunity and low delay level shift circuit according to claim 1, characterized in that: When positive dVSW / dt noise comes, the ninth PMOS transistor MP9 , the tenth PMOS transistor MP10 , the eleventh PMOS transistor MP11 , and the twelfth PMOS transistor MP12 are used to block the noise.

3. The high noise immunity and low delay level shift circuit according to claim 2, characterized in that: When positive dVSW / dt comes, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 are turned off, so that the noise cannot be transmitted to the output end; the ability of the circuit to eliminate noise depends on the gate-source and source-drain breakdown voltages of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fifth PMOS tube PM5, the sixth PMOS tube MP6, the seventh PMOS tube MP7 and the thirteenth PMOS tube MP13, and the source-drain breakdown voltages of the fourth PMOS tube MP4, the eighth PMOS tube MP8 and the fourteenth PMOS tube MP14; when negative dVSW / dt comes, the second PMOS tube MP2, the third PMOS tube MP3, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are turned off, so that the noise cannot be transmitted to the output end.

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