File access method and storage medium based on GPGPU multi-channel register

Abstract

The present application relates to the technical field of file access in a computer, and discloses a file access method and storage medium based on a GPGPU multi-channel register. By introducing the multi-channel access technology, each channel is equipped with a dedicated request queue cache and control logic; and then the multi-thread bundle parallel access is realized through an operand collection unit and an arbitration mechanism, so that the register file access efficiency will be significantly improved, the access conflict and delay will be greatly reduced, the pipeline stagnation waiting time will be shortened, and the overall computing performance will be significantly improved.

Description

Technical Field

[0001] The present application relates to the technical field of file access in computers, for example, to a file access method and storage medium based on GPGPU multi-channel registers. Background Art

[0002] With the growing number of computationally intensive applications, such as deep learning, big data analysis, and scientific simulation, the demand for high-performance computing continues to rise. GPGPU plays an important role in these fields due to its powerful parallel computing capabilities and high-density execution units. GPGPU is an extension of GPU technology, extending the parallel computing capabilities of GPU to the field of general computing. Register files are a key component of the GPGPU architecture, which is responsible for storing intermediate results and state variables during the calculation process. In GPGPU, a large number of threads running in parallel need to frequently access register files. However, with the increase in the number of computing units, a single access channel may become a bandwidth bottleneck. Unreasonable access patterns and high latency increase energy consumption and reduce energy efficiency. The existing register file architecture is difficult to smoothly expand to cope with the growing computing needs.

[0003] Therefore, the access efficiency of register files in existing GPGPUs is relatively low, which directly affects the overall computing performance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0006] The present disclosure provides a file access method based on a GPGPU multi-channel register, the method comprising:

[0007] After the upper scheduling unit activates and generates multiple thread warps, the active thread warps start fetching instructions according to their respective instruction addresses;

[0008] After fetching the instruction, it decodes the number and type of operands contained in each instruction in turn, and sends them to the operand collection unit together with the instruction address and thread warp ID as decoding information;

[0009] After the operand collection unit receives the decoding information, the resource management module detects the currently idle collectors and assigns the idle collectors to the active thread warps according to the polling and GTY scheduling strategies;

[0010] After receiving register read requests from different collectors, the MUX unit in the target channel of the multiple channels records the number of register requests with different WIDs and the same RID according to the WID and RID in the register read request as the address of the lookup table, and at the same time, the multiplexer selects the corresponding collector request according to the corresponding address and transmits it to the request buffer queue of the corresponding channel;

[0011] The register control unit accesses the register logic block according to the register index information in the request cache queue and stores the read register value, WID and RID in the response cache queue of the corresponding channel.

[0012] In some embodiments, the method further comprises:

[0013] After the DEMUX unit in the channel corresponding to the active thread bundle detects that the response buffer queue is not empty, it first reads the lookup table in the MUX unit. According to the access records of the same RID by different WIDs in the lookup table, the register value corresponding to the RID in the cache is repeatedly written into the collection table in the collector corresponding to different WIDs, and the valid position under the corresponding operand entry is set to 1 to indicate that the operand value has been obtained.

[0014] In some embodiments, after the valid bits of all operand entries in other channels among the multiple channels are set, the dispatch unit will send the relevant information in the collection table to the subsequent execution units in sequence and release the collector resources at the same time.

[0015] In some embodiments, the resource management module detects currently idle collectors and allocates the idle collectors to active warps according to polling and GTY scheduling strategies, including:

[0016] Divide the active thread bundles according to the principle that the smaller the WID, the higher the priority;

[0017] The resource management module detects the currently idle collectors and allocates the idle collectors to the active thread warps after partitioning according to the polling and GTY scheduling strategies.

[0018] In some embodiments, the method further comprises:

[0019] The resource management module allocates the active thread warps to the corresponding idle collectors, and stores the WID and the operand RID and type information contained in the instruction into the collection table of the collector, wherein the collection table includes the thread warp information;

[0020] A register read request is generated based on the operands RID and WID that need to be collected.

[0021] In some embodiments, the operand collection unit includes multiple operand collectors, a resource manager, and a thread bundle buffer pool, wherein the number of operand collectors is determined according to resource constraints, each operand collector maintains a collection table for storing register values, WID, and RID information, the resource management module is used to monitor the status of the operand collector in real time, and the thread bundle buffer pool is used to cache thread bundles that are not allocated to collector resources.

[0022] In some embodiments, the method further comprises:

[0023] The registers are evenly distributed into different register logic blocks, and a request cache queue is added in each channel, and multiple operand collectors are introduced.

[0024] The embodiment of the present disclosure provides a storage medium storing program instructions, which, when run, execute the file access method based on GPGPU multi-channel registers in the above embodiment.

[0025] The file access method and storage medium based on GPGPU multi-channel register provided in the embodiments of the present disclosure can achieve the following technical effects:

[0026] By introducing multi-channel access technology, each channel is equipped with a dedicated request queue cache and control logic, and the number of channels supports dynamic adjustment. Multi-thread bundle parallel access is then achieved through the operand collection unit and arbitration mechanism, which significantly improves the register file access efficiency, greatly reduces access conflicts and delays, shortens pipeline stagnation waiting time, and significantly improves the overall computing performance.

[0027] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0029] Figure 1 It is a flowchart of a file access method based on GPGPU multi-channel registers provided by an embodiment of the present disclosure;

[0030] Figure 2 is a schematic diagram of a file access system based on GPGPU multi-channel registers provided by an embodiment of the present disclosure;

[0031] Figure 3 It is a schematic diagram of register logic block LR division provided by an embodiment of the present disclosure;

[0032] Figure 4 is a schematic diagram of the structure of an operand collection unit provided by an embodiment of the present disclosure;

[0033] Figure 5 It is a structural diagram of another file access system based on GPGPU multi-channel registers provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0035] The terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0036] Unless otherwise stated, the term "plurality" means two or more.

[0037] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0038] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0039] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0040] The following describes a file access method and a storage medium based on a general-purpose computing on Graphics Processing Units (GPGPU) multi-channel register provided by an embodiment of the present disclosure in conjunction with the accompanying drawings.

[0041] Figure 1 It is a flowchart of a file access method based on GPGPU multi-channel registers provided in an embodiment of the present disclosure.

[0042] like Figure 1 As shown, the file access method based on GPGPU multi-channel register may include:

[0043] S01, after the upper scheduling unit activates and generates multiple thread warps, the active thread warps start fetching instructions according to their respective instruction addresses;

[0044] S02, after fetching the instructions, decoding is performed in sequence to obtain the number and type of operands contained in each instruction, and the operands are sent to the operand collection unit together with the instruction address and the thread bundle identity (Identity Document, ID) as decoding information;

[0045] S03, after the operand collection unit receives the decoding information, the resource management module detects the currently idle collectors and allocates the idle collectors to the active thread warps according to the polling and Greedy-Then-Youngest (GTY) scheduling strategies;

[0046] S04, after receiving register read requests from different collectors, a multiplexer (MUX) unit in a target channel among the multiple channels records the number of register requests with different WIDs and the same RID according to the Workload Identity Document (WID) and the Resource Identity Document (RID) in the register read request as the address of a lookup table, and at the same time, a multiplexer selects the corresponding collector request according to the corresponding address and transmits it to the request buffer queue of the corresponding channel;

[0047] S05, the register control unit accesses the register logic block to store the read register value, WID and RID into the response cache queue of the corresponding channel according to the register index information in the request cache queue.

[0048] In the present disclosure, by introducing multi-channel access technology, the register file is divided into multiple independent logic blocks (Logic Region, LR), and each channel is equipped with a dedicated request queue cache and control logic, and the number of channels supports dynamic adjustment. Then, the operand collection unit and arbitration mechanism are used to achieve multi-thread bundle parallel access, which significantly improves the register file access efficiency, greatly reduces access conflicts and delays, shortens the pipeline stagnation waiting time, and significantly improves the overall computing performance.

[0049] In some embodiments, after the demultiplexer (DEMUX) unit in the channel corresponding to the active thread warp detects that the response buffer queue is not empty, it first reads the lookup table in the MUX unit, and based on the access records of the same RID by different WIDs in the lookup table, repeatedly writes the register value corresponding to the RID in the cache into the collection table in the collectors corresponding to different WIDs, and sets the valid position under the corresponding operand entry to 1 to indicate that the operand value has been obtained.

[0050] Among them, according to the access records of the same RID by different WIDs in the lookup table, the register value corresponding to the RID in the cache is repeatedly written into the collection table in the collector corresponding to the different WIDs, and the valid position 1 under the corresponding operand entry indicates that the operand value has been obtained. Specifically, according to the access records of the same RID by different WIDs in the lookup table, the nature and number of working units accessing a certain RID are determined, and then the access situation is divided according to the nature and number of different working units, and WID matching is performed based on the feature identifiers in the divided registers, and then the corresponding register is selected based on multi-channel access, combined with the register read requests of different collectors, the register value corresponding to the RID in the cache is repeatedly written into the collection table in the collector corresponding to the different WIDs, and the valid position 1 under the corresponding operand entry indicates that the operand value has been obtained, so as to accurately determine the operand value that has been obtained.

[0051] In some embodiments, after the valid bits of all operand entries in other channels among the multiple channels are set, the dispatch unit will send the relevant information in the collection table to the subsequent execution units in sequence and release the collector resources at the same time.

[0052] In some embodiments, the resource management module detects currently idle collectors and allocates the idle collectors to active warps according to the polling and GTY scheduling policies, including:

[0053] Divide the active thread bundles according to the principle that the smaller the WID, the higher the priority;

[0054] The resource management module detects the currently idle collectors and allocates the idle collectors to the active thread warps after partitioning according to the polling and GTY scheduling strategies.

[0055] In some embodiments, Figure 1 The method may also include:

[0056] The resource management module allocates the active thread warps to the corresponding idle collectors, and stores the WID and the operand RID and type information contained in the instruction into the collection table of the collector, wherein the collection table includes the thread warp information;

[0057] A register read request is generated based on the operands RID and WID that need to be collected.

[0058] In some embodiments, the operand collection unit includes multiple operand collectors, a resource manager, and a thread bundle buffer pool, wherein the number of operand collectors is determined according to resource constraints, each operand collector maintains a collection table for storing register values, WID, and RID information, the resource management module is used to monitor the status of the operand collector in real time, and the thread bundle buffer pool is used to cache thread bundles that are not allocated to collector resources.

[0059] In some embodiments, Figure 1 The method may also include:

[0060] The register files are evenly distributed into different register logic blocks, and a request cache queue is added in each channel, and multiple operand collectors are introduced.

[0061] Figure 2 is a schematic diagram of a file access system based on GPGPU multi-channel registers provided by an embodiment of the present disclosure, Figure 3 is a schematic diagram of register logic block LR division provided by an embodiment of the present disclosure, Figure 4 It is a schematic diagram of the structure of an operand collection unit provided in an embodiment of the present disclosure.

[0062] Combination Figure 2-Figure 4 ,right Figure 1 The file access method based on GPGPU multi-channel registers is continued to be described.

[0063] The register file access system mainly includes an operand collection unit, a MUX unit, a request cache queue, a register control unit, a register LR, a DEMUX unit, a response cache queue and a dispatch unit. The register logic block can be flexibly configured according to the number of channels. Considering many factors such as resources, the system currently supports four-channel register logic block configuration. When the upper scheduling unit activates and generates multiple thread warps, the operands in the instruction and the thread warp related decoding information are sent to the operand collection unit through instruction fetching and decoding. After receiving the decoding information, the operand collection unit detects the currently idle collector inside and allocates the idle collector resources to the active thread warp in turn, while the thread warp not allocated to the collector enters the pending buffer pool. After that, the collector generates an access request for the corresponding LR according to the currently active thread warp ID (WID) and the operand register ID (RID) contained in the executed instruction. The MUX unit receives register read requests from different collectors, selects the read request of the channel according to WID and RID, and caches it in the corresponding request queue. Then, the register control unit accesses the register logic block according to the register index information in the cache queue and stores the read register value, WID, RID and other information in the response cache queue. The DEMUX unit re-indexes to the corresponding collector according to the ID information in the response queue, writes the register value into the collection table in the collector, and sets the valid position 1 under the operand entry to indicate that the register value has been obtained. Repeat the above operations until all operand entries are valid. The dispatch unit will send the relevant information in the collection table to the subsequent execution unit and release the collector resources at the same time.

[0064] The operand collection unit is mainly composed of multiple operand collectors, resource managers, and thread bundle buffer pools. The number of collectors can be flexibly adjusted according to resource constraints, and a maximum of 4 collectors can be instantiated. Each operand collector maintains a collection table to store register values, WID, RID and other information. The resource management module is responsible for real-time monitoring of the status of the operand collector, and the thread bundle buffer pool is used to cache thread bundles that are not allocated to collector resources. When the operand collection unit receives the decoding information, the resource management module begins to detect the currently idle collectors. According to the polling and GTY (Greedy-Then-Youngest) scheduling strategies, the currently active thread bundle WID is first prioritized, following the principle that the smaller the WID, the higher the priority. Then, the idle collector resources are allocated to the active thread bundles in turn. If there are thread bundles that are not allocated to the collector, they enter the pending buffer pool. When there are new active thread bundles requesting collector resources, they are allocated to the newly added active thread bundles first. If there are no new active thread bundles, the collector resources are allocated to the thread bundles in the buffer pool according to the priority. After the collector is allocated by the resource management module, the WID, RID, and information such as the type and type of operands contained in the instruction are stored in the collection table entry. The collection table generally includes four entries corresponding to operand 1 (OP1), operand 2 (OP2), operand 3 (OP3), and thread warp overhead information, and generates corresponding operand read requests.

[0065] The present disclosure introduces multi-channel access technology to evenly distribute registers into different logic blocks (LogicRegion, LR), thereby reducing the probability of operand access conflicts, optimizing the register file access mechanism in the GPGPU architecture, adding a request cache queue in each access channel, introducing multiple operand collectors, maximally supporting multiple thread bundles in parallel access, reducing the pipeline stagnation time, and ensuring the continuity and fluency of calculation. At the same time, a composite arbitration mechanism is introduced to correctly forward the operand read request to the corresponding LR to ensure the stability of the access system, and after the operand collection is completed, it is accurately returned to the corresponding operand collection unit through the DEMUX unit. The register access system divides the register file into multiple independent logic blocks LR by introducing multi-channel access technology, and each channel is equipped with a dedicated request queue cache and control logic, and the number of channels supports dynamic adjustment. Then, the operand collection unit and arbitration mechanism are used to realize multi-thread bundle parallel access, so that the register file access efficiency will be significantly improved, access conflicts and delays will be greatly reduced, the pipeline stagnation waiting time will be shortened, and the overall computing performance will be significantly improved.

[0066] In a specific example, the file access method based on GPGPU multi-channel registers may include S1)-S5):

[0067] S1) When the upper scheduling unit activates and generates multiple thread warps, the active thread warps start to fetch instructions according to their respective instruction addresses. After the instructions are fetched, they are decoded in sequence to obtain the number and type of operands contained in each instruction, and are passed to the operand collection unit together with the instruction address, thread warp ID and other information.

[0068] S2) When the operand collection unit receives the decoding information, the resource management module starts to detect the currently idle collectors. According to the polling and GTY (Greedy-Then-Youngest) scheduling strategies, the currently active thread bundles WID are first prioritized, following the principle that the smaller the WID, the higher the priority. Assume that there are currently 6 active thread bundles, namely W0, W1, W2, W3, W4, and W5, with priorities W0>W1>W2>W3>W4>W5, and the collection unit contains 4 collectors. At this time, the resource manager detects that there are 2 idle collectors, namely Collector 1 (C1) and Collector 3 (C3), and assigns them to W0 and W1. W2~W5 that are not assigned to the collectors enter the pending buffer pool. If it is detected that C0 and C2 enter the idle state at this time, and two active thread warp requests W6 and W7 are received at the same time, C0 and C2 are preferentially allocated to W6 and W7 according to the GTY policy. On the contrary, if no new active thread warp is generated, the pending thread warp W3 and W4 are read from the buffer pool according to the priority and occupy the C0 and C2 collectors. At this time, the active thread warp is allocated to the corresponding collector after scheduling by the resource management module, and the WID and the operand RID and type contained in the instruction can be stored in the collector's collection table. The collection table generally includes four entries corresponding to operand 1 (OP1), operand 2 (OP2), operand 3 (OP3) and thread warp information, and then a register read request is generated according to the operand RID and WID that need to be collected.

[0069] S3) Taking channel 0 as an example, when the MUX unit in the channel receives register read requests from different collectors C1 and C3, it records the number of register requests with different WIDs and the same RID based on the request information WID and RID as the address of the lookup table. At the same time, the multiplexer selects the corresponding collector request based on the address and passes it to the request buffer queue of the channel. After that, the register control unit accesses the register logic block based on the register index information in the request buffer queue and stores the read register value, WID, RID and other information in the response buffer queue of the corresponding channel.

[0070] S4) When the DEMUX unit in channel 0 detects that the response buffer queue is not empty, it first reads the lookup table in the MUX unit. According to the access records of the same RID by different WIDs in the lookup table, the register value corresponding to the RID in the cache is repeatedly written into the collection table in the collector corresponding to different WIDs and the valid position under the operand entry is set to 1 to indicate that the operand value has been obtained.

[0071] S5) The operand reading process of channels 1, 2, and 3 is the same as S3) and S4). Repeat the above operations until the valid bits of all operand entries are set. The dispatch unit will send the relevant information in the collection table to the subsequent execution units in sequence and release the collector resources at the same time.

[0072] The present invention introduces multi-channel access technology to evenly distribute registers into different LRs, optimizes register file access and logic control mechanisms in the GPGPU architecture, introduces multiple operand collectors and buffer queues, supports parallel access of multiple thread warps to the maximum extent, reduces pipeline stagnation time, and ensures computing continuity and fluency.

[0073] Combination Figure 5 As shown, the embodiment of the present disclosure provides another file access system 500 based on GPGPU multi-channel registers, including a processor 504 and a memory 501. Optionally, the system may also include a communication interface 502 and a bus 503. Among them, the processor 504, the communication interface 502, and the memory 501 can communicate with each other through the bus 503. The communication interface 502 can be used for information transmission. The processor 504 can call the logic instructions in the memory 501 to execute the file access method based on the GPGPU multi-channel register of the above embodiment.

[0074] In addition, the logic instructions in the memory 501 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0075] The memory 501 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 504 executes the function application and data processing by running the program instructions / modules stored in the memory 501, that is, the file access method based on the GPGPU multi-channel register in the above embodiment is implemented.

[0076] The memory 501 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 501 may include a high-speed random access memory and may also include a non-volatile memory.

[0077] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute a file access method based on a GPGPU multi-channel register.

[0078] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0079] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0080] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or including (comprising) refer to the existence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or these groups. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same or similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0081] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. Technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. Technicians can clearly understand that for the convenience and simplicity of description, the specific working process of the systems, devices and units described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0082] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0083] The flowchart and block diagram in the accompanying drawings show the possible architecture, functions and operations of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A file access method based on GPGPU multi-channel registers, characterized in that: The method comprises: After the upper scheduling unit activates and generates multiple thread warps, the active thread warps start fetching instructions according to their respective instruction addresses; After fetching the instruction, it decodes the number and type of operands contained in each instruction in turn, and sends them to the operand collection unit together with the instruction address and thread warp ID as decoding information; After the operand collection unit receives the decoding information, the resource management module detects the currently idle collectors and assigns the idle collectors to the active thread warps according to the polling and GTY scheduling strategies; After receiving register read requests from different collectors, the MUX unit in the target channel of the multiple channels records the number of register requests with different WIDs and the same RID according to the WID and RID in the register read request as the address of the lookup table, and at the same time, the multiplexer selects the corresponding collector request according to the corresponding address and transmits it to the request buffer queue of the corresponding channel; The register control unit accesses the register logic block according to the register index information in the request cache queue and stores the read register value, WID and RID in the response cache queue of the corresponding channel; The resource management module detects currently idle collectors and allocates idle collectors to active thread warps according to polling and GTY scheduling strategies, including: Divide the active thread bundles according to the principle that the smaller the WID, the higher the priority; The resource management module detects the currently idle collectors and allocates the idle collectors to the active thread bundles after the division according to the polling and GTY scheduling strategies; The method further comprises: The resource management module allocates active thread warps to corresponding idle collectors, stores WID and operand RID and type information contained in the instruction into the collector's collection table, where the collection table includes thread warp information; and generates a register read request according to the operand RID and WID to be collected.

2. The method according to claim 1, characterized in that The method further comprises: After the DEMUX unit in the channel corresponding to the active thread bundle detects that the response buffer queue is not empty, it first reads the lookup table in the MUX unit. According to the access records of the same RID by different WIDs in the lookup table, the register value corresponding to the RID in the cache is repeatedly written into the collection table in the collector corresponding to different WIDs, and the valid position under the corresponding operand entry is set to 1 to indicate that the operand value has been obtained.

3. The method according to claim 1, characterized in that After the valid bits of all operand entries in other channels among the multiple channels are set, the dispatch unit sends the relevant information in the collection table to the subsequent execution units in sequence and releases the collector resources at the same time.

4. The method according to claim 1, characterized in that: The operand collection unit includes multiple operand collectors, a resource manager and a thread bundle buffer pool, wherein the number of operand collectors is determined according to resource constraints, each operand collector maintains a collection table for storing register values, WID, and RID information, the resource management module is used to monitor the status of the operand collector in real time, and the thread bundle buffer pool is used to cache thread bundles that are not allocated to collector resources.

5. The method according to claim 1, characterized in that The method further comprises: The registers are evenly distributed into different register logic blocks, and a request cache queue is added in each channel, and multiple operand collectors are introduced.

6. A storage medium storing program instructions, characterized in that: When the program instructions are run, the file access method based on the GPGPU multi-channel register is executed as described in any one of claims 1 to 5.

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