A 48-channel 48-port PCIe5.0Switch reset architecture

Abstract

The present invention belongs to the field of integrated circuit technology, and relates to a 48-channel 48-port PCIe5.0Switch reset architecture. The reset control module includes a basic reset control module, including a port signal selection logic module and a timing synchronization module; a basic reset signal from outside the chip is received and processed, and according to the port configuration information of the PCIe 5.0 Switch, the basic reset signal is sent to the designated port control module of the PCIe 5.0 Switch as needed; a hot reset and secondary bus reset control module includes an input control processing module and an output timing adjustment module. The present invention can support the basic reset, hot reset and secondary bus reset functions of the PCIe 5.0 Switch in the basic working mode and the Virtual Switch working mode, and provide a global or local recovery mechanism under abnormal conditions to ensure the reliability and stability of the system.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a 48-channel 48-port PCIe5.0Switch reset architecture. Background Art

[0002] With the rapid development of computer technology and the sharp increase in data processing needs, PCIe (Peripheral Component Interconnect Express), as a high-speed serial computer expansion bus standard, has become an important bridge connecting high-speed devices and hosts. The latest PCIe 5.0 version, compared with its predecessor, has doubled the bandwidth, providing strong support for high-speed data transmission and high-performance computing, and is of great significance in data centers, artificial intelligence and other fields. As the core interconnect component in the system, the PCIe 5.0 Switch chip plays a vital role. It can not only efficiently manage communications between multiple devices, but also optimize system performance and improve overall throughput and bandwidth utilization.

[0003] In the design of PCIe 5.0 Switch chip, reset control architecture is a crucial component, and its design directly affects the stability and reliability of the system. The main functions of the reset architecture include full-chip basic reset, hot reset and secondary bus reset, which respectively deal with different system states and abnormal conditions. Full-chip basic reset is responsible for restoring the entire chip to its initial state during system power-on initialization and major abnormal conditions. It can ensure the normal operation of all modules at system startup and reinitialize the system after a serious fault occurs to avoid unrecoverable errors. The hot reset function is used to reset specific modules during system operation, which will not affect the normal operation of the entire system. It is a local reset mechanism. The secondary bus reset function is used to reset the sub-devices connected to the PCIe Switch chip port to ensure that sub-devices can be quickly isolated and restored when problems occur, thereby ensuring the stability and efficient operation of the entire system.

[0004] Therefore, a reset architecture design for the PCIe 5.0 Switch chip is needed to support the full-chip basic reset, hot reset and secondary bus reset functions of the PCIe 5.0 Switch chip in basic working mode and Virtual Switch working mode to ensure the normal startup and operation of the system, and provide a full or partial recovery mechanism under abnormal circumstances to ensure the reliability and stability of the system. Summary of the invention

[0005] The purpose of the present invention is to provide a 48-channel 48-port PCIe 5.0 Switch reset architecture to realize the full-chip basic reset, hot reset and secondary bus reset functions of the PCIe 5.0 Switch chip in the basic working mode and the Virtual Switch working mode, and to restore the various parts of the chip to a known stable state when the system is initialized and an abnormal signal is received, so as to realize stable and efficient operation of the entire system.

[0006] In order to solve the above technical problems, the present invention provides a 48-channel 48-port PCIe 5.0 Switch reset architecture, including a reset control module, wherein the reset control module includes:

[0007] A basic reset control module, including a port signal selection logic module and a timing synchronization module; used to receive and process a basic reset signal from outside the chip, and send the basic reset signal to a designated port control module of the PCIe 5.0 Switch as needed according to the port configuration information of the PCIe 5.0 Switch;

[0008] The hot reset and secondary bus reset control module includes an input control processing module and an output timing adjustment module; it is used to receive and process the hot reset and secondary bus reset request signals from each port control module of the PCIe 5.0 Switch, and send the hot reset signal to the designated port control module of the PCIe 5.0 Switch as needed according to the port configuration information of the PCIe 5.0 Switch.

[0009] Preferably, the PCIe 5.0 Switch supports a basic working mode of single master and multiple slaves and a Virtual Switch working mode of realizing multiple masters and multiple slaves through virtual switches; wherein in the basic working mode, up to 48 PCIe ports are connected; and in the Virtual Switch working mode, up to 6 virtual switches are supported simultaneously.

[0010] Preferably, the PCIe 5.0 Switch reset architecture supports basic reset, hot reset and secondary bus reset functions in the basic working mode and the VirtualSwitch working mode.

[0011] Preferably, when the basic reset control module receives a full-chip power-on basic reset signal from outside the chip, the basic reset control module synchronizes the timing of the full-chip power-on basic reset signal with the timing of the port, and sends it to all 48 ports of the PCIe 5.0 Switch to perform a full-chip basic reset on all ports.

[0012] Preferably, when the PCIe 5.0 Switch is in the Virtual Switch working mode and the basic reset control module receives a basic reset signal from a designated virtual switch outside the chip, the port signal selection logic module processes the input basic reset signal of the designated virtual switch according to the port configuration information of the PCIe 5.0 Switch, and outputs the basic reset signal of the virtual switch of all corresponding ports under the hierarchical structure of the designated virtual switch itself. After being synchronized with the timing of the port, the basic reset signal is sent to all corresponding ports under the designated virtual switch of the PCIe 5.0 Switch to perform a basic reset on the designated virtual switch.

[0013] Preferably, each of the virtual switches corresponds to a virtual basic reset signal VSx, where x=0~5; and according to the configuration of the port register, each of the virtual switches also has a status signal VSx_pt [47:0] for indicating the port information, where x=0~5; the signal width is 48 bits, which are used to indicate the status of 48 ports respectively, that is, when a bit is set to 1, it indicates that the port belongs to the virtual switch hierarchy.

[0014] Preferably, the basic resetting of the designated virtual switch specifically includes: resetting all PCI-PCI bridges in the virtual switch hierarchy to achieve a comprehensive basic reset of the virtual switch, while other working virtual switches will not be affected.

[0015] Preferably, when the hot reset and secondary bus reset control module receives a hot reset request or a secondary bus reset request from an upstream port controller, the input control processing module will judge based on the port register configuration information and route the designated port hot reset signal to be output, and the output hot reset signal will be sent to all downstream ports corresponding to the upstream port after passing through the output timing adjustment module.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention receives the basic reset signal from the outside of the chip and the hot reset and secondary bus reset request signals from the control modules of each port of the PCIe5.0 Switch through a reset control module, processes and routes the input signal through the internal basic reset control module and the hot reset and secondary bus reset control module, and then transmits the reset signal to the specified PCIe5.0 Switch port to perform different reset operations. The reset architecture design can support the basic reset, hot reset and secondary bus reset functions of the PCIe5.0 Switch in the basic working mode and the Virtual Switch working mode, and provide a global or local recovery mechanism in abnormal situations to ensure the reliability and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the overall structure of the reset control module of the present invention.

[0019] Figure 2 This is a partial design architecture diagram of the basic reset control module in the reset control module of the present invention.

[0020] Figure 3 It is a schematic diagram of the port signal gating logic in the basic reset control module of the present invention.

[0021] Figure 4 The figure is a schematic diagram of the basic reset effect of specifying a VS in the Virtual Switch working mode of the present invention.

[0022] Figure 5 The figure is a schematic diagram of the operation of the hot reset and secondary bus reset control modules in the reset control module of the present invention during the hot reset process.

[0023] Figure 6 The figure is a working logic diagram of the input control processing module in the hot reset and secondary bus reset control module of the present invention.

[0024] Figure 7 The figure is a working logic diagram of the output timing adjustment module in the hot reset and secondary bus reset control module of the present invention.

[0025] Figure 8 It is a schematic diagram of the operation of the hot reset and secondary bus reset control modules in the reset control module of the present invention during the secondary bus reset process. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] The embodiment of the present invention provides a 48-channel 48-port PCIe 5.0 Switch reset architecture design. The PCIe5.0 Switch chip supports the basic working mode (single master and multiple slaves) and the Virtual Switch (virtual switch realizes multiple masters and multiple slaves) working mode. In the Virtual Switch working mode, up to 6 virtual switches are supported at the same time. The PCIe 5.0 Switch reset architecture design in the present invention supports the basic reset, hot reset and secondary bus reset functions in two working modes.

[0028] like Figure 1 As shown, the reset architecture of the present invention mainly includes a reset control module, and a basic reset control module and a hot reset and secondary bus reset control module inside it. Among them, the basic reset control module includes a port signal selection logic module and a timing synchronization module, which are used to receive and process the basic reset signal from the outside of the chip, and send the basic reset signal to the designated port control module of the PCIe 5.0 Switch as needed according to the port configuration information of the PCIe 5.0 Switch; the hot reset and secondary bus reset control module includes an input control processing module and an output timing adjustment module, which are used to receive and process the hot reset and secondary bus reset request signals from each port control module of the PCIe 5.0 Switch, and send the hot reset signal to the designated port control module of the PCIe 5.0 Switch as needed according to the port configuration information of the PCIe 5.0 Switch.

[0029] like Figure 2 As shown, when the reset control module receives a full-chip power-on basic reset signal from outside the chip, the full-chip power-on basic reset signal first enters the signal selection logic module and is converted into the basic reset signal output of 48 ports, and then is sent to all 48 ports of the PCIe 5.0 Switch through timing synchronization, performing a full-chip basic reset on all ports and restoring the initialization state.

[0030] The full-chip power-on reset signal is the only way to clear fatal errors that occur on the PCIe 5.0 Switch. In addition, when the PCIe 5.0 Switch works in Virtual Switch mode, each virtual switch has a corresponding virtual basic reset signal. According to the configuration of the port register, each virtual switch also has a status signal VSx_pt [47:0] (x=0~5) used to indicate the port's belonging information; the signal width is 48 bits, which is used to indicate the belonging status of 48 ports: when a bit is set to 1, it means that the port belongs to the virtual switch hierarchy.

[0031] In the Virtual Switch working mode, the virtual reset signal (VSx basic reset signal, x = 0~5) received by the basic reset control module from a virtual switch outside the chip will enter the port signal selection logic module and perform logical operations with the port configuration status signal VSx_pt.

[0032] like Figure 3 As shown in the figure, only when the basic reset signal of a virtual switch is pulled high and port m belongs to the hierarchy of the virtual switch, the port m_VS reset signal will be set to 1. Through the above logic operation, the port signal selection logic module can output the VS basic reset signal corresponding to all ports contained in the virtual switch hierarchy to be reset. After the timing processing asynchronous reset synchronous release, the port corresponding VS basic reset signal (port n_VS basic reset signal, n = 0~47) is sent to all corresponding ports in the virtual switch hierarchy, resetting all PCI-PCI bridges in the virtual switch hierarchy, realizing the comprehensive basic reset of the virtual switch, while other working virtual switches will not be affected.

[0033] like Figure 4 Shown above Figure 3 In one embodiment of the process shown, in the Virtual Switch working mode, if the basic reset control module receives a VS0 basic reset signal from outside the chip, the reset control module will perform a logical operation on the signal and convert it into a VS basic reset signal corresponding to all ports contained in the virtual switch VS0 hierarchy, that is, port 0~3_VS basic reset signal, and output it to upstream port 0 and downstream ports 1~3 to achieve basic reset of these ports. Similarly, port 4~7_VS basic reset signal, and output it to upstream port 4 and downstream ports 5~7 to achieve basic reset of these ports; port 8~11_VS basic reset signal, and output it to upstream port 8 and downstream ports 9~11 to achieve basic reset of these ports.

[0034] like Figure 5 and Figure 6As shown, when a port x set as upstream of the PCIe 5.0 Switch receives a hot reset request from the root complex RC, the port will send a hot reset request signal to the reset control module of the present invention and then reset the port itself; the hot reset request signal will enter the input control processing module in the hot reset and secondary bus reset control module. The port configuration information of the PCIe 5.0 Switch will send the corresponding status of the upstream and downstream ports to the input control processing module through a 48-bit wide signal. Each bit of the signal represents whether the port is the downstream port to which the upstream port that initiated the hot reset request belongs. The input control processing module uses this logic to select the hot reset signal of the port x that initiated the hot reset request to all its downstream ports, and send it to the output timing adjustment module.

[0035] like Figure 7 As shown, the output timing adjustment module of each port receives the hot reset signal from different upstream ports, and after timing adjustment, sends the hot reset signal to the downstream port to make the downstream port perform the hot reset operation.

[0036] Similarly, if Figure 8 As shown, when a port set as upstream of the PCIe 5.0 Switch receives a secondary bus reset request from the root complex RC, the port will send a secondary bus reset request signal to the reset control module of the present invention. This process will not reset the upstream port itself; the secondary bus reset request signal will enter the input control processing module in the hot reset and secondary bus reset control module. The input control processing module selects the hot reset signal of all downstream ports of the port x that initiates the secondary bus reset request through the port configuration information and sends it to the output timing adjustment module. The output timing adjustment module of each port receives the hot reset signal from different upstream ports, and after timing adjustment, sends the hot reset signal to the downstream port to make the downstream port perform a hot reset operation.

[0037] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A 48-channel 48-port PCIe5.0Switch reset architecture, including a reset control module, characterized in that: The reset control module comprises: A basic reset control module, including a port signal selection logic module and a timing synchronization module; used to receive and process a basic reset signal from outside the chip, and send the basic reset signal to a designated port control module of the PCIe 5.0 Switch as needed according to the port configuration information of the PCIe 5.0 Switch; A hot reset and secondary bus reset control module, including an input control processing module and an output timing adjustment module; used to receive and process hot reset and secondary bus reset request signals from each port control module of the PCIe 5.0 Switch, and send the hot reset signal to the designated port control module of the PCIe 5.0 Switch as needed according to the port configuration information of the PCIe 5.0 Switch; The PCIe 5.0 Switch supports a basic working mode of single master and multiple slaves and a Virtual Switch working mode of multiple masters and multiple slaves through a virtual switch; wherein in the basic working mode, 48 PCIe ports can be connected; and in the Virtual Switch working mode, 6 virtual switches can be supported simultaneously; When the PCIe 5.0 Switch is in the Virtual Switch working mode, and the basic reset control module receives a basic reset signal from a designated virtual switch outside the chip, the port signal selection logic module processes the basic reset signal of the designated virtual switch input according to the port configuration information of the PCIe 5.0 Switch, and outputs the basic reset signal of the virtual switch of all corresponding ports under the hierarchical structure of the designated virtual switch itself. After the basic reset signal is synchronized with the timing of the port, it is sent to all corresponding ports under the designated virtual switch of the PCIe 5.0 Switch to perform a basic reset on the designated virtual switch; The port signal selection logic module includes: six NOT gates, six OR gates 1, one OR gate 2 and an AND gate; six VSx basic reset signals are respectively connected to one of the input ends of the six OR gates 1, six port configuration state signals VSx_pt are respectively connected to the input ends of the six NOT gates, the output ends of the six NOT gates are respectively connected to the other input ends of the six OR gates 1, the output ends of the six OR gates 1 are respectively connected to the six input ends of an AND gate, the output end of an AND gate outputs a port m_VS reset signal, the port m_VS reset signal and the full-chip power-on basic reset signal are respectively connected to the two input ends of an OR gate 2, and the output end of an OR gate 2 outputs a port m_basic reset signal; In the Virtual Switch working mode, the basic reset control module receives a virtual reset signal from a virtual switch outside the chip, namely, a VSx basic reset signal, where the value of x ranges from 0 to 5; the VSx basic reset signal will enter the port signal selection logic module and perform a logical operation with the port configuration status signal VSx_pt; Only when the basic reset signal of one of the virtual switches is pulled high and port m belongs to the hierarchy of the virtual switch, the port m_VS reset signal will be set to 1; through the above logic operation, the port signal selection logic module can output the VS basic reset signals corresponding to all ports contained in the virtual switch hierarchy to be reset; the port corresponding VS basic reset signal, that is, the port n_VS basic reset signal, where the value range of n is 0 to 47; after the asynchronous reset is synchronously released through timing processing, it is sent to all corresponding ports in the virtual switch hierarchy, resetting all PCI-PCI bridges in the virtual switch hierarchy, realizing the comprehensive basic reset of the virtual switch, while other working virtual switches will not be affected; When the hot reset and secondary bus reset control module receives a hot reset request or a secondary bus reset request from an upstream port controller, the input control processing module determines according to the port register configuration information and routes the designated port hot reset signal to be output, and the output hot reset signal is sent to all downstream ports corresponding to the upstream port after passing through the output timing adjustment module; When the hot reset and secondary bus reset control module receives a hot reset request from an upstream port controller, the port will send a hot reset request signal to the reset control module and then reset the port itself; When the hot reset and secondary bus reset control module receives a secondary bus reset request from an upstream port controller, the port will send a secondary bus reset request signal to the reset control module. This process does not reset the upstream port itself.

2. A 48-channel 48-port PCIe5.0Switch reset architecture as claimed in claim 1, characterized in that: The PCIe 5.0 Switch reset architecture supports basic reset, hot reset, and secondary bus reset functions in the basic working mode and the Virtual Switch working mode.

3. A 48-channel 48-port PCIe5.0Switch reset architecture as claimed in claim 1, characterized in that: When the basic reset control module receives a full-chip power-on basic reset signal from outside the chip, the basic reset control module synchronizes the timing of the full-chip power-on basic reset signal with the timing of the port, and sends it to all 48 ports of the PCIe 5.0 Switch to perform a full-chip basic reset on all ports.

4. A 48-channel 48-port PCIe5.0Switch reset architecture as claimed in claim 1, characterized in that: Each of the virtual switches corresponds to a virtual basic reset signal VSx, where the value of x ranges from 0 to 5; and according to the configuration of the port register, each of the virtual switches also has a status signal VSx_pt [47:0] for indicating the port information, where the value of x ranges from 0 to 5; the signal width is 48 bits, which are used to indicate the status of 48 ports respectively, that is, when one of the bits is set to 1, it indicates that the port belongs to the virtual switch hierarchy.

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