Layout structure of integrated circuit standard cells

Abstract

The embodiment of the present disclosure relates to a layout structure of an integrated circuit standard cell, comprising: a first conductive type transistor group and a second conductive type transistor group arranged on a device layer; the first conductive type transistor group and the second conductive type transistor group are arranged along a first direction; a first input metal line and a first output metal line arranged on a first metal layer, the first input metal line and the first output metal line are electrically connected with the first conductive type transistor group and the second conductive type transistor group; the first input metal line is projected on the device layer between the first conductive type transistor group and the second conductive type transistor group; a second input metal line and a second output metal line arranged on a second metal layer, the second input metal line is electrically connected with the first input metal line, and the second output metal line is electrically connected with the first output metal line; the first metal layer is between the device layer and the second metal layer.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to the technical field of semiconductor technology, in particular to a layout structure of an integrated circuit standard cell. BACKGROUND

[0002] With the improvement of the integration of integrated circuits, the complexity of integrated circuits is also increasing. In order to improve the reliability of integrated circuit layout design and reduce the cost of layout design, a standard cell is introduced into the integrated circuit layout.

[0003] The standard cell itself has a logic function, and different standard cells can be composed of different gate circuits, so that different standard cells can have different logic functions after being electrically connected. These spare standard cells can be combined to form a new logic circuit to improve the circuit problem, thereby reducing the cost and cycle of layout design. Generally, the transistors in the standard cell realize the input and output of signals through the connection with the metal layer, and the connection mode between the transistors and the metal layer will affect the quality of signal transmission, and then affect the performance of the logic circuit composed of the standard cells.

[0004] However, the current connection mode between the standard cell and the metal layer is not good, which leads to poor performance of the logic circuit composed of the standard cells. SUMMARY

[0005] The embodiment of the present disclosure provides a layout structure of an integrated circuit standard cell, which at least has advantages of optimizing the connection mode between the standard cell and the metal layer and ensuring the good performance of the logic circuit composed of the standard cells.

[0006] The embodiment of the present disclosure provides a layout structure of an integrated circuit standard cell, which comprises: a first conductive type transistor group and a second conductive type transistor group arranged on a device layer; the first conductive type transistor group and the second conductive type transistor group are arranged along a first direction; a first input metal line and a first output metal line arranged on a first metal layer, the first input metal line and the first output metal line are electrically connected with the first conductive type transistor group and the second conductive type transistor group; the first input metal line is projected between the first conductive type transistor group and the second conductive type transistor group on the device layer; a second input metal line and a second output metal line arranged on a second metal layer, the second input metal line is electrically connected with the first input metal line, and the second output metal line is electrically connected with the first output metal line; the first metal layer is located between the device layer and the second metal layer.

[0007] In some embodiments, the first group of transistors includes a plurality of first transistors arranged along a second direction; the second group of transistors includes a plurality of second transistors arranged along the second direction; the first direction is orthogonal to the second direction.

[0008] In some embodiments, the device layer includes an active layer and a gate layer; source regions and drain regions of the plurality of first transistors are located in the active layer, and gates of the plurality of first transistors are located in the gate layer; gates of the plurality of first transistors are connected by first gate connection lines located in the gate layer; source regions and drain regions of the plurality of second transistors are located in the active layer, and gates of the plurality of second transistors are located in the gate layer; gates of the plurality of second transistors are connected by second gate connection lines located in the gate layer.

[0009] In some embodiments, the first input metal line includes a plurality of first input sub-metal lines extending along the first direction and spaced along the second direction, and a first input metal connection line extending along the second direction; one end of each of the first input sub-metal lines has a projection on the gate layer that overlaps the first gate connection line, and the other end of each of the first input sub-metal lines has a projection on the gate layer that overlaps the second gate connection line; the plurality of first input sub-metal lines are connected to the first gate connection line and the second gate connection line by a plurality of first vias.

[0010] In some embodiments, any two adjacent first transistors of the plurality of first transistors share a common drain region; any two adjacent second transistors of the plurality of second transistors share a common drain region.

[0011] In some embodiments, the first output metal line includes a plurality of first output sub-metal lines arranged one-to-one and electrically connected with the common drain regions in the first group of transistors, and a plurality of second output sub-metal lines arranged one-to-one and electrically connected with the common drain regions in the second group of transistors, each of the first output sub-metal lines and each of the second output sub-metal lines extending along the first direction, wherein the first output sub-metal line located at the outermost side of the plurality of first output sub-metal lines is denoted as an edge first output sub-metal line, and the second output sub-metal line located at the outermost side of the plurality of second output sub-metal lines is denoted as an edge second output sub-metal line; the first output metal line further includes a first output metal connection line extending along the second direction and connecting the plurality of first output sub-metal lines, a second output metal connection line extending along the second direction and connecting the plurality of second output sub-metal lines, and a third output sub-metal line extending along the first direction and connecting the edge first output sub-metal line and the edge second output sub-metal line.

[0012] In some embodiments, the first output metal connection line, the second output metal connection line, the third output sub-metal line, the edge first output sub-metal line and the edge second output sub-metal line encircle the first input metal line.

[0013] In some embodiments, the second input metal line includes a plurality of second input sub-metal lines arranged one-to-one corresponding to the plurality of first input sub-metal lines, the second input sub-metal line overlaps the first input sub-metal line in the projection of the first metal layer, and the second input sub-metal line is connected to the first input sub-metal line through a plurality of second vias.

[0014] In some embodiments, the second input metal line further includes a plurality of first parallel wires extending along the first direction, the first parallel wires are connected to the second input sub-metal line through a second input metal connection line extending along the second direction.

[0015] In some embodiments, the first parallel wire partially overlaps the first conductive type transistor group and the second conductive type transistor group in the projection of the device layer.

[0016] The technical scheme of the layout structure of the integrated circuit standard cell provided by the embodiments of the present disclosure has at least the following advantages:

[0017] In the technical scheme of the layout structure of the integrated circuit standard cell provided by the embodiments of the present disclosure, the first metal layer and the second metal layer are arranged, and the first metal layer is located between the device layer and the second metal layer. The first input metal line and the first output metal line arranged in the first metal layer are electrically connected to the first conductive type transistor group and the second conductive type transistor group, and are used to directly transmit the signals of the first conductive type transistor group and the second conductive type transistor group.

[0018] The second input metal line arranged in the second metal layer is electrically connected to the first input metal line, and the second output metal line is electrically connected to the first output metal line. Because the second metal layer is arranged, the second input metal line and the second output metal line can realize the input and output of the signals of the standard cell, that is, the second metal layer plays a role of communication between the standard cell and the outside. In this way, when the layout of the wires of the first metal layer is considered, the layout of the wires of the external power supply line does not need to be considered, so that the connection mode between the first metal layer and the first conductive type transistor group and the second conductive type transistor group can be increased, the layout flexibility of the first metal layer is improved, and then the connection mode between the first metal layer and the transistor can be optimized, and the excellent performance of the circuit is ensured.

[0019] And, the first input metal line is located between the first conductive type transistor group and the second conductive type transistor group in the orthographic projection of the device layer, that is, the first input metal line has a large orthographic projection area with the first conductive type transistor group and the second conductive type transistor group, so that the first input metal line can be designed to have more connection nodes with the first conductive type transistor group and the second conductive type transistor group, which is beneficial to reduce the connection impedance and improve the speed of the first input metal line input signal. BRIEF DESCRIPTION OF DRAWINGS

[0020] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, unless otherwise specified; in order to clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, a brief introduction will be given to the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0021] Figure 1 A schematic diagram of a first metal layer in a layout structure of an integrated circuit standard cell provided by an embodiment of the present disclosure is shown in the figure.

[0022] Figure 2 A schematic diagram of a second metal layer in a layout structure of an integrated circuit standard cell provided by an embodiment of the present disclosure is shown in the figure.

[0023] Figure 3 A schematic diagram of an active layer and a gate layer in a layout structure of an integrated circuit standard cell provided by an embodiment of the present disclosure is shown in the figure.

[0024] Figure 4 A schematic diagram of a first metal layer in another layout structure of an integrated circuit standard cell provided by an embodiment of the present disclosure is shown in the figure.

[0025] Figure 5 A schematic diagram of a second metal layer in another layout structure of an integrated circuit standard cell provided by an embodiment of the present disclosure is shown in the figure.

[0026] Figure 6 A schematic diagram of a layout structure of an integrated circuit standard cell provided by an embodiment of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0027] As can be known from the background art, the connection mode between the transistor and the metal layer of the current standard cell needs to be optimized, one of the reasons is that the current layout structure design of the integrated circuit standard cell is to adopt a single layer of metal layer structure, so that the metal layer is directly connected with the transistor and the power line. The setting of the metal layer not only needs to consider the position of the external power line, but also needs to consider the positional relationship among the gate, the source and the drain in the transistor group. Since the positional relationship among the gate, the source and the drain is fixed, in order to transmit the signals of the gate and the source through the metal layer, the position of the metal layer is also relatively fixed, so that the connection mode between the metal layer and the transistor is relatively single, which is easy to cause the problem of excessive connection impedance between the input metal layer and the transistor.

[0028] The layout structure of the standard cell provided by the embodiment of the present disclosure is provided. The second input metal line and the first input metal line are electrically connected, and the second output metal line and the first output metal line are electrically connected. Since the second metal layer is provided, the second input metal line and the second output metal line can realize the input and output of the signals of the standard cell, that is, the second metal layer plays a role of communication between the standard cell and the outside. In this way, when the wiring mode of the first metal layer is laid out, the wiring mode of the external power line does not need to be considered, so that the connection mode between the first metal layer and the first conductive type transistor group and the second conductive type transistor group can be increased, the layout flexibility of the first metal layer is improved, and then the connection mode between the first metal layer and the transistor can be optimized, and the excellent performance of the circuit is ensured. The first input metal line is located between the first conductive type transistor group and the second conductive type transistor group in the orthographic projection of the device layer, that is, the first input metal line has a large area of orthographic projection with the first conductive type transistor group and the second conductive type transistor group, so that the first input metal line can be designed with more connection nodes between the first conductive type transistor group and the second conductive type transistor, which is beneficial to reduce the connection impedance and improve the rate of the input signal of the first input metal line.

[0029] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0030] Figure 1 A schematic diagram of the first metal layer in the layout structure of the integrated cell standard cell is provided for an embodiment of the present disclosure; Figure 2 A schematic diagram of the second metal layer in the layout structure of the integrated cell standard cell is provided for an embodiment of the present disclosure.

[0031] Reference Figure 1 andFigure 2 The layout structure of the integrated circuit standard cell comprises: a first conductive type transistor group 101 and a second conductive type transistor group 102 arranged on a device layer, the first conductive type transistor group 101 and the second conductive type transistor group 102 are arranged at intervals along a first direction X. The layout structure of the integrated circuit standard cell further comprises: a first input metal line 103 and a first output metal line 104 arranged on a first metal layer, the first input metal line 103 and the first output metal line 104 are electrically connected with the first conductive type transistor group 101 and the second conductive type transistor group 102. The first input metal line 103 is projected on the device layer between the first conductive type transistor group 101 and the second conductive type transistor group 102. The layout structure of the integrated circuit standard cell further comprises: a second input metal line 105 and a second output metal line 106 arranged on a second metal layer, the second input metal line 105 is electrically connected with the first input metal line 103, and the second output metal line 106 is electrically connected with the first output metal line 104; the first metal layer is located between the device layer and the second metal layer.

[0032] In some embodiments, the integrated circuit can include various types of memories, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), or SDRAM (Synchronous Dynamic Random-Access Memory).

[0033] The standard cell itself has a logic function, the input end of the standard cell can be used to input an external signal into the standard cell, and the output end of the standard cell can be used to output a signal generated by the standard cell to the outside. In the actual design process of the integrated circuit, after the design is completed and verified, it may be found that there are problems in the circuit, such as the problem that the function of the integrated circuit does not meet the expected function. Therefore, it is necessary to modify the integrated circuit, and specifically, the standby standard cell pre-set in the standard cell layout can be used to compose a new logic circuit that meets the required logic function.

[0034] The first metal layer is used to lead out signals of the first conductive type transistor group 101 and the second conductive type transistor group 102 or input external signals to the first conductive type transistor group 101 and the second conductive type transistor group 102. The external signals can be input to the first conductive type transistor group 101 and the second conductive type transistor group 102 via the first input metal line 103, and the signals generated by the first conductive type transistor group 101 and the second conductive type transistor group 102 can be transmitted to external circuits via the first output metal line 104. The first input metal line 103 and the first output metal line 104 are independently arranged from each other, so that the electrical signals transmitted in the first input metal line 103 and the first output metal line 104 do not interfere with each other, thereby ensuring the integrity of the signals.

[0035] Reference Figure 1 In some embodiments, the first conductive type transistor group 101 includes a plurality of first transistors arranged along a second direction Y, and the second conductive type transistor group 102 includes a plurality of second transistors arranged along the second direction Y. The first direction X is orthogonal to the second direction Y, and in some embodiments, the first direction X is perpendicular to the second direction Y.

[0036] In some embodiments, the first conductive type transistor group 101 can include a plurality of first transistors connected in parallel, which can be equivalent to an equivalent first transistor, and the second conductive type transistor group 102 can include a plurality of second transistors connected in parallel, which can be equivalent to an equivalent second transistor.

[0037] In some embodiments, the first conductive type and the second conductive type can be different. For example, the first conductive type can be one of P-type or N-type, and the equivalent first transistor formed is one of a P-type transistor or an N-type transistor. The second conductive type can be the other of P-type or N-type, and the equivalent second transistor formed is the other of a P-type transistor or an N-type transistor.

[0038] Alternatively, in some embodiments, the first conductive type and the second conductive type can be the same. For example, the first conductive type can be P-type, and the equivalent first transistor formed is a P-type transistor. The second conductive type can also be P-type, and the equivalent second transistor formed is a P-type transistor. The first conductive type can also be N-type, and the equivalent first transistor formed is an N-type transistor. The second conductive type can also be N-type, and the equivalent second transistor formed is an N-type transistor. In this way, the standard cell formed can be an inverter.

[0039] The embodiments of the present application do not limit the specific types of the equivalent first transistor and the equivalent second transistor, different transistor combinations form different gate circuits, and thus different standard cells can have different logic functions.

[0040] In some embodiments, the source of the first transistor and the second transistor inputs a data signal (which can be a power voltage signal VDD or a ground signal VSS), and the gate of the first transistor and the second transistor receives a driving signal. The driving signal is transmitted to the gate of the first transistor and the second transistor via the first input metal line 103. The first transistor and the second transistor are turned on based on the driving signal, so that the data signal of the source of the first transistor and the second transistor is transmitted to the drain, and the data signal is transmitted to the first output metal line 104 through the drain, and then transmitted to the external circuit by the first output metal line 104.

[0041] Reference Figure 3 In some embodiments, the device layer includes an active layer and a gate layer; the source region and the drain region of the plurality of first transistors are located in the active layer, and the gate is located in the gate layer; the gates of the plurality of first transistors are connected by the first gate connection line 19 located in the gate layer; the source region and the drain region of the plurality of second transistors are located in the active layer, and the gate is located in the gate layer; the gates of the plurality of second transistors are connected by the second gate connection line 20 located in the gate layer. That is, the first gate connection line 19 electrically connects the gates of the plurality of first transistors, so that the plurality of first transistors are connected in parallel to form an equivalent first transistor. The second gate connection line 20 connects the plurality of second transistors in parallel, so that the plurality of second transistors are connected in parallel to form an equivalent second transistor.

[0042] In some embodiments, the active layer includes a first sub-active layer 11 and a second sub-active layer 12, the first sub-active layer 11 is used to form the plurality of first transistors, and the second sub-active layer 12 is used to form the plurality of second transistors. The gate layer includes a first sub-gate layer 17 and a second sub-gate layer 18, the first sub-gate layer 17 is used to form the gate of the first transistor, and the second sub-gate layer 18 is used to form the gate of the second transistor.

[0043] In some embodiments, the first sub-active layer 11 includes a first source region 13, a first drain region 14, and a first channel region, and the second sub-active layer 12 includes a second source region 15, a second drain region 16, and a second channel region. In some embodiments, the number of the first source region 13 and the first drain region 14 can be multiple, and the number of the first sub-gate layer 17 can be multiple, and each of the multiple first sub-gate layers 17 has a projection on the first sub-active layer 11 that coincides with the first channel region. In some embodiments, the number of the second source region 15 and the second drain region 16 can be multiple, and the number of the second sub-gate layer 18 can be multiple, and each of the multiple second sub-gate layers 18 has a projection on the second sub-active layer 12 that coincides with the second channel region. One first source region 13, one first drain region 14, and one first channel region can be used to form one first transistor, and one second source region 15, one second drain region 16, and one second channel region can be used to form one second transistor.

[0044] In some embodiments, the first sub-active layer 11, the second sub-active layer 12, the first sub-gate layer 17, and the second sub-gate layer 18 extend along the first direction X, the first sub-active layer 11 and the second sub-active layer 12 are arranged at intervals along the second direction Y, and the first sub-gate layer 17 and the second sub-gate layer 18 are arranged at intervals along the second direction Y. The first gate connection line 19 and the second gate connection line 20 extend along the second direction Y. The first gate connection line 19 connects the end of each of the first sub-gate layers 17 facing the second sub-gate layer 18, and the second gate connection line 20 connects the end of each of the second sub-gate layers 18 facing the first sub-gate layer 17.

[0045] The first input metal line 103 is electrically connected to the first sub-gate layer 17 and the second sub-gate layer 18, and the first output metal line 104 is electrically connected to the first drain region 14 and the second drain region 16.

[0046] Reference Figure 1 , Figure 3 and Figure 4 In some embodiments, the first input metal line 103 includes a plurality of first input sub-metal lines 111 extending along the first direction X and arranged at intervals along the second direction Y, and a first input metal connection line 112 extending along the second direction Y. One end of each of the plurality of first input sub-metal lines 111 overlaps the first gate connection line 19 in the projection of the gate layer, and the other end overlaps the second gate connection line 20 in the projection of the gate layer. The plurality of first input sub-metal lines 111 are connected to the first gate connection line 19 and the second gate connection line 20 through a plurality of first vias 21.

[0047] In some embodiments, the first via 21 coincides with the intersection of the first input sub-metal line 111 and the first gate connecting line 19 in the orthographic projection of the first gate layer, and the first via 21 coincides with the intersection of the first input sub-metal line 111 and the second gate connecting line 20 in the orthographic projection of the second gate layer. In some embodiments, the first via 21 penetrates the first gate layer and the second input sub-metal line, and the material of the first via 21 can be a conductive material, for example, can be a metal, specifically any one of copper, nickel, tin or tungsten.

[0048] Each of the plurality of first input sub-metal lines 111 is electrically connected to the first gate through the first via 21, and each of the plurality of second input sub-metal lines is electrically connected to the second gate through the first via 21, so that the number of connection nodes between the first input sub-metal line 111 and the first gate is increased, and the number of connection nodes between the second input sub-metal line and the second gate is increased. In this way, the connection impedance between the first input sub-metal line 111 and the first gate can be reduced, the connection impedance between the second input sub-metal line and the second gate can be reduced, and the transmission performance of the first input metal line 103 to the signal can be improved.

[0049] In some embodiments, the number of the plurality of first input sub-metal lines 111 is greater than or equal to 3, for example, can be 3, 4 or 5, etc. In some embodiments, the first input metal connecting line 112 spans the plurality of first input sub-metal lines 111, and the orthographic projection of the first input metal connecting line 112 on the device layer has an overlapping portion with the plurality of first input sub-metal lines 111. The first input metal connecting line 112 is connected to the plurality of first input metal lines 103, so that the second input metal line 105 is arranged to input the external signal to the first input metal connecting line 112, and then the external signal is transmitted from the first input metal connecting line 112 to the plurality of first input sub-metal lines 111, that is, the plurality of first input sub-metal lines 111 can input the external signal to the first conductive type transistor group 101, which greatly reduces the complexity of the layout of the circuit.

[0050] In some embodiments, any two adjacent first transistors in the plurality of first transistors share a common drain region, and any two adjacent second transistors in the plurality of second transistors share a common drain region. In some embodiments, any two adjacent first transistors in the plurality of first transistors share a common source region, and any two adjacent second transistors in the plurality of second transistors share a common source region. In this way, the area occupied by the device layer can be reduced.

[0051] For a more complete understanding of the present application, reference is made to the following description taken in conjunction with the accompanying drawings. Figure 3The first drain region 14 and the first source region 13 are located on both sides of the first channel region in the first sub-active layer 11, and there is one first drain region 14 or one first source region 13 between two adjacent first channel regions. That is, in the first sub-active layer 11, the arrangement of the first drain region 14, the first source region 13 and the first channel region is: first source region 13, first channel region, first drain region 14, first channel region, first source region 13, and so on in turn.

[0052] With reference to Figure 1 , Figure 3 and Figure 4 In some embodiments, the first output metal line 104 includes a plurality of first output sub-metal lines 121 arranged and electrically connected one by one with the common drain regions in the first conductive type transistor group 101, a plurality of second output sub-metal lines 122 arranged and electrically connected one by one with the common drain regions in the second conductive type transistor group 102, each first output sub-metal line 121 and each second output sub-metal line 122 extend along the first direction X, wherein the outermost first output sub-metal line 121 in the plurality of first output sub-metal lines 121 is denoted as an edge first output sub-metal line, and the outermost second output sub-metal line 122 in the plurality of second output sub-metal lines 122 is denoted as an edge second output sub-metal line; the first output metal line 104 further includes a first output metal connecting line 124 extending along the second direction Y and connecting the plurality of first output sub-metal lines 121, a second output metal connecting line 125 extending along the second direction Y and connecting the plurality of second output sub-metal lines 122, and a third output sub-metal line 123 extending along the first direction X and used for connecting the edge first output sub-metal line and the edge second output sub-metal line.

[0053] In some embodiments, the first output sub-metal line 121 is in alignment with a common drain region in the first conductive type transistor group 101 in a projection on the active layer, i.e. the first output sub-metal line 121 is in alignment with the first drain region 14 in a projection on the first sub-active layer 11. The second output sub-metal line 122 is in alignment with a common drain region in the second conductive type transistor group 102 in a projection on the active layer, i.e. the second output sub-metal line 122 is in alignment with the second drain region 16 in a projection on the second sub-active layer 12. In some embodiments, the first output sub-metal line 121 and the first drain region 14 can be electrically connected by a first conductive contact plug, and the second output sub-metal line 122 and the second drain region 16 can be electrically connected by a second conductive contact plug. In some embodiments, the first conductive contact plug can be made of a metal material, such as any one of copper, nickel, tin or tungsten. In some embodiments, the second conductive contact plug can be made of a metal material, such as any one of copper, nickel, tin or tungsten.

[0054] In some embodiments, the gap between each first input sub-metal line 111 and the adjacent first output sub-metal line 121 is directly opposite, such that the first input sub-metal lines 111 and the first output sub-metal lines 121 are staggered, so as to avoid the problem of signal disturbance caused by contact between the first input sub-metal lines 111 and the first output sub-metal lines 121.

[0055] The first output metal connection line 124 connects the ends of all the first output sub-metal lines 121 away from the second output sub-metal lines 122, so as to electrically connect the plurality of first output sub-metal lines 121 to each other, and the second output metal connection line 125 connects the ends of all the second output sub-metal lines 122 away from the first output sub-metal lines 121, so as to electrically connect the plurality of second output sub-metal lines 122 to each other. In this way, the signal of any one of the plurality of first transistors can be output through any one of the first output sub-metal lines 121, and the signal of any one of the plurality of second transistors can be output through any one of the second output sub-metal lines 122, so as to simplify the circuit design by eliminating the need for the second output metal line 106 to be electrically connected to each first output sub-metal line 121 and each second output sub-metal line 122.

[0056] It can be found that the first output metal connection line 124 is located on the side of the first sub-active layer 11 away from the first input metal connection line 112, and the second output metal connection line 125 is located on the side of the second sub-active layer 12 away from the first input metal connection line 112, so as to increase the distance between the first output metal connection line 124, the second output metal connection line 125 and the first input metal connection line 112, and facilitate avoiding the problem of transmission disturbance between the input signal and the output signal.

[0057] The number of edge first output sub-metal lines is two, which are respectively located at the outermost of the plurality of first output sub-metal lines 121. The number of edge second output sub-metal lines is two, which are respectively located at the outermost of the plurality of second output sub-metal lines 122.

[0058] The number of third output sub-metal lines 123 is two, and the two third output sub-metal lines 123 extend along the second direction Y. Each third output sub-metal line 123 connects an edge first output sub-metal line and an edge second output sub-metal line. The connection line of the edge first output sub-metal line, the third output sub-metal line 123, and the edge second output sub-metal line is in a straight line and extends along the second direction Y.

[0059] In some embodiments, the first output metal connection line 124, the second output metal connection line 125, the third output sub-metal line 123, the edge first output sub-metal line, and the edge second output sub-metal line surround the first input metal line 103. That is, the first input metal line 103 is located at the center of the region between the first conductive type transistor group 101 and the second conductive type transistor group 102. Therefore, the first input metal line 103 has a large area opposite to the first conductive type transistor group 101 and the second conductive type transistor group 102, thereby being able to form more connection nodes, reduce the connection impedance between the first input metal line 103 and the first conductive type transistor group 101 and the second conductive type transistor group 102, and improve the transmission performance of the first input metal line 103 to the input signal.

[0060] In some embodiments, the first input metal line 103 is electrically connected to the first conductive type transistor group 101 and the second conductive type transistor group 102 through the first via 21. Since the first input metal line 103 is located at the center of the region between the first conductive type transistor group 101 and the second conductive type transistor group 102, compared with the case that the first input metal line 103 is located at the edge of the region between the first conductive type transistor group 101 and the second conductive type transistor group 102, more first vias 21 can be used to electrically connect the first input metal line 103 to the first conductive type transistor group 101 and the second conductive type transistor group 102, thereby reducing the connection impedance and improving the transmission rate of the first input metal line 103 to the input signal.

[0061] In some embodiments, the second metal layer is configured to form different connections between the plurality of device layers to constitute different logic circuits. It can be understood that when the circuit needs to be upgraded, different device layers need to be combined, and the second metal layer can be changed to form electrical connections between different device layers through the second input metal line 105 and the second output metal line 106, so as to combine different logic circuits. Figure 6 A schematic diagram after the first metal layer and the second metal layer are stacked is shown.

[0062] Reference Figure 2 , Figure 3 and Figure 5 In some embodiments, the second input metal line 105 includes a plurality of second input sub-metal lines 131 corresponding to the plurality of first input sub-metal lines 111 one by one. The second input sub-metal line 131 overlaps the first input sub-metal line 111 in the projection of the first metal layer, and the second input sub-metal line 131 is connected to the first input sub-metal line 111 through the plurality of second vias 22. The second input sub-metal line 131 can be electrically connected to an external circuit or an external element, receive an external signal generated by the external circuit or the external element, and transmit the external signal to the first input sub-metal line 111 overlapping the second input sub-metal line 131. The first input sub-metal line 111 transmits the external signal to the first conductive type transistor group 101 and the second conductive type transistor group 102.

[0063] The number of first input sub-metal lines 111 is equal to the number of second input sub-metal lines 131, so that one second input sub-metal line 131 and one first input sub-metal line 111 are electrically connected one by one through the second via 22. In this way, the rate of transmitting the external signal from the second input sub-metal line 131 to the first input sub-metal line 111 can be improved. In some embodiments, the number of first input sub-metal lines 111 is a plurality, so that the electrical signal can be transmitted to the first conductive type transistor group 101 and the second conductive type transistor group 102 through the plurality of first input sub-metal lines 111, and the electrical transmission performance of the first input sub-metal line 111 is enhanced. In some embodiments, the second via 22 penetrates the first input sub-metal line 111 and the second input sub-metal line 131. The material of the second via 22 can be a conductive material, for example, can be metal, specifically any one of copper, nickel, tin, or tungsten.

[0064] In some embodiments, the second input metal line 105 further comprises a plurality of first parallel wires 132 extending along the first direction X, and the first parallel wires 132 are connected to the second input sub-metal lines 131 through second input metal connecting lines 133 extending along the second direction Y. In some embodiments, the first parallel wires 132 serve to transmit external signals to the second input sub-metal lines 131. This is because, since the second input sub-metal lines 131 overlap the first input sub-metal lines 111, and the first input sub-metal lines 111 are located at the center of the region between the first conductive type transistor group 101 and the second conductive type transistor group 102, the second input sub-metal lines 131 are also located at the center of the region between the first conductive type transistor group 101 and the second conductive type transistor group 102. If the second input sub-metal lines 131 need to receive external signals, the first parallel wires 132 are also needed to transmit the external signals to the second input sub-metal lines 131.

[0065] In some embodiments, the number of the second input sub-metal lines 131 is a plurality, for example, 3 or more, and the two outermost second input sub-metal lines 131 are referred to as edge second input sub-metal lines 131, and the rest are referred to as center second input sub-metal lines 131. The number of the first parallel wires 132 can be 2, and the two first parallel wires 132 are respectively located on the side of the edge second input sub-metal lines 131 away from the center second input sub-metal lines 131, and are respectively adjacent to the edge second input sub-metal lines 131.

[0066] In some embodiments, the number of the second input metal connecting lines 133 is 2, and the two second input metal connecting lines 133 are respectively connected to one edge second input sub-metal line 131 and one first parallel wire 132. In this way, the first parallel wires 132 transmit external signals to the edge second input sub-metal lines 131. Since the second input sub-metal lines 131 are electrically connected to the first input sub-metal lines 111 through the second via 22, and the first input sub-metal lines 111 are electrically connected to the first gate connecting line 19 and the second gate connecting line 20 through the first via 21, the edge second input metal line 105 further transmits external signals to the first gate connecting line 19 and the second gate connecting line 20, and then transmits the external signals to the center second input sub-metal lines 131 through the first gate connecting line 19 and the second gate connecting line 20, so that the center second input sub-metal lines 131 transmit the external signals to the corresponding first transistors. Since a plurality of second input sub-metal lines 131 and first input sub-metal lines 111 are provided, the transmission path of the external signals is increased, thereby improving the transmission rate of the external signals.

[0067] In some embodiments, the first parallel wire 132 partially overlaps the first conductive type transistor group 101 and the second conductive type transistor group 102 in the projection of the device layer. That is, the first parallel wire 132 is arranged in stack with the first conductive type transistor group 101 and the second conductive type transistor group 102, so that the first parallel wire 132 occupies a smaller area in the layout structure of the standard cell, avoiding further increasing the area of the standard cell.

[0068] In some embodiments, the plurality of first output sub-metal lines 121 are electrically connected by the first output metal connection line 124, and the plurality of second output sub-metal lines 122 are electrically connected by the second output metal connection line 125. That is, the plurality of first output sub-metal lines 121 are in communication with each other, and the plurality of second output sub-metal lines 122 are in communication with each other. In this way, any first transistor in the first conductive type transistor group 101 can output a signal through any first output sub-metal line 121, and any second transistor in the second conductive type transistor group 102 can output a signal through any second output sub-metal line 122. Based on this, in some embodiments, the second output metal line 106 does not need to be electrically connected to each first output sub-metal line 121 and each second output sub-metal line 122, thereby being able to save the number of second output metal lines 106.

[0069] In some embodiments, the first parallel wire 132 can also be arranged to overlap the edge first output sub-metal line and the edge second output sub-metal line in the orthographic projection of the first metal layer. In this way, the standard cell can have a smaller size without affecting the output of the first output metal line 104 to the signal. Specifically, each first parallel wire 132 extends in the first direction X, and the projection of each first parallel wire 132 in the first metal layer overlaps an edge first output sub-metal line, a third output sub-metal line 123, and an edge second output sub-metal line 122 in turn.

[0070] In some embodiments, among the plurality of first output sub-metal lines 121, the edge first output sub-metal line is referred to as a center first output sub-metal line; among the plurality of second output sub-metal lines 122, the edge second output sub-metal line is referred to as a center second output sub-metal line, the second output metal line 106 extends in the first direction X, the projection of the second output metal line 106 in the first metal layer respectively overlaps the center first output sub-metal line and the center second output sub-metal line one by one, and the second output metal line 106 is connected to the center first output sub-metal line and the center second output sub-metal line through the third via hole 23.

[0071] As can be seen from the above analysis, since the plurality of first output sub-metal lines 121 are in communication with each other and the plurality of second output sub-metal lines 122 are in communication with each other, the second output metal line 106 does not need to be electrically connected to each of the first output sub-metal lines 121 and each of the second output sub-metal lines 122, thereby saving the number of second output metal lines 106. Based on this, the second output metal line 106 is arranged to correspond to only the center first output sub-metal line and the center second output sub-metal line, which can greatly save the number of second output metal lines 106, thereby facilitating reduction of the complexity of the wiring.

[0072] In some embodiments, the second output metal line 106 extends along the first direction X and across the region between the first type transistor group and the second type transistor group, and a normal projection of the second output metal line 106 on the first metal layer overlaps with a center first output sub-metal line and a center second output sub-metal line that are directly opposite in the first direction X. That is, the first output sub-metal line 121 and the second output sub-metal line 122 that are directly opposite in the first direction X share the same second output metal line 106.

[0073] In some embodiments, the second output metal line 106 and the second input sub-metal line 131 are arranged alternately between the first type transistor group and the second type transistor group, which on the one hand reasonably plans the wiring between the second output metal line 106 and the second input sub-metal line 131, preventing the signals transmitted by the second output metal line 106 and the second input sub-metal line 131 from interfering with each other. On the other hand, the space is utilized to a greater extent, ensuring that the standard cell size is small.

[0074] Reference Figure 4 and Figure 5 In some embodiments, the layout structure of the integrated circuit standard cell further includes: a plurality of first source electrode lines 141 and a plurality of second source electrode lines 142 on the first metal layer, the first source electrode lines 141 and the second source electrode lines 142 both extend along the first direction X; the plurality of first source electrode lines 141 are arranged one-to-one corresponding to the source regions of the plurality of first transistors, and the plurality of second source electrode lines 142 are arranged one-to-one corresponding to the source regions of the plurality of second transistors; a first power transfer line 143 and a second power transfer line 144 on the second metal layer, the first power transfer line 143 extends along the first direction X, and a projection of the first power transfer line 143 on the first metal layer at least partially overlaps with the first source electrode lines 141 and is connected to the first source electrode lines 141 through fourth vias 24; the second power transfer line 144 extends along the first direction X, and a projection of the first power transfer line 143 on the first metal layer at least partially overlaps with the second source electrode lines 142 and is connected to the second source electrode lines 142 through fifth vias 25.

[0075] In some embodiments, the first source electrode line 141 is in alignment with the first source region 13 in the orthogonal projection on the active layer, and the second source electrode line 142 is in alignment with the second source region 15 in the orthogonal projection on the active layer. The first source electrode line 141 is electrically connected with the first source region 13 for transmitting a data signal to the first source region 13, and the second source electrode line 142 is electrically connected with the second source region 15 for transmitting a data signal to the second source region 15. In some embodiments, the first source electrode line 141 can be electrically connected with a power voltage signal VDD or a ground terminal signal VSS, and the second source electrode line 142 can be electrically connected with the power voltage signal VDD or the ground terminal signal VSS.

[0076] Reference Figure 4 In some embodiments, the first source electrode line 141 is electrically connected with the first source region 13 through a third conductive contact plug 31, and the second source electrode line 142 is electrically connected with the second source region 15 through a fourth conductive contact plug 32. In some embodiments, the material of the third conductive contact plug 31 can be a metal material, such as any one of copper, nickel, tin or tungsten. In some embodiments, the material of the fourth conductive contact plug 32 can be a metal material, such as any one of copper, nickel, tin or tungsten.

[0077] The first power transfer line 143 is in alignment with the first source electrode line 141 in the orthogonal projection on the first metal layer, and the first power transfer line 143 further extends out of the first sub-active layer 11. The second power transfer line 144 is in alignment with the second source electrode line 142 in the orthogonal projection on the first metal layer, and the second power transfer line 144 further extends out of the second sub-active layer 12. The first power transfer line 143 is used for receiving an external data signal and transmitting the data signal to the first source electrode line 141, and the second power transfer line 144 is used for receiving an external data signal and transmitting the data signal to the second source electrode line 142.

[0078] The first power transfer line 143 and the second output metal line 106 are arranged alternately in the second direction Y, and the second power transfer line 144 and the second output metal line 106 are arranged alternately in the second direction Y. In some embodiments, a second input sub-metal line 131 is opposite to the first power transfer line 143 in the first direction X, and a second input sub-metal line 131 is opposite to the second power transfer line 144 in the first direction X. In this way, different metal lines transmit different signals without interfering with each other, and the routing in this way does not occupy a large area, so that the area of the standard cell is not too large.

[0079] In some embodiments, the layout structure of the standard cell further includes a first power supply line (not shown) and a second power supply line (not shown) on the third metal layer, both extending along the second direction Y; the first power supply line is connected with the first power supply jumper 143 through a sixth via (not shown), and the second power supply line is connected with the second power supply jumper 144 through a seventh via (not shown). In some embodiments, the first power supply line can be a power supply voltage or a ground terminal, and the second power supply line can be a power supply voltage or a ground terminal. The third metal layer is located on the side of the second metal layer away from the first metal layer. In some embodiments, the first power supply line is overlapped with part of the first conductive type transistor group 101 in the orthographic projection of the device layer, and the second power supply line is overlapped with part of the second conductive type transistor group 102 in the orthographic projection of the device layer.

[0080] Reference Figure 6 In some embodiments, the layout structure of the standard cell further includes a first well region 151 and a second well region 152 on the device layer, both extending along the second direction Y; the first well region 151 and the second well region 152 are located at the edge of the standard cell. Specifically, the first well region 151 is located on the side of the first conductive type transistor group 101 away from the second conductive type transistor group 102, and the second well region 152 is located on the side of the second conductive type transistor group 102 away from the first conductive type transistor group 101. In other words, the first well region 151 and the second well region 152 are respectively located on the opposite sides of the active layer in the first direction X.

[0081] In some embodiments, the doping ion type of the first well region 151 is different from the first conductive type, i.e., the doping ion type of the first well region 151 is different from the doping ion type of the first transistor. The doping ion type of the second well region 152 is different from the second conductive type, i.e., the doping ion type of the second well region 152 is different from the doping ion type of the second transistor. In this way, the first well region 151 can prevent the leakage current of the first transistor from being transmitted to the first well region 151, and the second well region 152 can prevent the leakage current of the second transistor from being transmitted to the outside of the second well region 152. That is, the first well region 151 and the second well region 152 play a role in preventing the outward leakage of the first transistor and the second transistor, thereby avoiding the problem that the leakage current has a bad influence on the performance of external elements outside the first well region 151 and the second well region 152.

[0082] In some embodiments, the first power supply jumper 143 further extends to the first well region 151 and is electrically connected with the first well region 151 through an eighth via 26, and the second power supply jumper 144 further extends to the second well region 152 and is electrically connected with the second well region 152 through a ninth via 27.

[0083] In the layout structure of the integrated circuit standard cell provided by the above embodiment, the second metal layer is arranged to play a role of communication between the standard cell and the outside. In this way, when the wire mode of the first metal layer is laid out, the wire mode of the external power supply line does not need to be considered, so that the connection mode between the first metal layer and the first conductive type transistor group 101 and the second conductive type transistor group 102 can be increased, the layout flexibility of the first metal layer is improved, and then the connection mode between the first metal layer and the transistor can be optimized, and the excellent performance of the circuit is ensured.

[0084] An embodiment of the present disclosure further provides a semiconductor memory comprising the layout structure of the integrated circuit standard cell as described above.

[0085] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A layout structure of an integrated circuit standard cell, characterized in that: include: A first conductivity type transistor group and a second conductivity type transistor group are provided in the device layer; The first conductive type transistor group and the second conductive type transistor group are arranged spaced apart along a first direction; a first input metal line and a first output metal line provided in the first metal layer, the first input metal line and the first output metal line being electrically connected to the first conductivity type transistor group and the second conductivity type transistor group; an orthographic projection of the first input metal line on the device layer being located between the first conductivity type transistor group and the second conductivity type transistor group; a second input metal line and a second output metal line provided in the second metal layer, the second input metal line being electrically connected to the first input metal line, and the second output metal line being electrically connected to the first output metal line; The first metal layer is located between the device layer and the second metal layer; The first conductive type transistor group includes a plurality of first transistors arranged along the second direction; The second conductive type transistor group includes a plurality of second transistors arranged along a second direction; The first direction is orthogonal to the second direction; The device layer includes an active layer and a gate layer; The source regions and drain regions of the plurality of first transistors are located in the active layer, and the gates are located in the gate layer; The gates of the plurality of first transistors are connected via a first gate connection line located in the gate layer; The source regions and drain regions of the plurality of second transistors are located in the active layer, and the gates are located in the gate layer; the gates of the plurality of second transistors are connected via a second gate connection line located in the gate layer; The first input metal line includes a plurality of first input sub-metal lines extending along the first direction and spaced apart along the second direction, and a first input metal connection line extending along the second direction; One end of each of the first input sub-metal lines has its projection on the gate layer overlapped with the first gate connection line, and the other end has its projection on the gate layer overlapped with the second gate connection line; The plurality of first input sub-metal lines are connected to the first gate connection line and the second gate connection line through a plurality of first vias.

2. The layout structure of the integrated circuit standard cell according to claim 1, characterized in that: Any adjacent two of the plurality of first transistors share a common drain region; any adjacent two of the plurality of second transistors share a common drain region.

3. The layout structure of the integrated circuit standard cell according to claim 2, characterized in that: The first output metal line includes a plurality of first output sub-metal lines arranged in one-to-one correspondence with and electrically connected to the common drain region of the first conductive type transistor group, and a plurality of second output sub-metal lines arranged in one-to-one correspondence with and electrically connected to the common drain region of the second conductive type transistor group, each of the first output sub-metal lines and each of the second output sub-metal lines extending along the first direction, wherein the outermost first output sub-metal line among the plurality of first output sub-metal lines is recorded as an edge first output sub-metal line, and the outermost second output sub-metal line among the plurality of second output sub-metal lines is recorded as an edge second output sub-metal line; The first output metal line also includes a first output metal connecting line extending along the second direction and connecting the multiple first output sub-metal lines, a second output metal connecting line extending along the second direction and connecting the multiple second output sub-metal lines, and a third output sub-metal line extending along the first direction and used to connect the edge first output sub-metal line and the edge second output sub-metal line.

4. The layout structure of the integrated circuit standard cell according to claim 3, characterized in that: The first output metal connection line, the second output metal connection line, the third output sub-metal line, the edge first output sub-metal line, and the edge second output sub-metal line surround the first input metal line.

5. The layout structure of the integrated circuit standard cell according to claim 4, characterized in that: The second input metal line includes a plurality of second input sub-metal lines arranged in one-to-one correspondence with the plurality of first input sub-metal lines, the projection of the second input sub-metal line on the first metal layer overlaps with the first input sub-metal line, and the second input sub-metal line is connected to the first input sub-metal line through a plurality of second vias.

6. The layout structure of the integrated circuit standard cell according to claim 5, characterized in that: The second input metal line further includes a plurality of first parallel running lines extending along the first direction, and the first parallel running lines are connected to the second input sub-metal line through a second input metal connection line extending along the second direction.

7. The layout structure of the integrated circuit standard cell according to claim 6, characterized in that: The projection of the first parallel running line on the device layer partially overlaps with the first conductive type transistor group and the second conductive type transistor group.

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