ADC clock mismatch calibration method and device based on ramp signal and N-channel time-interleaved ADC

Abstract

The present invention provides a ramp-signal-based ADC clock mismatch calibration method and device, as well as an N-channel time-interleaved ADC. The method comprises: sampling a first ramp signal output by a ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result; sampling a second ramp signal output by the ramp signal generating circuit through an ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal; and adjusting the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated. The present invention uses sampled data as a calibration standard, and the calibration result can accurately measure the sampled data. The calibration logic is simple, the structural complexity is low, and the convergence speed is fast, effectively reducing hardware overhead and power consumption. Furthermore, the ramp signal requirements are low, avoiding non-ideal factors introduced by low linearity in the signal link.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a ramp signal-based ADC clock mismatch calibration method and device, and an N-channel time-interleaved ADC. Background Art

[0002] The analog-to-digital converter (ADC) is the bridge connecting analog and digital. With the continuous development of technology, the data transmission rate continues to increase, which also puts higher requirements on the ADC's operating speed. The use of multi-channel ADC interleaved sampling has become an effective way to improve the ADC's operating speed.

[0003] Although time-interleaved ADCs effectively increase the operating speed, they also introduce many non-ideal factors. Among them, the mismatch of multi-phase clocks causes the sampling points of each channel to deviate from the ideal position, becoming one of the key factors affecting ADC performance.

[0004] The methods currently used to calibrate multi-phase clock mismatches in time-interleaved ADCs include: first, direct detection and calibration of the multi-phase clocks. This method only calibrates the clocks and does not consider the errors introduced by the sampling circuits; second, relying on an additional calibration channel to calibrate multiple channels by comparing sampling results; this method requires additional clocks and sampling channels, resulting in high hardware and power consumption overhead; and third, relying on specific input signals. This method often involves link nonlinearity that significantly impacts the calibration results, resulting in long calibration times and complex calibration logic. Summary of the Invention

[0005] The present invention provides a ramp signal-based ADC clock mismatch calibration method and device, and an N-channel time-interleaved ADC, to address the defects of the prior art of directly calibrating the clock, introducing additional calibration channels, or relying on specific input signals, which result in large calibration errors, long calibration time, complex calibration logic, and high hardware and power consumption.

[0006] The present invention provides an ADC clock mismatch calibration method based on a ramp signal, which is used for an N-channel time-interleaved ADC. The N-channel time-interleaved ADC includes a ramp signal generating circuit and N ADC channels with the same structure connected in parallel. The N ADC channels with the same structure include a preset reference ADC channel and N-1 ADC channels to be calibrated, where N is greater than or equal to 2.

[0007] The method comprises:

[0008] Sampling the first ramp signal output by the ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result;

[0009] Sampling a second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal;

[0010] The ADC channel to be calibrated is adjusted so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated.

[0011] According to the ADC clock mismatch calibration method based on a ramp signal provided by the present invention, the N-channel time-interleaved ADC also includes a trigger clock, which is used to trigger the ramp signal generating circuit through each rising edge to generate a second ramp signal with the same signal shape as the first ramp signal.

[0012] According to the ADC clock mismatch calibration method based on the ramp signal provided by the present invention, a digitally controlled variable delay line is provided in the ramp signal generating circuit and each of the ADC channels;

[0013] The digitally controlled variable delay line is used to control the sampling result of the reference ADC channel by adjusting the delay between the first ramp signal and the trigger clock;

[0014] and for controlling the sampling result of the ADC channel to be calibrated by adjusting the delay between the ADC channel to be calibrated and the reference ADC channel.

[0015] According to the ramp signal-based ADC clock mismatch calibration method provided by the present invention, the steps of sampling a first ramp signal output by a ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result specifically include: triggering the ramp signal generating circuit by a first rising edge of a trigger clock so that the ramp signal generating circuit outputs the first ramp signal;

[0016] The first ramp signal is input into a preset reference ADC channel for sampling, and the delay between the first ramp signal and the trigger clock is adjusted through a digitally controlled variable delay line of a ramp signal generating circuit so that the first sampling result output by the reference ADC channel is within a predetermined range.

[0017] According to the ramp signal-based ADC clock mismatch calibration method provided by the present invention, the step of sampling the second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result specifically includes: triggering the ramp signal generating circuit through the i-th rising edge of the trigger clock so that the ramp signal generating circuit outputs the second ramp signal;

[0018] The second ramp signal is input into the i-th ADC channel to be calibrated for sampling, so as to obtain a second sampling result output by the i-th ADC channel to be calibrated.

[0019] According to the ramp signal-based ADC clock mismatch calibration method provided by the present invention, the steps of adjusting the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, and completing the clock calibration of the ADC channel to be calibrated, specifically include:

[0020] The delay between the i-th ADC channel to be calibrated and the reference ADC channel is adjusted by the digitally controlled variable delay line of the i-th ADC channel to be calibrated, so that the second sampling result output by the i-th ADC channel to be calibrated is equal to the first sampling result output by the reference ADC channel.

[0021] According to the ramp signal-based ADC clock mismatch calibration method provided by the present invention, the N-channel time-interleaved ADC further includes DSP calibration logic; the method further includes:

[0022] The mismatch calibration of each of the to-be-calibrated ADC channels of the N-channel time-interleaved ADC is completed in sequence through the DSP calibration logic.

[0023] The present invention further provides an ADC clock mismatch calibration device based on a ramp signal, which is used in the ADC clock mismatch calibration method based on a ramp signal as described in any of the above items. The device is provided in an N-channel time-interleaved ADC, wherein the N-channel time-interleaved ADC includes a ramp signal generating circuit and N ADC channels of the same structure connected in parallel, wherein the N ADC channels of the same structure include a preset reference ADC channel and N-1 ADC channels to be calibrated, where N ≥ 2. The device includes:

[0024] a first sampling module, configured to sample the first ramp signal output by the ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result;

[0025] The second sampling module is configured to sample the second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal; and the calibration module is configured to adjust the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated.

[0026] The present invention also provides an N-channel time-interleaved ADC, comprising: a ramp signal generating circuit, N ADC channels with the same structure, and the above-mentioned ADC clock mismatch calibration device based on the ramp signal.

[0027] According to the N-channel time-interleaved ADC provided by the present invention, the ramp signal generating circuit is a first circuit in which a current source charges a capacitor.

[0028] According to the N-channel time-interleaved ADC provided by the present invention, the ramp signal generating circuit is a second circuit that triggers a clock to drive a capacitor through an inverter buffer.

[0029] According to the N-channel time-interleaved ADC provided by the present invention, the N-channel time-interleaved ADC further includes DSP calibration logic, and the DSP calibration logic is implemented by Verilog code.

[0030] According to the N-channel time-interleaved ADC provided by the present invention, a digitally controlled variable delay line is provided in the ramp signal generating circuit and each of the ADC channels. The digitally controlled variable delay line is implemented by a delay circuit, and the circuit structure of the delay circuit is determined according to a preset target adjustable accuracy and target adjustable range.

[0031] According to the N-channel time-interleaved ADC provided by the present invention, the delay circuit includes a third circuit composed of a variable-order inverter chain and a fourth circuit composed of an inverter driving a variable capacitor array load.

[0032] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the ADC clock mismatch calibration method based on a ramp signal as described above is implemented.

[0033] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program implements any of the above-mentioned ADC clock mismatch calibration methods based on a ramp signal.

[0034] The present invention further provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned ADC clock mismatch calibration methods based on a ramp signal.

[0035] The ramp signal-based ADC clock mismatch calibration method, device, and N-channel time-interleaved ADC provided by the present invention adjust the delay of a reference ADC channel, use the sampling result of the reference ADC channel as a reference sampling value, and adjust the sampling result of the ADC channel to be calibrated to be equal to the reference sampling value of the reference ADC channel, thereby completing the clock mismatch calibration of the ADC channel to be calibrated. Compared with the solution of directly calibrating the multi-phase clock, the present invention uses the sampling data as the calibration standard and the same sampling results of each channel as the standard for calibration completion, which not only solves the problem of clock mismatch, but also solves the problem of inaccurate sampling points caused by other mismatches between channels, and the problem of higher consistency between channels after calibration is completed; compared with the calibration method of statistical averaging of multi-channel data, the calibration logic of the present invention is simple, the structural complexity is low, the convergence speed is fast, and it can effectively reduce hardware overhead and power consumption; compared with the traditional method of using ramp signals for multi-phase clock calibration, the present invention does not require the ramp signal to maintain a consistent slope, thereby reducing the requirements for the ramp signal generating circuit and avoiding non-ideal factors introduced in the signal chain due to low linearity. In addition, the present invention does not require additional calibration channels, the calibration results can ensure the correctness of the sampling data, and has low requirements for the ramp signal generating circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 The present invention is a flowchart of an ADC clock mismatch calibration method based on a ramp signal provided by an embodiment of the present invention.

[0038] Figure 2 The present invention provides a calibration logic flow chart of an ADC clock mismatch calibration method based on a ramp signal.

[0039] Figure 3 This is a clock calibration circuit diagram of a two-channel SAR ADC provided by an embodiment of the present invention.

[0040] Figure 4 2 is a schematic structural diagram of a ramp signal generating circuit provided by an embodiment of the present invention.

[0041] Figure 5 This is a schematic diagram of the structure of the ADC clock mismatch calibration device based on the ramp signal provided by the embodiment of the present invention.

[0042] Figure 6It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0044] In practical applications, the main operating principle of a time-interleaved ADC is that the ADC contains M identical sampling channels. Each channel consists of a sampling switch and a sub-ADC operating at a lower frequency fs, and is driven by one of the M-phase clocks. Under the control of the M-phase clock, each channel is sampled sequentially, ultimately achieving a sampling frequency of M*fs. Although time-interleaved ADCs effectively increase the operating speed, they also introduce many non-ideal factors. Among them, the skew of the multi-phase clock causes the sampling points of each channel to deviate from the ideal position, becoming a key factor affecting ADC performance.

[0045] Currently, there are many methods for calibrating the mismatch skew of multiphase clocks in time-interleaved ADCs, which can be mainly divided into the following categories. One method is to directly detect and calibrate the multiphase clocks. After "&"ing the multiphase clocks, a pulse signal is obtained. Then, a DC level representing the phase relationship is obtained through a low-pass filter. By comparing the DC level values, the deviation between the phase clocks is obtained and calibration is performed. The advantages of this method are intuitive and easy to implement. The disadvantage is that it only calibrates the clock and does not consider the errors introduced by the sampling circuit. The other method relies on an additional calibration channel. This calibration channel has the same structure as the other sampling channels but operates at a different frequency. This calibration channel samples the input signal simultaneously with the other sampling channels, and calibration of multiple channels is achieved by comparing the sampling results. The advantages of this method are easy to expand and independent of specific input data. The disadvantage is that it requires additional clocks and sampling channels, which is hardware-intensive and power-intensive. One method relies on a specific input signal, such as a ramp signal with a fixed input slope. Ideally, the sampling values ​​of each channel should be evenly distributed for detection and calibration. The disadvantage of this method is that it is difficult to obtain an accurate ramp signal, and the nonlinearity of the link has a great impact on the calibration results. Another example is that it relies on an input sinusoidal signal or a random signal. By taking a statistical average of the sampling data of each channel, the error value between channels is obtained and calibrated. The disadvantage of this method is that the calibration time is long and the calibration logic is complex.

[0046] In view of this, in some possible implementation schemes, the present scheme provides an ADC clock mismatch calibration method based on a ramp signal, which is used for an N-channel time-interleaved ADC. The N-channel time-interleaved ADC includes a ramp signal generating circuit and N ADC channels with the same structure connected in parallel, wherein the N ADC channels with the same structure include a preset reference ADC channel and N-1 ADC channels to be calibrated, and N≥2.

[0047] In a possible embodiment, Figure 1 As shown in FIG, the ADC clock mismatch calibration method based on the ramp signal specifically includes the following steps:

[0048] Step 100: sampling a first ramp signal output by a ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result;

[0049] Step 200: Sampling a second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal;

[0050] Step 300 : Adjust the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated.

[0051] The following is a specific example of Figure 1 Detailed description of each step in.

[0052] Step 100: sampling a first ramp signal output by a ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result;

[0053] In some possible implementations, the N-channel time-interleaved ADC calibrated in this solution can utilize various commonly used sampling switches and ADC circuits, such as bootstrap switches and SAR ADCs. The N-channel time-interleaved ADC is equipped with a clock-triggered ramp signal generation circuit, a multi-channel time-interleaved ADC, DSP calibration logic, and a digitally controlled variable delay line.

[0054] In some possible implementation schemes, the N-channel time-interleaved ADC in this scheme includes a trigger clock, which is used to trigger the ramp signal generating circuit through each rising edge to generate the same ramp signal, that is, to generate a second ramp signal with the same signal shape as the first ramp signal.

[0055] In a possible embodiment, the ramp signal used for calibration is driven by a high-frequency clock. If only rising-edge triggering is used, the clock frequency is equal to the number of channels multiplied by the channel sampling frequency. The clock selection circuit that triggers the ramp signal can be implemented using a multiphase clock selection circuit or a clock counter circuit.

[0056] In a possible embodiment, the ramp signal can be generated by using a current source to charge a capacitor, or by using a clock to drive a capacitor through an inverter buffer. The slope of the ramp signal does not need to remain constant. Based on this, the ramp signal generating circuit can be configured as a first circuit in which a current source charges a capacitor, or as a second circuit in which a triggering clock drives a capacitor through an inverter buffer.

[0057] In a possible embodiment, a digitally controlled variable delay line is provided in the ramp signal generating circuit and each ADC channel; wherein the digitally controlled variable delay line is used to control the sampling result of the reference ADC channel by adjusting the delay between the first ramp signal and the trigger clock;

[0058] and for controlling the sampling result of the ADC channel to be calibrated by adjusting the delay between the ADC channel to be calibrated and the reference ADC channel.

[0059] In some possible implementation schemes, the digitally controlled variable delay line in this scheme is implemented using a delay circuit, such as an inverter driving a variable capacitor array load, a variable-level inverter chain, etc. The delay circuit is determined according to a preset target adjustable accuracy and target adjustable range.

[0060] It is worth noting that although both the inverter-driven variable capacitor array load and the variable-stage inverter chain can realize the delay circuit function of the digitally controlled variable delay line, the adjustable accuracy and adjustable range of the two are different. In practical applications, the specific form of the delay circuit needs to be determined based on the preset target adjustable accuracy and target adjustable range.

[0061] Based on the above embodiment, step 100 may specifically include:

[0062] triggering the ramp signal generating circuit by the first rising edge of the trigger clock, so that the ramp signal generating circuit outputs a first ramp signal;

[0063] The first ramp signal is input into a preset reference ADC channel for sampling, and the delay between the first ramp signal and the trigger clock is adjusted through a digitally controlled variable delay line of a ramp signal generating circuit so that the first sampling result output by the reference ADC channel is within a predetermined range.

[0064] In a possible embodiment, the ramp signal generating circuit is a second circuit in which a trigger clock drives a capacitor through an inverter buffer; the second circuit is triggered by the rising edge of the trigger clock to obtain a ramp signal output by the second circuit.

[0065] In a possible embodiment, the delay circuit used by the digitally controlled variable delay line is a third circuit composed of a variable-stage inverter chain; the delay between the first ramp signal and the trigger clock is adjusted by adjusting the third circuit.

[0066] Step 200: Sampling a second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal. Based on the above embodiment, step 200 may specifically include:

[0067] triggering the ramp signal generating circuit by the i-th rising edge of the trigger clock, so that the ramp signal generating circuit outputs a second ramp signal;

[0068] The second ramp signal is input into the i-th ADC channel to be calibrated for sampling, so as to obtain a second sampling result output by the i-th ADC channel to be calibrated.

[0069] Step 300: Adjust the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, completing the clock calibration of the ADC channel to be calibrated.

[0070] In some possible implementation schemes, according to the working principle of the time-interleaved ADC, the N-channel time-interleaved ADC used for calibration in this scheme includes N identical sampling channels, each channel consists of a sampling switch and a clock source operating at a lower frequency f. s The sub-ADC is composed of N phase clocks and driven by one phase of the N phase clock. Under the control of the N phase clock, each channel is sampled in turn, and finally N*f s The sampling frequency of .

[0071] In some possible implementation schemes, step 300 specifically includes:

[0072] The delay between the i-th ADC channel to be calibrated and the reference ADC channel is adjusted by the digitally controlled variable delay line of the i-th ADC channel to be calibrated, so that the second sampling result output by the i-th ADC channel to be calibrated is equal to the first sampling result output by the reference ADC channel.

[0073] It is understood that, to distinguish the first ramp signal sampled by the reference ADC channel, the ramp signal sampled by any ADC channel to be calibrated is defined as a second ramp signal. The second ramp signal and the first ramp signal are two ramp signals with the same signal shape, output by the same ramp signal generating circuit. In a possible embodiment, when calibrating the second ADC channel, the ramp signal generating circuit is triggered by the second rising edge of the trigger clock, causing the ramp signal generating circuit to output the second ramp signal, which is then input into the second ADC channel for sampling.

[0074] Similarly, if any other ADC channel to be calibrated needs to be calibrated, the ramp signal generating circuit is triggered by the i-th rising edge of the trigger clock, so that the ramp signal generating circuit outputs the i-th second ramp signal, and the i-th second ramp signal is input into the i-th ADC channel for sampling.

[0075] In a possible embodiment, the delay circuit used in the digitally controlled variable delay line is a fourth circuit composed of an inverter driving a variable capacitor array load; the delay between the i-th ADC channel to be calibrated and the reference ADC channel is adjusted by adjusting the fourth circuit.

[0076] In some possible implementations, the N-channel time-interleaved ADC also includes DSP calibration logic.

[0077] Furthermore, i is sequentially set to values ​​from 1 to N-1 by the DSP calibration logic to complete the mismatch calibration of each of the ADC channels to be calibrated of the N-channel time-interleaved ADC.

[0078] In a possible embodiment, the DSP calibration logic may be implemented using Verilog code, and the Verilog code is used to implement i taking values ​​from 1 to N-1 in sequence to complete mismatch calibration of one reference ADC channel and N-1 ADC channels to be calibrated.

[0079] In some possible embodiments, Figure 2 FIG. 1 is a calibration logic flow chart of an ADC clock mismatch calibration method based on a ramp signal provided in an embodiment of the present invention, such as Figure 2As shown, the calibration process of this solution is as follows: First, channel one is regarded as the calibration reference point. The ramp signal generation circuit is triggered by the first rising edge of the clock. The output ramp signal is sampled by the time-interleaved ADC. The delay between the ramp signal and the trigger clock is adjusted so that the sampling result of channel one is at the appropriate value, and the sampled value is recorded. Then, the ramp signal generation circuit is triggered by the second rising edge of the clock. The output ramp signal is sampled by the time-interleaved ADC. The delay between channel two and channel one is adjusted so that the sampling result of channel two is equal to the sampled value recorded by channel one, completing the calibration of channel two. Then, the ramp signal generation circuit is triggered by the third rising edge of the clock, and so on, completing the clock skew calibration of all channels.

[0080] The ADC clock mismatch calibration method based on a ramp signal provided by the present invention is used for multi-channel calibration of a time-interleaved ADC. The ramp signal triggered by the inside of the ADC is sampled by multiple channels, and the offset skew of the sampling clock of each channel is obtained by comparing the sampling results of each channel, and then calibration is performed. Compared with the traditional multi-phase clock calibration scheme, the present invention does not require an additional calibration channel, the calibration logic is simple, and can effectively reduce power consumption and hardware overhead. In particular, compared with the traditional calibration scheme based on a ramp signal, the present invention does not require the ramp signal to have an accurate slope, but only requires the ramp signal to maintain monotonicity, which greatly reduces the requirements for the ramp signal generating circuit and avoids the calibration result being affected by the linearity of the signal transmission link. In addition, the present invention is suitable for the calibration of a two-phase clock, and is also suitable for the calibration of a multi-phase clock.

[0081] In some possible embodiments, Figure 3 : is a clock calibration circuit diagram of a two-channel SAR ADC provided by an embodiment of the present invention, such as Figure 3 As shown in the figure, this solution implements clock calibration for a two-channel SAR ADC. The sampling clock is a two-phase 8GHz non-overlapping clock. During normal ADC operation, the ramp signal is turned off. During clock calibration, the input signal is set to 0, and the ramp signal is AC-coupled into the signal path. The ramp signal is triggered by two differential 8GHz clocks with a 50% duty cycle. A duty cycle calibration circuit ensures uniform spacing between the rising and falling edges. First, the ramp signal is triggered by the rising edge of the clock and sampled into the digital domain by ADC channel one. The delay between the ramp signal and the trigger clock is adjusted using a digitally controlled delay line (DCDL) to ensure that the sampled value is between -0.5 and +0.5, and the current sampled value is recorded. Then, the ramp signal is triggered by the falling edge of the clock and sampled into the digital domain by ADC channel two. Ideally, the two-phase clock skew is zero, and the sampled values ​​of the ramp signal should also be identical. The calibration strategy is to delay the clock using the digitally controlled delay line (DCDL) so that the sampled value of channel two is equal to that of channel one.

[0082] In a possible embodiment, the digitally controlled delay line used to adjust the delay between the ramp signal and the trigger clock comprises a variable-order inverter chain with an adjustment range of 570 ps and a 9 ps adjustment step. The delay is linearly controlled using a 6-bit binary code. This variable delay line does not require precise adjustment, only ensuring that the ramp signal can be sampled. The digitally controlled delay line used to adjust the delay between the two clock phases comprises an inverter driving a load through a variable resistor array. The delay has an adjustment range of 12 ps and a 100 fs adjustment step. The delay is linearly controlled using a 7-bit binary code. This variable delay line's adjustment range covers the maximum possible clock delay skew, and the adjustment step size is determined by the ADC sampling accuracy.

[0083] In a possible embodiment, due to the limited sampling accuracy of the ADC, the slope of the ramp signal cannot be too low. Otherwise, even if the clock skew is large, the sampling range will still not exceed one LSB, and calibration cannot be completed. Based on this consideration, this solution uses a clock inverter buffer to drive a variable capacitor array to implement a ramp signal. The slope can meet the requirements and is adjustable. Figure 4 FIG. 1 is a schematic diagram of a ramp signal generating circuit according to an embodiment of the present invention. Figure 4 As shown in FIG, the ramp signal is triggered twice only by performing a MUX on the input differential clock. The first trigger selects the P end, and the second trigger selects the N end.

[0084] It can be seen from the above embodiments that the multi-phase clock calibration method based on ramp signals provided by the present invention does not require additional calibration channels, the calibration result can ensure the accuracy of sampling data, and has low requirements on the ramp signal generating circuit.

[0085] Specifically, the present invention uses sampling data as the calibration standard: compared with the solution of directly calibrating the multi-phase clock, the present invention uses the same sampling results of each channel as the standard for completion of calibration. This not only takes the clock skew into account, but also takes into account the inaccurate sampling points caused by other mismatches between channels. After the calibration is completed, the consistency between channels is higher.

[0086] The calibration logic of the present invention is simple: compared with the calibration method of performing statistical averaging on multi-channel data, the calibration logic of the present invention is simple, the structural complexity is low, the convergence speed is fast, and the hardware overhead and power consumption can be effectively reduced.

[0087] The present invention has low requirements for the ramp signal: compared with the traditional method of using a ramp signal to calibrate a multi-phase clock, the present invention does not require the ramp signal to maintain a consistent slope, thereby reducing the requirements for the ramp signal generating circuit and avoiding non-ideal factors introduced in the signal chain due to low linearity.

[0088] The ADC clock mismatch calibration device based on a ramp signal provided by the present invention is described below. The ADC clock mismatch calibration device based on a ramp signal described below and the ADC clock mismatch calibration method based on a ramp signal described above can refer to each other.

[0089] In some possible implementation schemes, an ADC clock mismatch calibration device based on a ramp signal is further provided, which is used in the ADC clock mismatch calibration method based on a ramp signal as described in any one of the above items. Figure 5 FIG is a structural diagram of an ADC clock mismatch calibration device based on a ramp signal provided by an embodiment of the present invention, such as Figure 5 As shown, the ADC clock mismatch calibration device based on a ramp signal provided by the present solution is used for an N-channel time-interleaved ADC. The N-channel time-interleaved ADC includes a ramp signal generating circuit and N ADC channels of the same structure connected in parallel. The N ADC channels of the same structure include a preset reference ADC channel and N-1 ADC channels to be calibrated, where N ≥ 2.

[0090] The device comprises:

[0091] A first sampling module 51 is configured to sample the first ramp signal output by the ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result;

[0092] a second sampling module 52, configured to sample a second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal;

[0093] The calibration module 53 is configured to adjust the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated.

[0094] In an optional embodiment, the calibration module 53 is further configured to sequentially complete clock calibration of each ADC channel in the N-channel time-interleaved ADC.

[0095] The implementation principle and beneficial effects of the ramp signal-based ADC clock mismatch calibration device provided in an embodiment of the present invention are similar to the implementation principle and beneficial effects of the ramp signal-based ADC clock mismatch calibration method shown in the above embodiment. Please refer to the implementation principle and beneficial effects of the ramp signal-based ADC clock mismatch calibration method shown in the above embodiment, and no further details will be given here.

[0096] In some possible implementation schemes, an N-channel time-interleaved ADC is further provided, comprising: a ramp signal generating circuit, N ADC channels with the same structure, and the ADC clock mismatch calibration device based on the ramp signal as described above.

[0097] In a possible embodiment, the ramp signal generating circuit in the N-channel time-interleaved ADC of this solution is a first circuit formed by a current source charging a capacitor or a second circuit formed by a trigger clock driving a capacitor through an inverter buffer.

[0098] In a possible embodiment, the N-channel time-interleaved ADC in this solution also includes DSP calibration logic.

[0099] In a possible embodiment, the DSP calibration logic is implemented by Verilog code.

[0100] In a possible embodiment, a digitally controlled variable delay line is provided in the ramp signal generating circuit of the N-channel time-interleaved ADC and each of the ADC channels in this solution. The digitally controlled variable delay line is implemented by a delay circuit, and the circuit structure of the delay circuit is determined according to a preset target adjustable accuracy and target adjustable range.

[0101] In a possible embodiment, the delay circuit includes a third circuit consisting of a variable-number inverter chain and a fourth circuit consisting of an inverter driving a variable capacitor array load.

[0102] The implementation principle and beneficial effects of the N-channel time-interleaved ADC provided in the embodiment of the present invention are similar to the implementation principle and beneficial effects of the ADC clock mismatch calibration method based on the ramp signal shown in the above embodiment. Please refer to the implementation principle and beneficial effects of the ADC clock mismatch calibration method based on the ramp signal shown in the above embodiment, and no further details will be given here.

[0103] Figure 6 An example of a physical structure diagram of an electronic device is shown below. Figure 6As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 may call logic instructions in the memory 630 to execute an ADC clock mismatch calibration method based on a ramp signal, the method comprising: sampling a first ramp signal output by a ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result; sampling a second ramp signal output by the ramp signal generating circuit through an ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal; and adjusting the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated.

[0104] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0105] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can perform the ADC clock mismatch calibration method based on a ramp signal provided by the above methods. The method includes: sampling a first ramp signal output by a ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result; sampling a second ramp signal output by the ramp signal generating circuit through an ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal; and adjusting the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated.

[0106] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to perform the ADC clock mismatch calibration method based on the ramp signal provided by the above methods. The method includes: sampling a first ramp signal output by a ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result; sampling a second ramp signal output by the ramp signal generating circuit through an ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal; adjusting the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing the clock calibration of the ADC channel to be calibrated.

[0107] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0108] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for calibrating ADC clock mismatch based on a ramp signal, characterized in that: For an N-channel time-interleaved ADC, the N-channel time-interleaved ADC comprising a ramp signal generating circuit and N ADC channels of identical structure connected in parallel, wherein the N ADC channels of identical structure include a preset reference ADC channel and N-1 ADC channels to be calibrated, where N ≥ 2; The method comprises: Sampling the first ramp signal output by the ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result; Sampling a second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal; Adjusting the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated; The N-channel time-interleaved ADC further includes a trigger clock, wherein the trigger clock is used to trigger the ramp signal generating circuit through each rising edge to generate a second ramp signal with the same signal shape as the first ramp signal; A digitally controlled variable delay line is provided in the ramp signal generating circuit and each of the ADC channels; The digitally controlled variable delay line is used to control the sampling result of the reference ADC channel by adjusting the delay between the first ramp signal and the trigger clock; and for controlling the sampling result of the ADC channel to be calibrated by adjusting the delay between the ADC channel to be calibrated and the reference ADC channel; triggering the ramp signal generating circuit by the first rising edge of the trigger clock, so that the ramp signal generating circuit outputs a first ramp signal; The ramp signal generating circuit is triggered by the i-th rising edge of the trigger clock, so that the ramp signal generating circuit outputs a second ramp signal.

2. The ADC clock mismatch calibration method based on a ramp signal according to claim 1, wherein: The step of sampling the first ramp signal output by the ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result specifically includes: The first ramp signal is input into a preset reference ADC channel for sampling, and the delay between the first ramp signal and the trigger clock is adjusted through a digitally controlled variable delay line of a ramp signal generating circuit so that the first sampling result output by the reference ADC channel is within a predetermined range.

3. The ADC clock mismatch calibration method based on a ramp signal according to claim 2, wherein: The step of sampling the second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result specifically includes: The second ramp signal is input into the i-th ADC channel to be calibrated for sampling, so as to obtain a second sampling result output by the i-th ADC channel to be calibrated.

4. The ADC clock mismatch calibration method based on a ramp signal according to claim 3, wherein: The step of adjusting the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated, specifically includes: The delay between the i-th ADC channel to be calibrated and the reference ADC channel is adjusted by the digitally controlled variable delay line of the i-th ADC channel to be calibrated, so that the second sampling result output by the i-th ADC channel to be calibrated is equal to the first sampling result output by the reference ADC channel.

5. The ADC clock mismatch calibration method based on a ramp signal according to any one of claims 1 to 4, characterized in that: The N-channel time-interleaved ADC also includes DSP calibration logic; The method comprises: The mismatch calibration of each of the to-be-calibrated ADC channels of the N-channel time-interleaved ADC is completed in sequence through the DSP calibration logic.

6. An ADC clock mismatch calibration device based on a ramp signal, used in the ADC clock mismatch calibration method based on a ramp signal according to any one of claims 1 to 5, characterized in that: For an N-channel time-interleaved ADC, the N-channel time-interleaved ADC comprising a ramp signal generating circuit and N ADC channels of identical structure connected in parallel, wherein the N ADC channels of identical structure include a preset reference ADC channel and N-1 ADC channels to be calibrated, where N ≥ 2; The device comprises: a first sampling module, configured to sample the first ramp signal output by the ramp signal generating circuit through a preset reference ADC channel to obtain a first sampling result; a second sampling module, configured to sample a second ramp signal output by the ramp signal generating circuit through the ADC channel to be calibrated to obtain a second sampling result, wherein the second ramp signal has the same signal shape as the first ramp signal; a calibration module, configured to adjust the ADC channel to be calibrated so that the second sampling result is equal to the first sampling result, thereby completing clock calibration of the ADC channel to be calibrated; The N-channel time-interleaved ADC further includes a trigger clock, wherein the trigger clock is used to trigger the ramp signal generating circuit through each rising edge to generate a second ramp signal with the same signal shape as the first ramp signal; A digitally controlled variable delay line is provided in the ramp signal generating circuit and each of the ADC channels; The digitally controlled variable delay line is used to control the sampling result of the reference ADC channel by adjusting the delay between the first ramp signal and the trigger clock; and for controlling the sampling result of the ADC channel to be calibrated by adjusting the delay between the ADC channel to be calibrated and the reference ADC channel; triggering the ramp signal generating circuit by the first rising edge of the trigger clock, so that the ramp signal generating circuit outputs a first ramp signal; The ramp signal generating circuit is triggered by the i-th rising edge of the trigger clock, so that the ramp signal generating circuit outputs a second ramp signal.

7. An N-channel time-interleaved ADC, characterized in that: include: A ramp signal generating circuit, N ADC channels with identical structures, and the ADC clock mismatch calibration device based on a ramp signal as claimed in claim 6.

8. The N-channel time-interleaved ADC according to claim 7, wherein: The ramp signal generating circuit is a first circuit in which a current source charges a capacitor.

9. The N-channel time-interleaved ADC according to claim 7, wherein: The ramp signal generating circuit is a second circuit that triggers a clock to drive a capacitor through an inverter buffer.

10. The N-channel time-interleaved ADC according to claim 7, wherein: The N-channel time-interleaved ADC further includes DSP calibration logic, which is implemented by Verilog code.

11. The N-channel time-interleaved ADC according to claim 7, wherein: A digitally controlled variable delay line is provided in the ramp signal generating circuit and each of the ADC channels. The digitally controlled variable delay line is implemented by a delay circuit, and the circuit structure of the delay circuit is determined according to a preset target adjustable accuracy and target adjustable range.

12. The N-channel time-interleaved ADC according to claim 11, wherein: The delay circuit includes a third circuit composed of a variable-number inverter chain and a fourth circuit composed of an inverter driving a variable capacitor array load.

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