Erase rate control for memory devices

Abstract

This application relates to erase rate control for memory devices. For example, during an erase operation, a memory device can perform error correction operations on data read from a memory array of the memory device. The memory device can determine an amount of errors detected or corrected during the erase operation, and determine a condition of the memory array based on the amount of errors. The memory device can indicate the determined condition of the memory array to a host device. In some cases, the memory device can perform an erase operation based on one or more conditions of the memory array. For example, as the condition of the memory array deteriorates, the memory device can perform erase operations at an increasing rate.

Description

[0001] Related application information

[0002] This application is a divisional application. The parent of this divisional application is the patent application entitled “SCRUB RATE CONTROL FOR A MEMORY DEVICE” having an application date of May 8, 2020, an application number of 202080049507.X, and an invention title of “SCRUB RATE CONTROL FOR A MEMORY DEVICE.”

[0003] Cross-reference

[0004] This patent application claims priority to PCT Application No. PCT / US2020 / 032166 to Boehm et al., entitled “SCRUB RATE CONTROL FOR A MEMORY DEVICE,” filed May 8, 2020, which claims priority to U.S. Patent Application No. 16 / 433,891 to Boehm et al., entitled “SCRUB RATE CONTROL FOR A MEMORY DEVICE,” filed June 6, 2019, each of which is assigned to the present assignee and each of which is expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0005] The technical field relates to scrub rate control for a memory device. BACKGROUND

[0006] The following relates generally to a system including at least one memory device, and more specifically to scrub rate control for a memory device.

[0007] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, often represented by a logical one or a logical zero. In other devices, more than two states can be stored. To access stored information, a component of a device can read or sense at least one stored state in a memory device. To store information, a component of a device can write or program a state in a memory device.

[0008] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source.

[0009] In some cases, memory devices can be used within systems that specify a high level of reliability. Such systems can include, for example, automobiles or other systems in which safety is involved. However, the health of a memory device can degrade over time, which can lead to unrecoverable memory errors or other issues. SUMMARY

[0010] A method is described. The method can include performing an erase operation at a memory device, including reading data and error correction information stored in each row of a plurality of rows of a memory array of the memory device, and detecting bit errors in the data of each row based at least in part on the error correction information; monitoring the bit errors detected for the plurality of rows for the erase operation during the erase operation; determining an amount of the bit errors detected during the erase operation based at least in part on the monitoring; determining a condition of the memory array based at least in part on the amount of the bit errors detected; and performing, by the memory device, an action associated with the condition of the memory array.

[0011] A method is described. The method can include performing a first set of erase operations at a memory device, including detecting bit errors in a memory array of the memory device according to a first rate associated with a first condition of the memory array for erasing the memory array; determining an amount of the bit errors detected during each erase operation of the first set of erase operations; determining a second condition of the memory array associated with a second rate for erasing the memory array based at least in part on one or more of the amount of the bit errors detected; and performing a second set of erase operations, including detecting bit errors in the memory array according to the second rate for erasing the memory array.

[0012] An apparatus is described. The apparatus can include an array of memory cells; and circuitry coupled with the array of memory cells and usable to cause the apparatus to: perform an erase operation including reading data and error correction information stored in each row of a plurality of rows of the array of memory cells, and detecting bit errors in the data of each row based at least in part on the error correction information; monitor the bit errors detected for the plurality of rows of the erase operation during the erase operation; determine an amount of the bit errors detected during the erase operation based at least in part on the monitoring; determine a condition of the array of memory cells based at least in part on the amount of the bit errors detected; and perform, by the apparatus, an action associated with the condition of the array of memory. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 Examples of systems that support erase rate control for memory devices in accordance with examples as disclosed herein are described.

[0014] Figure 2 Examples of memory dies that support erase rate control for memory devices in accordance with examples as disclosed herein are described.

[0015] Figure 3 Examples of systems that support erase rate control for memory devices in accordance with examples as disclosed herein are described.

[0016] Figure 4 and 5 Examples of process flows that support erase rate control for memory devices in accordance with examples as disclosed herein are described.

[0017] Figure 6 A block diagram of a memory device that supports erase rate control for memory devices in accordance with examples as disclosed herein is shown.

[0018] Figures 7 to 11 A flow diagram illustrating one or more methods that support erase rate control for memory devices in accordance with examples as disclosed herein is shown. DETAILED DESCRIPTION

[0019] Memory devices can operate as part of electronic devices under a variety of conditions, such as personal computers, wireless communication devices, servers, Internet of Things (IoT) devices, electronic components of motor vehicles, and the like. In some cases, memory devices supporting certain applications, such as motor vehicles, in some cases with autonomous or semi-autonomous driving capabilities, can be subject to increased reliability constraints. Accordingly, memory devices (e.g., DRAM) for some applications can be expected to operate subject to relatively high industry standards or specifications, such as higher reliability constraints.

[0020] In some cases, data stored in a memory device can be corrupted (e.g., due to leakage, parasitic coupling, or electromagnetic interference (EMI)). Corruption of data can refer to an unintended change in a logical value of data stored within a memory device, and thus can refer to an unexpected change in a logical value stored by one or more memory cells (e.g., from a logical one (1) to a logical zero (0), or vice versa). For example, a memory device can perform a read operation to determine a logical value of data stored within the memory device and can output the logical value read from a memory cell. A deviation of a stored logical value of a bit from its original and expected logical value can be referred to as an error, a bit error, or a data error, and can be caused by corruption of a stored voltage on a memory cell. Some memory devices can be configured to detect and, in at least some cases, correct (repair) such data corruption or errors internally, thereby recovering data stored prior to corruption. This error detection and correction can rely on one or more error-correcting codes (ECCs) (e.g., block codes, convolutional codes, Hamming codes, low-density parity-check codes, turbo codes, polar codes), and related processes, operations, and techniques can be referred to as ECC processes, ECC operations, ECC techniques, or in some cases simply as ECC. Error detection and correction of data previously stored at a memory device internally within the memory device can be commonly referred to as internal or on-die ECC (whether within a single-die memory device or a multi-die memory device), and a memory device that supports internal or on-die ECC can be referred to as an ECC memory or an on-die ECC memory. Other types of ECC can be performed in a memory system. For example, embedded ECC can refer to embedded ECC information within data stored in a memory device that is checked (e.g., or corrected) by a host device (e.g., by the host device). That is, for embedded ECC, the memory device can not be aware of the ECC information and can treat both the data and the ECC information as data. In another example, extra ECC bits can accompany data in a data channel for read and / or write operations, and can be used to detect or correct errors that occur when transferring data between the memory device and a host device. This type of ECC can be referred to as link ECC.

[0021] During execution of a write command, a memory device with ECC memory can perform error correction operations on data to be stored at a memory array (e.g., received from a host device) to generate error correction information corresponding to the data. As part of a write operation, the memory device can store the data and the error correction information at the memory array. The memory device can be configured to scrub the memory array (e.g., according to a particular rate) in order to detect or correct errors within data stored at the memory array. The rate at which the scrub operation is performed can correspond to a periodicity of scrubbing the entire memory array. To perform the scrub operation, the memory device can generate internal commands (e.g., memory commands and addresses) to scrub each row of the memory array. Alternatively, the memory device can receive one or more scrub commands from the host device indicating a phase of the scrub operation. The scrub operation can include the memory device reading the data, performing error correction operations on the data (e.g., detecting errors within the data, generating corrected data), and in some cases, writing the corrected data back to the memory array. A single scrub operation can correspond to the memory device scrubbing each of the rows of the memory array. Because the scrub operation can be able to correct errors before the amount of errors accumulate beyond the capability of error correction operations, the scrub operation can improve the reliability of the memory device.

[0022] The amount of detected or corrected errors determined during the execution of the scrub operation can be indicative of a condition of the memory array (e.g., corresponding to the integrity of data stored at the memory array). For example, detecting or correcting a relatively lower amount of errors during the scrub operation can be indicative of a good condition of the memory array (e.g., corresponding to a relatively higher level of data integrity of the memory array). Alternatively, detecting or correcting a relatively higher amount of errors during the scrub operation can be indicative of a degraded or unsatisfactory condition of the memory array (e.g., corresponding to a relatively lower level of data integrity of the memory array). In some cases, the memory device can indicate the condition of the memory array to the host device. Further, the rate at which the scrub operation is performed can correspond to the condition of the memory array. For example, as the condition of the memory array degrades, the memory device can perform the scrub operation according to a faster rate. Increasing the scrub rate based on the condition of the memory array can increase the reliability of the memory device.

[0023] The features of the present disclosure are initially described in the context of a memory system and memory dies as described with reference to Figures 1 to 3 The features of the present disclosure are further described in the context of process flows as described with reference to Figure 4 and 5 These and other features of the present disclosure are further illustrated by and described with reference to apparatus diagrams and flowcharts related to scrub rate control for memory devices as described with reference to Figures 6 to 11

[0024] ​Figure 1 An example of a system 100 utilizing one or more memory devices in accordance with examples as disclosed herein is described. The system 100 can include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110. The system 100 can include one or more memory devices, but for ease of description, the one or more memory devices can be described as a single memory device 110.

[0025] The system 100 can include a portion of an electronic device such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. The system 100 can be an example of a portable electronic device. The system 100 can be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. The memory device 110 can be a component of the system configured to store data for one or more other components of the system 100. In some examples, the system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0026] At least a portion of the system 100 can be an example of a host device. Such a host device can be an example of a device that uses memory to perform processes such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other stationary or portable electronic device, etc. In some cases, a host device can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 105. In some cases, the external memory controller 105 can be referred to as a host or a host device. In some examples, the system 100 is a graphics card.

[0027] In some cases, the memory device 110 can be a standalone device or component configured to communicate with other components of the system 100 and provide physical memory addresses / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configured to cooperate with at least one or more different types of system 100. The signaling between the components of the system 100 and the memory device 110 can be used to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packaging of the system 100 and the memory device 110, clock signaling and synchronization between the system 100 and the memory device 110, timing conventions, and / or other factors.

[0028] Memory device 110 can be configured to store data for the components of system 100. In some cases, memory device 110 can serve as a slave-type device of system 100 (e.g., responding to and executing commands provided by external memory controller 105 for system 100). Such commands can include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 can include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies can be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0029] System 100 can further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 can be in electronic communication with one another using a bus 140.

[0030] Processor 120 can be configured to control at least portions of system 100. Processor 120 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it can be a combination of these types of components. In such cases, processor 120 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other examples.

[0031] BIOS component 125 can be a software component that includes a BIOS operating as firmware, which can initialize and run various hardware components of system 100. BIOS component 125 can also manage data flow between processor 120 and the various components of system 100, such as peripheral components 130, I / O controller 135, and the like. BIOS component 125 can include a program or software stored in read-only memory (ROM), flash memory, or any other nonvolatile storage medium.

[0032] Peripheral components 130 can be any input or output device, or an interface for such devices, that can be integrated into or with system 100. Examples can include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or an accelerated graphics port. Peripheral components 130 can be other components understood by one of skill in the art to be peripheral devices.

[0033] The I / O controller 135 can manage data communication between the processor 120, and the peripheral components 130, input devices 145, or output devices 150. The I / O controller 135 can manage peripherals that are not integrated into or with the system 100. In some cases, the I / O controller 135 can represent a physical connection or port to the external peripherals. The I / O controller 135 can also manage incoming peripheral data, such as packets received from the peripheral components 130, 145, or 150. In some cases, the I / O controller 135 can perform processing on the incoming packets.

[0034] The input 145 can represent a device or signal external to the system 100 that provides input to the system 100 or its components. This can include a user interface or an interface to or from another device. In some cases, the input 145 can be a peripheral device that interfaces with the system 100 via one or more peripheral components 130, or can be managed by the I / O controller 135.

[0035] The output 150 can represent a device or signal external to the system 100 that is configured to receive output from the system 100 or any of its components. Examples of the output 150 can include a display, an audio speaker, a printing device, or another processor or printed circuit board, among others. In some cases, the output 150 can be a peripheral device that interfaces with the system 100 via one or more peripheral components 130, or can be managed by the I / O controller 135.

[0036] The components of the system 100 can be made up of general or special-purpose circuitry designed to carry out their functions. This can include various circuit elements, for example, wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to carry out the functions described herein.

[0037] The memory device 110 can include a device memory controller 155 and one or more memory dies 160. Each memory die 160 can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N), and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 can be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store digital data of at least one bit. Referring to Figure 2 Features of the memory array 170 and / or memory cells are described in greater detail.

[0038] Memory device 110 can be an example of a two-dimensional (2D) array of memory cells or can be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device can include a single memory die 160. A 3D memory device can include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N can be stacked on one another or in close proximity to one another. In some cases, a memory die 160-N in a 3D memory device can be referred to as a tier, level, layer, or die. A 3D memory device can include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). This can increase the number of memory cells that can be located on a substrate as compared to a single 2D memory device, which in turn can reduce production costs or increase performance of the memory array, or both. In some 3D memory devices, different tiers can share at least one common access line, such that some tiers can share at least one of a word line, a digit line, and / or a plate line.

[0039] Device memory controller 155 can include circuitry or components configured to control operations of memory device 110. Thus, device memory controller 155 can include hardware, firmware, and software that enables memory device 110 to execute commands and can be configured to receive, transmit, or execute commands, data, or control information regarding memory device 110. Device memory controller 155 can be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 can receive data and / or commands from external memory controller 105. For example, memory device 110 can receive a write command instructing memory device 110 to store certain data on behalf of a component of system 100 (e.g., processor 120) or receive a read command instructing memory device 110 to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 can control operations of memory device 110 described herein in conjunction with local memory controller 165 of memory die 160. Examples of components included in device memory controller 155 and / or local memory controller 165 can include receivers to demodulate signals received from external memory controller 105, decoders to modulate and transmit signals to external memory controller 105, logic, decoders, amplifiers, filters, etc.

[0040] The local memory controller 165 (e.g., local to the memory die 160) can be configured to control operations of the memory die 160. Also, the local memory controller 165 can be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 can support the device memory controller 155 to control operations of the memory device 110 as described herein. In some cases, the memory device 110 does not include the device memory controller 155, and the local memory controller 165 or the external memory controller 105 can perform various functions described herein. Thus, the local memory controller 165 can be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0041] The external memory controller 105 can be configured to enable transfer of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 can act as an intermediary between components of the system 100 and the memory device 110, such that the components of the system 100 can not need to know the operational details of the memory device. The components of the system 100 can present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 can convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 can include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 can include a common data clock that generates a common (source) data clock signal.

[0042] In some cases, the external memory controller 105 or other components of the system 100, or their functions described herein, can be implemented by the processor 120. For example, the external memory controller 105 can be hardware, firmware, or software implemented by the processor 120 or other components of the system 100, or some combination thereof. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein can be implemented by the memory device 110. For example, the external memory controller 105 can be hardware, firmware, or software implemented by the device memory controller 155 or the one or more local memory controllers 165, or some combination thereof. In some cases, the external memory controller 105 can be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controllers 165. Likewise, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controllers 165 can in some cases be performed by the external memory controller 105 (separate from or included in the processor 120).

[0043] The components of the system 100 can exchange information with the memory device 110 using a plurality of channels 115. In some examples, the channels 115 can enable communication between the external memory controller 105 and the memory device 110. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. A pin can be an example of a conductive input or output point of a device of the system 100, and a pin can be configured to function as part of a channel.

[0044] In some cases, the pins or pads of a terminal can be part of a signal path of a channel 115. Additional signal paths can be coupled with the terminals of a channel for routing signals within the components of the system 100. For example, the memory device 110 can include signal paths (e.g., internal to the memory device 110 or its components, such as internal to the memory die 160) that route signals from the terminals of a channel 115 to various components of the memory device 110 (e.g., the device memory controller 155, the memory die 160, the local memory controllers 165, the memory array 170).

[0045] Channels 115 (and associated signal paths and terminals) can be dedicated to communicating a particular type of information. In some cases, a channel 115 can be an aggregated channel and thus can include multiple individual channels. For example, a data channel 190 can be x4 (e.g., include four signal paths), x8 (e.g., include eight signal paths), x16 (include sixteen signal paths), and so forth. Signals communicated over a channel can use double data rate (DDR) signaling. For example, some symbols of a signal can be registered on a rising edge of a clock signal, and other symbols of the signal can be registered on a falling edge of the clock signal. Signals communicated over a channel can use single data rate (SDR) signaling. For example, one symbol of a signal can be recorded for each clock cycle.

[0046] In some cases, channels 115 can include one or more command and address (CA) channels 186. CA channels 186 can be configured to communicate commands between external memory controller 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, a CA channel 186 can include a read command with an address of the data required. In some cases, CA channels 186 can be registered on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channels 186 can include any number of signal paths to decode address and command data (e.g., eight or nine or more signal paths).

[0047] In some cases, channels 115 can include one or more clock signal (CK) channels 188. CK channels 188 can be configured to communicate one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal can be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, a clock signal can be a differential output (e.g., a CK_t signal and a CK_c signal) and the signal paths of CK channels 188 can be configured accordingly. In some cases, a clock signal can be single-ended. CK channels 188 can include any number of signal paths. In some cases, a clock signal CK (e.g., a CK_t signal and a CK_c signal) can provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Clock signal CK can thus be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. System clock signal CK can be generated by a system clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, and so forth).

[0048] In some cases, the channels 115 can include one or more data (DQ) channels 190. The data channels 190 can be configured to transfer data and / or control information between the external memory controller 105 and the memory device 110. For example, the data channels 190 can transfer information to be written to the memory device 110 (e.g., bidirectionally) or information read from the memory device 110.

[0049] In some cases, the channels 115 can include one or more condition indicator channels 192. The condition indicator channels 192 can indicate a condition of one or more of the memory arrays 170 to the external memory controller 105. That is, the memory device 110 (e.g., through the device memory controller 155 or the local memory controller 165) can determine a condition of one or more of the memory arrays 170, where the condition of the memory array corresponds to a level of integrity of data stored at the memory array. The memory device 110 can determine the condition of the memory array 170 based on an amount of errors detected during an erase operation. For example, as the amount of errors detected during an erase operation increases, the memory device 110 can determine that the condition of the memory array deteriorates. The memory device 110 can indicate the determined condition of the memory array 170 to the external memory controller 105 through the condition indicator channels 192. In some cases, a rate of the erase operation can be based on the condition indicated by the condition indicator channels 192 through the memory device 110. For example, as the condition of the memory array 170 degrades, the memory device 110 can perform the erase operation according to a higher rate. Increasing the erase rate based on the condition of the memory array 170 can increase the reliability of the memory device 110.

[0050] In some cases, the channels 115 can include one or more other channels 194 that can be dedicated to other purposes. These other channels 194 can include any number of signal paths.

[0051] In some cases, the other channels 194 can include one or more write clock signal (WCK) channels. While the 'W' in WCK can nominally represent "write," the write clock signals WCK (e.g., WCK_t signals and WCK_c signals) can provide a timing reference generally used for access operations of the memory device 110 (e.g., a timing reference used for both read and write operations). Thus, the write clock signals WCK can also be referred to as data clock signals WCK. The WCK channels can be configured to transfer a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal can be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signals can be differential outputs (e.g., WCK_t signals and WCK_c signals), and the signal paths of the WCK channels can be configured accordingly. The WCK channels can include any number of signal paths. The data clock signals WCK can be generated by a data clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

[0052] In some cases, the other channels 194 can include one or more error detection code (EDC) channels. The EDC channels can be configured to transfer error detection signals, such as checksums, to improve system reliability. The EDC channels can include any number of signal paths.

[0053] The channels 115 can couple the external memory controller 105 with the memory device 110 using a variety of different architectures. Examples of various architectures can include buses, point-to-point connections, crossbar switches, high-density interposers such as silicon interposers, or channels formed in organic substrates, or some combination thereof. For example, in some cases, the signal paths can include, at least in part, a high-density interposer such as a silicon interposer or a glass interposer.

[0054] The signals transferred on the channels 115 can be modulated using a variety of different modulation schemes. In some cases, the signals transferred between the external memory controller 105 and the memory device 110 can be modulated using a binary symbol (or binary level) modulation scheme. A binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of a binary symbol modulation scheme can be configured to represent one bit of digital data (e.g., a symbol can represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and so forth.

[0055] In some cases, a multi-symbol (or multi-level) modulation scheme can be used to modulate signals communicated between the external memory controller 105 and the memory device 110. A multi-symbol modulation scheme can be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme can be configured to represent more than one bit of digital data (e.g., a symbol can represent a logic 00, a logic 01, a logic 10, or a logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and the like. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) can be a signal modulated using a modulation scheme that includes at least three levels for encoding more than one bit of information. Multi-symbol modulation schemes and symbols can alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0056] Figure 2 Examples of a memory die 200 are described in accordance with examples as disclosed herein. The memory die 200 can be an example of the memory die 160 described with reference to Figure 1 The memory die 200 can include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 can be programmable to store two or more states. For example, a memory cell 205 can be configured to store one bit of digital logic at a time (e.g., a logic 0 and a logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) can be configured to store more than one bit of digital logic at a time (e.g., a logic 00, a logic 01, a logic 10, or a logic 11).

[0057] The memory cells 205 can store electrical charges representing programmable states in capacitors. DRAM architectures can include capacitors that include dielectric materials to store electrical charges representing programmable states. Other storage devices and components are possible in other memory architectures. For example, non-linear dielectric materials can be used.

[0058] Operations such as reads and writes can be performed on the memory cells 205 by activating or selecting access lines such as word lines 210 and / or digit lines 215. In some cases, a digit line 215 can also be referred to as a bit line. References to access lines, word lines, and digit lines, or the like, can be interchanged without affecting understanding or operation. Activating or selecting a word line 210 or a digit line 215 can include applying a voltage to the respective line.

[0059] The memory die 200 can include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. The memory cells 205 can be located at the intersections of the word lines 210 and digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or digit lines 215), a single memory cell 205 can be accessed at its intersection.

[0060] Access to the memory cells 205 can be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 can receive a row address from a local memory controller 260 and activate a word line 210 based on the received row address. The column decoder 225 can receive a column address from the local memory controller 260 and activate a digit line 215 based on the received column address. For example, the memory die 200 can include a plurality of word lines 210 labeled WL_1 through WL_M and a plurality of digit lines 215 labeled DL_1 through DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, e.g., WL_1 and DL_3, a memory cell 205 at their intersection can be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as an address of a memory cell 205.

[0061] The memory cells 205 can include a logical storage component, such as a capacitor 230 and a switch component 235. The capacitor 230 can be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of the capacitor 230 can be coupled with the switch component 235, and a second node of the capacitor 230 can be coupled with a voltage source 240. In some cases, the voltage source 240 can be a cell plate reference voltage, such as Vpl, or can be grounded, such as Vss. In some cases, the voltage source 240 can be an example of a plate line coupled with a plate line driver. The switch component 235 can be an example of a transistor or any other type of switching device that selectively establishes or disestablishes electronic communication between two components.

[0062] Selecting or deselecting a memory cell 205 can be accomplished by activating or deactivating a switch component 235. The capacitor 230 can be in electronic communication with the digit line 215 using the switch component 235. For example, when the switch component 235 is deactivated, the capacitor 230 can be isolated from the digit line 215, and when the switch component 235 is activated, the capacitor 230 can be coupled with the digit line 215. In some cases, the switch component 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, where a voltage difference between the transistor gate and the transistor source can be greater than or less than a threshold voltage of the transistor. In some cases, the switch component 235 can be a p-type transistor or an n-type transistor. The word line 210 can be in electronic communication with the gate of the switch component 235, and can activate / deactivate the switch component 235 based on a voltage applied to the word line 210.

[0063] The word line 210 can be a conductive line in electronic communication with the memory cell 205 that is used to perform access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with the gate of the switch component 235 of the memory cell 205, and can be configured to control the switch component 235 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of the capacitor of the memory cell 205, and the memory cell 205 can not include a switch component.

[0064] The digit line 215 can be a conductive line that connects the memory cell 205 with a sense component 245. In some architectures, the memory cell 205 can be selectively coupled with the digit line 215 during a portion of an access operation. For example, the word line 210 and the switch component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication with the digit line 215 (e.g., constant).

[0065] The sense component 245 can be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 can be extremely small. Accordingly, the sense component 245 can include one or more sense amplifiers to amplify a signal output by the memory cell 205. The sense amplifiers can detect small changes in charge of the digit line 215 during a read operation and can generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 can output a signal (e.g., discharge charge) to its corresponding digit line 215. The signal can cause a voltage of the digit line 215 to change. The sense component 245 can be configured to compare the signal received from the memory cell 205 across the digit line 215 to a reference signal 250 (e.g., a reference voltage). The sense component 245 can determine a storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 250, the sense component 245 can determine that the storage state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 250, the sense component 245 can determine that the storage state of the memory cell 205 is a logic 0. The sense component 245 can include various transistors or amplifiers to detect and amplify differences in signals.

[0066] For a read operation, the detected logic state of the memory cell 205 can be output through the ECC block 265 and the I / O 255. Here, the ECC block 265 can perform an error correction operation on the detected logic state of the memory cell 205 and output data (e.g., original data or corrected data) via the I / O 255. In some other cases, the detected logic state of the memory cell 205 can bypass the ECC block 265 and be output via the I / O 255. In some cases, the detected logic state of the memory cell 205 can be output by the I / O 255 through the ECC block 265 and around the ECC block 265. Here, the detected logic state of the memory cell 205 can be output from the memory die 200 while the ECC block 265 performs an error correction operation on the detected logic state of the memory cell 205. In some cases, the sense component 245 can be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sense component 245 can be in electronic communication with the row decoder 220 or the column decoder 225.

[0067] The local memory controller 260 can control operations of the memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sense component 245, ECC block 265). The local memory controller 260 can be a referenceFigure 1 An example of a local memory controller 165 is described. In some cases, one or more of the row decoder 220, the column decoder 225, the sense component 245, and the ECC block 265 can be co-located with the local memory controller 260. The local memory controller 260 can be configured to receive commands and / or data from the external memory controller 105 (or the device memory controller 155 described with reference to Figure 1 The described device memory controller 155). The local memory controller 260 can translate the commands and / or data into information usable by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 260 can generate row and column address signals to activate a target word line 210 and a target digit line 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or varied, and can be different for the various operations discussed in operating the memory die 200.

[0068] In some cases, the local memory controller 260 can be configured to perform a write operation (e.g., a program operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 can be programmed during a single write operation. The local memory controller 260 can identify a target memory cell 205 on which to perform the write operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 can apply a particular signal (e.g., voltage) to the digit line 215 during the write operation to store a particular state (e.g., charge) in the capacitor 230 of the memory cell 205, which can indicate the desired logic state.

[0069] As part of a write operation, the ECC block 265 or the local memory controller 260 can perform one or more error correction operations on data received from a host device. For example, as part of a write operation, the ECC block 265 can receive data from a host device. The ECC block 265 can determine or generate error correction information associated with the data. In some cases, the ECC block 265 can include or can cause error detection logic (not shown) to perform the error detection operations described herein. As part of a write operation, the ECC block 265 can cause the data and the error correction information to be stored in one or more memory cells 205. In another example, as part of a read operation, the ECC block 265 can receive data and associated error correction information from a memory array. The ECC block 265 can perform an error correction operation based on the data and the error correction information. Performing error correction operations at the memory device (e.g., by the ECC block 265 or the local memory controller 260) can improve the reliability of the memory device.

[0070] The local memory controller 260 can be configured to erase the memory die 200 (e.g., according to a particular rate) in order to detect or correct errors at one or more of the memory cells 205. The rate at which erase operations are performed can correspond to (e.g., inversely) the periodicity of erasing the entire memory array (e.g., the memory array 170). To perform an erase operation, the local memory controller 260 can generate internal commands (and addresses indicating one or more rows of the memory die 200) to erase each row of the memory die 200. Alternatively, the local memory controller 260 can receive one or more erase commands associated with an erase operation from a host device (e.g., with reference to an external memory controller). Figure 1 An erase operation can include the local memory controller 260 initiating a read operation, the ECC block 265 performing error correction operations on the data (e.g., detecting errors within the data, generating corrected data), and in some cases, the local memory controller 260 returning the corrected data to be written to the memory cells of the memory die 200. A single erase operation can correspond to the local memory controller 260 erasing each of the rows of the memory die 200. Based on the number of ECC bits stored with the data, an erase operation can increase the reliability of the memory die 200 by correcting bit errors before they accumulate to a level that can not be corrected by the ECC block 265.

[0071] The amount of detected or corrected errors determined during the execution of the erase operation can be indicative of a condition of the memory die 200 (e.g., corresponding to the integrity of data stored at the memory die 200). For example, a relatively lower amount of errors detected or corrected during the erase operation can be indicative of a good condition of the memory die 200 (e.g., corresponding to a relatively higher level of data integrity of the memory die 200). Alternatively, a relatively higher amount of errors detected or corrected during the erase operation can be indicative of a degraded or unsatisfactory condition of the memory die 200 (e.g., corresponding to a relatively lower level of data integrity of the memory die 200). In some cases, the local memory controller 260 can indicate the condition of the memory array to the host device (e.g., via the I / O 255). Further, the rate at which the erase operation is performed can correspond to the condition of the memory die 200. For example, as the condition of the memory die 200 degrades, the local memory controller 260 can perform the erase operation according to a faster rate. Increasing the erase rate based on the condition of the memory die 200 can increase the reliability of the memory die 200.

[0072] In some cases, the local memory controller 260 can be configured to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During the read operation, a logical state stored in a memory cell 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 260 can identify a target memory cell 205 on which to perform the read operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transfer a signal to the sense component 245 in response to biasing the access line. The sense component 245 can amplify the signal. The local memory controller 260 can trigger the sense component 245 (e.g., latch the sense component) and thereby compare the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sense component 245 can determine the logical state stored on the memory cell 205. As part of the read operation, the local memory controller 260 can transfer the logical state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155).

[0073] In some memory architectures, accessing memory cell 205 can degrade or destroy the logical state stored in memory cell 205. For example, activating a word line in a DRAM architecture can partially or fully discharge the capacitor of the target memory cell. Sensing component 245 can restore the voltage on digit line 215 according to the sensed logical state, which can restore the voltage on memory cell 205 to the same or similar voltage as used in the write operation. However, if a bit error occurs, meaning that sensing component 245 detects a bit that was written to a first value (e.g., 0 or 1) as a second, different value, the activation of the word line and the sensing operation will restore a different or incorrect bit value. Thus, once a bit error occurs, the incorrect value can be maintained in the memory cell until the data with the bit error is read out by on-die ECC (e.g., ECC block 265) or by the host controller and return write-corrected data (e.g., using embedded ECC) corrects the data.

[0074] Figure 3 An example of a system 300 that supports erase rate control for a memory device according to examples as disclosed herein is described. System 300 can include one or more components, etc., described herein with reference to Figure 1 and 2 For example, system 300 can include a host device 305, which can be an example of external memory controller 105 as described with reference to Figure 1 a memory device 310, which can be an example of memory device 110, memory die 160, or memory die 200 as described with reference to Figure 1 and 2 controller 155, one or more local memory controllers 165, or local memory controller 260 as described with reference to Figure 1 and 2 a memory array 370, which can be an example of memory array 170 as described with reference to Figure 1 error correction circuitry 320, which can be an example of local memory controller 260 or ECC block 265 as described with reference to Figure 2 as discussed with reference to Figure 1 Memory device 310 can also include a memory interface 315 and registers 325.

[0075] The host device 305 can send commands that can be received via the memory interface 315 to the memory device 310 over the CA channel 386. The commands can include access commands to perform one or more access operations (e.g., read operations, write operations, refresh operations, erase operations) at the memory array 370. The controller 360 can receive the commands from the memory interface 315, process the commands, and perform the commands on the memory array 370. The error correction circuitry 320 can perform one or more error correction operations on data associated with the access commands.

[0076] During a write operation, the host device 305 can send a write command to the memory interface 315 over the CA channel 386. The write command can include data to be written to the memory array 370 (e.g., sent via the DQ channel 390). The memory interface 315 can send the data to the controller 360, which can in turn transfer the data to the error correction circuitry 320. The error correction circuitry 320 can generate error correction information based on the data received from the controller 360. For example, the error correction circuitry 320 can generate parity or Hamming code information based on the data. The error correction circuitry 320 can transfer the error correction information to the controller 360 for storage at the memory array 370 along with the data. The controller 360 can store the data at the memory array 370 (e.g., at a location indicated by the write command received from the host device 305). The controller 360 can also store the error correction information at the memory array 370. In some cases, the error correction information can be stored at the same location as the data (e.g., same subarray, same row). In some other cases, the error correction information can be stored at a different portion of the memory array 370 than the data.

[0077] Memory device 310 can be configured to perform an erase operation (e.g., according to a particular ratio) in order to detect or correct errors in data stored at memory array 370. When performing the erase operation, controller 360 can read data from each of the rows of memory array 370. Controller 360 can also read error correction information (i.e., associated with the data) from memory array 370. Controller 360 can transmit both the data and the error correction information to error correction circuitry 320. Error correction circuitry 320 can perform an error correction operation based on the data to detect and / or correct errors associated with the data (e.g., due to leakage, parasitic coupling, or EMI). During the error correction operation, error correction circuitry 320 can generate error correction information based on the data received from controller 360. Error correction circuitry 320 can compare the received error correction information to the generated error correction information. In the event that the received error correction information and the generated error correction information do not match, error correction circuitry 320 can detect an error. In some cases, error correction circuitry 320 can generate correction data based on the error detected during the error correction operation.

[0078] In the event that error correction circuitry 320 generates correction data, error correction circuitry 320 can further transmit the correction data to controller 360. Here, controller 360 can transmit the correction data to memory array 370 for storage at memory array 370 (e.g., at the same row as the previously stored uncorrected data). That is, controller 360 can write the correction data to memory array 370.

[0079] In some cases, memory device 310 can perform an erase operation while performing other access operations. For example, memory device 310 can perform a refresh operation (e.g., based on a refresh command from host device 305, based on a refresh command generated by controller 360). The refresh operation can include controller 360 reading data from memory array 370, which can also restore the state of the memory cells of memory array 370 (e.g., based on the state detected by the sense amplifiers). Thus, the refresh operation can write back the same data as read from memory array 370, regardless of bit errors. However, in some cases, controller 360 can perform an erase operation while performing a refresh operation. Here, controller 360 can transmit the data read from memory array 370 for the refresh operation to error correction circuitry 320. Error correction circuitry 320 can perform an error correction operation on the data read from memory array 370 and transmit correction data back to controller 360. Controller 360 can write the correction data back to memory array 370, thus performing the erase operation as part of or in addition to performing the refresh operation.

[0080] Error correction circuitry 320 can further communicate an indication of the amount of errors detected during an error correction operation to controller 360. Controller 360 can monitor the amount of errors detected during each error correction operation to determine the amount of errors detected during an erase operation. Controller 360 can store the amount of errors detected during an erase operation at one of registers 325. For example, registers 325 can store the amount of bit errors detected for the last N erase operations. Registers 325 can be a first-in-first-out (FIFO) buffer, for example.

[0081] Based on the error metric determined from the amount of errors detected during an erase operation, controller 360 can determine a condition of memory array 370. The condition of memory array 370 can correspond to the integrity of the data stored at memory array 370 (e.g., a level of confidence in the accuracy of the data). For example, a first condition can correspond to a high level of integrity of the data stored at memory array 370, while a second condition can correspond to a lower level of integrity of the data stored at memory array 370. Each condition of memory array 370 can be based on one or more thresholds. The thresholds can be preset (e.g., preconfigured) thresholds. Additionally or alternatively, host device 305 can indicate one or more thresholds to controller 360. Here, the thresholds can be dynamic and can be configured by host device 305.

[0082] Controller 360 can determine the condition of memory array 370 by comparing the error metric to one or more thresholds (e.g., defining one or more ranges of errors). For example, controller 360 can utilize two thresholds to determine one of three possible conditions of memory array 370. Here, if the error metric is less than a first threshold (e.g., one hundred (100)), controller 360 can determine that the memory array is associated with a first condition. Further, if the error metric is between the first threshold and a second threshold (e.g., one thousand (1000)), controller 360 can determine that memory array 370 is associated with a second condition (e.g., corresponding to a lower level of integrity of the data stored at memory array 370). Additionally, if the error metric is greater than the second threshold, controller 360 can determine that memory array 370 is associated with a third condition.

[0083] In a first case, the error metric can correspond to the amount of errors detected within memory array 370, or a function (e.g., average, moving average, weighted average) of one or more amounts of errors (e.g., within a plurality of erase operations).

[0084] In a second case, the error condition can correspond to a detected change in the amount of errors. Here, the memory array 370 can receive an indication of the detected amount of errors from the error correction circuitry 320 and compare the detected amount of errors to the detected amount of errors detected during a previous erase operation. For example, the controller 360 can store the amount of errors detected during each erase operation at a register in the register 325. The controller 360 can then compare the amount of errors detected in the most recent erase operation to the amount stored within the register in the register 325 (e.g., corresponding to the amount of errors detected within the previous erase operation). Based on the difference between the amount of errors detected in the most recent erase operation and the previous erase operation, the controller 360 can determine a condition of the memory array 370. For example, the controller 360 can compare the difference to one or more threshold values corresponding to one or more conditions of the memory array 370.

[0085] In a third case, the controller 360 can determine a condition of the memory array 370 by comparing a current rate of change of the detected amount of errors to a previous rate of change of the detected amount of errors. Here, the controller 360 can determine a rate of change of the detected errors within a first (e.g., previous) time period and store an indication of the determined rate of change. For example, the controller 360 can store the indication of the determined rate of change in one of the registers 325. Based on the indicated amount of errors detected during the most recent erase operation and the previous amount of detected errors (e.g., stored at one or more of the registers 325), the controller 360 can determine a recent rate of change of the amount of errors detected within the most recent time period. The controller 360 can determine a condition of the memory array 370 by comparing the difference in the rate of change of the detected errors to one or more threshold values.

[0086] The memory device 310 can transmit an indicator of the condition of the memory array 370 to the host device 305 (e.g., over the condition indicator channel 392). In some cases, the condition indicator channel 392 can be dedicated to condition indication. Additionally or alternatively, the memory device 310 can output an indicator of the condition of the memory array 370 to a register (e.g., one of the registers 325) that can be polled by the host device 305.

[0087] The memory device 310 can perform an erase operation based on an erase command. Each erase command can be associated with one or more rows of the memory array 370 to be erased. In a first case, the memory device 310 can receive one or more erase commands from the host device over the CA channel 386. In a second case, the memory device 310 can generate each of the erase commands. Here, the controller 360 can generate the erase commands internally.

[0088] The rate at which the erase operation is performed can depend on the rate at which erase commands are received. In a first case, the rate at which the erase operation is performed can be based on the rate of erase commands (e.g., a higher rate for generating or receiving erase commands can correspond to a higher rate for performing erase operations). Additionally, the rate at which the erase operation is performed can be based on the amount of rows associated with each erase command (e.g., a greater amount of rows of the memory array 370 performed due to each erase command can correspond to a higher rate for performing erase operations). In either case, the rate at which the erase operation is performed can be based on the condition of the memory array 370. That is, if the controller 360 determines that the condition of the memory array 370 corresponds to a relatively high data integrity, the rate at which the erase operation is performed can be lower than if the controller 360 determines that the condition of the memory array 370 corresponds to a lower data integrity.

[0089] The memory device 310 can initially perform erase operations according to a nominal rate. The nominal rate can be a defined rate for performing erase operations (e.g., predefined, configured by the host device 305). That is, upon startup, the system 300 can perform erase operations according to the nominal rate (e.g., prior to determining the condition of the memory array 370). In some cases, the nominal rate can be based on the operating conditions of the system 300. For example, there can be different nominal rates defined for various temperatures of the memory device 310. That is, at extreme operating temperatures (e.g., temperatures exceeding 95 °C), the nominal rate can be higher than if the memory device is near room temperature. Additionally or alternatively, the nominal rate can be based on the voltage associated with the memory array 370.

[0090] As the controller 360 determines (and indicates to the host device 305) different conditions of the memory array 370, the rate at which erase operations are performed can change. In the case that the memory device 310 receives erase commands from the host device 305, as the indicated condition of the memory array 370 worsens, the host device 305 can transmit erase commands at a higher rate (e.g., compared to the nominal rate). Additionally or alternatively, each erase command can be associated with a greater number of rows of the memory array 370 to be erased. In the case that the memory device 310 generates erase commands, as the determined condition of the memory array 370 worsens, the controller 360 can generate (and perform) erase commands at a higher rate. Additionally or alternatively, as the determined condition of the memory array 370 worsens, the memory device 310 can erase a greater number of rows of the memory array 370 for each erase command.

[0091] If the controller determines and indicates a first condition of the memory array 370 (e.g., corresponding to a relatively high level of data integrity), the rate for performing the erase operation can correspond to a nominal rate. However, as the condition of the memory array 370 worsens, the memory device 310 can perform the erase operation at a higher rate (e.g., two (2) times, three (3) times, four (4) times the nominal rate). Thus, as the condition of the memory array 370 deteriorates, the memory device 310 can perform the erase operation at a higher rate. This can improve the reliability of the memory device 310.

[0092] Figure 4 An example of a process flow 400 that supports erase rate control for a memory device is described in accordance with examples as disclosed herein. The process flow 400 can implement aspects described with reference to Figures 1 to 3 The systems 100 and 300 and the memory die 200. The process flow 400 can include operations performed by a host device 405, which can be an example of a host device 305 as described with reference to Figure 3 The systems 100 and 300 and the memory die 200. The process flow 400 can include operations performed by a host device 405, which can be an example of a host device 305 as described with reference to Figure 1 The systems 100 and 300 and the memory die 200. The process flow 400 can include operations performed by a host device 405, which can be an example of a host device 305 as described with reference to Figures 1 to 3 The systems 100 and 300 and the memory die 200. The process flow 400 can include operations performed by a host device 405, which can be an example of a host device 305 as described with reference to

[0093] At 415, the memory device 410 can optionally receive a first plurality of erase commands from the host device 405 according to a first rate for erasing the memory array. Here, the memory device 410 can perform an erase operation based on receiving an erase command from the host device. In some examples, each of the plurality of erase commands can be associated with one or more of a plurality of rows of the memory array (e.g., according to a row counter). In some cases, the first rate can be based on a voltage or temperature, or both, associated with the memory array.

[0094] At 420, the memory device 410 can optionally receive an indication of a first rate for erasing the memory array from the host device 405, the first rate associated with a first condition of the memory array. The condition of the memory array can be associated with an integrity of data stored at the memory array.

[0095] At 425, the memory device 410 can optionally generate a first plurality of erase commands for erasing the memory array according to a first rate based on the first condition. For example, in cases where the memory device 410 does not receive an erase command from the host device 405, the memory device 410 can generate the first plurality of erase commands.

[0096] At 430, the memory device 410 can perform an erase operation. The erase operation can include the memory device 410 reading data and error correction information stored in each row of a plurality of rows of a memory array of the memory device 410, and detecting bit errors in the data on each based at least on the error correction information. The memory device 410 can further correct the bit errors in the data of each row based on detecting the bit errors in the data of each row. In some cases, performing the erase operation can be based on receiving the first plurality of erase commands (e.g., at 415). In some other cases, performing the erase operation can be based on generating the first plurality of erase commands (e.g., at 425). In some cases (e.g., when the host device 405 transmits an indication of a first rate), performing the erase operation is based on receiving an indication of a first rate for erasing the memory array. The indication of the first rate can be, for example, an amount of rows to be erased for each erase command received from the host device 405, or if the memory device 410 generates erase commands, the indication of the first rate can be a rate for generating erase commands or an amount of rows to be erased for each erase command. The memory device 410 can further receive a refresh command from the host device 405 according to a refresh rate of the memory device 410, and perform the erase operation based on performing a refresh operation. For example, the memory device 410 can perform the erase operation as part of the refresh command. In some examples, the refresh can be performed at a higher rate compared to the erase operation. For example, the refresh can be performed using an interval of 64 ms (every 64 ms, each row is refreshed), while the erase operation can be performed at a lower rate. In some examples where the erase operation is performed as part of the refresh, the erase operation can be performed on some portion of the refresh command. For example, for an erase rate of 1 second (at least once every 1 second interval, each row is erased), and a refresh rate of 64 ms, the memory device 410 can perform the erase operation on 1 / 16 of the refresh command (e.g., the erase operation is performed on 1 / 16 of the rows for every refresh cycle).

[0097] Additionally or alternatively, the memory device 410 can receive a plurality of erase commands over a period of time interspersed with access commands (e.g., corresponding to an erase rate). When the memory device 410 receives an access command (e.g., a read command), the memory device 410 can also perform an erase operation (e.g., a write back of corrected data) on the accessed row as part of the read command and can mark the row as erased, and thus can skip the accessed row when cycling through rows as part of the erase command. Additionally, a written row can also be skipped when cycling through rows as part of the erase command. That is, a full erase operation (erase of all rows) can be performed based on a combination of erase commands and access commands (e.g., read commands, write commands). In some cases, the order of rows or sets of rows for erase operations can be updated based on row accesses during the period of time for the erase operation to reflect the order of rows or sets of rows for the combination of access commands and erase commands. Thus, the next erase operation can follow a similar modified order, which can ensure that each row is erased or accessed according to the erase rate.

[0098] The memory device 410 can store error correction information for a plurality of rows of the memory array (e.g., when receiving a write command). Performing an erase operation can include the memory device 410 comparing the stored error correction information with error correction information generated from the stored data. When the memory device 410 performs an erase operation, for each of a plurality of erase commands, the memory device 410 can perform error correction operations for one or more of the plurality of rows to generate second data based on data read from the memory array and the error correction information. For each of the plurality of erase commands, the memory device 410 can further write the second data to one or more of the plurality of rows of the memory array. Here, for each of the plurality of erase commands, the memory device 410 can perform a read and correction of a first number of bit errors in the plurality of rows of the memory array.

[0099] At 435, the memory device 410 can monitor the number of bit errors detected for the plurality of rows of the erase operation during the erase operation. For example, the memory device 410 can count the amount of errors detected and / or corrected for each row.

[0100] At 440, the memory device 410 can determine, based on the monitoring, the amount of bit errors detected during the erase operation (e.g., a sum of the amount of errors detected and / or corrected for each row).

[0101] At 445, the memory device 410 can determine a condition of the memory array based on the amount of detected bit errors. In some cases, the memory device 410 can determine the condition of the memory array by comparing the amount of detected bit errors to one or more thresholds. Additionally or alternatively, the memory device 410 can determine the condition of the memory array by determining a difference between the amount of detected bit errors during the erase operation and a second amount of detected bit errors during a second erase operation performed prior to the erase operation.

[0102] In some other cases, the memory device 410 can determine the condition of the memory array by determining a rate of change of the amount of detected errors. For example, the memory device 410 can determine a first difference between the amount of detected bit errors during the erase operation and a second amount of detected bit errors during a second erase operation performed prior to the erase operation. The memory device 410 can further determine a second difference between respective amounts of detected bit errors during erase operations including at least one erase operation performed prior to the second erase operation. Here, the memory device 410 can determine the condition of the memory array based on determining a change between the first difference and the second difference.

[0103] In some instances, the memory device 410 determines the condition of the memory array based on determining that the condition of the memory array has changed from a first condition to a second condition associated with a lower integrity of data stored at the memory array compared to the first condition.

[0104] The memory device 410 can perform an action associated with the determined condition of the memory array. For example, performing the action can include the memory device 410 adjusting a rate for performing erase operations. In one case, the memory device 410 can increase a frequency of performing erase commands. In another case, the memory device 410 can increase a number of rows erased during performance of erase commands.

[0105] In some cases, performing the action can include transmitting an indicator of the condition of the memory array. For example, the memory device 410 can transmit an indicator of the condition of the memory array to the host device 405 at 450.

[0106] At 455, the memory device 410 can optionally receive a second plurality of erase commands from the host device 405. In some cases, the memory device 410 can receive the second plurality of erase commands according to a second rate for erasing the memory array that is greater than the first rate. That is, in cases where the memory device 410 performs erase operations based on erase commands received from the host device, the memory device 410 can receive the second plurality of erase commands from the host device 405. In some cases, the second rate can be based on the current condition of the memory array (e.g., as determined at 445). The memory device 410 can receive the second plurality of erase commands after receiving the first plurality of erase commands.

[0107] Additionally or alternatively, at 460, the memory device 410 can optionally generate a second plurality of erase commands for erasing the memory array according to a second rate that is greater than the first rate. That is, in cases where the memory device 410 performs erase operations based on erase commands generated at the memory device 410, the memory device 410 can generate the second plurality of erase commands. In some cases, the second rate can be based on the current condition of the memory array (e.g., as determined at 445). In some cases, the memory device 410 can generate the second plurality of erase commands after transmitting an indicator of the condition of the memory array. In some other cases, the memory device 410 can generate the second plurality of erase commands based on performing an action associated with the condition of the memory array. In some cases, the memory device 410 can determine the second rate for erasing the memory array based on determining that the condition of the memory array has changed from the first condition to the second condition.

[0108] At 465, the memory device 410 can optionally perform a second erase operation according to the second rate for erasing the memory array (e.g., after receiving the erase commands at 455 or generating the erase commands at 460). In some cases, performing the second erase operation can include the memory device 410 reading data and error correction information stored in each row of a plurality of rows of the memory array and correcting bit errors in the data of each row based on the error correction information. Here, performing the second erase operation can further include, for each of the second plurality of erase commands, the memory device 410 performing a second amount of reads and corrections of bit errors for a plurality of rows of the memory array. The second amount of rows can be greater than the first amount of rows.

[0109] Figure 5 An example of a process flow 500 that supports erase rate control for a memory device in accordance with examples as disclosed herein is described. The process flow 500 can implement operations performed by a host device 505, which can be as described with reference to Figures 1 to 3 The described systems 100 and 300 and memory die 200. The process flow 500 can include operations performed by a host device 505, which can be as described with reference toFigure 3 An example of a host device 305 is described. The host device 505 can implement aspects as described with reference to Figure 1 Aspects of an external memory controller 105 are described. The process flow 500 can further include operations performed by a memory device 510, which can be an example of a memory device 110, a memory array 170, or a memory die 200 or a memory device 310 as described with reference to Figures 1 to 3 Aspects of an external memory controller 105 are described. The process flow 500 can further include operations performed by a memory device 510, which can be an example of a memory device 110, a memory array 170, or a memory die 200 or a memory device 310 as described with reference to

[0110] At 515, the memory device 510 can optionally receive a configuration from the host device 505 for performing erase operations, the configuration indicating a first rate for erasing the memory array. The indication of the first rate can be, for example, an amount of rows to be erased for each erase command received from the host device 505, or if the memory device 510 generates erase commands, the indication of the first rate can be a rate for generating erase commands or an amount of rows to be erased for each erase command.

[0111] At 520, the memory device 510 can optionally receive a first plurality of erase commands from the host device according to the first rate for erasing the memory array from the host device 505. In some other cases, the memory device 510 can generate the first plurality of erase commands (e.g., based on configuration information). In either case, each of the erase commands can be associated with a portion of data stored in the memory array (e.g., according to a row counter).

[0112] At 525, the memory device 510 can perform a first set of erase operations. The erase operations can include the memory device 510 detecting or correcting bit errors in the memory array of the memory device 510 according to the first rate for erasing the memory array associated with a first condition of the memory array. In some cases, the memory device 510 can perform the first set of erase operations based on receiving the first plurality of erase commands (e.g., in a case where the memory device 510 receives the first plurality of erase commands from the host device 505 at 515).

[0113] While performing the erase operations, for each of the portions of data (e.g., indicated by each of the erase commands), the memory device 510 can read first data and error correction information from the memory array. For each of the portions of data, the memory device 510 can further perform an error correction operation on the first data read from the memory array to generate second data, where performing the error correction operation is based on the error correction information. For each of the portions of data, the memory device 510 can write the second data to the memory array, where performing each of the first set of erase operations is based on the writing.

[0114] At 530, the memory device 510 can determine an amount of bit errors detected during each erase operation in the first set of erase operations.

[0115] At 535, the memory device 510 can determine a second condition of the memory array associated with a second rate for erasing the memory array based on the amount of bit errors detected. The second condition of the memory array can correspond to a lower integrity of data stored at the memory array compared to the first condition of the memory array. Further, the second rate for erasing the memory array can be greater than the first rate for erasing the memory array.

[0116] The memory device 510 can determine the second condition of the memory array based on a comparison of the amount of bit errors detected during one of the first set of erase operations to one or more threshold values. Additionally or alternatively, the memory device 510 can determine the second condition of the memory array based on determining a difference between respective amounts of bit errors detected during a first erase operation and a second erase operation of the first set of erase operations. In some other examples, the memory device 510 can determine a first difference between respective amounts of bit errors detected during a first subset of the first set of erase operations. The memory device 510 can further determine a second difference between respective amounts of bit errors detected during a second subset of the first set of erase operations, the first set of erase operations including at least one erase operation performed after the first subset of the first set of erase operations. Here, the memory device 510 can determine the second condition of the memory array based on determining a change between the first difference and the second difference.

[0117] At 540, the memory device 510 can transmit an indicator of the second condition of the memory array to the host device 505.

[0118] At 545, the memory device 510 can receive a second plurality of erase commands from the host device according to the second rate for erasing the memory array from the host device 505.

[0119] At 550, the memory device 510 can optionally determine the second rate for erasing the memory array based on determining the second condition of the memory array (e.g., at 535). In this case, the memory device 510 can generate the second plurality of erase commands.

[0120] At 555, the memory device 510 can perform a second set of erase operations including detecting bit errors in the memory array according to a second rate for erasing the memory array. In some cases, the memory device 510 can perform the second set of erase operations based on receiving a second plurality of erase commands (e.g., in cases where the memory device 510 receives the second plurality of erase commands from the host device 505 at 545). Additionally or alternatively, the memory device 510 can perform the second set of erase operations based on determining the second rate for erasing the memory array.

[0121] Figure 6 A block diagram 600 showing a memory device 605 that supports erase rate control for a memory device according to examples as disclosed herein is demonstrated. The memory device 605 can be an example of aspects of the memory device as described with reference to Figure 1 and 3 to 5. The memory device 605 can include an erase operation manager 610, an error monitor 615, an error amount manager 620, a condition manager 625, an action manager 630, an erase command component 635, and an erase rate manager 640. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0122] The erase operation manager 610 can perform an erase operation at the memory device including reading data and error correction information stored in each row of a set of rows of a memory array of the memory device, and detecting bit errors in the data of each row based on the error correction information. In some cases, the erase operation manager 610 can correct the bit errors in the data of each row based on detecting the bit errors in the data of each row. In some examples, the erase operation manager 610 can receive a set of commands for accessing the memory array from a host device. The erase operation manager 610 can perform an operation indicated by the set of commands for accessing the memory array, where performing the erase operation is based on performing the operation. In some cases, for each of the set of erase commands, the erase operation manager 610 can perform an error correction operation on data read from the memory array of one or more of the set of rows to generate second data based on the error correction information. In some cases, for each of the set of erase commands, the erase operation manager 610 can write the second data to the one or more of the set of rows of the memory array. In some cases, performing the erase operation further includes the erase operation manager 610 comparing the data and the error correction information stored in each row of the set of rows of the memory array. The error correction information can be for a plurality of rows of the memory array and stored at the memory device.

[0123] In some examples, the erase operation manager 610 can perform a second erase operation according to a second rate for erasing the memory array. In some cases, performing the second erase operation can include the erase operation manager 610 reading data and error correction information stored in each row of the set of rows of the memory array and correcting bit errors in the data of each row based on the error correction information. Here, performing the second erase operation can include the erase operation manager 610 performing a read and correction of a second amount of bit errors in the set of rows of the memory array for each of the second set of erase commands, and where the second amount is greater than the first amount in the set of rows.

[0124] The error monitor 615 can monitor bit errors detected for the set of rows of the erase operation during the erase operation.

[0125] The error amount manager 620 can determine an amount of bit errors detected during the erase operation based on the monitoring.

[0126] The condition manager 625 can determine a condition of the memory array based on the amount of bit errors detected. In some cases, the condition of the memory array indicates an integrity of data stored at the memory array. In some examples, the condition manager 625 can compare the amount of bit errors detected to one or more thresholds, where determining the condition of the memory array is based on the comparison. In some cases, the condition manager 625 can determine a difference between the amount of bit errors detected during the erase operation and a second amount of bit errors detected during a second erase operation performed prior to the erase operation, where determining the condition of the memory array is based on the difference.

[0127] In some cases, the condition manager 625 can determine a first difference between the amount of bit errors detected during the erase operation and a second amount of bit errors detected during a second erase operation performed prior to the erase operation. The condition manager 625 can determine a second difference between respective amounts of bit errors detected during the erase operation that includes at least one erase operation performed prior to the second erase operation. In some examples, the condition manager 625 can determine a change between the first difference and the second difference, where determining the condition of the memory array is based on the change.

[0128] In some examples, the condition manager 625 can determine that the condition of the memory array has changed from a first condition to a second condition associated with a lower integrity of data stored at the memory array compared to the first condition, where determining the condition of the memory array is based on determining that the condition of the memory array has changed.

[0129] The action manager 630 can perform an action associated with a condition of the memory array by the memory device. In some cases, performing the action associated with the condition of the memory array can include transmitting an indicator of the condition of the memory array from the memory device to the host device.

[0130] The erase command component 635 can receive a first set of erase commands from the host device according to a first rate for erasing the memory array, where performing the erase operation is based on receiving the first set of erase commands. In some cases, the first rate is based on a voltage or a temperature, or a voltage and a temperature, associated with the memory array.

[0131] In some examples, the erase command component 635 can receive a second set of erase commands according to a second rate for erasing the memory array that is greater than the first rate. In some cases, the second rate is based on a second condition of the memory array. In some examples, the erase command component 635 can receive the second set of erase commands from the host device after receiving the first set of erase commands.

[0132] Additionally or alternatively, the erase command component 635 can generate a first set of erase commands for erasing the memory array according to a first rate based on the first condition by the memory device, where performing the erase operation is based on generating the first set of erase commands. In some examples, the erase command component 635 can generate a second set of erase commands for erasing the memory array by the memory device according to a second rate that is greater than the first rate based on performing the action associated with the condition of the memory array.

[0133] The erase rate manager 640 can receive an indication of a first rate for erasing the memory array from the host device, the first rate being associated with a first condition, where performing the erase operation is based on receiving the indication of the first rate for erasing the memory array. In some examples, the erase rate manager 640 can determine a second rate for erasing the memory array at the memory device based on determining that the condition of the memory array has changed from the first condition to a second condition.

[0134] The erase operation manager 610 can perform a first set of erase operations at the memory device according to a first rate for erasing the memory array associated with a first condition of the memory array, the first set of erase operations including detecting or correcting bit errors in the memory array of the memory device. In some examples, the erase operation manager 610 can perform a second set of erase operations according to a second rate for erasing the memory array, the second set of erase operations including detecting or correcting bit errors in the memory array. In some cases, the second rate for erasing the memory array is greater than the first rate for erasing the memory array. In some cases, the second rate for erasing the memory array is greater than a first rate for erasing the memory array based on performing the action associated with the condition of the memory array.

[0135] For each of the data portions, the erase operation manager 610 can read first data and error correction information from the memory array. In some cases, for each of the data portions, the erase operation manager 610 can perform an error correction operation on the first data read from the memory array to generate second data, where performing the error correction operation is based on the error correction information. In some cases, for each of the data portions, the erase operation manager 610 can write the second data to the memory array, where each of the first set of erase operations is performed based on the writing.

[0136] The error amount manager 620 can determine an amount of bit errors detected during each erase operation of the first set of erase operations.

[0137] The condition manager 625 can determine a second condition of the memory array associated with a second rate for erasing the memory array based on the amount of bit errors detected. In some cases, the second condition of the memory array corresponds to a lower integrity of data stored at the memory array compared to the first condition of the memory array. In some instances, the condition manager 625 can compare the amount of bit errors detected during one of the first set of erase operations to one or more threshold values, where determining the second condition of the memory array is based on the comparison. In some cases, the condition manager 625 can determine a difference between respective amounts of bit errors detected during a first erase operation and a second erase operation of the first set of erase operations, where the second condition of the memory array is based on the difference.

[0138] In some cases, the condition manager 625 can determine a first difference between respective amounts of bit errors detected during a first subset of the first set of erase operations. The condition manager 625 can determine a second difference between respective amounts of bit errors detected during a second subset of the first set of erase operations, the first set of erase operations including at least one erase operation performed after the first subset of the first set of erase operations. In some instances, the condition manager 625 can determine a change between the first difference and the second difference, where determining the second condition of the memory array is based on the change.

[0139] The action manager 630 can transmit, to the host device, an indicator of the second condition of the memory array.

[0140] The erase command component 635 can receive a set of erase commands from the host device, each erase command corresponding to one or more of the set of rows of the memory array. In some examples, the erase command component 635 can receive a set of erase commands from the host device, each erase command corresponding to a portion of data stored in the memory array. In some examples, the erase command component 635 can receive a first set of erase commands from the host device according to a first rate for erasing the memory array, where performing the first set of erase operations according to the first rate is based on receiving the first set of erase commands.

[0141] In some examples, the erase command component 635 can receive a second set of erase commands from the host device according to a second rate for erasing the memory array, where performing the second set of erase operations according to the second rate is based on receiving the second set of erase commands.

[0142] The erase rate manager 640 can receive a configuration for performing erase operations prior to performing the first set of erase operations, the configuration indicating a first rate for erasing the memory array. In some examples, the erase rate manager 640 can determine a second rate for erasing the memory array based on determining a second condition of the memory array, where performing the second set of erase operations is based on determining the second rate for erasing the memory array.

[0143] Figure 7 A flow diagram illustrating one or more methods 700 to support erase rate control for a memory device in accordance with examples as disclosed herein is shown. The operations of method 700 can be implemented by a memory device or its components as described herein. For example, the operations of method 700 can be performed by a memory device as described with reference to Figure 6 FIGS. 1 through 6B. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0144] At 705, the memory device can perform an erase operation at the memory device, including reading data and error correction information stored in each row of a set of rows of a memory array of the memory device, and detecting bit errors in the data of each row based on the error correction information. The operations of 705 can be performed according to the methods described herein. In some examples, aspects of the operations of 705 can be performed by an erase operation manager as described with reference to Figure 6 FIGS. 1 through 6B. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0145] At 710, the memory device can monitor bit errors detected for the set of rows of the erase operation during the erase operation. The operations of 710 can be performed according to the methods described herein. In some examples, aspects of the operations of 710 can be performed by an error monitor as described with reference to Figure 6 FIGS. 1 through 6B. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0146] At 715, the memory device can determine an amount of bit errors detected during the erase operation based on the monitoring. The operations of 715 can be performed according to the methods described herein. In some examples, aspects of the operations of 715 can be performed by an error amount manager as described with reference to Figure 6 FIG. 7.

[0147] At 720, the memory device can determine a condition of the memory array based on the amount of bit errors detected. The operations of 720 can be performed according to the methods described herein. In some examples, aspects of the operations of 720 can be performed by a condition manager as described with reference to Figure 6 FIG. 7.

[0148] At 725, the memory device can perform an action associated with the condition of the memory array. For example, the memory device can transmit an indicator of the condition of the memory array from the memory device to the host device. In another example, the memory device can increase a number of rows to be erased during execution of an erase command. In another example, the memory device can increase a rate at which the memory array is erased. The operations of 725 can be performed according to the methods described herein. In some examples, aspects of the operations of 725 can be performed by an indicator transmitter as described with reference to Figure 6 FIG. 7.

[0149] In some examples, an apparatus as described herein can perform one or more of the methods, such as the method 700. The apparatus can include features, means, or instructions for performing an erase operation at a memory device, the erase operation including reading data and error correction information stored in each row of a set of rows of a memory array of the memory device and detecting bit errors in the data of each row based on the error correction information, monitoring bit errors detected for the set of rows of the erase operation during the erase operation, determining an amount of bit errors detected during the erase operation based on the monitoring, determining a condition of the memory array based on the amount of bit errors detected, and performing, by the memory device, an action associated with the condition of the memory array.

[0150] Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for comparing the amount of bit errors detected to one or more thresholds, where determining the condition of the memory array can be based on the comparison.

[0151] Some instances of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for determining a difference between an amount of bit errors detected during the scrub operation and a second amount of bit errors detected during a second scrub operation performed prior to the scrub operation, where determining the condition of the memory array can be based on the difference.

[0152] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for determining a first difference between an amount of bit errors detected during the scrub operation and a second amount of bit errors detected during a second scrub operation performed prior to the scrub operation; determining a second difference between respective amounts of bit errors detected during the scrub operation, the scrub operation including at least one scrub operation performed prior to the second scrub operation; and determining a change between the first difference and the second difference, where determining the condition of the memory array can be based on the change.

[0153] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for storing error correction information for the set of rows of the memory array of the memory device, where performing the scrub operation further includes comparing data and the error correction information stored in each row of the plurality of rows of the memory array.

[0154] In some examples of the method 700, performing the action includes transmitting an indicator of the condition of the memory array from the memory device to the host device.

[0155] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for receiving a first set of scrub commands from the host device according to a first rate for scrubbing the memory array, where performing the scrub operation can be based on receiving the first set of scrub commands; and after transmitting the indicator of the condition of the memory array to the host device, receiving a second set of scrub commands from the host device according to a second rate for scrubbing the memory array that can be greater than the first rate.

[0156] Some instances of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for determining that the condition of the memory array can have changed from a first condition to a second condition associated with a lower integrity of data stored at the memory array compared to the first condition, where determining the condition of the memory array can be based on determining that the condition of the memory array can have changed.

[0157] In some examples of the method 700 and the apparatus described herein, the second rate can be based on the second condition of the memory array.

[0158] In some cases of the method 700 and the apparatus described herein, the first rate can be based on a voltage or a temperature, or a voltage and a temperature, associated with the memory array.

[0159] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for receiving, from the host device, an indication of a first rate for erasing the memory array, the first rate associated with a first condition, where performing the erase operation can be based on receiving the indication of the first rate for erasing the memory array; determining, at the memory device, a second rate for erasing the memory array based on determining that the condition of the memory array can have changed from the first condition to a second condition; and performing a second erase operation in accordance with the second rate for erasing the memory array.

[0160] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for generating, by the memory device, a first set of erase commands for erasing the memory array in accordance with a first rate based on the first condition, where performing the erase operation can be based on generating the first set of erase commands; and generating, by the memory device, a second set of erase commands based on performing an action associated with the condition of the memory array in accordance with a second rate that can be greater than the first rate.

[0161] Some cases of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for correcting bit errors in the data of each row based on detecting the bit errors in the data of each row.

[0162] In some examples of the method 700 and the apparatus described herein, performing the erase operation can include operations, features, means, or instructions for receiving, from the host device, a set of erase commands, each erase command corresponding to one or more of the set of rows of the memory array; for each of the set of erase commands, performing an error correction operation on data read from the memory array of the one or more of the set of rows to generate second data based on error correction information; and for each of the set of erase commands, writing the second data to the one or more of the set of rows of the memory array.

[0163] In some cases of the methods 700 and the apparatuses described herein, performing the erase operation can include operations, features, means, or instructions for receiving a second set of erase commands from the host device after receiving the first set of erase commands, and performing a second erase operation based on performing the action associated with the condition of the memory array, including reading data and error correction information stored in each row of the set of rows of the memory array, and correcting bit errors in the data of each row based on the error correction information, where performing the second erase operation can include operations, features, means, or instructions for, for each of the second set of erase commands, performing a read and correction of a second quantity of bit errors of the set of rows of the memory array, and where the second quantity of the set of rows can be greater than the first quantity of the set of rows.

[0164] Some examples of the methods 700 and the apparatuses described herein can further include operations, features, means, or instructions for receiving a set of commands from the host device for accessing the memory array, and performing operations indicated by the set of commands for accessing the memory array, where performing the erase operation can be based on performing the operations.

[0165] In some examples of the methods 700 and the apparatuses described herein, the condition of the memory array indicates an integrity of data stored at the memory array.

[0166] Figure 8 A flow diagram illustrating one or more methods 800 that support erase rate control for memory devices in accordance with examples as disclosed herein is shown. The operations of method 800 can be implemented by a memory device or its components as described herein. For example, the operations of method 800 can be performed by a memory device as described with reference to Figs. 1-2, 4, and 5 A-5C according to examples as disclosed herein. As illustrated, the method 800 includes receiving a set of erase commands from a host device at 805. Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of a memory device to perform described functions. Additionally or alternatively, a memory device can perform aspects of the described functions using special-purpose hardware.

[0167] At 805, the memory device can perform an erase operation at the memory device, including reading data and error correction information stored in each row of a set of rows of a memory array of the memory device, and detecting bit errors in the data of each row based on the error correction information. The operations of 805 can be performed according to the methods described herein. In some examples, aspects of the operations of 805 can be performed by an erase operation manager as described with reference to Figs. 1-2, 4, and 5 A-5C according to examples as disclosed herein. Figure 6

[0168] At 810, the memory device can monitor bit errors detected for the set of rows of the erase operation during the erase operation. The operations of 810 can be performed according to the methods described herein. In some examples, aspects of the operations of 810 can be performed by an erase operation manager as described with reference to Figs. 1-2, 4, and 5 A-5C according to examples as disclosed herein.​Figure 6 The error monitor described is executed.

[0169] At 815, the memory device can determine an amount of bit errors detected during the erase operation based on the monitoring. The operations of 815 can be performed according to the methods described herein. In some examples, aspects of the operations of 815 can be performed by an error amount manager as described with reference to Figure 6 FIG. 7.

[0170] At 820, the memory device can compare the amount of detected bit errors to one or more thresholds. The operations of 820 can be performed according to the methods described herein. In some examples, aspects of the operations of 820 can be performed by a condition manager as described with reference to Figure 6 FIG. 7.

[0171] At 825, the memory device can determine a condition of the memory array based on the amount of detected bit errors, where determining the condition of the memory array is based on the comparison. The operations of 825 can be performed according to the methods described herein. In some examples, aspects of the operations of 825 can be performed by a condition manager as described with reference to Figure 6 FIG. 7.

[0172] At 830, the memory device can perform an action associated with the condition of the memory array. For example, the memory device can transmit an indicator of the condition of the memory array from the memory device to a host device. In another example, the memory device can increase a number of rows to be erased during execution of an erase command. In another example, the memory device can increase a rate at which the memory array is erased. The operations of 830 can be performed according to the methods described herein. In some examples, aspects of the operations of 830 can be performed by an indicator transmitter as described with reference to Figure 6 FIG. 7.

[0173] Figure 9 A flow diagram illustrating an example of a method 900 to support one or more methods for erase rate control for a memory device as disclosed herein is shown. The operations of method 900 can be implemented by a memory device or its components as described herein. For example, the operations of method 900 can be performed by a memory device as described with reference to Figure 6 FIG. 7. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0174] At 905, the memory device can perform an erase operation at the memory device, including reading data and error correction information stored in each row of a set of rows of a memory array of the memory device, and detecting bit errors in the data of each row based on the error correction information. The operations of 905 can be performed according to the methods described herein. In some examples, aspects of the operations of 905 can be performed by an erase operation manager as described with reference to Figure 6 FIG. 7.

[0175] At 910, the memory device can monitor bit errors detected for the set of rows of the erase operation during the erase operation. The operations of 910 can be performed according to the methods described herein. In some examples, aspects of the operations of 910 can be performed by an error monitor as described with reference to Figure 6 FIG. 7.

[0176] At 915, the memory device can determine an amount of bit errors detected during the erase operation based on the monitoring. The operations of 915 can be performed according to the methods described herein. In some examples, aspects of the operations of 915 can be performed by an error amount manager as described with reference to Figure 6 FIG. 7.

[0177] At 920, the memory device can determine a difference between the amount of bit errors detected during the erase operation and a second amount of bit errors detected during a second erase operation performed prior to the erase operation. The operations of 920 can be performed according to the methods described herein. In some examples, aspects of the operations of 920 can be performed by a condition manager as described with reference to Figure 6 FIG. 7.

[0178] At 925, the memory device can determine a condition of the memory array based on the amount of bit errors detected, where determining the condition of the memory array is based on the difference. The operations of 925 can be performed according to the methods described herein. In some examples, aspects of the operations of 925 can be performed by a condition manager as described with reference to Figure 6 FIG. 7.

[0179] At 930, the memory device can perform an action associated with the condition of the memory array. For example, the memory device can transmit an indicator of the condition of the memory array from the memory device to a host device. In another example, the memory device can increase a number of rows to be erased during an execution of an erase command. In another example, the memory device can increase a rate at which the memory array is erased. The operations of 930 can be performed according to the methods described herein. In some examples, aspects of the operations of 930 can be performed by an indicator transmitter as described with reference to Figure 6 FIG. 7.

[0180] Figure 10A flow diagram illustrating supporting one or more methods 1000 for erase rate control for a memory device according to examples as disclosed herein is shown. The operations of method 1000 can be implemented by a memory device or its components as described herein. For example, the operations of method 1000 can be performed by a memory device as described with reference to Figure 6 FIG. 1 in some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0181] At 1005, the memory device can perform an erase operation at the memory device, including reading data and error correction information stored in each row of a set of rows of a memory array of the memory device, and detecting bit errors in the data of each row based on the error correction information. The operations of 1005 can be performed according to the methods described herein. In some examples, aspects of the operations of 1005 can be performed by an erase operation manager as described with reference to Figure 6 FIG. 1.

[0182] At 1010, the memory device can monitor bit errors detected for the set of rows of the erase operation during the erase operation. The operations of 1010 can be performed according to the methods described herein. In some examples, aspects of the operations of 1010 can be performed by an error monitor as described with reference to Figure 6 FIG. 1.

[0183] At 1015, the memory device can determine an amount of bit errors detected during the erase operation based on the monitoring. The operations of 1015 can be performed according to the methods described herein. In some examples, aspects of the operations of 1015 can be performed by an error amount manager as described with reference to Figure 6 FIG. 1.

[0184] At 1020, the memory device can determine a first difference between the amount of bit errors detected during the erase operation and a second amount of bit errors detected during a second erase operation performed prior to the erase operation. The operations of 1020 can be performed according to the methods described herein. In some examples, aspects of the operations of 1020 can be performed by a condition manager as described with reference to Figure 6 FIG. 1.

[0185] At 1025, the memory device can determine a second difference between respective amounts of bit errors detected during the erase operation, the erase operation including at least one erase operation performed prior to the second erase operation. The operations of 1025 can be performed according to the methods described herein. In some examples, aspects of the operations of 1025 can be performed by a condition manager as described with reference to Figure 6 FIG. 1.

[0186] At 1030, the memory device can determine a change between the first difference and the second difference. The operations of 1030 can be performed according to the methods described herein. In some examples, aspects of the operations of 1030 can be performed by a condition manager as described with reference to Figure 6

[0187] At 1035, the memory device can determine a condition of the memory array based on the amount of detected bit errors, wherein determining the condition of the memory array is based on the change. The operations of 1035 can be performed according to the methods described herein. In some examples, aspects of the operations of 1035 can be performed by a condition manager as described with reference to Figure 6

[0188] At 1040, the memory device can transmit an indicator of the condition of the memory array from the memory device to the host device. The operations of 1040 can be performed according to the methods described herein. In some examples, aspects of the operations of 1040 can be performed by an indicator transmitter as described with reference to Figure 11

[0189] Figure 6 A flow diagram illustrating a method or methods 1100 that support erase rate control for a memory device in accordance with examples as disclosed herein is shown. The operations of method 1100 can be implemented by a memory device or its components as described herein. For example, the operations of method 1100 can be performed by a memory device as described with reference to Figure 6 In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0190] At 1105, the memory device can perform a first set of erase operations at the memory device according to a first rate for erasing the memory array associated with a first condition of the memory array, the first set of erase operations including detecting bit errors in a memory array of the memory device. The operations of 1105 can be performed according to the methods described herein. In some examples, aspects of the operations of 1105 can be performed by an erase operation manager as described with reference to Figure 6

[0191] At 1110, the memory device can determine an amount of bit errors detected during each erase operation of the first set of erase operations. The operations of 1110 can be performed according to the methods described herein. In some examples, aspects of the operations of 1110 can be performed by an error amount manager as described with reference to Figure 6

[0192] ​​​​​At 1115, the memory device may determine a second condition of the memory array associated with a second rate for erasing the memory array based on one or more of the amounts of bit errors detected. The operations of 1115 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to ​ Aspects of the operations of the condition manager execution 1115 are described.

[0193] At 1120, the memory device may perform a second set of erase operations, including detecting bit errors in the memory array according to a second rate for erasing the memory array. The operations of 1120 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to ​ The erase operations manager performs aspects of the operations of 1120 as described.

[0194] In some examples, an apparatus as described herein may perform one or more methods, such as method 1100. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing a first set of erase operations at a memory device, including detecting bit errors in a memory array of the memory device according to a first rate for erasing the memory array associated with a first condition of the memory array; determining an amount of bit errors detected during each erase operation in the first set of erase operations; determining a second condition of the memory array associated with a second rate for erasing the memory array based on one or more of the amounts of detected bit errors; and performing a second set of erase operations, including detecting bit errors in the memory array according to the second rate for erasing the memory array.

[0195] Some examples of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for transmitting an indicator of the second condition of the memory array to a host device.

[0196] Some aspects of the method 1100 and apparatus described herein may further include operations, features, devices, or instructions for: receiving a first set of erase commands from a host device according to a first rate for erasing the memory array, wherein performing the first set of erase operations according to the first rate may be based on receiving the first set of erase commands; and receiving a second set of erase commands from the host device according to a second rate for erasing the memory array, wherein performing the second set of erase operations according to the second rate may be based on receiving the second set of erase commands.

[0197] Some examples of the method 1100 and the apparatus described herein can further include operations, features, means, or instructions for receiving a configuration for performing erase operations prior to performing the first set of erase operations, the configuration indicating a first rate for erasing the memory array, and determining a second rate for erasing the memory array based on determining the second condition of the memory array, where performing the second set of erase operations can be based on determining the second rate for erasing the memory array.

[0198] In some cases of the method 1100 and the apparatus described herein, the second condition of the memory array can correspond to a lower integrity of data stored at the memory array compared to the first condition of the memory array, and the second rate for erasing the memory array can be greater than the first rate for erasing the memory array.

[0199] Some examples of the method 1100 and the apparatus described herein can further include operations, features, means, or instructions for comparing an amount of bit errors detected during one of the first set of erase operations to one or more thresholds, where determining the second condition of the memory array can be based on the comparison.

[0200] Some examples of the method 1100 and the apparatus described herein can further include operations, features, means, or instructions for determining a difference between respective amounts of bit errors detected during a first erase operation and a second erase operation of the first set of erase operations, where determining the second condition of the memory array can be based on the difference.

[0201] Some cases of the method 1100 and the apparatus described herein can further include operations, features, means, or instructions for determining a first difference between respective amounts of bit errors detected during a first subset of the first set of erase operations, determining a second difference between respective amounts of bit errors detected during a second subset of the first set of erase operations, the first set of erase operations including at least one erase operation performed after the first subset of the first set of erase operations, and determining a change between the first difference and the second difference, where determining the second condition of the memory array can be based on the change.

[0202] Some examples of the method 1100 and apparatus described herein can further include operations, features, means, or instructions for receiving, from the host device, a set of erase commands, each erase command corresponding to a portion of data stored in the memory array, reading, from the memory array, first data and error correction information for each of the portions of data, performing an error correction operation on the first data read from the memory array for each of the portions of data to generate second data, where performing the error correction operation can be based on the error correction information, and writing the second data to the memory array for each of the portions of data, where performing each of the first set of erase operations can be based on the writing.

[0203] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0204] In some examples, a device with erase rate control for a memory device can perform aspects of the functions described herein using special-purpose hardware. The device can include an array of memory cells, circuitry coupled with the array of memory cells. The circuitry can be to cause the device to monitor, during an erase operation, bit errors detected for the set of rows of the erase operation, determine, based on the monitoring, an amount of bit errors detected during the erase operation, determine, based on the amount of bit errors detected, a condition of the array of memory cells, and perform, by the device, an action associated with the condition of the array of memory cells.

[0205] In some cases, the circuitry can be further to cause the device to transmit, to the host device, an indicator of the condition of the array of memory cells based on performing the action associated with the condition of the array of memory cells.

[0206] In some cases, the circuitry can be further to cause the device to receive, from the host device, a first set of erase commands according to a first rate for erasing the array of memory cells, where performing the erase operation can be based on receiving the first set of erase commands, and receive, from the host device, a second set of erase commands according to a second rate for erasing the array of memory cells that can be greater than the first rate after transmitting the indicator of the condition of the array of memory cells to the host device.

[0207] In some cases, the circuitry can be further to cause the device to receive a first set of erase commands from the host device, where performing the erase operation includes, for each of the first set of erase commands, performing a read and detection of a first quantity of bit errors of the set of rows of the memory cell array. The circuitry can be to cause the device to receive a second set of erase commands from the host device after receiving the first plurality of erase commands; and perform a second erase operation based on performing an action associated with a condition of the memory array, including reading data and error correction information stored in each row of the set of rows of the memory cell array, and detecting bit errors in the data of each row based on the error correction information, where performing the second erase operation includes, for each of the second set of erase commands, performing a read and detection of a second quantity of bit errors of the set of rows of the memory cell array, and where the second quantity of the set of rows can be greater than the first quantity of the set of rows.

[0208] In some examples, the circuitry can be further to cause the device to compare the quantity of detected bit errors to one or more thresholds, where determining the condition of the memory cell array can be based on the comparison.

[0209] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0210] The terms "electronic communication," "electrically conductive contact," "connected," and "coupled" can refer to a relationship between components in which an electrical signal is supported to flow between the components. Components are considered to be in electronic communication with each other (or in electrically conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of an electrical signal between the components at any time. The conductive path between components that are in electronic communication with each other (or in electrically conductive contact or connected or coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some cases, the flow of a signal between connected components can be interrupted for a period of time, for example, using one or more intervening components such as switches or transistors.

[0211] The term "coupled" refers to a condition of being moved from an open- circuit relationship between components, in which a signal cannot currently pass between the components through a conductive path, to a closed-circuit relationship between the components, in which a signal can pass between the components through a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows a signal to flow between the other components via a conductive path through which the signal was not previously permitted to flow.

[0212] The term "isolated" refers to a relationship between components in which a signal cannot currently flow between the components. If there is an open circuit between the components, the components are isolated from each other. For example, components that are isolated from each other by a switch positioned between the two components are isolated from each other when the switch is open. When a controller decouples two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path through which the signal was previously permitted to flow.

[0213] Devices including memory arrays discussed herein can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0214] Switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive material such as metal. The source and drain can be conductive and can include heavy doping such as degenerate semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., the majority of carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0215] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to provide an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0216] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference label to refer to the first instance of a component and a second reference label to refer to the second instance of the component. If only the first reference label is used in the description, it is also intended to cover the second instance of the component, and vice versa.

[0217] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0218] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0219] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a referral to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0220] Computer-readable media includes both non-transitory computer storage media, and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0221] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: performing an erase operation at a memory device, the erase operation comprising reading data stored in one or more rows of the memory device and detecting errors in the data of the one or more rows based at least in part on reading the data; counting an amount of errors during the erase operation based at least in part on reading the data stored in the one or more rows and detecting the errors in the data of the one or more rows; comparing the amount of errors to two or more thresholds associated with three or more ranges, each of the three or more ranges being associated with a respective one of three or more conditions associated with the memory device; as well as An indicator of the amount of the error is output by the memory device based at least in part on the comparison, the outputting being based at least in part on a condition of the three or more conditions and a range of the three or more ranges, wherein the condition of the three or more conditions and the range of the three or more ranges are indicative of the integrity of the data stored at the one or more rows of the memory device.

2. The method of claim 1 , wherein outputting the indicator comprises: The amount of the error is stored in a register of the memory device.

3. The method of claim 1 , wherein outputting the indicator comprises: The indicator of the amount of the errors is sent from the memory device to a host device coupled to the memory device.

4. The method of claim 1, wherein the erase operation further comprises reading error correction information stored in the one or more rows of the memory device, wherein the error in the data is detected based at least in part on reading the error correction information.

5. The method according to claim 4, further comprising: correcting the errors detected in the data of the one or more rows based at least in part on reading the data and the error correction information; as well as The error correction information and the data are written to the one or more rows of the memory device based at least in part on correcting the error.

6. The method according to claim 1, further comprising: receiving one or more write commands from a host device coupled to the memory device, wherein the one or more write commands include second data to be written to one or more second rows of the memory device; generating error correction information based at least in part on the second data in the one or more write commands; as well as The error correction information and the second data are written to one or more second rows of the memory device based at least in part on generating the error correction information.

7. The method according to claim 1, further comprising: receiving, from a host device coupled to the memory device, a set of commands for accessing the one or more rows of the memory device; as well as Operations indicated by the set of commands for accessing the one or more rows of the memory device are performed, wherein the erase operation is performed based at least in part on performing the operations.

8. The method according to claim 1, further comprising: A difference is determined between the amount of errors detected during the erase operation and a second amount of errors detected during a second erase operation that precedes the erase operation, wherein an indicator of the amount of errors is output based at least in part on the difference.

9. The method according to claim 1, further comprising: determining a first difference between the amount of errors detected during the erase operation and a second amount of errors detected during a second erase operation that precedes the erase operation; determining a second difference between respective amounts of errors detected during erase operations including at least one erase operation performed prior to the second erase operation; as well as detecting a change between the first difference and the second difference, Wherein the indicator of the amount of the error is output based at least in part on the change.

10. The method according to claim 9, further comprising: receiving, from a host device coupled to the memory device, an indication of a first rate for erasing the one or more rows of the memory device, the first rate being associated with the condition, wherein the erase operation is performed based at least in part on receiving the indication of the first rate for erasing the one or more rows of the memory device; determining, at the memory device, a second rate for erasing the one or more rows of the memory device based at least in part on determining that the condition of the three or more conditions has changed from the first condition to a second condition, the second condition being associated with lower integrity of data stored at the one or more rows compared to the first condition; as well as A third erase operation is performed according to the second rate for erasing the one or more rows.

11. The method of claim 1 , wherein performing the erase operation comprises: receiving a plurality of erase commands from a host device coupled to the memory device, each of the plurality of erase commands corresponding to at least one of the one or more rows of the memory device; for each of the plurality of erase commands, performing an error correction operation on the data read from the one or more rows of the memory device for the at least one row to generate second data based at least in part on error correction information; as well as For each of the plurality of erase commands, the second data is written to the at least one row of the one or more rows of the memory device.

12. The method of claim 11 , wherein performing the erase operation comprises: For each of the plurality of erase commands, performing the reading of a first amount and the correcting of the errors in the one or more rows of the memory device, the method further comprising: receiving a second plurality of erase commands from the host device after receiving the first plurality of erase commands; and performing a second erase operation based at least in part on outputting the indicator of the amount of errors, the second erase operation comprising reading the data and the error correction information stored in each of the one or more rows of the memory device and correcting errors in the data of each row based at least in part on the error correction information, wherein performing the second erase operation comprises performing the reading and the correction of the errors in a second amount of the one or more rows of the memory device for each of the second plurality of erase commands, and wherein the second amount in the one or more rows is greater than the first amount in the one or more rows.

13. A device comprising: at least one memory device; as well as at least one controller coupled to the at least one memory device and configured to cause the apparatus to: performing an erase operation at a memory device, the erase operation comprising reading data stored in one or more rows of the memory device and detecting errors in the data of the one or more rows based at least in part on reading the data; counting an amount of errors during the erase operation based at least in part on reading the data stored in the one or more rows and detecting the errors in the data of the one or more rows; comparing the amount of errors to two or more thresholds associated with three or more ranges, each of the three or more ranges being associated with a respective one of three or more conditions associated with the memory device; as well as An indicator of the amount of the error is output by the memory device based at least in part on the comparison, the outputting being based at least in part on a condition of the three or more conditions and a range of the three or more ranges, wherein the condition of the three or more conditions and the range of the three or more ranges are indicative of the integrity of the data stored at the one or more rows of the memory device.

14. The apparatus of claim 13, wherein the apparatus further comprises: register, wherein the at least one controller is coupled to the register, and to output the indicator, the at least one controller is further configured to cause the apparatus to: The amount of the error is stored to the register of the memory device.

15. The apparatus of claim 13, wherein the memory device further comprises: a memory interface coupled to a host device, wherein the at least one controller is coupled to the memory interface, and to output the indicator, the at least one controller is further configured to cause the apparatus to: The indicator of the amount of errors is sent to the host device via the memory interface.

16. The apparatus of claim 13, wherein the erase operation further comprises reading error correction information stored in the one or more rows of the memory device, wherein the error in the data is detected based at least in part on reading the error correction information.

17. The apparatus of claim 16, wherein the apparatus further comprises: error correction circuitry, wherein the at least one controller is coupled to the error correction circuitry and is further configured to cause the apparatus to: correcting, by the error correction circuitry, the errors detected in the data of the one or more rows based at least in part on reading the data and the error correction information; as well as The error correction information and the data are written to the one or more rows of the memory device based at least in part on correcting the error.

18. The apparatus of claim 13, wherein the apparatus further comprises: error correction circuitry, wherein the at least one controller is coupled to the error correction circuitry and is further configured to cause the apparatus to: receiving, at the at least one controller, one or more write commands from a host device coupled to the memory device, wherein the one or more write commands include second data to be written to one or more second rows of the memory device; generating, at the at least one controller, error correction information based at least in part on the second data in the one or more write commands; as well as The error correction information and the second data are written to one or more second rows of the memory device based at least in part on generating the error correction information.

19. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by at least one processor of an electronic device, cause the electronic device to: performing an erase operation at a memory device, the erase operation comprising reading data stored in one or more rows of the memory device and detecting errors in the data of the one or more rows based at least in part on reading the data; counting an amount of errors during the erase operation based at least in part on reading the data stored in the one or more rows and detecting the errors in the data of the one or more rows; comparing the amount of errors to two or more thresholds associated with three or more ranges, each of the three or more ranges being associated with a respective one of three or more conditions associated with the memory device; as well as An indicator of the amount of the error is output by the memory device based at least in part on the comparison, the outputting being based at least in part on a condition of the three or more conditions and a range of the three or more ranges, wherein the condition of the three or more conditions and the range of the three or more ranges are indicative of the integrity of the data stored at the one or more rows of the memory device.

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