Non-volatile semiconductor memory device and electronic equipment

Abstract

The present invention relates to the technical field of flash memory, and specifically discloses a non-volatile semiconductor storage device and an electronic device, including: a storage cell array, a high-voltage switch array, and a page buffer array. The page buffer array is connected to the storage cell array through the high-voltage switch array. Each high-voltage switch unit includes a plurality of high-voltage switch modules arranged in sequence along the second horizontal direction of the first plane. Each high-voltage switch module is connected to the corresponding page buffer and storage cell through its respective corresponding connection line unit; the connection manners of every two adjacent high-voltage switch modules in each high-voltage switch unit with their respective corresponding connection line units are all different so that the voltage difference between the adjacent terminals of every two adjacent high-voltage switch modules is less than a preset threshold. The non-volatile semiconductor storage device provided by the present invention can avoid the occurrence of avalanche phenomenon without increasing the chip size.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory, and in particular to a non-volatile semiconductor storage device and an electronic device. Background Art

[0002] Semiconductor memories can be roughly divided into volatile semiconductor memories and non-volatile semiconductor memories. Volatile semiconductor memories have fast read and write speeds, but the disadvantage is that the stored content will be lost once the power is turned off. In contrast, non-volatile semiconductor memories can save content even if the power supply is stopped. Therefore, non-volatile semiconductor memories are used to store content that needs to be saved regardless of whether the power supply is on or off, and flash memory is a representative example of non-volatile memory.

[0003] Flash memory devices require a higher voltage (VPP) than the power supply voltage (VDD) to operate. When the memory cell is erased, a high voltage of more than 20V is required. The layout distance between two adjacent high-voltage switch devices in the existing multiple high-voltage switch devices will produce a voltage difference and may cause avalanche phenomenon. If the layout distance between two adjacent high-voltage switch devices is increased, the chip size will increase.

[0004] Therefore, how to avoid the occurrence of avalanche phenomenon without increasing the chip size has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The present invention provides a non-volatile semiconductor storage device and an electronic device, which solve the problem in the related art that the avalanche phenomenon cannot be avoided without increasing the chip size.

[0006] As a first aspect of the present invention, a nonvolatile semiconductor memory device is provided, comprising: a memory cell array, a high voltage switch array and a page buffer array, wherein the page buffer array is connected to the memory cell array through the high voltage switch array, the memory cell array comprises a plurality of memory cells sequentially arranged along a first horizontal direction, the high voltage switch array comprises a plurality of high voltage switch units sequentially arranged along the first horizontal direction, the page buffer array comprises a plurality of page buffers sequentially arranged along the first horizontal direction, and the page buffers correspond to the high voltage switch units and to the memory cells in a one-to-one manner;

[0007] Each of the high-voltage switch units includes a plurality of high-voltage switch modules arranged in sequence along a second horizontal direction of the first plane, and each high-voltage switch module is connected to a corresponding page buffer and a storage unit through a corresponding connection line unit;

[0008] The connection line units corresponding to each high-voltage switch module extend along the second horizontal direction of the second plane, and the connection line units of multiple high-voltage switch modules in the same high-voltage switch unit are sequentially arranged at intervals along the first horizontal direction of the second plane, where the first plane and the second plane are stacked in the vertical direction, the first horizontal direction is perpendicular to the second horizontal direction, and both the first horizontal direction and the second horizontal direction are perpendicular to the vertical direction;

[0009] The connection modes of each adjacent two high-voltage switch modules in each high-voltage switch unit with their respective corresponding connection line units are all different so that the voltage difference between the adjacent terminals of each adjacent two high-voltage switch modules is less than a preset threshold.

[0010] Further, each high-voltage switch module includes a control terminal, a first terminal, and a second terminal extending along the first horizontal direction. The first terminal and the second terminal are respectively located on both sides of the control terminal in the second horizontal direction and are spaced apart from the control terminal;

[0011] The first terminal and the second terminal are connected to the connection line unit corresponding to the high-voltage switch module where they are located through a voltage line unit, and the connection modes of the voltage line units of each adjacent two high-voltage switch modules are all different.

[0012] Further, the connection line unit includes a storage unit connection line and a page buffer input / output connection line. The storage unit connection line and the page buffer input / output connection line are respectively located on both sides of the control terminal,

[0013] For any adjacent two high-voltage switch modules in the same high-voltage switch unit, when the first terminal of one high-voltage switch module is connected to the storage unit connection line through a voltage line unit and the second terminal is connected to the page buffer input / output connection line through a voltage line unit, the first terminal of the other high-voltage switch module is connected to the page buffer input / output connection line through a voltage line unit and the second terminal is connected to the storage unit connection line through a voltage line unit, so that the voltage difference between the voltage line units of the adjacent two terminals of the adjacent two high-voltage switch modules is less than a preset threshold.

[0014] Further, the voltage line unit includes a first voltage line and a second voltage line. The first voltage line is configured with a working voltage, and the second voltage line is configured with a supply voltage. The voltage value of the working voltage is higher than that of the supply voltage,

[0015] For any two adjacent high-voltage switch modules in the same high-voltage switch unit, when the first terminal of one high-voltage switch module is connected to the storage unit connection line through the first voltage line and the second terminal is connected to the page buffer input / output connection line through the second voltage line, the first terminal of the other high-voltage switch module is connected to the page buffer input / output connection line through the second voltage line and the second terminal is connected to the storage unit connection line through the first voltage line, so that the voltage difference between the two adjacent terminals of the two adjacent high-voltage switch modules is 0.

[0016] Further, the first voltage line and the second voltage line are in different planes from the first terminal, the second terminal, and the connection line unit.

[0017] One end of the first voltage line is connected to the storage unit connection line to form a first overlapping contact point, the other end of the first voltage line is connected to the first terminal or the second terminal to form a second overlapping contact point, one end of the second voltage line is connected to the page buffer input / output connection line to form a third overlapping contact point, and the other end of the second voltage line is connected to the second terminal or the first terminal to form a fourth overlapping contact point.

[0018] Further, the operating voltage includes an erase voltage, and the power supply voltage includes voltage VDD or voltage VSS.

[0019] Further, the high-voltage switch module includes a high-voltage transistor, the control terminal includes a gate terminal, when the first terminal includes a source terminal, the second terminal includes a drain terminal, and when the first terminal includes a drain terminal, the second terminal includes a source terminal.

[0020] Further, the spacing distances between any two adjacent high-voltage switch modules in the same high-voltage switch unit are all the same, and the spacing distances between the two adjacent terminals of any two adjacent high-voltage switch modules in the same high-voltage switch unit are all the same.

[0021] Further, the storage unit includes a NAND Flash storage unit.

[0022] As another aspect of the present invention, there is provided an electronic device, which includes the non-volatile semiconductor storage device described above.

[0023] The non-volatile semiconductor memory device provided by the present invention sets the connection modes of any two adjacent high-voltage switch modules in each high-voltage switch unit corresponding to each page buffer to be different, so that after a voltage is applied to the connection line unit, a too large voltage difference between two adjacent terminals of two adjacent high-voltage switch modules can be avoided, achieving the purpose of eliminating the electron avalanche phenomenon caused by the voltage difference. In addition, since this method does not require changing the distance between two adjacent high-voltage switch modules, it will not cause an increase in the chip size. Therefore, the non-volatile semiconductor memory device of the present invention can avoid the occurrence of the avalanche phenomenon without increasing the chip size. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and are used to explain the present invention together with the following specific embodiments, but do not constitute a limitation to the present invention.

[0025] Figure 1 It is a circuit schematic diagram of a non-volatile semiconductor memory device with high-voltage switch modules.

[0026] Figure 2a It is a layout schematic diagram of high-voltage switch modules in a non-volatile semiconductor memory device of the prior art.

[0027] Figure 2b For Figure 2a Simplified schematic diagram.

[0028] Figure 3 It is a structural block diagram of the non-volatile semiconductor memory device provided by the present invention.

[0029] Figure 4a It is a layout schematic diagram of high-voltage switch modules in the non-volatile semiconductor memory device provided by the present invention.

[0030] Figure 4b For Figure 4a Simplified schematic diagram. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0032] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0034] For non-volatile flash memory storage devices that can perform electrical programming and erasing operations, due to their characteristic of being able to store data even when powered off, they are widely used. This type of flash memory storage device is mainly used to store boot codes.

[0035] For non-volatile flash memory storage devices, the operating voltage required during their operation is usually higher than the power supply voltage. For example, when performing write and erase operations, a high voltage of more than 20V is required. Therefore, a high-voltage switch module (PBTR1, PBTR2) needs to be configured in each non-volatile flash memory storage device to control the write and erase actions under high voltage. As Figure 1 shown, specifically, it is a circuit schematic diagram of a non-volatile flash memory storage device with a high-voltage switch module. Specifically, the data of the storage unit is read through each bit line (BL, BLn) and temporarily stored in the page buffer (PB1, PB2) and then output by the page buffer; or data is received through the input / output PAD (Input / Output PAD) of the non-volatile flash memory storage device, and then the data to be written into the storage unit is temporarily stored in the page buffer.

[0036] According to Figure 1 it can be known that one end of each bit line is connected to the storage unit, and the other end is connected to the high-voltage switch. The high-voltage switch can control the operating voltage during programming and erasing operations under the control signal of the control line BLSW; in addition, a control module is configured to protect the page buffer from the influence of high voltage, specifically Figure 1 not shown.

[0037] Figure 2a Specifically, it is a layout schematic diagram of the page buffer high-voltage switch of the flash memory device in the prior art. As Figure 2a shown, the flash memory device is composed of multiple Page Buffer high-voltage transistors (PBTR1, PBTR2, PBTR3, PBTR4). The page buffer high-voltage transistor (e.g., PBTR1) is composed of a gate terminal (G1), a first terminal (BL1_D), and a second terminal (BL1p_S). The first terminal (BL1_D) and the second terminal (BL1p_S) can be used as the drain and source respectively, or vice versa. During the erase operation, the first terminal (BL1_D) is applied with an erase voltage (Verase), while the second terminal (BL1p_S) is applied with VSS (or VDD). The voltage of the erase voltage (Verase) may be about 20V. It should be understood that the 20V voltage level here is only a simple example.

[0038] Specifically, multiple page buffer high-voltage transistors of the same page buffer can be arranged adjacent to each other in the Y direction. The second terminal BL1p_S in the first page buffer high-voltage transistor PBTR1 and the first terminal BL2_D in the second page buffer high-voltage transistor PBTR2 are arranged adjacent to each other in parallel. That is, during the erase operation, the second terminal BL1p_S in the first page buffer high-voltage transistor PBTR1 is applied with VSS (or VDD), while the first terminal BL2_D in the second page buffer high-voltage transistor PBTR2 is applied with the erase voltage Verase, and they are arranged adjacent to each other. Similarly, the second terminal BL2p_S in the second page buffer high-voltage transistor PBTR2 and the first terminal BL3_D in the third page buffer high-voltage transistor PBTR3 are adjacent and parallel. That is, during the erase operation, the second terminal BL2p_S in the second page buffer high-voltage transistor PBTR2 is applied with VSS (or VDD), while the erase voltage Verase is applied to the first terminal BL3_D in the third page buffer high-voltage transistor PBTR3, and they are adjacent and parallel. The second terminal BL3p_S in the above-mentioned third page buffer high-voltage transistor PBTR3 and the first terminal BL4_D in the fourth page buffer high-voltage transistor PBTR4 are adjacent and parallel. That is, during the erase operation, the second terminal BL3p_S in the third page buffer high-voltage transistor PBTR3 is applied with VSS (or VDD), while the erase voltage Verase is applied to the first terminal BL4_D in the fourth page buffer high-voltage transistor PBTR4, and they are adjacent and parallel.

[0039] Figure 2b is at Figure 2aA schematic diagram showing the voltages applied to adjacent terminals of the page buffer high-voltage transistor after being sorted. As described above, when an erase operation is performed on the second terminal BL1p_S of PBTR1 and the first terminal BL2_D of PBTR2, or the second terminal BL2p_S of PBTR2 and the first terminal BL3_D of PBTR3, or the second terminal BL3p_S of PBTR3 and the first terminal BL4_D of PBTR4, if different biases of high voltage Verase and VSS (or VDD) are applied to the terminals, a voltage difference will be generated between the terminals. When the voltage difference exceeds a certain limit, an electron avalanche phenomenon will occur. In the prior art for eliminating the electron avalanche phenomenon, it is usually necessary to increase the distance between two adjacent terminals of two adjacent transistors, which will lead to an increase in the chip size.

[0040] Based on this, in this embodiment, a non-volatile semiconductor memory device is provided. Figure 3 It is a structural block diagram of the non-volatile semiconductor memory device 10 provided according to an embodiment of the present invention, as Figure 3 shown, including:

[0041] A memory cell array 100, a high-voltage switch array 200, and a page buffer array 300. The page buffer array 300 is connected to the memory cell array 100 through the high-voltage switch array 200. The memory cell array 100 includes a plurality of memory cells 110 arranged in sequence along a first horizontal direction. The high-voltage switch array 200 includes a plurality of high-voltage switch units 210 arranged in sequence along the first horizontal direction. The page buffer array 300 includes a plurality of page buffers 310 arranged in sequence along the first horizontal direction. There is a one-to-one correspondence between the page buffers 310 and the high-voltage switch units 210, and between the high-voltage switch units 210 and the memory cells 110;

[0042] Each of the high-voltage switch units 210 includes a plurality of high-voltage switch modules 211 arranged in sequence along a second horizontal direction of a first plane. Each high-voltage switch module 211 is connected to the corresponding page buffer 310 and memory cell 110 through its respective corresponding connection line unit 400;

[0043] The connection line unit 400 corresponding to each high-voltage switch module 211 extends along the second horizontal direction of a second plane, and the connection line units 400 of the plurality of high-voltage switch modules 211 in the same high-voltage switch unit 210 are arranged at intervals in sequence along the first horizontal direction of the second plane, where the first plane and the second plane are stacked in the vertical direction, the first horizontal direction and the second horizontal direction are perpendicular to each other, and both the first horizontal direction and the second horizontal direction are perpendicular to the vertical direction;

[0044] In each high-voltage switch unit 210, the connection modes of every two adjacent high-voltage switch modules 211 with their respective corresponding connection line units 400 are all different, so that the voltage difference between adjacent terminals of every two adjacent high-voltage switch modules 211 is less than a preset threshold.

[0045] It should be noted that, in the embodiment of the present invention, Figure 4a the shown X direction is used as the first direction, the Y direction is used as the second direction, the Z direction is used as the vertical direction, and the first plane and the second plane are stacked vertically in the Z direction. It should be understood that the directions in the embodiment of the present invention can be two-way, that is, the positive X direction and the negative X direction both represent the first direction, the positive Y direction and the negative Y direction both represent the second direction, and the positive Z direction and the negative Z direction both represent the vertical direction.

[0046] In the embodiment of the present invention, when an erase command is executed, since different connection modes are set between every two adjacent high-voltage switch modules and the connection line unit in the same high-voltage switch unit, it is possible to avoid a high voltage difference between adjacent terminals of two adjacent high-voltage switch modules, that is, it is possible to make the voltage difference between adjacent terminals of two adjacent high-voltage switch modules less than a preset threshold, so that the occurrence of the avalanche phenomenon can be avoided without changing the adjacent spacing of the original high-voltage switch modules.

[0047] Therefore, for the non-volatile semiconductor memory device provided by the present invention, for multiple high-voltage switch modules in each high-voltage switch unit corresponding to each page buffer, the connection modes of any two adjacent high-voltage switch modules with their respective corresponding connection line units are set to be different, so that after a voltage is applied to the connection line unit, a too high voltage difference between two adjacent terminals of two adjacent high-voltage switch modules can be avoided, achieving the purpose of eliminating the electron avalanche phenomenon caused by the voltage difference. In addition, since this method does not require changing the spacing between two adjacent high-voltage switch modules, it will not cause an increase in the chip size. Therefore, the non-volatile semiconductor memory device of the present invention can avoid the occurrence of the avalanche phenomenon without increasing the chip size.

[0048] As a specific implementation manner of the present invention, as Figure 4a shown, each of the high-voltage switch modules 211 includes a control terminal AG extending along the first horizontal direction, a first terminal, and a second terminal. The first terminal and the second terminal are respectively located on both sides of the control terminal in the second horizontal direction and are spaced apart from the control terminal;

[0049] The first terminal and the second terminal are connected to the connection line unit 400 corresponding to the high-voltage switch module 211 where they are located through a voltage line unit 500, and the connection modes of the voltage line units 500 of every two adjacent high-voltage switch modules 211 are all different.

[0050] It should be noted that each high-voltage switch module 211 includes a control terminal, and a first terminal and a second terminal located on both sides of the control terminal. The first terminal and the second terminal are not actually shown in Figure 4a but only the positions thereof are indicated by arrows.

[0051] In the embodiment of the present invention, each high-voltage switch module in the same high-voltage switch unit is connected to the corresponding connection line unit through a voltage line unit, and the connection modes of the voltage line units of every two adjacent high-voltage switch modules are different, so that the voltage difference between adjacent terminals of every two adjacent high-voltage switch modules is less than a preset threshold value, that is, the voltage difference between two adjacent terminals of two adjacent high-voltage switch modules is less than the preset threshold value, thereby preventing electron avalanche from occurring.

[0052] More specifically, as Figure 4a shown, the connection line unit 400 includes a storage unit connection line 410 and a page buffer input / output connection line 420. The storage unit connection line 410 and the page buffer input / output connection line 420 are respectively located on both sides of the control terminal,

[0053] For any two adjacent high-voltage switch modules 211 in the same high-voltage switch unit 210, when the first terminal of one high-voltage switch module 211 is connected to the storage unit connection line 410 through the voltage line unit 500 and the second terminal is connected to the page buffer input / output connection line 420 through the voltage line unit 500, the first terminal of the other high-voltage switch module 211 is connected to the page buffer input / output connection line through the voltage line unit 500 and the second terminal is connected to the storage unit connection line through the voltage line unit 500, so that the voltage difference between the voltage line units 500 of two adjacent terminals of two adjacent high-voltage switch modules 211 is less than the preset threshold value.

[0054] In an embodiment of the present invention, for any two adjacent high-voltage switch modules 211 in the same high-voltage switch unit 210, the first terminal of one high-voltage switch module 211 is connected to the storage unit connection line, and the second terminal is connected to the page buffer input / output connection line. The first terminal of the other high-voltage switch module is connected to the page buffer input / output connection line, and the second terminal is connected to the storage unit connection line. It can be seen from this that the connection methods of two adjacent high-voltage switch modules to the connection line unit are different, and the connections are opposite here. Whether the second terminal of one high-voltage switch module and the first terminal of the other high-voltage switch module are adjacent, or the first terminal of one high-voltage switch module and the second terminal of the other high-voltage switch module are adjacent, the voltage difference between these two adjacent terminals will not be greater than a preset threshold. That is, the two adjacent terminals are respectively connected to their corresponding storage unit connection lines or page buffer input / output connection lines through their respective voltage line units. The voltage difference between the two adjacent terminals is the voltage difference between the two storage unit connection lines corresponding to the two adjacent terminals, or the voltage difference between two adjacent page buffer input / output connection lines. Since the voltage difference between two storage unit connection lines or the voltage difference between two adjacent page buffer input / output connection lines is almost zero, that is, less than the preset threshold, no avalanche phenomenon caused by the voltage difference will occur between the two adjacent terminals of two adjacent high-voltage switch modules.

[0055] More specifically, the voltage line unit 500 includes a first voltage line 510 and a second voltage line 520. The first voltage line 510 is configured with a working voltage, and the second voltage line 520 is configured with a power supply voltage. The voltage value of the working voltage is higher than that of the power supply voltage.

[0056] For any two adjacent high-voltage switch modules 211 in the same high-voltage switch unit 210, when the first terminal of one high-voltage switch module 211 is connected to the storage unit connection line through the first voltage line and the second terminal is connected to the page buffer input / output connection line through the second voltage line, the first terminal of the other high-voltage switch module is connected to the page buffer input / output connection line through the second voltage line and the second terminal is connected to the storage unit connection line through the first voltage line, so that the voltage difference between the two adjacent terminals of the two adjacent high-voltage switch modules is 0.

[0057] It can be understood that in the embodiments of the present invention, for any two adjacent high-voltage switch modules 211 in the same high-voltage switch unit 210, the first terminal of one high-voltage switch module 211 is connected to the storage unit connection line through the first voltage line, and the second terminal is connected to the page buffer input / output connection line through the second voltage line. For the other high-voltage switch module 211, the first terminal is connected to the page buffer input / output connection line through the second voltage line, and the second terminal is connected to the storage unit connection line through the first voltage line. This makes the voltage difference between the adjacent two terminals of the two adjacent high-voltage switch modules zero, thus effectively solving the occurrence of the avalanche phenomenon caused by the voltage difference between the adjacent terminals.

[0058] It should be noted that the operating voltage includes the erase voltage, and the power supply voltage includes voltage VDD or voltage VSS. In the embodiments of the present invention, the erase voltage can specifically be 20V, or it can be other operating voltages, which are not limited here. In the embodiments of the present invention, voltage VDD is specifically the positive voltage of the power supply voltage, for example, 5V, and voltage VSS can specifically be the ground voltage of the power supply voltage, for example, 0V. The specific magnitude of the power supply voltage can be set according to needs and is not limited here.

[0059] Take Figure 4a the shown structure as an example. Figure 4a Only four high-voltage switch modules in one high-voltage switch unit are schematically shown. It should be understood that a specific high-voltage switch unit can include multiple high-voltage switch modules, and the number of high-voltage switch modules is specifically set according to needs and is not limited here.

[0060] Take Figure 4aTaking the four high-voltage switch modules shown in the figure as an example, they are the first high-voltage switch module APBTR1, the second high-voltage switch module APBTR2, the third high-voltage switch module APBTR3, and the fourth high-voltage switch module APBTR4. The first high-voltage switch module APBTR1 includes a control terminal AG1, a first terminal ABL1_D, and a second terminal ABL1p_S. In the embodiment of the present invention, the first terminal ABL1_D and the second terminal ABL1p_S can be the drain and the source respectively, or can be set conversely. During the erase operation, the first voltage line connected to the first terminal ABL1_D is configured as the erase voltage Verase, while the second voltage line connected to the second terminal ABL1p_S is configured as VSS (or VDD). The second high-voltage switch module APBTR2, the third high-voltage switch module APBTR3, and the fourth high-voltage switch module APBTR4 all include a control terminal, a first terminal, and a second terminal, and the difference lies in the different connection methods of the voltage lines connected to their respective first terminals and second terminals. Specifically, the second voltage line connected to the first terminal ABL2p_S of the second high-voltage switch module APBTR2 is configured as VSS (or VDD), and the first voltage line connected to the second terminal ABL2p_D of the second high-voltage switch module APBTR2 is configured as the erase voltage Verase. In this way, for the adjacent first high-voltage switch module APBTR1 and the second high-voltage switch module APBTR2, the second voltage lines connected to the two adjacent terminals, that is, the second terminal ABL1p_S of the first high-voltage switch module APBTR1 and the first terminal ABL2p_S of the second high-voltage switch module APBTR2, are both configured as VSS (or VDD). Therefore, the voltage difference between them will not exceed the preset threshold, and thus the avalanche phenomenon will not be triggered. By analogy, the first voltage line connected to the first terminal ABL3p_D of the third high-voltage switch module APBTR3 is configured as the erase voltage Verase, while the second voltage line connected to the second terminal ABL3p_S is configured as VSS (or VDD). Then, for the adjacent second high-voltage switch module APBTR2 and the third high-voltage switch module APBTR3, the first voltage lines connected to the two adjacent terminals, that is, the second terminal ABL2p_D of the second high-voltage switch module APBTR2 and the first terminal ABL3p_D of the third high-voltage switch module APBTR3, are both configured as the erase voltage Verase. When the erase voltages are set to the same voltage, the voltage difference between them is 0, and the avalanche phenomenon will not be triggered either.The second voltage line connected to the first terminal ABL4p_S of the fourth high-voltage switch module APBTR4 is configured as VSS (or VDD), and the first voltage line connected to the second terminal ABL4p_D of the fourth high-voltage switch module APBTR4 is configured as the erase voltage Verase. As for the adjacent third high-voltage switch module APBTR3 and fourth high-voltage switch module APBTR4, the second voltage lines connected to the two adjacent terminals, namely the second terminal ABL3p_S of the third high-voltage switch module APBTR3 and the first terminal ABL4p_S of the fourth high-voltage switch module APBTR4, are both configured as VSS (or VDD). Therefore, the voltage difference between them will not exceed the preset threshold, and thus the avalanche phenomenon will not be triggered.

[0061] It can be seen that in the embodiment of the present invention, by changing the connection mode of the voltage lines of the two adjacent terminals of each adjacent two high-voltage switch modules, the two adjacent terminals of each adjacent two high-voltage switch modules have the same voltage or the voltage difference between them is not greater than the preset threshold, thereby eliminating the avalanche phenomenon caused by the too large voltage difference between adjacent terminals in the prior art.

[0062] It should be noted that the interval distance between any adjacent two high-voltage switch modules in the same high-voltage switch unit is the same, and the interval distance between the two adjacent terminals of any adjacent two high-voltage switch modules in the same high-voltage switch unit is the same.

[0063] It should be understood that for the interval distance between any adjacent two high-voltage switch modules in the same high-voltage switch unit is the same, and the interval distance between the two adjacent terminals of adjacent two high-voltage switch modules is the same. In this way of the present invention, there is no need to change the interval distance between adjacent two high-voltage switch modules. Only by changing the connection mode of the first terminal and the second terminal in each high-voltage switch module to the connection line unit, the avalanche phenomenon caused by the voltage difference can be eliminated, and the chip area will not be increased.

[0064] It should be understood that, as Figure 4aA plurality of high-voltage switch modules in the same high-voltage switch unit shown are sequentially and adjacently arranged along the Y direction. Specifically, the second terminal ABL1p_S in the first high-voltage switch module APBTR1 and the first terminal ABL2p_S in the second high-voltage switch module APBTR2 are adjacently and parallelly arranged. That is, during the erasing operation, the second terminal ABL1p_S in the first high-voltage switch module APBTR1 and the first terminal ABL2p_S in the second high-voltage switch module APBTR2 are applied with VSS (or VDD) and are arranged adjacent to each other. The second terminal ABL2_D in the second high-voltage switch module APBTR2 and the first terminal ABL3_D in the third high-voltage switch module APBTR3 are adjacently and parallelly arranged. That is, during the erasing operation, the second terminal ABL2_D in the second high-voltage switch module APBTR2 and the first terminal ABL3_D in the third high-voltage switch module APBTR3 are applied with the erasing voltage VSS (or VDD) and are arranged adjacent to each other. The second terminal ABL3p_S in the third high-voltage switch module APBTR3 and the first terminal ABL4p_S in the fourth high-voltage switch module APBTR4 are adjacently and parallelly arranged. That is, during the erasing operation, the second terminal ABL3p_S in the third high-voltage switch module APBTR3 and the first terminal ABL4p_S in the fourth high-voltage switch module APBTR4 are applied with VSS (or VDD) and are arranged adjacent to each other.

[0065] Figure 4b is Figure 4a A schematic diagram shown after arranging the voltages applied to the adjacent terminals of the high-voltage switch module shown.

[0066] As described above, when erasing operations are performed on the second terminal ABL1p_S of the first high-voltage switch module APBTR1 and the first terminal ABL2p_S of the second high-voltage switch module APBTR2, and the second terminal ABL3p_S of the third high-voltage switch module APBTR3 and the first terminal ABL4p_S of the fourth high-voltage switch module APBTR4, the terminals are respectively applied with VSS (or VDD) and VSS (or VDD). When erasing operations are performed on the first terminal ABL1_D of the first high-voltage switch module APBTR1, the second terminal ABL2_D of the second high-voltage switch module APBTR2, the first terminal ABL3_D of the third high-voltage switch module APBTR3, and the second terminal ABL4_D of the fourth high-voltage switch module APBTR4, each terminal is applied with the erasing voltage Verase, forming a structure where there is no voltage difference between terminals. Therefore, the non-volatile semiconductor memory device provided by the present invention eliminates the avalanche phenomenon without increasing the chip area by arranging adjacent to each other in a state where the same voltage is applied between two adjacent terminals of every two adjacent high-voltage switch modules.

[0067] In an embodiment of the present invention, the first voltage line 510 and the second voltage line 520 are in different planes from the first terminal, the second terminal, and the connection line unit.

[0068] One end of the first voltage line 510 is connected to the storage unit connection line 410 to form a first overlapping contact point 511, and the other end of the first voltage line 510 is connected to the first terminal or the second terminal to form a second overlapping contact point 512. One end of the second voltage line 520 is connected to the page buffer input / output connection line 420 to form a third overlapping contact point 521, and the other end of the second voltage line is connected to the second terminal or the first terminal to form a fourth overlapping contact point 522.

[0069] It should be understood that since the connection line unit 400 and the first terminal and the second terminal belong to different planes, that is, they belong to two different upper and lower layers, there will be upper and lower overlapping points between them. And the voltage line unit and the connection line unit belong to different planes. Therefore, there are upper and lower overlapping points between the first voltage line 510 and the storage unit connection line 410, and between the second voltage line 520 and the page buffer input / output line.

[0070] It should be noted that the wiring of the overlapping contact points in the embodiment of the present invention uses the DPT (Double Patterning Technique) method to wire to the high-voltage switch module. The wiring of the first terminal and the second terminal of each high-voltage switch module in the embodiment of the present invention uses the wiring of the same material of the DPT Pattern. It should be understood that DPT is a graphic technology that can overcome the limitations of lithography equipment. The DPT method first generates an even pattern and then generates an odd pattern. The specific DPT Pattern in the embodiment of the present invention is well known to those skilled in the art and will not be elaborated here.

[0071] In an embodiment of the present invention, the high-voltage switch module 211 includes a high-voltage transistor, and the control terminal includes a gate terminal. When the first terminal includes a source terminal, the second terminal includes a drain terminal, and when the first terminal includes a drain terminal, the second terminal includes a source terminal.

[0072] It should be understood that the specific implementation manner of the high-voltage switch module may be a high-voltage transistor, and the control terminal may specifically include a gate terminal, and the first terminal and the second terminal can be interchanged, that is, when the first terminal includes a source terminal, the second terminal includes a drain terminal, and vice versa.

[0073] In an embodiment of the present invention, the storage unit 110 includes a NAND Flash storage unit.

[0074] It should be understood that the specific implementation of the storage unit 110 in the embodiments of the present invention may be a NAND Flash storage unit.

[0075] In summary, for the non-volatile semiconductor storage device provided by the embodiments of the present invention, for each of the multiple high-voltage switch modules in each high-voltage switch unit corresponding to each page buffer, the connection manner between any two adjacent high-voltage switch modules and their respective corresponding connection line units is set to be different, that is, the voltage line connection manner between two adjacent terminals of any two adjacent high-voltage switch modules is different. Thus, after the connection line unit is applied with a voltage, the voltage difference between two adjacent terminals of any two adjacent high-voltage switch modules can be made less than a preset threshold, so as to achieve the purpose of eliminating the electron avalanche phenomenon caused by the voltage difference. In addition, since this method does not require changing the distance between two adjacent high-voltage switch modules, it will not cause an increase in the chip size. Therefore, the non-volatile semiconductor storage device of the present invention can avoid the occurrence of the avalanche phenomenon without increasing the chip size.

[0076] As another embodiment of the present invention, there is provided an electronic device, which includes the non-volatile semiconductor storage device described above.

[0077] In the embodiments of the present invention, the electronic device adopts the non-volatile storage device described above. Since a high voltage of more than 20V will be applied between the storage unit array and the page buffer array during the electrical programming and erasing operations of the flash memory cells, in order to protect the page buffer, a high-voltage switch module is configured for the page buffer. By setting the connection manner between any two adjacent high-voltage switch modules and their respective corresponding connection line units to be different, that is, the voltage line connection manner between two adjacent terminals of any two adjacent high-voltage switch modules is different, after the connection line unit is applied with a voltage, the voltage difference between two adjacent terminals of any two adjacent high-voltage switch modules can be made less than a preset threshold, so as to achieve the purpose of eliminating the electron avalanche phenomenon caused by the voltage difference. In addition, since this method does not require changing the distance between two adjacent high-voltage switch modules, it will not cause an increase in the chip size, thereby being able to enhance the competitive advantage of the non-volatile storage device, and the electronic device adopting this non-volatile storage device similarly has a competitive advantage.

[0078] Specifically, the electronic device may specifically include a set-top box, an intelligent camera, a smart home, etc., or other electronic devices for storing startup codes.

[0079] It is understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A nonvolatile semiconductor storage device, characterized in that: include: A memory cell array, a high voltage switch array and a page buffer array, wherein the page buffer array is connected to the memory cell array through the high voltage switch array, the memory cell array comprises a plurality of memory cells sequentially arranged along a first horizontal direction, the high voltage switch array comprises a plurality of high voltage switch units sequentially arranged along the first horizontal direction, the page buffer array comprises a plurality of page buffers sequentially arranged along the first horizontal direction, and the page buffers correspond to the high voltage switch units and the high voltage switch units correspond to the memory cells in a one-to-one manner; Each of the high-voltage switch units includes a plurality of high-voltage switch modules arranged in sequence along a second horizontal direction of the first plane, and each high-voltage switch module is connected to a corresponding page buffer and a storage unit through a corresponding connection line unit; The connecting line units corresponding to each high-voltage switch module extend along the second horizontal direction of the second plane, and the connecting line units of multiple high-voltage switch modules in the same high-voltage switch unit are sequentially arranged at intervals along the first horizontal direction of the second plane, wherein the first plane and the second plane are stacked in the vertical direction, the first horizontal direction is perpendicular to the second horizontal direction, and the first horizontal direction and the second horizontal direction are both perpendicular to the vertical direction; The connection modes of each two adjacent high-voltage switch modules in each high-voltage switch unit and the corresponding connecting line units are different so that the voltage difference between adjacent terminals of each two adjacent high-voltage switch modules is less than a preset threshold value; Each of the high-voltage switch modules comprises a control terminal, a first terminal and a second terminal extending along a first horizontal direction, wherein the first terminal and the second terminal are respectively located on both sides of the control terminal in the second horizontal direction and are spaced apart from the control terminal; The first terminal and the second terminal are connected to the connection line units corresponding to the high-voltage switch modules through voltage line units, and the connection modes of the voltage line units of every two adjacent high-voltage switch modules are different.

2. The nonvolatile semiconductor memory device according to claim 1, wherein: The connection line unit includes a storage unit connection line and a page buffer input / output connection line, wherein the storage unit connection line and the page buffer input / output connection line are respectively located at two sides of the control terminal. For any two adjacent high-voltage switch modules in the same high-voltage switch unit, when the first terminal of one of the high-voltage switch modules is connected to the storage unit connection line through the voltage line unit and the second terminal is connected to the page buffer input-output connection line through the voltage line unit, the first terminal of the other high-voltage switch module is connected to the page buffer input-output connection line through the voltage line unit and the second terminal is connected to the storage unit connection line through the voltage line unit, so that the voltage difference of the voltage line units of two adjacent terminals of the two adjacent high-voltage switch modules is less than a preset threshold.

3. The nonvolatile semiconductor memory device according to claim 2, wherein: The voltage line unit includes a first voltage line and a second voltage line, the first voltage line is configured with an operating voltage, the second voltage line is configured with a supply voltage, and a voltage value of the operating voltage is higher than the supply voltage, For any two adjacent high-voltage switch modules in the same high-voltage switch unit, when the first terminal of one of the high-voltage switch modules is connected to the storage unit connection line through the first voltage line and the second terminal is connected to the page buffer input-output connection line through the second voltage line, the first terminal of the other high-voltage switch module is connected to the page buffer input-output connection line through the second voltage line and the second terminal is connected to the storage unit connection line through the first voltage line, so that the voltage difference between the two adjacent terminals of the two adjacent high-voltage switch modules is 0.

4. The nonvolatile semiconductor memory device according to claim 3, wherein: The first voltage line and the second voltage line are all in different planes from the first terminal, the second terminal and the connecting line unit. One end of the first voltage line is connected to the storage unit connection line to form a first overlapping contact point, the other end of the first voltage line is connected to the first terminal or the second terminal to form a second overlapping contact point, one end of the second voltage line is connected to the page buffer input and output connection line to form a third overlapping contact point, and the other end of the second voltage line is connected to the second terminal or the first terminal to form a fourth overlapping contact point.

5. The nonvolatile semiconductor memory device according to claim 3, wherein: The operating voltage includes an erase voltage, and the supply voltage includes a voltage VDD or a voltage VSS.

6. The nonvolatile semiconductor memory device according to claim 1, wherein: The high-voltage switch module includes a high-voltage transistor, the control terminal includes a gate terminal, the second terminal includes a drain terminal when the first terminal includes a source terminal, and the second terminal includes a source terminal when the first terminal includes a drain terminal.

7. The nonvolatile semiconductor memory device according to any one of claims 1 to 6, wherein: The spacing distance between any two adjacent high-voltage switch modules in the same high-voltage switch unit is the same, and the spacing distance between two adjacent terminals of any two adjacent high-voltage switch modules in the same high-voltage switch unit is the same.

8. The nonvolatile semiconductor memory device according to any one of claims 1 to 6, wherein: The storage unit includes a NAND Flash storage unit.

9. An electronic device, characterized in that: A nonvolatile semiconductor memory device comprising any one of claims 1 to 8.

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