Radio frequency switch control circuit, radio frequency switch and control method

Abstract

The present invention discloses a radio frequency switch control circuit, a radio frequency switch and a control method, and belongs to the field of semiconductor circuit technology. A level conversion module receives a TTL logic input level, and converts the TTL logic input level into a plurality of target output levels; a complementary reverse output module receives a plurality of target output levels, and outputs two complementary levels through a primary inverter and a secondary inverter according to the target output level of each path, and controls the opening and closing of the series-parallel complementary switch of the radio frequency switch through the two levels; an exclusive OR logic output module receives all the complementary two levels output by the complementary reverse output module, performs AND gate and OR gate logic processing on all the complementary two levels, and outputs a level of a single MOS switch that controls the radio frequency switch. The present invention achieves the purpose of using a few digital inputs to generate more digital step-down outputs, reduces the number of chip pins, realizes chip miniaturization design, and meets the current market requirements.

Description

Technical Field

[0001] The invention relates to a radio frequency switch control circuit, a radio frequency switch and a control method, and belongs to the technical field of semiconductor circuits. Background Art

[0002] RF switches are basic control circuit devices in communication systems. High-frequency, multi-throw, high-isolation RF switches have become one of the important components used in mainstream electronic countermeasure systems. As an important component of modern electronic systems, RF control circuits play an increasingly important role, such as controlling the on / off or conversion of signals, the size of gain, the amount of phase shift, etc. With the popularization and development of RF switch applications, circuit performance indicators are becoming better and better, and the demand for control signal generation circuits for RF switches is also increasing, which leads to an increase in chip pins and an increase in area. It is hoped that as few digital signals as possible can be used to control RF switches, reduce the number of external chip pins, and make the circuit more integrated and miniaturized. Summary of the invention

[0003] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a radio frequency switch control circuit, a radio frequency switch and a control method.

[0004] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions.

[0005] In one aspect, the present invention provides a radio frequency switch control circuit, comprising: a level conversion module, a complementary reverse output module and an exclusive OR logic output module;

[0006] The level conversion module receives the TTL logic input level and converts the TTL logic input level into a plurality of target output levels;

[0007] The complementary reverse output module receives a plurality of target output levels, and outputs two complementary levels through a primary inverter and a secondary inverter according to the target output level of each path, and controls the opening and closing of the series-parallel complementary switches of the RF switch through the two levels;

[0008] The exclusive OR logic output module receives all the complementary two-way levels output by the complementary reverse output module, performs AND gate and OR gate logic processing on all the complementary two-way levels, and outputs one-way level of a single MOS switch that controls the radio frequency switch.

[0009] The level conversion module realizes the conversion from TTL logic input level 0-5V to output level -5V-0V. The complementary reverse output module realizes the control of two RF switches respectively, and the same or logical output realizes the control of one RF switch. The present invention can realize the output of five digital logics through two digital control signals, thereby controlling the RF switch and accurately controlling the on and off of the RF signal.

[0010] Further, the level conversion module includes a plurality of level conversion circuits, each of which includes a step-down diode and a large resistance circuit;

[0011] The large resistance circuit includes a resistor and a D-pHEMT, where D-pHEMT represents a depletion-type pseudo high electron mobility transistor;

[0012] The step-down diode is composed of a plurality of source-drain connected D-pHEMTs in series, the gate of the first D-pHEMT of the step-down diode is connected to the TTL logic input level, the source or drain of the last D-pHEMT is connected to the drain of the D-pHEMT of the large resistance circuit and the complementary reverse output module; the source of the D-pHEMT of the large resistance circuit is connected to one end of the resistor, and the other end of the resistor is connected to the gate of the D-pHEMT of the large resistance circuit and the power supply voltage VDD.

[0013] The circuit uses 8 source-drain connected D-pHEMTs in series as step-down diodes, and uses the D-PHEMTs working in a near-cutoff state as large resistors to step down the input TTL signal (5V / 0V) into a DCFL signal (0V / -5V). The voltage drop generated by each diode is about 0.6V to 0.7V. The circuit is connected to a -5V power supply voltage, so when 5V is input, 0V is output, and when 0V is input, -5V is output.

[0014] Further, the complementary reverse output module includes a plurality of complementary reverse output circuits corresponding one-to-one to the plurality of level conversion circuits;

[0015] The complementary reverse output circuit includes three inverter circuits, one of which constitutes the primary inverter, and the other two inverter circuits are connected in series to constitute the secondary inverter;

[0016] The inverter circuit includes a first inverter D-pHEMT, a second inverter D-pHEMT, a first inverter resistor, a second inverter resistor and an inverter E-pHEMT, where E-pHEMT represents an enhanced pseudo high electron mobility transistor;

[0017] The drain of the first D-pHEMT of the inverter is the input end of the inverter circuit, the gate of the first D-pHEMT of the inverter is connected to one end of the first resistor of the inverter and the gate of the inverter E-pHEMT, the source of the first D-pHEMT of the inverter is connected to the other end of the first resistor of the inverter, the source of the inverter E-pHEMT is connected to the power supply voltage VDD, the drain of the inverter E-pHEMT is connected to one end of the second resistor of the inverter and the gate of the second D-pHEMT of the inverter, the drain of the inverter E-pHEMT also serves as the output end of the inverter circuit, the drain of the second D-pHEMT of the inverter is grounded, and the source of the second D-pHEMT of the inverter is connected to the other end of the second resistor;

[0018] The input ends of the primary inverter and the secondary inverter are both connected to the target output level, the output end of the secondary inverter outputs a first complementary level, and the output end of the primary inverter outputs a second complementary level.

[0019] The inverter uses E-pHEMT as the switch reverse unit, and D-pHEMT works in the cut-off state as a load tube. D-pHEMT is added to the gate end of E-pHEMT to limit the current and reduce the influence of gate current on the logic function. The -5V power supply is connected at the bottom. When the input is 5V, the Level Shifter is stepped down to 0V, so that the inverter E-pNEMT is turned on and the output is a low level -5V. When the input is 0V, the voltage is stepped down to -5V, the inverter switch tube is cut off, and the output is 0V. The other path is reversed through two stages of inverters. At this point, VOUT_1A, VOUT_1B, VOUT_2A, and VOUT_2B are controlled by VIN_A and VIN_B respectively.

[0020] The output signal VOUT_1B of the first-stage inverter always maintains the opposite direction to the input signal VIN_A. After the second-stage inverter is reversed twice, the output signal VOUT_1A always maintains the same direction as the input signal VIN_A, thereby realizing the complementary reverse output function.

[0021] Further, the XNOR logic output module includes two AND gate circuits and one OR gate circuit;

[0022] The AND gate circuit includes a NAND gate and a NAND gate inverter circuit, and the OR gate circuit includes a NOR gate and a NOR gate inverter circuit;

[0023] The NAND gate includes a first NAND gate D-pHEMT, a second NAND gate D-pHEMT, a third NAND gate D-pHEMT, a first NAND gate E-pHEMT, a second NAND gate E-pHEMT, a first NAND gate resistor, a second NAND gate resistor and a third NAND gate resistor;

[0024] The drain of the first NAND gate D-pHEMT is connected to the first complementary level output by a secondary inverter, the gate of the first NAND gate D-pHEMT is respectively connected to one end of the first NAND gate resistor and the gate of the first NAND gate E-pHEMT, the source of the first NAND gate D-pHEMT is connected to the other end of the first NAND gate resistor, the drain of the first NAND gate E-pHEMT is connected to the gate of the third NAND gate D-pHEMT, one end of the third NAND gate resistor and the input end of the NAND gate inverter circuit, and the other end of the third NAND gate resistor is connected to the NAND gate. The drain of the third NAND gate D-pHEMT is connected to the ground, the source of the first NAND gate E-pHEMT is connected to the drain of the second NAND gate E-pHEMT, the source of the second NAND gate E-pHEMT is connected to the power supply voltage VDD, the gate of the second NAND gate E-pHEMT is respectively connected to one end of the second NAND gate resistor and the gate of the second NAND gate D-pHEMT, the drain of the second NAND gate D-pHEMT is connected to the first complementary level output by another secondary inverter, and the source of the second NAND gate D-pHEMT is connected to the other end of the second NAND gate resistor;

[0025] The NOR gate includes a first NOR gate D-pHEMT, a second NOR gate D-pHEMT, a third NOR gate D-pHEMT, a first NOR gate resistor, a second NOR gate resistor, a third NOR gate resistor, a first NOR gate E-pHEMT and a second NOR gate E-pHEMT;

[0026] The drain of the first D-pHEMT of the NOR gate is connected to the output end of the NAND gate inverter circuit in the AND gate circuit, the source of the first D-pHEMT of the NOR gate is connected to one end of the first resistor of the NOR gate, the gate of the first D-pHEMT of the NOR gate is respectively connected to the other end of the first resistor of the NOR gate and the gate of the first E-pHEMT of the NOR gate, the source of the first E-pHEMT of the NOR gate is connected to the power supply voltage VDD, and the drain of the first E-pHEMT of the NOR gate is respectively connected to one end of the third resistor of the NOR gate, the gate of the third D-pHEMT of the NOR gate, the drain of the second E-pHEMT of the NOR gate and the input of the NOR gate inverter circuit. The drain of the third NOR gate D-pHEMT is grounded, the source of the third NOR gate D-pHEMT is connected to the other end of the third NOR gate resistor, the drain of the second NOR gate D-pHEMT is connected to the output end of the NAND gate inverter circuit of another AND gate circuit, the gate of the second NOR gate D-pHEMT is respectively connected to one end of the second NOR gate resistor and the gate of the second NOR gate E-pHEMT, the source of the second NOR gate D-pHEMT is connected to the other end of the second NOR gate resistor, the source of the second NOR gate E-pHEMT is connected to the power supply voltage VDD, and the output end of the NOR gate inverter circuit is the output port of the exclusive OR logic output module.

[0027] The AND gate circuit based on GaAs technology can be composed of a NAND gate and an inverter. The NAND gate is similar to the inverter structure. An additional input terminal is connected in series on the main switch circuit. Two EPHEMTs are connected in series. Only when the two input signals are high at the same time can they be turned on and output a low level. Otherwise, they output a high level, and then the AND gate logic is realized through the inverter. The OR gate can also be composed of a NOR gate and an inverter. On the basis of the original inverter, an additional input terminal is connected in parallel. Two EPHEMTs are connected in parallel. As long as one of the inputs is high, a low level is output, and then the OR gate logic is realized through the inverter.

[0028] Furthermore, the enhancement-mode pseudo-high electron mobility transistor and the depletion-mode pseudo-high electron mobility transistor are both GaAs-based transistors.

[0029] The enhancement type pseudo high electron mobility transistor mainly plays the role of a switch in the present invention, with a high level input to turn on and a low level to cut off. The depletion type pseudo high electron mobility transistor plays two roles in the present invention. One is to connect its source and drain to form a diode structure as a component of the level conversion module; the other is to set it to work close to the cut-off region and act as a large resistor to reduce the layout area.

[0030] Further, the TTL logic input level is 5V / 0V, the target output level is 0V / -5V, the two complementary levels are a high level of 0V and a low level of -5V, and the one level is a high level of 0V or a low level of -5V.

[0031] In a second aspect, the present invention provides a radio frequency switch, including a MOS switch S1, a first grounding resistor, a series-parallel complementary switch S2, a second grounding resistor, a series-parallel complementary switch S3, a third grounding resistor, a radio frequency input terminal RFIN, and a radio frequency switch control circuit;

[0032] One end of the MOS switch S1 is grounded through a first grounding resistor, the other end of the MOS switch S1 is connected to the radio frequency input terminal RFIN, a first fixed end of the series-parallel complementary switch S2 is grounded through a second grounding resistor, a second fixed end of the series-parallel complementary switch S2 is connected to the radio frequency input terminal RFIN, a moving end of the series-parallel complementary switch S2 is connected to the first radio frequency signal RF1, a first fixed end of the series-parallel complementary switch S3 is grounded through a second grounding resistor, a second fixed end of the series-parallel complementary switch S3 is connected to the radio frequency input terminal RFIN, and a moving end of the series-parallel complementary switch S3 is connected to the second radio frequency signal RF2;

[0033] The complementary reverse output module of the radio frequency switch control circuit is used to control the closing direction of the series-parallel complementary switch S2 and the series-parallel complementary switch S3, and the exclusive-OR logic output module of the radio frequency switch control circuit is used to control the opening and closing of the MOS switch S1.

[0034] Two control bits are used to simultaneously control the MOS switch S1 and the series-parallel complementary switch S2 and the series-parallel complementary switch S3; the level conversion module realizes the conversion from the input level 0-5V to the output level -5V-0V. The complementary reverse output module realizes the control of the series-parallel complementary switch S2 and the series-parallel complementary switch S3, and the companion logic output realizes the control of the MOS switch S1.

[0035] Furthermore, the first pair of complementary two-way levels output by the complementary reverse output module are VOUT_1A and VOUT_1B respectively;

[0036] The second pair of complementary levels output by the complementary reverse output module are VOUT_2A and VOUT_2B respectively, and the level output by the XOR logic output module is VOUT_3;

[0037] The TTL logic input levels are VIN_A and VIN_B, wherein VIN_A controls the levels corresponding to VOUT_1A and VOUT_1B, and VIN_B controls the levels corresponding to VOUT_2A and VOUT_2B.

[0038] Further, the circuit structures of the series-parallel complementary switch S2 and the series-parallel complementary switch S3 both include: a first MOS transistor and a second MOS transistor;

[0039] The gate of the first MOS tube inputs a first level signal, the source of the first MOS tube inputs a radio frequency signal, the drain of the first MOS tube is connected to the drain of the second MOS tube and the radio frequency input terminal RFIN, the gate of the second MOS tube inputs a second level signal, and the source of the second MOS tube is connected to the power supply voltage VDD;

[0040] When the first level signal is at a high level and the second level signal is at a low level, the first MOS tube is turned on, the second MOS tube is turned off, and the series-parallel complementary switch is closed upward;

[0041] When the first level signal is at a low level and the second level signal is at a high level, the first MOS tube is disconnected, the second MOS tube is turned on, and the series-parallel complementary switch is closed downward.

[0042] In a third aspect, the present invention provides a control method for a radio frequency switch.

[0043] The input TTL logic input levels are VIN_A low level and VIN_B high level, then the outputs are VOUT_1A low level, VOUT_1B high level, VOUT_2A high level, VOUT_2B low level, and VOUT_3 low level. At this time, the MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed downward, and the series-parallel complementary switch S3 is closed upward. The second RF signal RF2 is connected to the RF input terminal RFIN, and the first RF signal RF1 is short-circuited to the ground;

[0044] The input TTL logic input levels are VIN_A high level and VIN_B low level, then the outputs are VOUT_1A high level, VOUT_1B low level, VOUT_2A low level, VOUT_2B high level, and VOUT_3 low level. At this time, the MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed upward, and the series-parallel complementary switch S3 is closed downward. The first RF signal RF1 is connected to the RF input terminal RFIN, and the second RF signal RF2 is short-circuited to the ground;

[0045] The input TTL logic input levels are VIN_A low level and VIN_B low level respectively, then the outputs are VOUT_1A low level, VOUT_1B high level, VOUT_2A low level, VOUT_2B high level, and VOUT_3 high level. At this time, the MOS switch S1 is closed, the series-parallel complementary switch S2 is closed downward, and the series-parallel complementary switch S3 is closed downward. The first radio frequency signal RF1 and the second radio frequency signal RF2 are both short-circuited to the ground;

[0046] The input TTL logic input levels are VIN_A high level and VIN_B high level respectively, then the outputs are VOUT_1A high level, VOUT_1B low level, VOUT_2A high level, VOUT_2B low level, and VOUT_3 high level. At this time, the MOS switch S1 is closed, the series-parallel complementary switch S2 is closed upward, and the series-parallel complementary switch S3 is closed upward, and the first RF signal RF1 and the second RF signal RF2 are both short-circuited to ground.

[0047] The beneficial effects achieved by the present invention are:

[0048] The present invention realizes the purpose of generating more digital step-down outputs with fewer digital inputs through the circuit design of a level conversion module, a complementary reverse output module and an XOR logic output module, thereby controlling the on and off of the radio frequency switch, reducing the number of chip pins, realizing chip miniaturization design, and meeting the current market requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the structure of the digital logic generation circuit of the present invention;

[0050] Figure 2It is a schematic diagram of the structure of the radio frequency switch circuit of the present invention;

[0051] Figure 3 It is the series-parallel complementary switch structure of the present invention;

[0052] Figure 4 is a schematic diagram of the simulation results of the input signal VIN_A;

[0053] Figure 5 is a schematic diagram of the simulation results of the input signal VIN_B;

[0054] Figure 6 is a schematic diagram of simulation results of the output signal VOUT_1A;

[0055] Figure 7 is a schematic diagram of simulation results of the output signal VOUT_1B;

[0056] Figure 8 is a schematic diagram of simulation results of the output signal VOUT_2A;

[0057] Fig. 9 is a schematic diagram of simulation results of the output signal VOUT_2B;

[0058] Fig.10 Schematic diagram of simulation results of output signal VOUT_3. DETAILED DESCRIPTION

[0059] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0060] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and the like may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0061] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0062] Embodiment 1, this embodiment introduces one aspect, the present invention provides a radio frequency switch control circuit, including: a level conversion module, a complementary reverse output module and an exclusive OR logic output module;

[0063] The level conversion module receives the TTL logic input level and converts the TTL logic input level into a plurality of target output levels;

[0064] The complementary reverse output module receives a plurality of target output levels, and outputs two complementary levels through a primary inverter and a secondary inverter according to the target output level of each path, and controls the opening and closing of the series-parallel complementary switches of the RF switch through the two levels;

[0065] The exclusive OR logic output module receives all the complementary two-way levels output by the complementary reverse output module, performs AND gate and OR gate logic processing on all the complementary two-way levels, and outputs one-way level of a single MOS switch that controls the radio frequency switch.

[0066] In this embodiment, Figure 1 As shown, transistors D1 to D25 use depletion-type pseudo high electron mobility transistors D-pHEMT; and transistors E1 to E9 use enhancement-type pseudo high electron mobility transistors E-pHEMT.

[0067] The level conversion module includes two level conversion circuits, each of which includes a step-down diode and a large resistance circuit;

[0068] The large resistance circuit of the first level conversion circuit includes a resistor R1 and a transistor D9;

[0069] The step-down diode of the first level conversion circuit is composed of 8 source-drain connected transistors D1-D8 in series, the gate of transistor D1 is connected to the TTL logic input level VIN_A, the source or drain of transistor D8 is connected to the drain of transistor D9 of the large resistance circuit and the complementary reverse output module; the source of transistor D9 of the large resistance circuit is connected to one end of resistor R1, and the other end of resistor R1 is connected to the gate of transistor D9 of the large resistance circuit and the power supply voltage VDD.

[0070] The large resistance circuit of the second level conversion circuit includes a resistor R1 and a transistor D9;

[0071] The step-down diode of the second level conversion circuit is composed of 8 source-drain connected transistors d1-d8 in series, the gate of transistor d1 is connected to the TTL logic input level VIN_B, the source or drain of transistor d8 is connected to the drain of transistor d9 of the large resistance circuit and the complementary reverse output module; the source of transistor d9 of the large resistance circuit is connected to one end of resistor r1, and the other end of resistor r1 is connected to the gate of transistor d9 of the large resistance circuit and the power supply voltage VDD.

[0072] The level conversion circuit uses 8 source-drain connected D-pHEMTs in series as step-down diodes, and uses the D-PHEMTs working in a near-cutoff state as large resistors to step down the input TTL signal (5V / 0V) into a DCFL signal (0V / -5V). The voltage drop generated by each diode is about 0.6V to 0.7V. The circuit is connected to a -5V power supply voltage, so when 5V is input, 0V is output, and when 0V is input, -5V is output.

[0073] The complementary reverse output module includes two complementary reverse output circuits corresponding one to one to the two level conversion circuits;

[0074] The complementary reverse output circuit includes three inverter circuits, one of which constitutes the primary inverter, and the other two inverter circuits are connected in series to constitute the secondary inverter;

[0075] The two inverter circuits of the secondary inverter are composed of:

[0076] The first inverter circuit includes: a transistor D10, a transistor D11, a resistor R2, a resistor R4 and a transistor E1;

[0077] The drain of transistor D10 is the input end of the first inverter circuit in the two-stage inverter, the gate of transistor D10 is connected to one end of resistor R2 and the gate of transistor E1, the source of transistor D10 is connected to the other end of resistor R2, the source of transistor E1 is connected to power supply voltage VDD, the drain of transistor E1 is connected to one end of resistor R4 and the gate of transistor D11, the drain of transistor E1 also serves as the output end of the first inverter circuit in the two-stage inverter, the drain of transistor D11 is grounded, and the source of transistor D11 is connected to the other end of resistor R4.

[0078] The second inverter circuit includes: a transistor D12, a transistor D13, a resistor R6, a resistor R7 and a transistor E3;

[0079] The drain of transistor D12 is connected to the input end of the second inverter circuit in the two-stage inverter and the output end of the first inverter circuit in the two-stage inverter, the gate of transistor D12 is connected to one end of resistor R6 and the gate of transistor E3, the source of transistor D12 is connected to the other end of resistor R6, the source of transistor E3 is connected to power supply voltage VDD, the drain of transistor E3 is connected to one end of resistor R7 and the gate of transistor D13, the drain of transistor E3 also serves as the output end of the second inverter circuit in the two-stage inverter, the drain of transistor D13 is grounded, and the source of transistor D13 is connected to the other end of resistor R7.

[0080] The first-stage inverter includes: transistor D14, transistor D15, resistor R3, resistor R5 and transistor E2;

[0081] The drain of transistor D14 is the input end of the first-stage inverter, the gate of transistor D14 is connected to one end of resistor R3 and the gate of transistor E2, the source of transistor D14 is connected to the other end of resistor R3, the source of transistor E3 is connected to the power supply voltage VDD, the drain of transistor E2 is connected to one end of resistor R5 and the gate of transistor D15, the drain of transistor E2 also serves as the output end of the first-stage inverter, the drain of transistor D15 is grounded, and the source of transistor D15 is connected to the other end of resistor R5.

[0082] Another complementary reverse output circuit also includes three inverter circuits, one of which constitutes the primary inverter, and the other two inverter circuits are connected in series to constitute the secondary inverter;

[0083] The two inverter circuits of the secondary inverter are composed of:

[0084] The first inverter circuit includes: a transistor d10, a transistor d11, a resistor r2, a resistor r4 and a transistor e1;

[0085] The drain of transistor d10 is the input end of the first inverter circuit in the two-stage inverter, the gate of transistor d10 is connected to one end of resistor R2 and the gate of transistor e1, the source of transistor d10 is connected to the other end of resistor R2, the source of transistor e1 is connected to the power supply voltage VDD, the drain of transistor e1 is connected to one end of resistor R4 and the gate of transistor d11, the drain of transistor R1 also serves as the output end of the first inverter circuit in the two-stage inverter, the drain of transistor d11 is grounded, and the source of transistor d11 is connected to the other end of resistor R4.

[0086] The second inverter circuit includes: a transistor d12, a transistor d13, a resistor r6, a resistor r7 and a transistor e3;

[0087] The drain of transistor d12 is connected to the input end of the second inverter circuit in the secondary inverter and the output end of the first inverter circuit in the secondary inverter, the gate of transistor d12 is connected to one end of resistor r6 and the gate of transistor e3, the source of transistor d12 is connected to the other end of resistor r6, the source of transistor e3 is connected to the power supply voltage VDD, the drain of transistor e3 is connected to one end of resistor r7 and the gate of transistor d13, the drain of transistor e3 also serves as the output end of the second inverter circuit in the secondary inverter, the drain of transistor d13 is grounded, and the source of transistor d13 is connected to the other end of resistor r7.

[0088] The first-stage inverter includes: transistor d14, transistor d15, resistor r3, resistor r5 and transistor e2;

[0089] The drain of transistor D14 is the input end of the first-stage inverter, the gate of transistor D14 is connected to one end of resistor R3 and the gate of transistor E2, the source of transistor D14 is connected to the other end of resistor R3, the source of transistor E3 is connected to the power supply voltage VDD, the drain of transistor E2 is connected to one end of resistor R5 and the gate of transistor D15, the drain of transistor E2 also serves as the output end of the first-stage inverter, the drain of transistor D15 is grounded, and the source of transistor D15 is connected to the other end of resistor R5.

[0090] The input ends of the primary inverter and the secondary inverter are both connected to the target output level, the output end of the secondary inverter outputs a first complementary level, and the output end of the primary inverter outputs a second complementary level.

[0091] The inverter uses E-pHEMT as the switch reverse unit, and D-pHEMT works in the cut-off state as a load tube. D-pHEMT is added to the gate end to limit the current and reduce the influence of the gate current on the logic function. The -5V power supply is connected at the bottom. When the input is 5V, the Level Shifter steps down to 0V, making the inverter E-pNEMT turn on and output a low level of -5V. When the input is 0V, the voltage is stepped down to -5V, the inverter switch tube is cut off, and the output is 0V. The other path is reversed through two stages of inverters. So far, VOUT_1A, VOUT_1B, VOUT_2A, and VOUT_2B are controlled by VIN_A and VIN_B respectively.

[0092] The XOR logic output module includes two AND gate circuits and one OR gate circuit;

[0093] The AND gate circuit includes a NAND gate and a NAND gate inverter circuit, and the OR gate circuit includes a NOR gate and a NOR gate inverter circuit;

[0094] The NAND gate of the first AND gate circuit includes a transistor D16, a transistor D17, a transistor D18, a transistor E4, a transistor E5, a resistor R8, a resistor R9 and an AND resistor R10; the inverter circuit of the first AND gate circuit includes a transistor D19, a transistor D20, a transistor E6, a resistor R11 and an AND resistor R12;

[0095] Wherein, the drain of transistor D17 is connected to VOUT_1A, the gate of transistor D17 is respectively connected to one end of resistor R8 and the gate of transistor E4, the source of transistor D17 is connected to the other end of resistor R8, the drain of transistor E4 is connected to the gate of transistor D18, one end of resistor R10 and the drain of transistor D19, the other end of resistor R10 is connected to the drain of transistor D18 and grounded, the source of transistor E4 is connected to the drain of transistor E5, the source of transistor E5 is connected to the power supply voltage VDD, the gate of transistor E5 is respectively connected to one end of resistor R9 and the gate of transistor D16, the drain of transistor D16 is connected to VOUT_2A, and the source of transistor D16 is connected to the other end of resistor R9;

[0096] The gate of transistor D19 is respectively connected to one end of resistor R11 and the gate of transistor E6, the source of transistor D19 is connected to the other end of resistor R11, the source of transistor E6 is connected to power supply voltage VDD, the drain of transistor E6 is respectively connected to one end of resistor R12 and the gate of transistor D20, and serves as the output end of the first AND gate circuit, the drain of transistor D20 is grounded, and the source of transistor D20 is connected to the other end of resistor R12.

[0097] Correspondingly, the NAND gate of another AND gate circuit includes transistor d16, transistor d17, transistor d18, transistor e4, transistor e5, resistor r8, resistor r9 and resistor r10; the inverter circuit of the first AND gate circuit includes transistor d19, transistor d20, transistor e6, resistor r11 and resistor r12;

[0098] Wherein, the drain of transistor d17 is connected to VOUT_1B, the gate of transistor d17 is respectively connected to one end of resistor r8 and the gate of transistor e4, the source of transistor d17 is connected to the other end of resistor r8, the drain of transistor e4 is connected to the gate of transistor d18, one end of resistor r10 and the drain of transistor d19, the other end of resistor r10 is connected to the drain of transistor d18 and grounded, the source of transistor e4 is connected to the drain of transistor e5, the source of transistor e5 is connected to the power supply voltage VDD, the gate of transistor e5 is respectively connected to one end of resistor r9 and the gate of transistor d16, the drain of transistor d16 is connected to VOUT_2B, and the source of transistor d16 is connected to the other end of resistor r9;

[0099] The gate of transistor d19 is respectively connected to one end of resistor r11 and the gate of transistor e6, the source of transistor d19 is connected to the other end of resistor r11, the source of transistor e6 is connected to the power supply voltage VDD, the drain of transistor e6 is respectively connected to one end of resistor r12 and the gate of transistor d20, and serves as the output end of the second AND gate circuit, the drain of transistor d20 is grounded, and the source of transistor d20 is connected to the other end of resistor r12.

[0100] The NOR gate includes a transistor D21, a transistor D22, a transistor D23, a resistor R13, a resistor R14, a resistor R15, a transistor E7 and a transistor E8; the NOT gate inverter circuit includes a transistor D24, a transistor D25, a transistor E9, a resistor R16 and an AND resistor R17;

[0101] Wherein, the drain of transistor D21 is connected to the output end of the first AND gate circuit, the source of transistor D21 is connected to one end of resistor R13, the gate of transistor D21 is respectively connected to the other end of resistor R1 and the gate of transistor E7, the source of transistor E7 is connected to the power supply voltage VDD, the drain of transistor E7 is respectively connected to one end of resistor R14, the gate of transistor D23, the drain of transistor E8 and the drain of transistor D24, the drain of transistor D23 is grounded, the source of transistor D23 is connected to the other end of resistor R14, the drain of transistor D22 is connected to the output end of the second AND gate circuit, the gate of transistor D22 is respectively connected to one end of resistor R15 and the gate of transistor E8, the source of transistor D22 is connected to the other end of resistor R15, and the source of transistor E8 is connected to the power supply voltage VDD;

[0102] The gate of transistor D24 is respectively connected to one end of resistor R16 and the gate of transistor E9, the source of transistor D24 is connected to the other end of resistor R16, the source of transistor E9 is connected to power supply voltage VDD, the drain of transistor E9 is respectively connected to one end of resistor R17 and the gate of transistor D25, and serves as the output end of the exclusive OR logic output module to output VOUT_3, the drain of transistor D25 is grounded, and the source of transistor D25 is connected to the other end of resistor R17.

[0103] The VOUT_3 signal is controlled by VIN_A and VIN_B at the same time. When the inputs are the same, the output is high level, and when they are not, the output is low level, which satisfies the logic output of the XOR gate. From the logical expression, we can see that VOUT_3 can be stepped down by VIN_A and VIN_B, and the reverse signal and the same direction signal are output through the AND gate and OR gate respectively. The AND gate and OR gate circuits are realized by using E / D-PHEMT as shown in Figure 3 The third part is shown as the logic output module.

[0104] The AND gate circuit based on GaAs technology can be composed of a NAND gate and an inverter. The NAND gate is similar to the inverter structure. An additional input terminal is connected in series on the main switch circuit. Two EPHEMTs are connected in series. Only when the two input signals are high at the same time can they be turned on and output a low level. Otherwise, they output a high level, and then the AND gate logic is realized through the inverter. The OR gate can also be composed of a NOR gate and an inverter. On the basis of the original inverter, an additional input terminal is connected in parallel. Two EPHEMTs are connected in parallel. As long as one of the inputs is high, a low level is output, and then the OR gate logic is realized through the inverter.

[0105] Example 2 is based on the same inventive concept as Example 1. Figure 2 As shown, this embodiment introduces a radio frequency switch, including a MOS switch S1, a first grounding resistor, a series-parallel complementary switch S2, a second grounding resistor, a series-parallel complementary switch S3, a third grounding resistor, a radio frequency input terminal RFIN and a radio frequency switch control circuit;

[0106] One end of the MOS switch S1 is grounded through a first grounding resistor, the other end of the MOS switch S1 is connected to the radio frequency input terminal RFIN, a first fixed end of the series-parallel complementary switch S2 is grounded through a second grounding resistor, a second fixed end of the series-parallel complementary switch S2 is connected to the radio frequency input terminal RFIN, a moving end of the series-parallel complementary switch S2 is connected to the first radio frequency signal RF1, a first fixed end of the series-parallel complementary switch S3 is grounded through a second grounding resistor, a second fixed end of the series-parallel complementary switch S3 is connected to the radio frequency input terminal RFIN, and a moving end of the series-parallel complementary switch S3 is connected to the second radio frequency signal RF2;

[0107] The complementary reverse output module of the radio frequency switch control circuit is used to control the closing direction of the series-parallel complementary switch S2 and the series-parallel complementary switch S3, and the exclusive-OR logic output module of the radio frequency switch control circuit is used to control the opening and closing of the MOS switch S1.

[0108] The working process of the RF switch is as follows: when MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed upward, and the series-parallel complementary switch S3 is closed downward, the RF1 signal enters the RF input terminal RFIN, and the RF2 signal is short-circuited to the ground; when MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed downward, and the series-parallel complementary switch S3 is closed upward, the RF2 signal enters the RF input terminal RFIN, and the RF2 signal is short-circuited to the ground; when S1 is closed, the RF input port is short-circuited to the ground, and no signal is input. MOS switch S1 is composed of a single MOS switch, and the series-parallel complementary switch S2 and the series-parallel complementary switch S3 adopt series-parallel complementary switches, such as Figure 3 As shown, taking the series-parallel complementary switch S2 as an example, when VOUT_1A and VOUT_1B input high level and low level respectively, the signal is turned on and flows from IN to OUT.

[0109] The series-parallel complementary switch includes a first MOS tube and a second MOS tube;

[0110] The gate of the first MOS tube inputs a first level signal, the source of the first MOS tube inputs a radio frequency signal, the drain of the first MOS tube is connected to the drain of the second MOS tube and the radio frequency input terminal RFIN, the gate of the second MOS tube inputs a second level signal, and the source of the second MOS tube is connected to the power supply voltage VDD;

[0111] When the first level signal is at a high level and the second level signal is at a low level, the first MOS tube is turned on, the second MOS tube is turned off, and the series-parallel complementary switch is closed upward;

[0112] When the first level signal is at a low level and the second level signal is at a high level, the first MOS tube is disconnected, the second MOS tube is turned on, and the series-parallel complementary switch is closed downward.

[0113] Two control bits are used to simultaneously control the MOS switch S1 and the series-parallel complementary switch S2 and the series-parallel complementary switch S3; the level conversion module realizes the conversion from the input level 0-5V to the output level -5V-0V. The complementary reverse output module realizes the control of the series-parallel complementary switch S2 and the series-parallel complementary switch S3, and the companion logic output realizes the control of the MOS switch S1.

[0114] Embodiment 3, based on the same inventive concept as other embodiments, this embodiment introduces a control method of a radio frequency switch.

[0115] The input TTL logic input levels are VIN_A low level and VIN_B high level, then the outputs are VOUT_1A low level, VOUT_1B high level, VOUT_2A high level, VOUT_2B low level, and VOUT_3 low level. At this time, the MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed downward, and the series-parallel complementary switch S3 is closed upward. The second RF signal RF2 is connected to the RF input terminal RFIN, and the first RF signal RF1 is short-circuited to the ground;

[0116] The input TTL logic input levels are VIN_A high level and VIN_B low level, then the outputs are VOUT_1A high level, VOUT_1B low level, VOUT_2A low level, VOUT_2B high level, and VOUT_3 low level. At this time, the MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed upward, and the series-parallel complementary switch S3 is closed downward. The first RF signal RF1 is connected to the RF input terminal RFIN, and the second RF signal RF2 is short-circuited to the ground;

[0117] The input TTL logic input levels are VIN_A low level and VIN_B low level respectively, then the outputs are VOUT_1A low level, VOUT_1B high level, VOUT_2A low level, VOUT_2B high level, and VOUT_3 high level. At this time, the MOS switch S1 is closed, the series-parallel complementary switch S2 is closed downward, and the series-parallel complementary switch S3 is closed downward. The first radio frequency signal RF1 and the second radio frequency signal RF2 are both short-circuited to the ground;

[0118] The input TTL logic input levels are VIN_A high level and VIN_B high level respectively, then the outputs are VOUT_1A high level, VOUT_1B low level, VOUT_2A high level, VOUT_2B low level, and VOUT_3 high level. At this time, the MOS switch S1 is closed, the series-parallel complementary switch S2 is closed upward, and the series-parallel complementary switch S3 is closed upward, and the first RF signal RF1 and the second RF signal RF2 are both short-circuited to ground.

[0119] The digital logic truth table required by the RF switch is shown in Table 1:

[0120] Table 1

[0121]

[0122] Among them, Li represents 0V, Hi represents 5V, Lo represents -5V, and Ho represents 0V. The input is two-way signal, and the output is five-way signal. VOUT_1A and VOUT_1B are two complementary outputs, which control the series-parallel complementary switch S2. VOUT_2A and VOUT_2B are two complementary outputs, which control the series-parallel complementary switch S3. VOUT_3 controls the MOS switch S1.

[0123] like Figure 4-Figure 10 As shown in the figure, the simulation results of the digital logic generation circuit are given, and the specific input and output conditions are as follows:

[0124] Using negative power supply -5V, when input VIN_A is 5V, VIN_B is 5V, complementary reverse output VOUT_1A outputs 0V, VOUT_1B outputs -5V; VOUT_2A outputs 0V, VOUT_2B outputs -5V. The OR logic VOUT_3 outputs 0V.

[0125] Using negative power supply -5V, when input VIN_A is 5V and VIN_B is 0V, complementary reverse output VOUT_1A outputs 0V, VOUT_1B outputs -5V; VOUT_2A outputs -5V, VOUT_2B outputs 0V. The same OR logic VOUT_3 outputs -5V.

[0126] Using negative power supply -5V, when input VIN_A is 0V and VIN_B is 5V, complementary reverse output VOUT_1A outputs -5V, VOUT_1B outputs 0V; VOUT_2A outputs 0V, VOUT_2B outputs -5V. The same OR logic VOUT_3 outputs -5V.

[0127] Using negative power supply -5V, when input VIN_A is 0V, VIN_B is 0V, complementary reverse output VOUT_1A outputs -5V, VOUT_1B outputs 0V; VOUT_2A outputs -5V, VOUT_2B outputs 0V. The same OR logic VOUT_3 outputs 0V.

[0128] Through the above design, the purpose of using two digital inputs to generate five digital step-down outputs is achieved, thereby controlling the on and off of the RF switch, reducing the number of chip pins, realizing chip miniaturization design, and meeting the current market requirements.

[0129] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0130] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0131] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0132] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0133] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A radio frequency switch control circuit, characterized in that: include: Level conversion module, complementary reverse output module and exclusive OR logic output module; The level conversion module receives the TTL logic input level and converts the TTL logic input level into a plurality of target output levels; The complementary reverse output module receives a plurality of target output levels, and outputs two complementary levels through a primary inverter and a secondary inverter according to the target output level of each path, and controls the opening and closing of the series-parallel complementary switches of the RF switch through the two levels; The XOR logic output module receives all the complementary two-way levels output by the complementary reverse output module, performs AND gate and OR gate logic processing on all the complementary two-way levels, and outputs one-way level of a single MOS switch that controls the RF switch; The level conversion module includes a plurality of level conversion circuits, each of which includes a step-down diode and a large resistance circuit; The large resistance circuit includes a resistor and a D-pHEMT, where D-pHEMT represents a depletion-type pseudo high electron mobility transistor; The buck diode is composed of a plurality of source-drain connected D-pHEMTs in series, the gate of the first D-pHEMT of the buck diode is connected to the TTL logic input level, the source or drain of the last D-pHEMT is connected to the drain of the D-pHEMT of the large resistance circuit and the complementary reverse output module; the source of the D-pHEMT of the large resistance circuit is connected to one end of the resistor, and the other end of the resistor is connected to the gate of the D-pHEMT of the large resistance circuit and the power supply voltage VDD; The complementary reverse output module includes a plurality of complementary reverse output circuits corresponding one-to-one to the plurality of level conversion circuits; The complementary reverse output circuit includes three inverter circuits, one of which constitutes the primary inverter, and the other two inverter circuits are connected in series to constitute the secondary inverter; The inverter circuit includes a first inverter D-pHEMT, a second inverter D-pHEMT, a first inverter resistor, a second inverter resistor and an inverter E-pHEMT, where E-pHEMT represents an enhanced pseudo high electron mobility transistor; The drain of the first D-pHEMT of the inverter is the input end of the inverter circuit, the gate of the first D-pHEMT of the inverter is connected to one end of the first resistor of the inverter and the gate of the inverter E-pHEMT, the source of the first D-pHEMT of the inverter is connected to the other end of the first resistor of the inverter, the source of the inverter E-pHEMT is connected to the power supply voltage VDD, the drain of the inverter E-pHEMT is connected to one end of the second resistor of the inverter and the gate of the second D-pHEMT of the inverter, the drain of the inverter E-pHEMT also serves as the output end of the inverter circuit, the drain of the second D-pHEMT of the inverter is grounded, and the source of the second D-pHEMT of the inverter is connected to the other end of the second resistor; The input ends of the primary inverter and the secondary inverter are both connected to the target output level, the output end of the secondary inverter outputs a first complementary level, and the output end of the primary inverter outputs a second complementary level; The XOR logic output module includes two AND gate circuits and one OR gate circuit; The AND gate circuit includes a NAND gate and a NAND gate inverter circuit, and the OR gate circuit includes a NOR gate and a NOR gate inverter circuit; The NAND gate includes a first NAND gate D-pHEMT, a second NAND gate D-pHEMT, a third NAND gate D-pHEMT, a first NAND gate E-pHEMT, a second NAND gate E-pHEMT, a first NAND gate resistor, a second NAND gate resistor and a third NAND gate resistor; The drain of the first NAND gate D-pHEMT is connected to the first complementary level output by a secondary inverter, the gate of the first NAND gate D-pHEMT is respectively connected to one end of the first NAND gate resistor and the gate of the first NAND gate E-pHEMT, the source of the first NAND gate D-pHEMT is connected to the other end of the first NAND gate resistor, the drain of the first NAND gate E-pHEMT is connected to the gate of the third NAND gate D-pHEMT, one end of the third NAND gate resistor and the input end of the NAND gate inverter circuit, and the other end of the third NAND gate resistor is connected to the NAND gate. The drain of the third NAND gate D-pHEMT is connected to the ground, the source of the first NAND gate E-pHEMT is connected to the drain of the second NAND gate E-pHEMT, the source of the second NAND gate E-pHEMT is connected to the power supply voltage VDD, the gate of the second NAND gate E-pHEMT is respectively connected to one end of the second NAND gate resistor and the gate of the second NAND gate D-pHEMT, the drain of the second NAND gate D-pHEMT is connected to the first complementary level output by another secondary inverter, and the source of the second NAND gate D-pHEMT is connected to the other end of the second NAND gate resistor; The NOR gate includes a first NOR gate D-pHEMT, a second NOR gate D-pHEMT, a third NOR gate D-pHEMT, a first NOR gate resistor, a second NOR gate resistor, a third NOR gate resistor, a first NOR gate E-pHEMT and a second NOR gate E-pHEMT; The drain of the first D-pHEMT of the NOR gate is connected to the output end of the NAND gate inverter circuit in the AND gate circuit, the source of the first D-pHEMT of the NOR gate is connected to one end of the first resistor of the NOR gate, the gate of the first D-pHEMT of the NOR gate is respectively connected to the other end of the first resistor of the NOR gate and the gate of the first E-pHEMT of the NOR gate, the source of the first E-pHEMT of the NOR gate is connected to the power supply voltage VDD, and the drain of the first E-pHEMT of the NOR gate is respectively connected to one end of the third resistor of the NOR gate, the gate of the third D-pHEMT of the NOR gate, the drain of the second E-pHEMT of the NOR gate and the input of the NOR gate inverter circuit. The drain of the third NOR gate D-pHEMT is grounded, the source of the third NOR gate D-pHEMT is connected to the other end of the third NOR gate resistor, the drain of the second NOR gate D-pHEMT is connected to the output end of the NAND gate inverter circuit of another AND gate circuit, the gate of the second NOR gate D-pHEMT is respectively connected to one end of the second NOR gate resistor and the gate of the second NOR gate E-pHEMT, the source of the second NOR gate D-pHEMT is connected to the other end of the second NOR gate resistor, the source of the second NOR gate E-pHEMT is connected to the power supply voltage VDD, and the output end of the NOR gate inverter circuit is the output port of the exclusive OR logic output module.

2. The radio frequency switch control circuit according to claim 1, characterized in that: The enhancement-mode pseudo high electron mobility transistor and the depletion-mode pseudo high electron mobility transistor are both GaAs-based transistors.

3. The radio frequency switch control circuit according to claim 1, characterized in that: The TTL logic input level is 5V / 0V, the target output level is 0V / -5V, the two complementary levels are a high level of 0V and a low level of -5V, and the one level is a high level of 0V or a low level of -5V.

4. A radio frequency switch, characterized in that: It comprises a MOS switch S1, a first grounding resistor, a series-parallel complementary switch S2, a second grounding resistor, a series-parallel complementary switch S3, a third grounding resistor, a radio frequency input terminal RFIN and a radio frequency switch control circuit according to any one of claims 1 to 3; One end of the MOS switch S1 is grounded through a first grounding resistor, the other end of the MOS switch S1 is connected to the radio frequency input terminal RFIN, a first fixed end of the series-parallel complementary switch S2 is grounded through a second grounding resistor, a second fixed end of the series-parallel complementary switch S2 is connected to the radio frequency input terminal RFIN, a moving end of the series-parallel complementary switch S2 is connected to the first radio frequency signal RF1, a first fixed end of the series-parallel complementary switch S3 is grounded through a second grounding resistor, a second fixed end of the series-parallel complementary switch S3 is connected to the radio frequency input terminal RFIN, and a moving end of the series-parallel complementary switch S3 is connected to the second radio frequency signal RF2; The complementary reverse output module of the radio frequency switch control circuit is used to control the closing direction of the series-parallel complementary switch S2 and the series-parallel complementary switch S3, and the exclusive-OR logic output module of the radio frequency switch control circuit is used to control the opening and closing of the MOS switch S1.

5. The radio frequency switch according to claim 4, characterized in that: The first pair of complementary two-way levels output by the complementary reverse output module are VOUT_1A and VOUT_1B respectively; The second pair of complementary levels output by the complementary reverse output module are VOUT_2A and VOUT_2B respectively, and the level output by the XOR logic output module is VOUT_3; The TTL logic input levels are VIN_A and VIN_B, wherein VIN_A controls the levels corresponding to VOUT_1A and VOUT_1B, and VIN_B controls the levels corresponding to VOUT_2A and VOUT_2B.

6. The radio frequency switch according to claim 5, characterized in that: The circuit structures of the series-parallel complementary switch S2 and the series-parallel complementary switch S3 both include: a first MOS transistor and a second MOS transistor; The gate of the first MOS tube inputs a first level signal, the source of the first MOS tube inputs a radio frequency signal, the drain of the first MOS tube is connected to the drain of the second MOS tube and the radio frequency input terminal RFIN, the gate of the second MOS tube inputs a second level signal, and the source of the second MOS tube is connected to the power supply voltage VDD; When the first level signal is at a high level and the second level signal is at a low level, the first MOS tube is turned on, the second MOS tube is turned off, and the series-parallel complementary switch is closed upward; When the first level signal is at a low level and the second level signal is at a high level, the first MOS tube is disconnected, the second MOS tube is turned on, and the series-parallel complementary switch is closed downward.

7. A control method for the radio frequency switch according to claim 5, characterized in that: The input TTL logic input levels are VIN_A low level and VIN_B high level, then the outputs are VOUT_1A low level, VOUT_1B high level, VOUT_2A high level, VOUT_2B low level, and VOUT_3 low level. At this time, the MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed downward, and the series-parallel complementary switch S3 is closed upward. The second RF signal RF2 is connected to the RF input terminal RFIN, and the first RF signal RF1 is short-circuited to the ground; The input TTL logic input levels are VIN_A high level and VIN_B low level, then the outputs are VOUT_1A high level, VOUT_1B low level, VOUT_2A low level, VOUT_2B high level, and VOUT_3 low level. At this time, the MOS switch S1 is disconnected, the series-parallel complementary switch S2 is closed upward, and the series-parallel complementary switch S3 is closed downward. The first RF signal RF1 is connected to the RF input terminal RFIN, and the second RF signal RF2 is short-circuited to the ground; The input TTL logic input levels are VIN_A low level and VIN_B low level respectively, then the outputs are VOUT_1A low level, VOUT_1B high level, VOUT_2A low level, VOUT_2B high level, and VOUT_3 high level. At this time, the MOS switch S1 is closed, the series-parallel complementary switch S2 is closed downward, and the series-parallel complementary switch S3 is closed downward. The first radio frequency signal RF1 and the second radio frequency signal RF2 are both short-circuited to the ground; The input TTL logic input levels are VIN_A high level and VIN_B high level respectively, then the outputs are VOUT_1A high level, VOUT_1B low level, VOUT_2A high level, VOUT_2B low level, and VOUT_3 high level. At this time, the MOS switch S1 is closed, the series-parallel complementary switch S2 is closed upward, and the series-parallel complementary switch S3 is closed upward, and the first RF signal RF1 and the second RF signal RF2 are both short-circuited to ground.

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