Chip testing method, system and storage medium

Abstract

The present application provides a chip testing method, system and storage medium, wherein a first electronic device intermittently sends a second electrical signal to a second electronic device, and receives a detection result corresponding to each second electrical signal, and the second electronic device is used to send a corresponding test instruction to the chip to be tested each time the second electrical signal is received, and obtain a target signal of the chip to be tested under a target test, and the second electronic device is also used to generate a corresponding detection result according to each target signal and send it to the first electronic device, and each detection result is used to indicate whether the chip to be tested passes the corresponding target test. Therefore, after receiving the detection result corresponding to each second electrical signal, the first electronic device can determine whether the chip to be tested is normal according to the detection result corresponding to each second electrical signal. And since the detection frequency of the second electronic device is greater than the detection frequency of the first electronic device, the detection cycle can be shortened, thereby improving the coverage and test accuracy of the chip during the chip testing process.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a chip testing method, system and storage medium. Background Art

[0002] Currently, chip testing is mostly done using Automatic Test Equipment (ATE). Chip ATE is a special device used to test and verify integrated circuit chips. Chip ATE can automatically execute test programs and perform functional tests, performance tests, and reliability tests on chips to ensure the quality and reliability of the chips.

[0003] The current chip automatic test equipment has a low detection frequency, resulting in high time precision, which in turn affects the chip coverage and test accuracy. Summary of the invention

[0004] The present application provides a chip testing method, system and storage medium to improve the coverage and testing accuracy of the chip during the testing process.

[0005] In a first aspect, the present application provides a chip testing method, the method being used in a first electronic device, the method comprising:

[0006] Sending a first electrical signal to the chip under test to turn on the chip under test;

[0007] intermittently sending a second electrical signal to a second electronic device, and receiving a detection result corresponding to each of the second electrical signals; the second electronic device is used to send a corresponding test instruction to the chip under test each time it receives the second electrical signal, and obtain a target signal of the chip under test under the target test; the second electronic device is also used to generate a corresponding detection result according to each target signal and send it to the first electronic device, and each detection result is used to indicate whether the chip under test passes the corresponding target test;

[0008] Determining whether the chip to be tested is normal according to the detection result corresponding to each of the second electrical signals;

[0009] The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

[0010] Optionally, sending a first electrical signal to the chip under test so that the chip under test is in a turned-on state specifically includes:

[0011] A preset voltage is sent to the chip under test to put the chip under test in an on state.

[0012] Optionally, intermittently sending the second electrical signal to the second electronic device specifically includes:

[0013] intermittently sending a reset signal and a test mode selection signal to the second electronic device, each test mode selection signal corresponding to a target test;

[0014] The reset signal is used to instruct the second electronic device to initialize, each of the test mode selection signals is used to instruct the second electronic device to send a corresponding test instruction to the chip under test, and each test instruction is used to instruct the chip under test to perform a corresponding target test.

[0015] Optionally, the test mode selection signal includes N channels, where N is an integer greater than 1;

[0016] Each of the test mode selection signals is determined by the level of each channel.

[0017] In a second aspect, the present application provides a chip testing method, the method being used for a second electronic device, the method comprising:

[0018] intermittently receiving a second electrical signal sent by the first electronic device;

[0019] Each time a second electrical signal is received, a corresponding test instruction is sent to the chip under test to obtain a target signal of the chip under test under a target test, wherein the chip under test is in an on state;

[0020] Each time a target signal is acquired, a corresponding detection result is generated according to the target signal, and the detection result is sent to the first electronic device, so that the first electronic device determines whether the chip to be tested is normal according to each detection result; each detection result is used to indicate whether the target chip passes the corresponding target test;

[0021] The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

[0022] Optionally, the second electrical signal includes a reset signal and a test mode selection signal;

[0023] The step of sending a corresponding test instruction to the chip under test each time a second electrical signal is received specifically includes:

[0024] Initialization is performed each time a reset signal and a test mode selection signal are received;

[0025] Generate corresponding test instructions according to the test mode selection signal, and send the test instructions to the chip under test; each test instruction is used to instruct the chip under test to perform a corresponding target test.

[0026] Optionally, generating a corresponding detection result according to the target signal specifically includes:

[0027] If the first level in the target signal is maintained for a preset time, the generated detection result is used to indicate that the chip under test has passed the target test;

[0028] If the second level in the target signal is maintained for a preset time, the generated detection result is used to indicate that the chip under test has failed the target test;

[0029] The first level is greater than the second level.

[0030] The obtaining of the target signal of the chip under test under the target test specifically includes:

[0031] When the chip under test changes from the second level to the first level, start collecting the first level signal;

[0032] Calculating the maintenance time of the first level according to the number of samples collected of the first level signal and the sampling period;

[0033] When the chip under test changes from the first level to the second level, start collecting the second level signal;

[0034] The maintenance time of the second level is calculated according to the number of samples collected of the second level signal and a sampling period.

[0035] In a third aspect, the present application provides a chip testing device, comprising:

[0036] A first sending module, used for sending a first electrical signal to the chip under test, so that the chip under test is in a turned-on state;

[0037] A second sending module is used to intermittently send a second electrical signal to a second electronic device, and receive a detection result corresponding to each of the second electrical signals; the second electronic device is used to send a corresponding test instruction to the chip under test each time it receives the second electrical signal, and obtain a target signal of the chip under test under the target test; the second electronic device is also used to generate a corresponding detection result according to each target signal and send it to the first electronic device, and each detection result is used to indicate whether the chip under test passes the corresponding target test;

[0038] A judging module, used for judging whether the chip to be tested is normal according to the detection result corresponding to each of the second electrical signals;

[0039] The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

[0040] In a fourth aspect, the present application provides a chip testing device, comprising:

[0041] A receiving module, used for intermittently receiving a second electrical signal sent by the first electronic device;

[0042] A third sending module is used to send a corresponding test instruction to the chip under test every time a second electrical signal is received, and obtain a target signal of the chip under test under a target test, wherein the chip under test is in an on state;

[0043] A fourth sending module is used to obtain a target signal each time, generate a corresponding detection result according to the target signal, and send the detection result to the first electronic device, so that the first electronic device determines whether the chip to be tested is normal according to each detection result; each detection result is used to indicate whether the target chip passes the corresponding target test;

[0044] The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

[0045] In a fifth aspect, the present application provides an electronic device, including: a memory and a processor;

[0046] The memory is used to store instructions; the processor is used to call the instructions in the memory to execute the method in the first aspect and any possible design of the first aspect.

[0047] In a sixth aspect, the present application provides an electronic device, including: a memory and a processor;

[0048] The memory is used to store instructions; the processor is used to call the instructions in the memory to execute the method in the second aspect and any possible design of the second aspect.

[0049] In a seventh aspect, the present application provides a chip testing system, comprising a first electronic device and a second electronic device, wherein the first electronic device is used to execute the method in the first aspect and any possible design of the first aspect, and the second electronic device is used to execute the method in the second aspect and any possible design of the second aspect.

[0050] Optionally, the first electronic device is an integrated circuit automatic tester, and the second electronic device is a field programmable logic gate array.

[0051] On the eighth aspect, the present application provides a computer-readable storage medium, in which computer instructions are stored. When at least one processor of an electronic device executes the computer instructions, the electronic device executes the above method.

[0052] In a ninth aspect, the present application provides a computer program product, which includes computer instructions. When at least one processor of an electronic device executes the computer instructions, the electronic device executes the above method.

[0053] The chip testing method, system and storage medium provided by the present application, the first electronic device sends a first electrical signal to the chip to be tested to put the chip to be tested in an on state, and then the first electronic device intermittently sends a second electrical signal to the second electronic device, and receives the detection result corresponding to each second electrical signal, the second electronic device is used to send a corresponding test instruction to the chip to be tested each time the second electrical signal is received, and obtain the target signal of the chip to be tested under each target test, and the second electronic device is also used to generate a corresponding detection result according to each target signal and send it to the first electronic device, and each detection result is used to indicate whether the chip to be tested passes the corresponding target test. Therefore, after receiving the detection result corresponding to each second electrical signal, the first electronic device can judge whether the chip to be tested is normal according to the detection result corresponding to each second electrical signal. And because the detection frequency of the second electronic device is greater than the detection frequency of the first electronic device, the detection cycle can be shortened, thereby improving the coverage and test accuracy of the chip during the chip testing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 A schematic diagram of a chip testing method provided in one embodiment of the present application;

[0056] Figure 2 A schematic diagram of a chip testing method provided in another embodiment of the present application;

[0057] Figure 3 A signaling interaction diagram of a chip testing system provided in one embodiment of the present application;

[0058] Figure 4 A schematic diagram of the structure of a chip testing device provided in one embodiment of the present application;

[0059] Figure 5 A schematic diagram of the structure of a chip testing device provided in another embodiment of the present application;

[0060] Figure 6 A schematic diagram of the hardware structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0062] Chips play an important role in many fields and play a vital role in promoting social progress and scientific and technological development. For example, chips are the foundation of the information technology industry, and chip technology is a leading industry for the development of high-tech in the future. The development of chips will lead and promote the development of other related industries, such as artificial intelligence, the Internet of Things, 5G, etc.

[0063] Currently, chip testing is mostly done using Automatic Test Equipment (ATE). Chip ATE is a special device used to test and verify integrated circuit chips. Chip ATE can automatically execute test programs and perform functional tests, performance tests, and reliability tests on chips to ensure the quality and reliability of the chips.

[0064] Chip automatic testing equipment has a variety of technical parameters, such as the number of test channels, test accuracy, test speed, chip support range, test voltage range, test function range, test temperature range, test interface, software support, data storage and output, reliability and stability, scalability and upgradeability, etc.

[0065] The number of test channels refers to the number of test channels that chip automatic test equipment usually has. Each channel can test one chip at the same time. The number of channels directly affects the test efficiency and production capacity.

[0066] Test accuracy refers to the deviation between the test result and the actual value. The higher the test accuracy, the more accurate the test result, and the better it can detect chip problems.

[0067] The test speed refers to the number of tests that each test channel can complete per second. The faster the test speed, the higher the test efficiency, and the faster the chip test can be completed.

[0068] The chip support range means that the chip automatic testing equipment needs to support multiple types of chip tests, including digital chips, analog chips, mixed signal chips, etc. The wider the chip support range, the more types of chips are applicable.

[0069] The test voltage range means that the chip automatic test equipment needs to be able to provide different test voltages to meet the operating voltage requirements of different chips. The wider the test voltage range, the more types of chips it can be applied to.

[0070] The test power range means that the chip automatic test equipment needs to be able to provide different test powers to meet the power consumption requirements of different chips. The wider the test power range, the more types of chips it can be applied to.

[0071] The test temperature range means that the chip automatic test equipment needs to be able to perform tests under different temperature conditions to simulate the performance of the chip under different working environments. The wider the test temperature range, the more types of chips are applicable.

[0072] The test interface refers to the interface that the chip automatic test equipment needs to provide to communicate with the chip under test. Common interfaces include I2C (Inter-Integrated Circuit, integrated circuit bus), SPI (Inter-Integrated Circuit, serial peripheral interface), etc. Different chips may require different interfaces.

[0073] Software support means that chip automatic test equipment needs to be equipped with corresponding test software to realize the writing, execution and analysis of test programs. The functions and ease of use supported by the software directly affect the efficiency and accuracy of the test.

[0074] Data storage and output means that chip automatic test equipment needs to be able to store and output test results for subsequent data analysis.

[0075] Reliability and stability mean that chip automatic testing equipment needs to have good reliability and stability and be able to operate stably for a long time to ensure the accuracy and reliability of the test results.

[0076] Scalability and upgradeability mean that chip automatic test equipment needs to have certain scalability and upgradeability to adapt to the ever-changing chip testing needs, and be able to easily add new test functions and interfaces, or upgrade hardware and software.

[0077] The applicant has found that the detection frequency of current chip automatic testing equipment is low, resulting in high time precision, which in turn affects the chip coverage and test accuracy.

[0078] For example, the detection frequency of chip automatic testing equipment is generally 100HMz, and the corresponding time accuracy is 10ns. Therefore, 10ns is a detection cycle. If the chip automatic testing equipment generates a 25ns high-level excitation signal, the chip under test can only generate an electrical signal for 20ns of the high-level excitation signal in the 25ns, and there is an error of 5ns (the deviation between the test result and the actual value), resulting in low chip coverage and test accuracy.

[0079] In response to the above problems, the present application proposes a chip testing method, wherein a first electronic device intermittently sends a second electrical signal to a second electronic device, and the second electronic device is used to generate a corresponding test instruction each time it receives a second electrical signal, so that the chip to be tested performs a target test and obtains a target signal of the chip to be tested under the target test. The second electronic device can also be used to output a detection result based on the target signal, and each detection result indicates whether the chip to be tested has passed the corresponding target test. Subsequently, the first electronic device can determine whether the chip to be tested is normal based on each detection result sent by the second electronic device. Since the detection frequency of the second electronic device is greater than the detection frequency of the first electronic device, the detection cycle can be shortened, thereby improving the chip coverage and test accuracy.

[0080] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0081] Figure 1 FIG. 1 is a flow chart of a chip testing method provided by an embodiment of the present application. Figure 1 As shown, with the first electronic device (for example, a chip automatic test device) as the execution subject, the method of this embodiment may include the following steps:

[0082] S101: A first electronic device sends a first electrical signal to a chip under test to turn on the chip under test.

[0083] In practical applications, the first electronic device may be a chip automatic testing device, or other chip testing equipment, such as a probe testing device.

[0084] In this step, the first electronic device sends a first electrical signal to the chip under test. The first electrical signal can be understood as a startup instruction. At this time, the chip under test starts to start up and is in a startup state.

[0085] It should be noted that after the chip under test is started, it can receive test instructions, enter test mode, etc. The test instructions can be understood as signal stimulation of the chip under test so that the chip under test can generate a corresponding target signal (electrical signal). The target signal can be, for example, voltage, current, resistance, etc. Subsequent electronic equipment can determine whether the chip under test has passed the corresponding target test based on the target signal.

[0086] In some examples, the first electronic device may send a preset voltage to the chip under test to turn on the chip under test, wherein the preset voltage may be determined according to the operating voltage of the chip under test.

[0087] In other examples, the first electronic device may also send a preset voltage and a preset current to the chip under test to turn on the chip under test, wherein the preset voltage and the preset current may be determined according to the operating voltage and the operating current of the chip under test.

[0088] In practical applications, the chip to be tested can be loaded on a test board (Loadboard), for example, a chip test socket (SOCKET) can be used to load the chip to be tested and the working circuit of the chip to be tested. When the chip to be tested is inserted into the chip test socket, the chip test socket can be electrically connected to the pins of the chip to be tested and send a test signal to the chip to be tested, and the chip test socket can read the output signal of the chip to be tested and transmit the output signal to the electronic device.

[0089] S102: The first electronic device intermittently sends a second electronic signal to the second electronic device, and receives a detection result corresponding to each second electronic signal.

[0090] Among them, the second electronic device is used to send a corresponding test instruction to the chip to be tested each time it receives the second electrical signal, so as to perform a target test on the chip to be tested and obtain a target signal of the chip to be tested under the target test; the second electronic device is also used to generate a corresponding detection result according to each target signal and send it to the first electronic device, and each detection result is used to indicate whether the chip to be tested has passed the corresponding target test.

[0091] For example, the target test may include a functional test. Accordingly, after receiving the test instruction sent by the second electronic device, the chip under test may enable the corresponding target function and output the corresponding target signal. At this time, each test result is used to indicate whether the corresponding target function is normal. The target function may include a read function, a write function, etc.

[0092] The target test may also include a performance test. Accordingly, after receiving the test instruction sent by the second electronic device, the chip to be tested may perform a target performance test and output a corresponding target signal. At this time, each test result is used to indicate whether the corresponding target performance is normal. The target performance may include frequency, power consumption, etc.

[0093] The target test may also include a reliability test. Accordingly, after receiving the test instruction sent by the second electronic device, the chip to be tested may perform a reliability test and output a corresponding target signal. At this time, each test result is used to indicate whether a reliability test has been passed. Reliability tests may include electrostatic discharge, locking effect, etc.

[0094] In the embodiment of the present application, the detection frequency of the second electronic device is greater than the detection frequency of the first electronic device, thereby shortening the detection cycle and further improving the coverage and test accuracy of the chip to be tested.

[0095] For example, if the detection frequency of the first electronic device is 100MHz and the detection frequency of the second electronic device is 200MHz, the detection period of the first electronic device is 10ns, and the detection period of the second electronic device is 5ns. If the first electronic device generates a 25ns high-level excitation signal, the chip to be tested can only generate an electrical signal for the 20ns high-level excitation signal in the 25ns. If the second electronic device generates a 25ns high-level excitation signal, the chip to be tested can generate an electrical signal for the 25ns high-level excitation signal. Therefore, the coverage and test accuracy of the chip to be tested can be improved through the second electronic device.

[0096] In order to facilitate understanding of the solution of the present application, an example is taken in which a first electronic device sends two second electrical signals to a second electronic device for explanation.

[0097] Specifically, the first electronic device first sends a first second electrical signal to the second electronic device. When the second electronic device receives the first second electrical signal, it sends a corresponding first test instruction to the chip under test, so that the chip under test outputs a first target signal corresponding to the first target test. The second electronic device obtains the first target signal output by the chip under test, and generates a corresponding first detection result based on the first target signal, and sends the first detection result to the first electronic device. The first detection result is used to indicate whether the chip under test passes the first target test. The first target test can be, for example, a functional test, a performance test, a reliability test, etc.

[0098] Then, the first electronic device sends a second second electrical signal to the second electronic device, and the second second electrical signal is different from the first second electrical signal. When the second electronic device receives the second second electrical signal, it sends a corresponding second test instruction to the chip to be tested, so that the chip to be tested outputs a second target signal corresponding to the second target test. After the chip to be tested outputs the second target signal, the second electronic device obtains the second target signal output by the chip to be tested, generates a corresponding second detection result based on the second target signal, and sends the second detection result to the first electronic device. The second detection result is used to indicate whether the chip to be tested passes the second target test. Since the second second electrical signal is different from the first second electrical signal, the second target test is different from the first target test. The second target test can be a functional test, a performance test, a reliability test, etc.

[0099] It can be understood that when the first electronic device intermittently sends a second electrical signal to the second electronic device, the second electronic device can generate corresponding test instructions based on each second electrical signal, so that the chip under test outputs a corresponding target signal according to each test instruction, and then the second electronic device can generate corresponding detection results based on each target signal. Each detection result is used to indicate whether the chip under test passes a target test, so that multiple functions, performance, etc. of the chip under test can be tested.

[0100] In practical applications, the second electronic device may be, for example, a Field Programmable Gate Array (FPGA), or other testing equipment with a higher detection frequency.

[0101] For example, considering that the time required for each target test may be the same or different, the intermittent can be periodic or non-periodic. For example, when the time required for each target test is the same, the first electronic device can send a second electrical signal to the second electronic device at a preset time interval; when the time required for at least some of the target tests is different, the first electronic device can send a second electrical signal to the second electronic device at different time intervals. Among them, at least some of the second electrical signals are different, for example, the second electrical signals sent each time are different, so that multiple tests can be performed on the chip to be tested later.

[0102] In some embodiments, the first electronic device may intermittently send a reset signal and a test mode selection signal to the second electronic device, and each test mode selection signal corresponds to a target test. The reset mode is used to instruct the second electronic device to initialize. It should be noted that each time the second electronic device sends a test instruction to the chip to be tested, if the next test instruction is sent after initialization, the accuracy of the test instruction can be improved, thereby improving the test accuracy. The test mode selection signal is used to instruct the second electronic device to send a corresponding test instruction to the chip to be tested, and each test instruction is used to instruct the chip to be tested to perform a corresponding target test.

[0103] For example, the test mode selection signal sent by the first electronic device to the second electronic device each time is different, so as to perform different tests on the chip under test, such as tests of different functions, tests of different performances, etc. The first electronic device may also send the same test mode selection signal to the second electronic device multiple times, so as to perform a certain target test on the chip under test multiple times, thereby improving the test accuracy.

[0104] As an implementation, the test mode selection signal includes N channels, where N is an integer greater than 1, and each test mode selection signal is determined by the level of each channel. Specifically, each channel can be a high level or a low level, and there can be 2 N There are 2 options, which can generate N A test mode selection signal can be used to select the chip under test. N Item test.

[0105] For example, if N is 3, there may be eight test mode selection signals, for example, low level, low level, and low level are the first test mode selection signal; high level, high level, and high level are the second test mode selection signal; low level, low level, and high level are the third test mode selection signal; low level, high level, and high level are the fourth test mode selection signal; low level, high level, and low level are the fifth test mode selection signal; high level, low level, and low level are the sixth test mode selection signal; high level, high level, and low level are the seventh test mode selection signal; and high level, low level, and high level are the eighth test mode selection signal.

[0106] As an implementation method, the correspondence between the test mode selection signal and the test instruction can be stored in the second electronic device in advance, so that after receiving the test mode selection signal, the second electronic device can quickly send the corresponding test instruction to the chip under test.

[0107] S103: The first electronic device determines whether the chip to be tested is normal according to the detection result corresponding to each second electrical signal.

[0108] Since each test result is used to indicate whether the chip under test has passed the corresponding target test, it is possible to determine whether the chip under test is normal based on these test results. For example, when each test result indicates that the chip under test has passed the corresponding target test, the chip under test is determined to be normal, and when there are one or more test results indicating that the chip under test has not passed the corresponding target test, the chip under test is determined to be abnormal.

[0109] The chip testing method provided in the present application is that a first electronic device intermittently sends a second electrical signal to a second electronic device, and the second electronic device is used to generate a corresponding test instruction each time it receives a second electrical signal, and obtain a target signal of the chip to be tested under the target test. The second electronic device can also be used to output a detection result based on the target signal, and a detection result indicates that the chip to be tested has passed the corresponding target test. Subsequently, the first electronic device can determine whether the chip to be tested is normal based on each detection result sent by the second electronic device. Since the detection frequency of the second electronic device is greater than the detection frequency of the first electronic device, the detection cycle can be shortened, thereby improving the chip coverage and detection accuracy.

[0110] Figure 2 A chip testing method provided in an embodiment of the present application is as follows: Figure 2 As shown, the chip testing method provided in this embodiment includes:

[0111] S201: A second electronic device intermittently receives a second electrical signal sent by a first electronic device.

[0112] For example, the second electronic device may receive the second electrical signal sent by the first electronic device at a preset time interval, or may receive the second electrical signal sent by the first electronic device at different time intervals. The second electrical signal is used to instruct the second electronic device to send a test instruction to the chip under test.

[0113] By way of example, the second electrical signal may include a reset signal and a test mode selection signal, wherein the reset signal is used to instruct the second electronic device to initialize, and the test mode selection signal is used to instruct the second electronic device to send a corresponding test instruction to the chip under test, and each test instruction is used to instruct the chip under test to perform a corresponding target test.

[0114] S202: The second electronic device sends a corresponding test instruction to the chip under test every time it receives a second electrical signal, and obtains a target signal of the chip under test under a target test.

[0115] Among them, the chip to be tested is in the turned-on state.

[0116] In this step, each time the second electronic device receives the second electrical signal sent by the first electronic device, it can send a corresponding test instruction to the chip under test. When the chip under test is in the turned-on state, if it receives the test instruction sent by the second electronic device, it can output the corresponding target signal.

[0117] For example, the test instruction is used to instruct the chip under test to perform a certain function test. When the chip under test receives the test instruction, it can turn on the function and output a corresponding target signal.

[0118] In this embodiment, if the second electrical signal includes a reset signal and a test mode selection signal, the second electronic device can first perform an initialization operation, and then send a corresponding test instruction to the chip under test according to the test mode selection signal. Since the test mode selection signal corresponds to a target test, the test instruction is used to instruct the chip under test to perform a target test. At this time, the chip under test can output the corresponding target signal.

[0119] S203: The second electronic device obtains a target signal each time, generates a corresponding detection result according to the target signal, and sends the detection result to the first electronic device, so that the first electronic device determines whether the chip to be tested is normal according to each detection result.

[0120] Each detection result is used to indicate whether the chip to be tested passes the corresponding target test, and the detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

[0121] In this step, after the second electronic device receives the target signal, it can generate a corresponding detection result according to the target signal. Since each target signal corresponds to a target test, it can be determined whether the chip under test passes the corresponding target test according to the target signal.

[0122] In actual applications, after receiving the second electrical signal, the second electronic device can select a signal according to the test mode and set the internal detection method of the second electronic device to correspond to the target test, so that the second electronic device can generate a corresponding detection result according to the target signal.

[0123] In some embodiments, the target signal may be a multi-bit signal, or a high level signal, a low level signal, etc. When the target signal is a multi-bit signal, a corresponding detection result may be generated according to each bit. When the target signal is a high level signal or a low level signal, a corresponding detection result may be generated according to the maintenance time of the high level signal or the low level signal.

[0124] Optionally, the second electronic device can determine whether the chip under test has passed the target test based on the maintenance time of the first level in the target signal and the maintenance time of the second level, and the first level is greater than the second level. Specifically, if the first level in the target signal is maintained for a preset time, the generated detection result is used to indicate that the chip under test has passed the target test; if the second level in the target signal is maintained for a preset time, the generated detection result is used to indicate that the chip under test has not passed the target test. For example, the preset time can be determined according to actual conditions, for example, it can be 1ns, the first level can be, for example, a high level, and the second level can be, for example, a low level.

[0125] For example, the first level signal can be collected when the chip under test changes from the second level to the first level, the first level maintenance time can be calculated according to the number of first level signal collections and the sampling period, and then it can be determined whether the first level maintenance time reaches the preset time. If so, the generated detection result indicates that the chip under test has passed the target test. The second level signal can also be collected when the chip under test changes from the first level to the second level, the second level maintenance time can be calculated according to the number of second level signal collections and the sampling period, and then it can be determined whether the second level maintenance time reaches the preset time. If so, the generated detection result indicates that the chip under test has not passed the target test.

[0126] The second electronic device may also generate a detection result according to the frequency, level width, etc. of the target signal.

[0127] In the chip testing method provided in this embodiment, the second electronic device generates a corresponding test instruction when receiving the second electrical signal, so that the chip to be tested outputs a corresponding target signal, and then the second electronic device outputs a detection result according to the target signal and sends the detection result to the first electronic device, so that the first electronic device determines whether the chip to be tested is normal according to the detection result. Since the detection frequency of the second electronic device is greater than the detection frequency of the first electronic device, the detection cycle can be shortened, thereby improving the chip coverage and detection accuracy.

[0128] Figure 3 A signaling interaction diagram of a chip testing method provided in an embodiment of the present application, such as Figure 3 As shown, the chip testing method provided in this embodiment includes:

[0129] S301: A first electronic device sends a first electrical signal to a chip under test.

[0130] S302: The signal to be tested is in an on state after receiving the first electrical signal.

[0131] S303: The first electronic device sends a first second electronic signal to the second electronic device.

[0132] S304: After receiving the first second electrical signal, the second electronic device sends a corresponding first test instruction to the chip under test.

[0133] S305 . After receiving the first test instruction, the chip under test outputs a first target signal corresponding to the first target test.

[0134] In this step, after receiving the first test instruction, the chip under test performs a first target test and outputs a corresponding first target signal.

[0135] S306: The second electronic device obtains the first target signal, and generates a corresponding first detection result according to the first target signal.

[0136] The first detection result is used to indicate whether the chip to be tested passes the first target test.

[0137] S307: The second electronic device sends the first detection result to the first electronic device.

[0138] S308: The first electronic device sends a second second electronic signal to the second electronic device.

[0139] S309: After receiving the second second electrical signal, the second electronic device sends a corresponding second test instruction to the chip under test.

[0140] S310 , after receiving the second test instruction, the chip under test outputs a second target signal corresponding to the second target test.

[0141] In this step, after receiving the second test instruction, the chip under test performs a second target test and outputs a corresponding second target signal.

[0142] S311. The second electronic device obtains a second target signal, and generates a corresponding second detection result according to the second target signal.

[0143] The second detection result is used to indicate whether the chip to be tested passes the second target test.

[0144] S312: The second electronic device sends the second detection result to the first electronic device.

[0145] S313: The first electronic device determines whether the chip to be tested is normal according to the first detection result and the second detection result.

[0146] For example, if the first detection result indicates that the chip to be tested has passed the first target test, and the second detection result indicates that the chip to be tested has passed the second target test, the chip to be tested is judged to be normal; if the first detection result indicates that the chip to be tested has not passed the first target test, or the second detection result indicates that the chip to be tested has not passed the second target test, the chip to be tested is judged to be abnormal.

[0147] In this embodiment, the first electronic device may continue to send a third second electrical signal, a fourth second electrical signal, a fifth second electrical signal, etc. to the second electronic device to perform a third target test, a fourth target test, a fifth target test, etc. on the chip to be tested.

[0148] Figure 4 FIG. 1 shows a schematic diagram of a chip testing device provided by an embodiment of the present application. Figure 4 As shown, the chip testing device 10 of this embodiment is used to implement the operation corresponding to the first electronic device in any of the above method embodiments. The chip testing device 10 of this embodiment includes:

[0149] A first sending module 11 is used to send a first electrical signal to the chip under test to put the chip under test in an on state;

[0150] The second sending module 12 is used to intermittently send a second electrical signal to a second electronic device, and receive a detection result corresponding to each of the second electrical signals; the second electronic device is used to send a corresponding test instruction to the chip under test each time it receives the second electrical signal, and obtain a target signal of the chip under test under the target test; the second electronic device is also used to generate a corresponding detection result according to each target signal and send it to the first electronic device, and each detection result is used to indicate whether the chip under test passes the corresponding target test;

[0151] A judging module 13, configured to judge whether the chip to be tested is normal according to the detection result corresponding to each of the second electrical signals;

[0152] The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

[0153] The chip testing device 10 provided in the embodiment of the present application can execute the above method embodiment. Its specific implementation principle and technical effects can be found in the above method embodiment, and this embodiment will not be repeated here.

[0154] Figure 5 FIG. 1 shows a schematic diagram of a chip testing device provided by an embodiment of the present application. Figure 5 As shown, the chip testing device 20 of this embodiment is used to implement the operation corresponding to the second electronic device in any of the above method embodiments. The chip testing device 20 of this embodiment includes:

[0155] The receiving module 21 is used to intermittently receive a second electrical signal sent by the first electronic device;

[0156] The third sending module 22 is used for sending a corresponding test instruction to the chip under test each time a second electrical signal is received, and obtaining a target signal of the chip under test under a target test, wherein the chip under test is in an on state;

[0157] The fourth sending module 23 is used to obtain a target signal each time, generate a corresponding detection result according to the target signal, and send the detection result to the first electronic device, so that the first electronic device determines whether the chip under test is normal according to each detection result; each detection result is used to indicate whether the target chip passes the corresponding target test;

[0158] The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

[0159] Optionally, the third sending module 22 may include an instruction generator, which is used to generate corresponding test instructions according to the second electrical signal. For example, different second electrical signals correspond to different tests, and corresponding test mode selection signals can be generated according to different second electrical signals. The test mode selection signal instructs the chip to be tested to enter the corresponding target test.

[0160] Optionally, the fourth sending module 23 may include a signal detector, and the type and quantity of the signal detector may be multiple, for example, the target signal may be a multi-bit signal, or a high-level signal, a low-level signal, etc. Some signal detectors may generate corresponding detection results according to each bit when the target signal is a multi-bit signal. Other signal detectors may generate corresponding detection results according to the maintenance time of the high-level signal or the low-level signal when the target signal is a high-level signal or a low-level signal.

[0161] The chip testing device 20 provided in the embodiment of the present application can execute the above method embodiment. Its specific implementation principles and technical effects can be found in the above method embodiment, and this embodiment will not be repeated here.

[0162] Figure 6 FIG. 1 shows a hardware structure diagram of an electronic device provided in an embodiment of the present application. Figure 6As shown, the electronic device 30 is used to implement the operation corresponding to the first electronic device or the second electronic device in any of the above method embodiments. The electronic device 30 of this embodiment may include: a memory 31, a processor 32 and a communication interface 33.

[0163] The memory 31 is used to store computer instructions. The memory 31 may include a high-speed random access memory (RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a disk or an optical disk.

[0164] The processor 32 is used to execute the computer instructions stored in the memory to implement the method in the above embodiment. For details, please refer to the relevant description in the above method embodiment. The processor 32 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the invention can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0165] Optionally, the memory 31 may be independent or integrated with the processor 32 .

[0166] The communication interface 33 may be connected to the processor 32. The processor 32 may control the communication interface 33 to implement the functions of receiving and sending signals.

[0167] The electronic device provided in this embodiment can be used to execute the above method, and its implementation method and technical effect are similar, which will not be described in detail in this embodiment.

[0168] The present application also provides a chip testing system, including a first electronic device and a second electronic device, wherein the first electronic device is used to execute the method in the above embodiment with the first electronic device as the execution subject, and the second electronic device is used to execute the method in the above embodiment with the second electronic device as the execution subject.

[0169] Optionally, the first electronic device may be an integrated circuit automatic tester, and the second electronic device may be a field programmable logic gate array.

[0170] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed by a processor, they are used to implement the methods provided in the various embodiments described above.

[0171] The present application also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium. At least one processor of a device can read the computer instructions from the computer-readable storage medium, and at least one processor executes the computer instructions so that the device implements the methods provided in the various embodiments described above.

[0172] An embodiment of the present application also provides a chip, which includes a memory and a processor, wherein the memory is used to store computer instructions, and the processor is used to call and execute the computer instructions from the memory, so that a device equipped with the chip executes the methods described in the various possible implementation modes above.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip testing method, characterized in that: The method is used for a first electronic device, where the first electronic device is an automatic test equipment ATE, and the method includes: Sending a first electrical signal to the chip under test to turn on the chip under test; Intermittently sending a second electrical signal to a second electronic device, and receiving a detection result corresponding to each of the second electrical signals; the second electronic device is used to send a corresponding test instruction to the chip under test each time it receives the second electrical signal, and obtain a target signal of the chip under test under the target test; the second electronic device is also used to generate a corresponding detection result according to the maintenance time of the first level and the maintenance time of the second level in each target signal and send it to the first electronic device, each detection result is used to indicate whether the chip under test passes the corresponding target test, and the first level is greater than the second level; Determining whether the chip to be tested is normal according to the detection result corresponding to each of the second electrical signals; The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

2. The method according to claim 1, characterized in that The sending of a first electrical signal to the chip under test so that the chip under test is in an on state specifically includes: A preset voltage is sent to the chip under test to put the chip under test in an on state.

3. The method according to claim 1, characterized in that Intermittently sending a second electrical signal to a second electronic device specifically includes: intermittently sending a reset signal and a test mode selection signal to the second electronic device, each test mode selection signal corresponding to a target test; The reset signal is used to instruct the second electronic device to initialize, each of the test mode selection signals is used to instruct the second electronic device to send a corresponding test instruction to the chip under test, and each test instruction is used to instruct the chip under test to perform a corresponding target test.

4. The method according to claim 3, characterized in that The test mode selection signal includes N channels, where N is an integer greater than 1; Each of the test mode selection signals is determined by the level of each channel.

5. A chip testing method, characterized in that: The method is used for a second electronic device, and the method includes: intermittently receiving a second electrical signal sent by the first electronic device; Each time a second electrical signal is received, a corresponding test instruction is sent to the chip under test to obtain a target signal of the chip under test under a target test, wherein the chip under test is in an on state; Each time a target signal is obtained, a corresponding detection result is generated according to the maintenance time of the first level and the maintenance time of the second level in the target signal, and the detection result is sent to a first electronic device, so that the first electronic device determines whether the chip under test is normal according to each of the detection results; each detection result is used to indicate whether the target chip passes the corresponding target test, wherein the first electronic device is an automatic test equipment ATE, and the first level is greater than the second level; The detection frequency of the second electronic device is greater than the detection frequency of the first electronic device.

6. The method according to claim 5, characterized in that The second electrical signal includes a reset signal and a test mode selection signal; The step of sending a corresponding test instruction to the chip under test each time a second electrical signal is received specifically includes: Initialization is performed each time a reset signal and a test mode selection signal are received; Generate corresponding test instructions according to the test mode selection signal, and send the test instructions to the chip under test; each test instruction is used to instruct the chip under test to perform a corresponding target test.

7. The method according to claim 5, characterized in that Generating a corresponding detection result according to the target signal specifically includes: If the first level in the target signal is maintained for a preset time, the generated detection result is used to indicate that the chip under test has passed the target test; If the second level in the target signal is maintained for a preset time, the generated detection result is used to indicate that the chip under test has failed the target test.

8. The method according to claim 7, characterized in that The obtaining of the target signal of the chip under test under the target test specifically includes: When the chip under test changes from the second level to the first level, start collecting the first level signal; Calculating the maintenance time of the first level according to the number of samples collected of the first level signal and the sampling period; When the chip under test changes from the first level to the second level, start collecting the second level signal; The maintenance time of the second level is calculated according to the number of samples collected of the second level signal and a sampling period.

9. A chip testing system, characterized in that: The method comprises a first electronic device and a second electronic device, wherein the first electronic device is used to execute the method described in any one of claims 1 to 4, and the second electronic device is used to execute the method described in any one of claims 5 to 8.

10. The chip testing system according to claim 9, characterized in that: The first electronic device is an integrated circuit automatic tester, and the second electronic device is a field programmable logic gate array.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which are used to implement the method according to any one of claims 1 to 8 when executed by a processor.

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