Signal time-frequency conversion method, device and electronic equipment

Abstract

The present invention provides a method, device and electronic device for time-frequency conversion of a signal, which belongs to the field of digital information transmission technology. The number of multiplexed antennas is determined by inputting the number of antennas, the input sampling rate and the working clock of the FFT engine, so that the FFT engine is deployed according to the throughput of the time-frequency conversion, and the utilization efficiency of the FFT engine is improved. The effective FFT frequency domain output value is output according to the reverse bit sequence, so that the output cache of the FFT engine is avoided, and the real-time output of the effective FFT frequency domain output value is realized, which reduces the computing power resources and the output delay. The effective FFT frequency domain output value of the number of multiplexed antennas is stored according to the address unit, so that the splicing of the effective FFT frequency domain output value is realized. By reading multiple address units in parallel, the efficiency of reading frequency domain data is improved. The present invention improves the time-frequency conversion efficiency of the signal through ping-pong writing and reading, the number of multiplexed antennas and the reverse bit sequence output.

Description

Technical Field

[0001] The present invention relates to the technical field of digital information transmission, and in particular to a signal time-frequency conversion method, device and electronic equipment. Background Art

[0002] Modern communication systems have an increasing demand for large bandwidth, while spectrum resources are limited. In order to efficiently utilize spectrum resources, Orthogonal Frequency-Division Multiplexing (OFDM) is increasingly being used. In OFDM systems, front-end preprocessing usually requires time-frequency conversion, performing a Fast Fourier Transform (FFT) operation on the time domain signal, converting the time domain signal into a frequency domain signal, and performing a frequency domain spectrum shift on a subcarrier set with a certain resolution (subcarrier spacing) in the frequency domain, i.e., a Fast Fourier Transform shift (FFTshift) operation. In this process, the throughput required by the system needs to be met, while taking into account processing latency and balancing the resources consumed to achieve the desired results (e.g., computing power).

[0003] Most of the existing signal time-frequency conversion methods use a parallel FFT acceleration structure, with as many FFT acceleration engines deployed as there are receiving antennas. The existing signal time-frequency conversion methods do not maximize the performance of the acceleration engine when consuming more resources, and do not achieve the best balance between resources and performance. At the same time, the FFT natural order output mode has a large processing delay, especially when the fast Fourier transform length (FFTsize) is large, the delay is greater.

[0004] In summary, the efficiency of existing signal time-frequency conversion methods is low. Summary of the invention

[0005] The present invention provides a signal time-frequency conversion method, device and electronic equipment, which are used to solve the defect of low efficiency of signal time-frequency conversion in the prior art and improve the efficiency of signal time-frequency conversion.

[0006] The present invention provides a time-frequency conversion method for a signal, comprising: determining the number of multiplexed antennas of a single FFT engine multiplexing conversion antenna based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of a fast Fourier transform (FFT) engine; obtaining an FFT time-domain sampling sequence from a time-domain data stream of a signal of each input antenna according to an FFT length; performing ping-pong writing and reading on multiple FFT time-domain sampling sequences to obtain multiple time-domain input sequences of the FFT engine; obtaining a conversion result of the time-domain input sequence conversion by the FFT engine according to the number of multiplexed antennas to obtain an FFT frequency-domain output sequence, writing multiple valid FFT frequency-domain output values ​​in each FFT frequency-domain output sequence into an address unit according to a bit-reversed output, the number of valid FFT frequency-domain output values ​​stored in the address unit being equal to the number of multiplexed antennas; and reading multiple address units in parallel to obtain frequency-domain data of the signal.

[0007] According to the time-frequency conversion method of the signal provided by the present invention, the number of multiplexed antennas of a single FFT engine multiplexing conversion antenna is determined based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the fast Fourier transform FFT engine, including: determining the amount of time domain input data based on the product of the number of input antennas and the input sampling rate; determining the number of FFT engines based on the ratio of the time domain input data amount and the working clock of the FFT engine; determining the number of multiplexed antennas based on the ratio of the number of input antennas to the number of FFT engines.

[0008] According to the time-frequency conversion method of the signal provided by the present invention, an FFT time domain sampling sequence is obtained from the time domain data stream of the signal of each input antenna according to the FFT length, including: inserting a start symbol and an end symbol in the time domain data stream in sequence according to the FFT length; obtaining each FFT time domain sampling sequence based on the start symbol and the end symbol adjacent to the start symbol, the number of time domain data points in the FFT time domain sampling sequence is equal to the FFT length; and obtaining multiple FFT time domain sampling sequences in the time domain data stream in sequence according to multiple start symbols and multiple end symbols.

[0009] According to the time-frequency conversion method of the signal provided by the present invention, multiple valid FFT frequency domain output values ​​in each FFT frequency domain output sequence are written into the address unit according to the reverse bit output, including: obtaining the numbers of multiple historical valid FFT frequency domain output values ​​in the historical FFT frequency domain output sequence of each input antenna; sorting the numbers of multiple FFT frequency domain output values ​​in each FFT frequency domain output sequence in reverse bit order, obtaining the valid FFT frequency domain output value corresponding to the number of the sorted FFT frequency domain output value based on the number of the historical valid FFT frequency domain output value, and writing the valid FFT frequency domain output values ​​into the address unit in sequence.

[0010] According to the time-frequency conversion method of the signal provided by the present invention, the serial numbers of multiple historical valid FFT frequency domain output values ​​in the historical FFT frequency domain output sequence of each input antenna are obtained, including: based on the FFT length and the number of valid FFT frequency domain output values, the DC output value, the positive frequency data interval and the negative frequency data interval in the historical FFT frequency domain output sequence are obtained, and the positive frequency data interval or the negative frequency data interval includes multiple historical valid FFT frequency domain output values; based on the DC output value, the positive frequency data interval and the negative frequency data interval, the serial numbers of multiple historical valid FFT frequency domain output values ​​are obtained.

[0011] According to the time-frequency conversion method of the signal provided by the present invention, the valid FFT frequency domain output values ​​are written into the address units in sequence, including: based on the number of multiplexed antennas, the valid FFT frequency domain output values ​​of the same output of the FFT frequency domain output sequence of at least one input antenna are written into the same address unit.

[0012] According to the time-frequency conversion method of the signal provided by the present invention, a plurality of FFT time domain sampling sequences are ping-pong written and read to obtain a plurality of time domain input sequences of the FFT engine, including: when the current FFT time domain sampling sequence is written based on the ping-pong cache unit, the previous FFT time domain sampling sequence adjacent to the current FFT time domain sampling sequence is read based on the pong cache unit matched by the ping-pong cache unit; or, when the current FFT time domain sampling sequence is written based on the pong cache unit, the previous FFT time domain sampling sequence is read based on the ping-pong cache unit matched by the pong cache unit; the current FFT time domain sampling sequence is used as the previous FFT time domain sampling sequence to continuously ping-pong write and read the plurality of FFT time domain sampling sequences until the FFT time domain sampling sequence is completely read, thereby obtaining a plurality of time domain input sequences.

[0013] The present invention also provides a signal time-frequency conversion device, comprising: a multiplexed antenna number determination module, used to determine the number of multiplexed antennas of a single FFT engine multiplexed conversion antenna based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the fast Fourier transform FFT engine; an FFT time domain sampling sequence acquisition module, used to obtain the FFT time domain sampling sequence from the time domain data stream of the signal of each input antenna according to the FFT length; a time domain input sequence acquisition module, used to perform ping-pong writing and reading on multiple FFT time domain sampling sequences to obtain multiple time domain input sequences of the FFT engine; a writing module, used to obtain the conversion result of the FFT engine on the time domain input sequence according to the number of multiplexed antennas, obtain the FFT frequency domain output sequence, and write multiple valid FFT frequency domain output values ​​in each FFT frequency domain output sequence into the address unit according to the bit reverse output, and the number of valid FFT frequency domain output values ​​stored in the address unit is equal to the number of multiplexed antennas; a reading module, used to read multiple address units in parallel to obtain the frequency domain data of the signal.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned time-frequency conversion methods for the signal when executing the computer program.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the time-frequency conversion method of any of the above-mentioned signals is implemented.

[0016] The time-frequency conversion method, device and electronic device of the signal provided by the present invention determine the number of multiplexed antennas by inputting the number of antennas, the input sampling rate and the working clock of the FFT engine, thereby realizing the deployment of the FFT engine according to the throughput of the time-frequency conversion. The processing volume of a single FFT engine is matched according to the number of multiplexed antennas, thereby improving the utilization efficiency of the FFT engine. The effective FFT frequency domain output value is output according to the reverse bit sequence, thereby avoiding the output cache of the FFT engine, realizing the real-time output of the effective FFT frequency domain output value, reducing the computing power resources and reducing the output delay at the same time. The effective FFT frequency domain output value of the number of multiplexed antennas is stored according to the address unit, thereby realizing the splicing of the effective FFT frequency domain output value. By reading multiple address units in parallel, the efficiency of reading frequency domain data is improved. The present invention improves the time-frequency conversion efficiency of the signal through ping-pong writing and reading, the number of multiplexed antennas and the reverse bit sequence output. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 This is one of the flow charts of the signal time-frequency conversion method provided by the present invention.

[0019] Figure 2 This is the second flow chart of the signal time-frequency conversion method provided by the present invention.

[0020] Figure 3 It is a schematic diagram of the process of ping-pong writing and reading the FFT time domain sampling sequence provided by the present invention.

[0021] Figure 4 It is a schematic diagram of the process of bit reverse output provided by the present invention.

[0022] Figure 5It is a schematic diagram of a flow chart of writing a valid FFT frequency domain output value into an address unit provided by the present invention.

[0023] Figure 6 It is a structural schematic diagram of the time-frequency conversion device of the signal provided by the present invention.

[0024] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] In the parallel FFT acceleration structure, as many FFT acceleration engines as there are receiving antennas (input antennas). For example, the FFT acceleration engine works in pipeline mode. When the input sampling rate of a single FFT acceleration engine is lower than the FFT acceleration engine working clock, for example, the input sampling rate is 122.88MHz and the FFT acceleration engine working clock is 245.76MHz, then the FFT acceleration engine will be idle for half of the time. This greatly wastes the performance of the FFT acceleration engine itself.

[0027] Natural order output, that is, adding an output buffer inside the FFT acceleration engine, outputting the FFT frequency domain output values ​​in natural order, and the FFT frequency domain output values ​​are numbered 0, 1, 2, 3, ..., FFT length (FFTsize) - 1. This increases both the processing delay and the overall system resource consumption.

[0028] Combine the following Figure 1-Figure 7 The invention describes a method, device and electronic device for time-frequency conversion of a signal.

[0029] Figure 1 It is one of the flow charts of the time-frequency conversion method of the signal provided by the present invention, such as Figure 1 As shown, the signal time-frequency conversion method includes steps S100 to S500, and each step is specifically as follows.

[0030] S100: Determine the number of multiplexed antennas for multiplexing antennas of a single FFT engine based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the Fast Fourier Transform (FFT) engine.

[0031] The number of multiplexed antennas of a single FFT engine multiplexing conversion antenna is determined based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the fast Fourier transform (FFT) engine. Specifically, the amount of time domain input data is determined based on the product of the number of input antennas and the input sampling rate; the number of FFT engines is determined based on the ratio of the amount of time domain input data and the working clock of the FFT engine; and the number of multiplexed antennas is determined based on the ratio of the number of input antennas to the number of FFT engines.

[0032] like Figure 2 As shown in the figure, the number of FFT engines that need to be deployed is evaluated based on the throughput requirements of the signal time-frequency conversion system. A first-level cache is added to the input end of the FFT engine. If the input sampling rate of the input antenna is lower than or less than 2 times the working clock of the FFT engine, multiple input antennas can reuse one FFT engine to maximize the processing capacity of the FFT engine.

[0033] like Figure 2 As shown, the executor of the present application is a time-frequency conversion system for signals, including a time domain synchronization unit, an input antenna, an FFT time domain sampling sequence ping-pong cache unit, a time-frequency conversion input control unit, an FFT engine, an FFTshift control unit, a frequency domain output control unit and an effective FFT frequency domain output sequence ping-pong cache unit.

[0034] The number of FFT engines to be deployed and the number of multiplexed antennas of a single FFT engine multiplexing conversion antenna are determined according to the number of input antennas, the input sampling rate of the input antennas, and the working clock of the FFT engine.

[0035] Number of FFT engines = (Number of input antennas Input sampling rate) / FFT engine working clock. If the calculated number of FFT engines is less than 1, at least one FFT engine is selected.

[0036] The number of multiplexed antennas of a single FFT engine multiplexing conversion antenna = the number of input antennas / the number of FFT engines.

[0037] The present application determines the number of FFT engines and the number of multiplexed antennas based on the number of input antennas, the input sampling rate and the FFT engine working clock, thereby realizing the reasonable deployment of FFT engines according to the amount of time domain input data, which is conducive to exerting the maximum processing capacity of the FFT engine and improving the utilization efficiency of the FFT engine.

[0038] S200: Acquire an FFT time-domain sampling sequence from a time-domain data stream of a signal from each input antenna according to an FFT length.

[0039] FFT size (FFTsize) is the number of data points in the time domain input sequence that are input to the FFT engine at one time. For example, if FFTsize=4096, it means that the number of data points in the time domain input sequence that are input to the FFT engine at one time is 4096.

[0040] According to the FFT length, time domain data points of a fixed length are obtained from the time domain data stream of each input antenna to obtain an FFT time domain sampling sequence.

[0041] An FFT time domain sampling sequence is obtained from the time domain data stream of the signal of each input antenna according to the FFT length. Specifically, a start symbol and an end symbol are sequentially inserted into the time domain data stream according to the FFT length; each FFT time domain sampling sequence is obtained based on the start symbol and the end symbol adjacent to the start symbol, and the number of time domain data points in the FFT time domain sampling sequence is equal to the FFT length; and multiple FFT time domain sampling sequences are sequentially obtained in the time domain data stream according to multiple start symbols and multiple end symbols.

[0042] The time-frequency synchronization unit inserts the start symbol at the start position and the end symbol at the end position in the time domain data stream of each input antenna according to the FFT length. The length of the interval between two adjacent start symbols and end symbols is the FFT length. The time domain data points of adjacent start symbols and end symbols constitute an FFT time domain sampling sequence (symbol). Multiple pairs of time domain data points between adjacent start symbols and end symbols are obtained in sequence to obtain multiple FFT time domain sampling sequences, for example, symbol0, symbol1, symbol2, ..., symboln.

[0043] The present invention determines the insertion positions of the start symbol and the end symbol according to the FFT length, thereby improving the efficiency of evenly segmenting the time domain data stream, and obtaining the FFT time domain sampling sequence according to the start symbol and the end symbol, thereby improving the efficiency of obtaining the FFT time domain sampling sequence.

[0044] S300: Ping-pong writing and reading are performed on multiple FFT time-domain sampling sequences to obtain multiple time-domain input sequences of the FFT engine.

[0045] Ping-pong writing and reading are performed on multiple FFT time domain sampling sequences to obtain multiple time domain input sequences of the FFT engine. Specifically, when the current FFT time domain sampling sequence is written based on the ping-pong cache unit, the pong cache unit matched based on the ping-pong cache unit reads the previous FFT time domain sampling sequence adjacent to the current FFT time domain sampling sequence; or, when the current FFT time domain sampling sequence is written based on the pong cache unit, the ping-pong cache unit matched based on the pong cache unit reads the previous FFT time domain sampling sequence; the current FFT time domain sampling sequence is used as the previous FFT time domain sampling sequence to continuously perform ping-pong writing and reading on multiple FFT time domain sampling sequences until the FFT time domain sampling sequence is completely read, thereby obtaining multiple time domain input sequences.

[0046] The FFT time domain sampling sequence ping-pong buffer unit includes multiple pairs of ping-pong buffer units. A pair of ping-pong buffer units includes a ping buffer unit and a pong buffer unit. When the ping buffer unit is written, the pong buffer unit matched by the ping buffer unit is read. When the pong buffer unit is written, the ping buffer unit matched by the pong buffer unit is read.

[0047] like Figure 3 As shown, for example, when the ping cache unit writes the current FFT time domain sampling sequence (symboln), the pong cache unit matched by the ping cache unit reads the previous FFT time domain sampling sequence (symboln-1) to obtain the time domain input sequence. Further, when the pong cache unit writes symboln+1, the ping cache unit matched by the pong cache unit reads symboln to obtain the time domain input sequence.

[0048] The present application ensures that writing and reading can be performed simultaneously without conflict through ping-pong writing and reading, thereby improving the efficiency of writing and reading multiple FFT time-domain sampling sequences, and further improving the efficiency of obtaining time-domain input sequences.

[0049] S400: Obtain the conversion result of the FFT engine on the time domain input sequence according to the number of multiplexed antennas, obtain the FFT frequency domain output sequence, and write multiple valid FFT frequency domain output values ​​in each FFT frequency domain output sequence into the address unit according to the bit reverse output.

[0050] The number of valid FFT frequency domain output values ​​stored in the address unit is equal to the number of multiplexed antennas.

[0051] like Figure 3As shown, according to the time-frequency conversion input control unit in the time-frequency conversion system of the signal, multiple time-frequency input sequences are allocated, and according to the number of multiplexed antennas, the time domain input sequence of at least one input antenna is allocated to one FFT engine. For example, if the number of multiplexed antennas is 2, the time domain input sequences of input antenna 1 and input antenna 2 are allocated to FFT engine 1 for time-frequency conversion. The time domain input sequence of input antenna 3 and the time domain input sequence of input antenna 4 are allocated to FFT engine 2 for time-frequency conversion.

[0052] The FFT engine performs time-frequency conversion on the time domain input sequence assigned to it to obtain an FFT frequency domain output sequence. The FFTshift control unit obtains the numbers of the valid FFT frequency domain output values ​​in the FFT frequency domain output sequence. The numbers of the multiple FFT frequency domain output values ​​in each FFT frequency domain output sequence are sorted in bit reverse order. Bit reversal is to arrange the numbers of the FFT frequency domain output values ​​in reverse order according to the bits of their binary representation (for example, the numbers of the FFT frequency domain output values ​​in the bit reverse output are sorted as 0, 512, 256,..., FFTsize-1). According to the numbers of the valid FFT frequency domain output values, the multiple valid FFT frequency domain output values ​​that are sorted in bit reverse order are written to the corresponding address units. The number of valid FFT frequency domain output values ​​stored in each address unit is equal to the number of multiplexed antennas, and each valid FFT frequency domain output value corresponds to a write address. For example, if the number of multiplexed antennas is P, then each address unit stores P valid FFT frequency domain output values. Figure 5 As shown, Rx1_Fftshift_out0 is the first valid FFT frequency domain output value of input antenna 1, corresponding to write address 0. Rx2_Fftshift_out0 is the first valid FFT frequency domain output value of input antenna 2, corresponding to write address 1. Similarly, RxP_Fftshift_out0 is the first valid FFT frequency domain output value of input antenna P, corresponding to write address P-1. P write addresses are concatenated to obtain an address unit, for example, write address 0, write address 1, ..., write address P-1 are concatenated to obtain address unit 0. Rx1_Fftshift_out1 is the second valid FFT frequency domain output value of input antenna 1, corresponding to write address P. Rx2_Fftshift_out1 is the second valid FFT frequency domain output value of input antenna 2, corresponding to write address P+1. Similarly, RxP_Fftshift_out1 is the second valid FFT frequency domain output value of input antenna P, corresponding to write address 2P-1. Concatenate write address P, write address P+1, ..., 2P-1 to obtain address unit 1.

[0053] S500: Read multiple address units in parallel to obtain frequency domain data of the signal.

[0054] The write addresses in multiple address units are read in parallel, and the corresponding write addresses in each address unit are read to obtain a valid FFT frequency domain output sequence. Ping-pong writing and reading are performed on the valid FFT frequency domain output sequence to obtain the frequency domain data of the signal. Ping-pong writing and reading can ensure that the writing and reading of the valid FFT frequency domain output sequence are performed at the same time without conflict, thereby improving the efficiency of writing and reading multiple valid FFT frequency domain output sequences, thereby improving the efficiency of obtaining frequency domain data.

[0055] The time-frequency conversion method of the signal provided by the embodiment of the present invention determines the number of multiplexed antennas by inputting the number of antennas, the input sampling rate, and the working clock of the FFT engine, thereby realizing the deployment of the FFT engine according to the throughput of the time-frequency conversion. The processing volume of a single FFT engine is matched according to the number of multiplexed antennas, thereby improving the utilization efficiency of the FFT engine. The effective FFT frequency domain output value is output according to the reverse bit sequence, thereby avoiding the output cache of the FFT engine, realizing the real-time output of the effective FFT frequency domain output value, reducing the computing power resources and reducing the output delay at the same time. The effective FFT frequency domain output value of the number of multiplexed antennas is stored according to the address unit, thereby realizing the splicing of the effective FFT frequency domain output value. By reading multiple address units in parallel, the efficiency of reading frequency domain data is improved. The present invention improves the time-frequency conversion efficiency of the signal through ping-pong writing and reading, the number of multiplexed antennas, and the reverse bit sequence output.

[0056] Based on the above embodiment, multiple valid FFT frequency domain output values ​​in each FFT frequency domain output sequence are written into the address unit according to the bit reverse order output, including step S410 to step S420, and each step is specifically as follows.

[0057] S410: Obtain serial numbers of multiple historical valid FFT frequency domain output values ​​in a historical FFT frequency domain output sequence of each input antenna.

[0058] S420: Sort the numbers of multiple FFT frequency domain output values ​​in each FFT frequency domain output sequence in reverse order, obtain the valid FFT frequency domain output values ​​corresponding to the numbers of the sorted FFT frequency domain output values ​​based on the numbers of the historical valid FFT frequency domain output values, and write the valid FFT frequency domain output values ​​into the address units in sequence.

[0059] Obtain serial numbers of multiple historical valid FFT frequency domain output values ​​in the historical FFT frequency domain output sequence of each input antenna. Specifically, obtain the DC output value, positive frequency data interval, and negative frequency data interval in the historical FFT frequency domain output sequence based on the FFT length and the number of valid FFT frequency domain output values, the positive frequency data interval or the negative frequency data interval including multiple historical valid FFT frequency domain output values; obtain serial numbers of multiple historical valid FFT frequency domain output values ​​based on the DC output value, positive frequency data interval, and negative frequency data interval.

[0060] The historical FFT frequency domain output values ​​in the historical FFT frequency domain output sequence are output in natural order, the data in the guard band is discarded from the historical FFT frequency domain output sequence, the data within the band is retained, and the direct current output value (DC) within the band, the positive frequency data in the positive frequency data interval, and the negative frequency data in the negative frequency data interval are arranged and output.

[0061] Under the natural order output condition, DC is the data numbered 0 (the first output) in the historical FFT frequency domain output sequence, and DC is also the first output in the bit reverse output.

[0062] like Figure 4 As shown in the figure, assuming FFTsize=1024, the number of valid FFT frequency domain output values ​​is 600, and the DC number is always the first (Fftout0). The positive frequency data is the tail 600 / 2-1=299 data in the historical FFT frequency domain output sequence, which is the historical FFT frequency domain output value with natural sequence number from 725 to 1023. The negative frequency data is 300 data, which is the historical FFT frequency domain output value with natural sequence number from 1 to 300. The historical FFT frequency domain output values ​​with numbers 301 to 724 in the middle are guard band data and are discarded.

[0063] Under the natural order output condition, the output rules of the historical FFT frequency domain output sequence are as follows. Input parameters: FFTsize and FFT_shift_out_len (number of valid FFT frequency domain output values). FFT_shift_out (historical valid FFT frequency domain output value) = [DC0, {FFTsize-FFT_shift_out_len / 2+1: FFTsize-1}, {1: FFT_shift_out_len / 2}]. Among them, DC0 is the DC in the first place, {FFTsize-FFT_shift_out_len / 2+1: FFTsize-1} is the positive frequency data interval, and {1: FFT_shift_out_len / 2} is the negative frequency data interval.

[0064] Regardless of whether it is natural order output or bit reverse order output, the number of the output valid FFT frequency domain output value is the same. Therefore, the number of the historical valid FFT frequency domain output value is obtained according to the DC output value, positive frequency data interval and negative frequency data interval of the historical FFT frequency domain output sequence of each input antenna in the natural order output. The valid FFT frequency domain output value of the FFT frequency domain output sequence in the bit reverse order output is directly obtained according to the number of the historical valid FFT frequency domain output value.

[0065] The present invention obtains the serial numbers of historical valid FFT frequency domain output values ​​through natural order output, thereby accurately obtaining the serial numbers of historical valid FFT frequency domain output values, directly obtaining the valid FFT frequency domain output values ​​in the bit reverse output according to the serial numbers of the historical valid FFT frequency domain output values, and then writing and reading the valid FFT frequency domain output values, avoiding the output cache of the FFT engine, realizing real-time output of the valid FFT frequency domain output values, reducing computing resources and reducing output delay at the same time.

[0066] The valid FFT frequency domain output values ​​are written into the address units in sequence. Specifically, based on the number of multiplexed antennas, the valid FFT frequency domain output values ​​of the same output of the FFT frequency domain output sequence of at least one input antenna are written into the same address unit.

[0067] The number of valid FFT frequency domain output values ​​in an address unit is determined according to the number of multiplexed antennas. Figure 5 As shown, if the number of multiplexed antennas is P, then the P valid FFT frequency domain output values ​​output at the same time (for example, the first time) in the P FFT frequency domain output sequences corresponding to the P input antennas are written to address unit 0. The P valid FFT frequency domain output values ​​output for the second time in the P FFT frequency domain output sequences corresponding to the P input antennas are written to address unit 1. By analogy, if the number of valid FFT frequency domain output values ​​is 600, the P valid FFT frequency domain output values ​​output for the 600th time in the P FFT frequency domain output sequences corresponding to the P input antennas are written to address unit 599. Each address unit includes P write addresses.

[0068] The present application splices the write addresses of valid FFT frequency domain output values ​​through address units, which is beneficial to improving the efficiency of reading and writing valid FFT frequency domain output values.

[0069] The time-frequency conversion device for a signal provided by the present invention is described below. The time-frequency conversion device for a signal described below and the time-frequency conversion method for a signal described above can be referred to each other.

[0070] like Figure 6 As shown, a time-frequency conversion device for a signal includes: a multiplexed antenna quantity determination module 601, which is used to determine the number of multiplexed antennas of a single FFT engine multiplexed conversion antenna based on the number of input antennas, the input sampling rate of the input antenna, and the working clock of the fast Fourier transform FFT engine.

[0071] The FFT time domain sampling sequence acquisition module 602 is used to acquire the FFT time domain sampling sequence from the time domain data stream of the signal of each input antenna according to the FFT length.

[0072] The time domain input sequence acquisition module 603 is used to perform ping-pong writing and reading on multiple FFT time domain sampling sequences to obtain multiple time domain input sequences of the FFT engine.

[0073] The writing module 604 is used to obtain the conversion result of the FFT engine on the time domain input sequence according to the number of multiplexed antennas, obtain the FFT frequency domain output sequence, and write multiple valid FFT frequency domain output values ​​in each FFT frequency domain output sequence into the address unit according to the bit reverse output. The number of valid FFT frequency domain output values ​​stored in the address unit is equal to the number of multiplexed antennas.

[0074] The reading module 605 is used to read multiple address units in parallel to obtain frequency domain data of the signal.

[0075] The time-frequency conversion device of the signal provided by the embodiment of the present invention determines the number of multiplexed antennas by inputting the number of antennas, the input sampling rate, and the working clock of the FFT engine, thereby realizing the deployment of the FFT engine according to the throughput of the time-frequency conversion. The processing volume of a single FFT engine is matched according to the number of multiplexed antennas, thereby improving the utilization efficiency of the FFT engine. The effective FFT frequency domain output value is output according to the reverse bit sequence, thereby avoiding the output cache of the FFT engine, realizing the real-time output of the effective FFT frequency domain output value, reducing the computing power resources and reducing the output delay at the same time. The effective FFT frequency domain output value of the number of multiplexed antennas is stored according to the address unit, thereby realizing the splicing of the effective FFT frequency domain output value. By reading multiple address units in parallel, the efficiency of reading frequency domain data is improved. The present invention improves the time-frequency conversion efficiency of the signal through ping-pong writing and reading, the number of multiplexed antennas, and the reverse bit sequence output.

[0076] In one embodiment, the module 601 for determining the number of multiplexed antennas is used to: determine the amount of time domain input data based on the product of the number of input antennas and the input sampling rate; determine the number of FFT engines based on the ratio of the amount of time domain input data and the working clock of the FFT engine; determine the number of multiplexed antennas based on the ratio of the number of input antennas to the number of FFT engines.

[0077] In one embodiment, the FFT time domain sampling sequence acquisition module 602 is used to: insert a start symbol and an end symbol in the time domain data stream in sequence according to the FFT length; acquire each FFT time domain sampling sequence based on the start symbol and the end symbol adjacent to the start symbol, and the number of time domain data points in the FFT time domain sampling sequence is equal to the FFT length; and acquire multiple FFT time domain sampling sequences in the time domain data stream in sequence according to multiple start symbols and multiple end symbols.

[0078] In one embodiment, the writing module 604 is used to: obtain the numbers of multiple historical valid FFT frequency domain output values ​​in the historical FFT frequency domain output sequence of each input antenna; sort the numbers of multiple FFT frequency domain output values ​​in each FFT frequency domain output sequence in reverse order, obtain the valid FFT frequency domain output value corresponding to the number of the sorted FFT frequency domain output value based on the number of the historical valid FFT frequency domain output value, and write the valid FFT frequency domain output value into the address unit in sequence.

[0079] In one embodiment, the writing module 604 is used to: obtain the DC output value, positive frequency data interval and negative frequency data interval in the historical FFT frequency domain output sequence based on the FFT length and the number of valid FFT frequency domain output values, the positive frequency data interval or the negative frequency data interval includes multiple historical valid FFT frequency domain output values; obtain the serial numbers of multiple historical valid FFT frequency domain output values ​​based on the DC output value, positive frequency data interval and negative frequency data interval.

[0080] In one embodiment, based on the number of multiplexed antennas, valid FFT frequency domain output values ​​of the same output of the FFT frequency domain output sequence of at least one input antenna are written into the same address unit.

[0081] In one embodiment, the time domain input sequence acquisition module 603 is used for: when writing the current FFT time domain sampling sequence based on the ping-pong cache unit, reading the previous FFT time domain sampling sequence adjacent to the current FFT time domain sampling sequence based on the pong cache unit matched by the ping-pong cache unit; or, when writing the current FFT time domain sampling sequence based on the pong cache unit, reading the previous FFT time domain sampling sequence based on the ping-pong cache unit; using the current FFT time domain sampling sequence as the previous FFT time domain sampling sequence to continuously perform ping-pong writing and reading on multiple FFT time domain sampling sequences until the FFT time domain sampling sequence is read, thereby obtaining multiple time domain input sequences.

[0082] Figure 7 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 7As shown, the electronic device may include: a processor (processor) 710 , a communication interface (Communications Interface) 720 , a memory (memory) 730 and a communication bus 740 , wherein the processor 710 , the communication interface 720 , and the memory 730 communicate with each other through the communication bus 740 . The processor 710 can call the logic instructions in the memory 730 to execute the time-frequency conversion method of the signal, which includes: determining the number of multiplexed antennas of a single FFT engine multiplexing conversion antenna based on the number of input antennas, the input sampling rate of the input antenna, and the working clock of the fast Fourier transform FFT engine; obtaining an FFT time domain sampling sequence from the time domain data stream of the signal of each input antenna according to the FFT length; performing ping-pong writing and reading on multiple FFT time domain sampling sequences to obtain multiple time domain input sequences of the FFT engine; obtaining the conversion result of the FFT engine converting the time domain input sequence according to the number of multiplexed antennas to obtain an FFT frequency domain output sequence, and writing multiple valid FFT frequency domain output values ​​in each FFT frequency domain output sequence into the address unit according to the bit reverse output, and the number of valid FFT frequency domain output values ​​stored in the address unit is equal to the number of multiplexed antennas; and reading multiple address units in parallel to obtain the frequency domain data of the signal.

[0083] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0084] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the time-frequency conversion method of the signal provided by the above-mentioned methods, the method comprising: determining the number of multiplexed antennas of a single FFT engine for multiplexing conversion antennas based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the fast Fourier transform FFT engine; obtaining an FFT time domain sampling sequence from the time domain data stream of the signal of each input antenna according to the FFT length; performing ping-pong writing and reading on multiple FFT time domain sampling sequences to obtain multiple time domain input sequences of the FFT engine; obtaining the conversion result of the FFT engine on the time domain input sequence according to the number of multiplexed antennas to obtain an FFT frequency domain output sequence, and writing multiple valid FFT frequency domain output values ​​in each FFT frequency domain output sequence into an address unit according to bit reverse output, the number of valid FFT frequency domain output values ​​stored in the address unit being equal to the number of multiplexed antennas; and reading multiple address units in parallel to obtain frequency domain data of the signal.

[0085] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0086] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for time-frequency conversion of a signal, characterized in that: include: Determine the number of multiplexed antennas of a single FFT engine multiplexed conversion antenna based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the fast Fourier transform FFT engine; Obtaining an FFT time domain sampling sequence from the time domain data stream of the signal of each input antenna according to the FFT length; Performing ping-pong writing and reading on the multiple FFT time domain sampling sequences to obtain multiple time domain input sequences of the FFT engine; Obtaining a conversion result of the FFT engine on the time domain input sequence according to the number of multiplexed antennas to obtain an FFT frequency domain output sequence, and writing a plurality of valid FFT frequency domain output values ​​in each of the FFT frequency domain output sequences into an address unit according to bit reverse output, wherein the number of valid FFT frequency domain output values ​​stored in the address unit is equal to the number of multiplexed antennas; Reading a plurality of the address units in parallel to obtain frequency domain data of the signal; The method of determining the number of multiplexed antennas of a single FFT engine multiplexing conversion antenna based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the fast Fourier transform FFT engine includes: Determine the amount of time-domain input data based on the product of the number of input antennas and the input sampling rate; Determining the number of FFT engines based on the ratio of the amount of time domain input data to the working clock of the FFT engine; The number of multiplexed antennas is determined based on a ratio of the number of input antennas to the number of FFT engines.

2. The signal time-frequency conversion method according to claim 1, characterized in that: The step of acquiring an FFT time domain sampling sequence from a time domain data stream of a signal of each input antenna according to the FFT length includes: Inserting a start symbol and an end symbol in sequence into the time domain data stream according to the FFT length; Acquire each of the FFT time domain sampling sequences based on the start symbol and the end symbol adjacent to the start symbol, wherein the number of time domain data points in the FFT time domain sampling sequence is equal to the FFT length; In the time domain data stream, a plurality of the FFT time domain sampling sequences are acquired in sequence according to a plurality of the start symbols and a plurality of the end symbols.

3. The signal time-frequency conversion method according to claim 1, characterized in that: The step of writing a plurality of valid FFT frequency domain output values ​​in each of the FFT frequency domain output sequences into an address unit according to the bit reverse order output comprises: Obtain serial numbers of multiple historical valid FFT frequency domain output values ​​in the historical FFT frequency domain output sequence of each input antenna; The numbers of multiple FFT frequency domain output values ​​in each of the FFT frequency domain output sequences are sorted in reverse order, and based on the numbers of the historical valid FFT frequency domain output values, valid FFT frequency domain output values ​​corresponding to the numbers of the sorted FFT frequency domain output values ​​are obtained, and the valid FFT frequency domain output values ​​are written into the address units in sequence.

4. The signal time-frequency conversion method according to claim 3, characterized in that: The obtaining the serial numbers of multiple historical valid FFT frequency domain output values ​​in the historical FFT frequency domain output sequence of each input antenna includes: Based on the FFT length and the number of valid FFT frequency domain output values, a DC output value, a positive frequency data interval, and a negative frequency data interval in the historical FFT frequency domain output sequence are obtained, wherein the positive frequency data interval or the negative frequency data interval includes a plurality of historical valid FFT frequency domain output values; The serial numbers of the plurality of historical valid FFT frequency domain output values ​​are obtained based on the DC output value, the positive frequency data interval and the negative frequency data interval.

5. The signal time-frequency conversion method according to claim 3, characterized in that: The step of writing the valid FFT frequency domain output values ​​into the address units in sequence comprises: Based on the number of multiplexed antennas, the valid FFT frequency domain output values ​​of the same output of the FFT frequency domain output sequence of at least one of the input antennas are written into the same address unit.

6. The signal time-frequency conversion method according to claim 1, characterized in that: The step of performing ping-pong writing and reading on the multiple FFT time domain sampling sequences to obtain multiple time domain input sequences for the FFT engine includes: When the current FFT time domain sampling sequence is written based on the ping cache unit, the pong cache unit matched based on the ping cache unit reads the previous FFT time domain sampling sequence adjacent to the current FFT time domain sampling sequence; or, when the current FFT time domain sampling sequence is written based on the pong cache unit, the ping cache unit matched based on the pong cache unit reads the previous FFT time domain sampling sequence; The current FFT time domain sampling sequence is used as the previous FFT time domain sampling sequence to continuously ping-pong write and read multiple FFT time domain sampling sequences until the FFT time domain sampling sequence is completely read, thereby obtaining multiple time domain input sequences.

7. A signal time-frequency conversion device, characterized in that: include: A multiplexed antenna quantity determination module is used to determine the number of multiplexed antennas of a single FFT engine multiplexed conversion antenna based on the number of input antennas, the input sampling rate of the input antennas, and the working clock of the fast Fourier transform FFT engine; An FFT time domain sampling sequence acquisition module, used to acquire an FFT time domain sampling sequence from a time domain data stream of a signal of each input antenna according to an FFT length; A time domain input sequence acquisition module, used for performing ping-pong writing and reading on a plurality of the FFT time domain sampling sequences to obtain a plurality of time domain input sequences of the FFT engine; A writing module is used to obtain the conversion result of the FFT engine on the time domain input sequence according to the number of multiplexed antennas, obtain an FFT frequency domain output sequence, and write multiple valid FFT frequency domain output values ​​in each of the FFT frequency domain output sequences into an address unit according to bit reverse output, wherein the number of valid FFT frequency domain output values ​​stored in the address unit is equal to the number of multiplexed antennas; A reading module, used for reading a plurality of the address units in parallel to obtain frequency domain data of the signal; The module for determining the number of multiplexed antennas is also used to determine the amount of time domain input data based on the product of the number of input antennas and the input sampling rate; determine the number of FFT engines based on the ratio of the amount of time domain input data and the working clock of the FFT engine; and determine the number of multiplexed antennas based on the ratio of the number of input antennas to the number of FFT engines.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the time-frequency conversion method of the signal according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for time-frequency conversion of a signal as claimed in any one of claims 1 to 6 is implemented.

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