A fine simulation method for power devices using heat transfer field coupling

Abstract

The application provides a power device fine simulation method using heat transfer field coupling, and belongs to the technical field of power semiconductor device finite element simulation. th ) curve calibration, chip power consumption function fitting, total power consumption function fitting and bonding wire power consumption function acquisition, and given heat sources are used to replace electrothermal simulation, the semiconductor device chip and the bonding wire power consumption in the simulation model are used to replace the electrothermal field coupling simulation effect in the simulation, so that the simulation precision equivalent to the electrothermal field can be ensured, the simulation time can be effectively reduced, and the effect of replacing the electrothermal simulation with the heat transfer simulation in the power semiconductor device simulation is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor simulation technology, and particularly to a refined simulation method for power devices utilizing heat transfer field coupling. Background Technology

[0002] Power semiconductor devices are widely used in power electronics, communications, aerospace, and automotive fields, and their performance and reliability directly affect the efficiency and stability of the entire system. Therefore, to ensure the stability of semiconductor devices in various fields, reliability tests are necessary before use to guarantee their reliable operation. Simulations of power semiconductor devices using various simulation software are required both before and after these tests, which is one of the important technical methods in current research and engineering applications.

[0003] The finite element simulation software COMSOL can simulate the electrical, thermal, and mechanical properties of devices under different operating conditions. It can identify potential failure mechanisms in advance, improve design reliability, optimize thermal management schemes, and quantitatively assess thermal fatigue life. It helps engineers optimize designs, improve product performance, and save costs and time, and is a key means to ensure stable operation and long life of devices.

[0004] In the development of power semiconductor devices, thermal management and thermal stress analysis are crucial. If the heat generated during operation is not dissipated in a timely manner, it will affect performance and lifespan. Traditional thermal management methods are time-consuming and costly, and lack sufficient feedback in the early design stages. COMSOL Multiphysics provides comprehensive analysis by accurately predicting temperature distribution, thermal stress, and thermal fatigue life through numerical simulation. In power cycling and temperature shock testing, COMSOL simulates solder creep and microstructure changes to optimize materials and processes. It features a user-friendly interface, supports custom models and parameters, and offers rich analysis capabilities through powerful post-processing. Through COMSOL simulation, engineers can solve problems during the design phase, improving efficiency and reliability while reducing costs.

[0005] Currently, traditional COMSOL simulations for power semiconductor devices primarily involve electrothermal simulations that mimic actual operating conditions. This method can accurately predict the temperature distribution and thermal stress of the device under different operating conditions. However, this simulation approach is often time-consuming, especially for complex 3D models and multiphysics coupled simulations, where computation time can increase significantly. Furthermore, to ensure the accuracy of simulation results, multiple mesh generation and solver setting optimizations are typically required, further increasing the simulation's time cost. Frequent simulation requirements mean that engineers must invest a significant amount of time in the design, verification, and optimization processes. This not only extends the product development cycle but may also lead to project delays.

[0006] Compared to electrothermal simulation, pure thermal simulation requires less computation and shorter solution time. This gives pure thermal simulation a significant advantage in computational efficiency, especially when frequent simulations and rapid iterations are needed. Furthermore, pure thermal simulation only considers heat transfer phenomena such as heat conduction, convection, and radiation, without involving other physical fields such as electric and magnetic fields. The model is relatively simple, easy to build and optimize, and facilitates the rapid acquisition of preliminary simulation results. While pure thermal simulation in COMSOL can analyze temperature distribution and heat conduction, its drawbacks include neglecting electrical effects, thermal stress and deformation, multiphysics coupling, device reliability assessment, environmental influences, and material nonlinear effects. This can lead to incomplete and inaccurate simulation results that fail to fully reflect the device's behavior under actual operating conditions. Summary of the Invention

[0007] This invention provides a refined simulation method for power devices using heat transfer field coupling to solve the problem of long simulation time for electrothermal simulation in semiconductor device simulation using COMSOL software.

[0008] According to one aspect of the present invention, a method for refined simulation of power devices utilizing heat transfer field coupling is provided, comprising the following steps:

[0009] Step 1: Establishing the COMSOL basic model;

[0010] Step 2: Transient thermal resistance (Z) th Curve calibration;

[0011] Step 3: Fit the chip power consumption curve;

[0012] Step 4: Obtain the total power consumption curve in actual testing;

[0013] Step 5: Obtain the bonding wire power consumption curve;

[0014] Step 6: Run the simulation.

[0015] The present invention has the following beneficial technical effects:

[0016] 1. Improved simulation accuracy: By calibrating the transient thermal impedance curve and fitting the power consumption curve, the thermal effects inside semiconductor devices can be accurately simulated, improving the accuracy of simulation results.

[0017] 2. Reduced simulation time: Replacing electrothermal simulation with heat transfer simulation reduces computational complexity and significantly reduces the simulation time.

[0018] 3. Clear relationship between power consumption and temperature: It can obtain detailed functional relationships between power consumption and temperature in various parts of the semiconductor device structure, which helps to optimize design and analyze faults.

[0019] 4. Resource saving: It reduces the reliance on complex electrothermal models, reduces the consumption of computing resources, and improves simulation efficiency. Attached Figure Description

[0020] Figure 1 This is a simulation flowchart of the present invention;

[0021] Figure 2 This is a three-dimensional model diagram of an embodiment of the present invention;

[0022] Figure 3 The transient thermal impedance (Z) of this invention th Curve calibration result curve;

[0023] Figure 4 The R obtained in this invention is fitted based on the device datasheet. ds(on) A graph showing the relationship between temperature and other parameters;

[0024] Figure 5 The V obtained by fitting the present invention ds A graph showing the functional relationship between temperature and temperature;

[0025] Figure 6 This is a curve showing the functional relationship between power consumption and temperature of a semiconductor device, fitted by this invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention.

[0028] This invention proposes a refined simulation method for power devices that utilizes heat transfer field coupling, replacing electrothermal field coupling with a heat transfer field, such as... Figure 1 As shown, it includes the following steps:

[0029] The basic model was established, the transient thermal resistance (Zth) curve was calibrated, the chip power consumption curve was fitted, the total power consumption curve was obtained in actual testing, and the bonding wire power consumption curve was fitted; among which:

[0030] The aforementioned basic model is established to create a basic simulation model in COMSOL, ensuring the accuracy of the basic simulation data and simulation precision, as well as the high efficiency of computation.

[0031] The transient thermal impedance (Zth) curve calibration is used to ensure that the heat flow path of the simulation model is consistent with the experimental heat flow path, thereby ensuring the accurate establishment of the simulation model;

[0032] The fitting process obtains the chip power consumption curve, which is then compared to the R value in the device datasheet provided by the semiconductor manufacturer. ds(on) The relationship curve between temperature and power consumption can be fitted to obtain its functional expression. By giving a current magnitude, the functional relationship curve between chip power consumption and temperature can be obtained.

[0033] The total power consumption curve was obtained from the actual test. In the actual power cycle test, the V0 of the device at different temperatures was read by software. ds Export the data and fit it to obtain V. ds The relationship curve between temperature and power consumption is obtained, and then the total power consumption of the device is obtained as a function of temperature based on the known current magnitude.

[0034] The fitting yields a bonding wire power consumption curve. Since the total power consumption of a semiconductor device is approximately composed of chip power consumption and bonding wire power consumption, the relationship curve between bonding wire power consumption and temperature is obtained by subtracting the relationship curves between chip power consumption and temperature and total power consumption and temperature.

[0035] The device under test includes a power semiconductor module.

[0036] The establishment of the COMSOL basic model includes: creating the geometric model, defining material properties, setting physical fields and boundary conditions, meshing, adding studies, setting the solver, and running the simulation.

[0037] More specifically, the COMSOL basic model establishment includes: analyzing the internal chip structure through SAM scanning to obtain dimensions, and then using SolidWorks software to create a 3D model of the semiconductor device. After importing the 3D model into COMSOL, an appropriate physics module is selected, and multiphysics interactions are implemented using the coupling interface. For material properties, parameters such as conductivity, dielectric constant, and thermal conductivity can be manually input or imported. Based on the 3D model, a suitable mesh generation method is selected, and the mesh density is optimized to increase simulation accuracy and computational efficiency, ensuring detailed mesh generation in key areas. This effectively simulates the physical behavior of the device and the multiphysics coupling effects.

[0038] The transient thermal resistance (Z) th Curve calibration includes: Experiment Z th Curve acquisition and simulation Z th Curve acquisition, curve comparison, and device parameter modification enable simulation and experiment to be more accurate. th coincide.

[0039] More specifically, for transient thermal resistance (Z) thCurve calibration, including: obtaining experimental and simulation Z-curve values. th Based on the differences in the curves, a suitable calibration method is selected to ensure that the heat flow path of the simulation model is consistent with the experimental heat flow path, thereby ensuring the accurate establishment of the simulation model. Specifically, this can be achieved by changing the active area of ​​the chip in the simulation model, modifying the thermal conductivity of the material (such as the thermal conductivity of the solder), etc., thus improving the simulation Z-axis. th By aligning the experimental curves with the simulation curves, the simulation model is optimized. These methods achieve a high degree of matching between the experimental and simulation models, ensuring the accuracy and reliability of the simulation results.

[0040] The fitted chip power consumption curve is obtained from the datasheet. ds(on) The relationship curve between temperature and R is obtained by fitting. ds(on) Functional relationship with temperature, calculation of chip power consumption function:

[0041] ;

[0042] Where Intercept represents the intercept, B1, B2, and B3 represent characters that refer to constants, and T represents temperature.

[0043] More specifically, the chip power consumption curve is obtained by fitting the data, including: using the on-resistance R from the device datasheet. ds(on) The relationship curve between temperature and current can be fitted to derive a functional expression. After passing a current I with known magnitude, the formula can be used... Calculate the chip's power consumption P, where R is the on-resistance R. ds(on) By combining the fitted curve of on-resistance versus temperature, the curve of chip power consumption versus temperature can be further derived:

[0044] ;

[0045] The process of obtaining the total power consumption curve in actual testing includes: conducting actual power cycle tests and collecting voltage, current, and power consumption data through a data acquisition system.

[0046] More specifically, obtaining the total power consumption curve in actual testing includes: In actual power cycle testing, using specialized test fixtures to precisely mount the semiconductor device in the test circuit. The semiconductor device is powered on according to a preset current, and the current, voltage, and power consumption data at different temperatures are automatically recorded by the device's built-in data acquisition system. By analyzing and processing the collected data, the total power consumption data at different temperatures can be obtained, and further, a functional relationship curve between total power consumption and temperature can be fitted.

[0047] ;

[0048] The process of obtaining the bonding wire power consumption curve includes: obtaining the bonding wire power consumption function curve from the chip power consumption function curve and the device total power consumption function curve.

[0049] ;

[0050] More specifically, the bonding wire power consumption curve is obtained by subtracting the chip power consumption curve from the total power consumption curve of the chip and the bonding wire power consumption curve obtained above. The bonding wire power consumption curve is obtained by importing the power consumption curves of the chip and the total power consumption curve into the COMSOL simulation software. The power consumption curves of the chip and the bonding wire are then imported into the COMSOL simulation software as the heat dissipation rates of the chip and the bonding wire, respectively, to achieve the effect of replacing electrothermal simulation with pure thermal simulation.

[0051] The methods and embodiments provided in this invention can be executed in COMSOL simulation software. Taking a MOSFET device running in COMSOL simulation software as an example, Figure 2 This is a 3D model of a semiconductor device based on COMSOL simulation software. For example... Figure 2 As shown, the refined simulation method for building a 3D model includes: First, setting precise parameters to ensure the accuracy of the simulation's foundational data. Next, selecting appropriate physics modules (such as solid mechanics, current, and solid heat transfer) and research types (such as transient analysis and steady-state analysis) to ensure the simulation accurately reflects real-world application scenarios. Then, defining material properties, including mechanical, electrical, and thermal performance parameters (such as Young's modulus, Poisson's ratio, thermal conductivity, and electrical conductivity), to accurately simulate material behavior. Next, setting boundary and initial conditions, including fixed constraints, heat flux, initial temperature, and initial current, to ensure the model realistically simulates actual operating conditions. Following this, mesh generation is performed, selecting a suitable mesh type based on model complexity and analysis requirements, and adjusting the mesh density to ensure the mesh meets simulation accuracy requirements. Finally, configuring solver parameters, including the solution step size and iteration count, and selecting an appropriate solver configuration based on the chosen research type and physics field to improve simulation accuracy and computational efficiency.

[0052] Figure 3 The transient thermal impedance (Z) of this invention is an embodiment of the present invention. th Curve calibration result curve, such as Figure 3As shown, after the basic 3D model was built, the semiconductor device was first studied in steady state using COMSOL simulation software. Under a given current condition, the device was heated to steady state, and the maximum junction temperature was measured using a chip probe, thus simulating the state of the semiconductor device being heated by a large current in the experiment. Subsequently, a transient study was conducted, allowing the device to cool down naturally, and the cooling curve of the semiconductor device was obtained. The cooling data was exported to Excel, and the thermal resistance at each moment was calculated, thus obtaining the transient thermal impedance (Z). th The Z curve is then calculated. Finally, the experimental and simulation results are used to calculate the Z curve. th By comparing the curves and selecting an appropriate calibration method based on the differences, a high degree of matching between the experimental and simulation models can be achieved, ensuring the accuracy and reliability of the simulation results.

[0053] Figure 4 The on-resistance R in this invention is fitted based on the device datasheet. ds(on) The relationship curve with temperature, such as Figure 4 As shown, data points are extracted from the relationship curve graph. Based on the shape and characteristics of the curve, an appropriate fitting model and fitting tool are selected, and finally the on-resistance R is fitted. ds(on) The functional relationship curve between temperature and power consumption can be further derived from the given current magnitude. Figure 5 As shown by the curve.

[0054] Figure 5 The on-state voltage drop V of the semiconductor device fitted by this invention is... ds The function curve of temperature, such as Figure 5 As shown, in actual power cycling tests, the load current applies a certain duty cycle to the device under test through the control of the control module. current By heating the device under test, the Vt of the device at different temperatures can be directly read in the software during the experiment. ds Export the data and fit it to obtain the device V. ds The curve showing the functional relationship between temperature and temperature.

[0055] Figure 6 This is the curve showing the functional relationship between power consumption and temperature of the semiconductor device fitted by this invention. The previous step already yielded V... ds The functional relationship curve between temperature and temperature, expressed by the formula This allows us to calculate the functional relationship between the device's total power consumption and temperature, such as... Figure 6 The solid line in the diagram shows the total power consumption of the device, which can be approximated as the sum of the chip power consumption and the bonding wire power consumption. The relationship between chip power consumption and temperature can be derived from... Figure 4 From the above, we can subtract the chip power consumption from the total power consumption to obtain the functional relationship between bonding wire power consumption and temperature, as follows: Figure 6The dotted lines are shown in the diagram.

[0056] Finally, the power consumption functions of both the chip and the bonding wire are imported into the COMSOL simulation software as the heat dissipation rates of the chip and the bonding wire, respectively, to achieve the effect of replacing electrothermal simulation with pure thermal simulation.

Claims

1. A refined simulation method for power devices utilizing heat transfer field coupling, characterized in that, The method includes the following steps: Step 1: Establishing the COMSOL basic model; Step 2: Transient thermal impedance Z th Curve calibration; Step 3: Fit the chip power consumption curve; Step 4: Obtain the total power consumption curve in actual testing; Step 5: Obtain the bonding wire power consumption curve; Step 6: Run the simulation; Step 3 includes: using the on-resistance R ds(on) The relationship curve between temperature and temperature is fitted to derive its functional expression: ； Where Intercept represents the intercept, B1, B2, and B3 represent characters that refer to constants, and T represents temperature; After passing through a known current I, use the formula Calculate the chip's power consumption P, where R is the on-resistance R. ds(on) By combining the fitted on-resistance versus temperature curve, the chip power consumption versus temperature curve can be derived: ； Step 4 includes: In actual power cycling testing, the semiconductor device is mounted in the test circuit using a test fixture, and the semiconductor device is powered on according to a preset current. The current, voltage, and power consumption data at different temperatures are automatically recorded by the data acquisition system. By analyzing and processing the collected data, the total power consumption data at different temperatures is obtained, and the functional relationship curve between total power consumption and temperature is further fitted. ； Step 5 includes: The total power consumption of the semiconductor device consists of the sum of chip power consumption and bonding wire power consumption. The bonding wire power consumption versus temperature curve is obtained by subtracting the chip power consumption versus temperature curve from the total power consumption versus temperature curve. ； The power consumption curves of the chip and the bonding wire are imported into the COMSOL simulation software as the heat dissipation rates of the chip and the bonding wire, respectively, to realize pure thermal simulation instead of electrothermal simulation.

2. The method according to claim 1, characterized in that, Step 1 includes: analyzing the internal chip structure using SAM scanning to obtain dimensions, then creating a 3D model of the semiconductor device using SolidWorks software; importing the 3D model into COMSOL, selecting an appropriate physics module, and using the coupling interface to realize multiphysics interactions; manually inputting or importing parameters such as conductivity, dielectric constant, and thermal conductivity for material properties; selecting a suitable meshing method based on the 3D model to mesh key regions, simulating the physical behavior of the semiconductor device and multiphysics coupling effects; configuring solver parameters, including the solution step size and number of iterations, where key regions include the active region, bond lines, bonds, and heat sinks.

3. The method according to claim 2, characterized in that, Step 2 includes: obtaining the experimental and simulated transient thermal impedance Z. th Based on the differences in the curves, a suitable calibration method is selected to ensure that the heat flow path of the 3D model is consistent with the experimental heat flow path, thereby ensuring the accurate establishment of the simulation model.

4. The method according to claim 3, characterized in that, A suitable calibration method is to adjust the active area of ​​the chip in the 3D model or modify the thermal conductivity of the material to achieve the desired calibration result. th The curve coincides with the experimental curve.

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