A test method for reducing chip test delay

Abstract

The present invention provides a test method for reducing chip test delay, including step 1, obtaining a jump address of a jump instruction, starting with the jump address, carrying a segment of pattern data of a first length and storing it in a first storage area, and using the same method to carry all pattern data at the same position of the jump instruction; step 2, continuously carrying several segments of pattern data of a second length in an external memory and storing them in a second storage area, parsing and executing the pattern data in sequence according to the carrying order, and deleting the executed pattern data; step 3, judging whether there is a jump instruction during the execution of step 2, if not, continuing to execute step 2 until the carrying, parsing and execution of all pattern data are completed, if yes, executing step 4; step 4, reconstructing the second storage area and jumping to the first storage area according to the jump instruction, parsing and executing the pattern data corresponding to the jump instruction, and then executing step 2. The present invention can reduce the jump delay of chip testing and improve the accuracy of testing.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a testing method for reducing chip testing delay. Background Art

[0002] During the chip performance test, when the execution of the vector in the Pattern file branches according to different test results, when the parsed data suddenly points to a line in the Pattern file, and this line may be in a corresponding location in the external memory, the corresponding data in the Pattern file is temporarily loaded from the external memory. There will be an extremely high delay from parsing to waveform emission, which seriously affects the test efficiency of the test equipment for the chip.

[0003] When temporarily loading the corresponding data in the pattern file from the external memory, there may be problems such as refreshing or busy. For example, when the loading unit has just sent a read request and the external memory is waiting for reading back, the external memory cannot respond to the data immediately, resulting in parsing interruption, resulting in output waveform errors, and seriously affecting the test effect of the test equipment on the chip. Summary of the invention

[0004] In view of this, the problem to be solved by the present invention is to provide a test method for reducing chip test delay, which can reduce the jump delay of chip test and improve the accuracy of test.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A test method for reducing chip test delay, comprising a test chip for parsing and executing pattern data and an external memory for storing pattern data, wherein a first storage area and a second storage area are set in the test chip;

[0007] Step 1, construct a first storage area, obtain a jump address of a jump instruction, move a segment of pattern data of a first length starting from the jump address and store it in the first storage area, and use the same method to move pattern data at the same position of all jump instructions;

[0008] Step 2, constructing and executing the second storage area, continuously transferring a plurality of pattern data of the second length in the external memory and storing them in the second storage area, parsing and executing the pattern data in sequence according to the transfer order, and deleting the executed pattern data;

[0009] Step 3: determine whether there is a jump instruction during the execution of step 2. If not, continue to execute step 2 until all pattern data are moved, parsed and executed. If yes, execute step 4.

[0010] Step 4, execute the first storage area, reconstruct the second storage area and jump to the first storage area according to the jump instruction, parse and execute the pattern data corresponding to the jump instruction, and then execute step 2.

[0011] Furthermore, the second storage area is provided with a water level value for determining the memory usage, and the transport speed of the pattern data is greater than the speed of parsing and executing the pattern data, so that the water level value of the second storage area is maintained in a stable range.

[0012] Furthermore, the reconstructing the second storage area includes: clearing all pattern data in the second storage area, obtaining a jump address corresponding to a jump instruction, sequentially moving pattern data of a second length after an interval of a first length of the jump address, and storing the data in the second storage area.

[0013] Furthermore, the first storage area includes an address table, and the address table includes address information of a jump instruction name and a pattern header segment;

[0014] Quickly locate the required pattern data through table lookup.

[0015] Furthermore, the jump instruction includes jumping to a specified position and returning to the jump position.

[0016] The advantages and positive effects of the present invention are:

[0017] By setting a first storage area in the test chip, each jump instruction corresponds to a jump address, and the pattern header of all jump instructions is stored in the first storage area. When a jump instruction appears during the parsing process of the test chip, the corresponding pattern header in the first storage area is directly parsed and executed to avoid jump delays.

[0018] A second storage area is provided in the test chip, which is used to transfer pattern data in the external memory in segments, so as to improve the continuity of pattern data parsing; when a jump instruction appears, the pattern data in the second storage area is cleared in time, and the address corresponding to the jump address after the first length is used as the new starting address, so as to continuously transfer several segments of pattern data of the second length; after the pattern header segment corresponding to the jump instruction in the first storage area is parsed, it returns to the second storage area to continue parsing, and there will be no parsing interruption, so as to improve the accuracy and continuity of the output waveform and improve the test effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0020] Figure 1 It is an overall flow chart of a test method for reducing chip test delay of the present invention;

[0021] Figure 2 It is a structural diagram of a pattern file of a test method for reducing chip test delay of the present invention.

[0022] In the figure: 1. pattern file; 2. jump address; 3. pattern header; 4. pattern segment; DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0025] The present invention provides a test method for reducing chip test delay, such as Figure 1 and Figure 2 As shown, it includes a test chip and an external memory, the external memory is used to store pattern files, and the pattern files include a large amount of pattern data. The test chip and the external memory are interoperable, so that the test chip can transfer pattern data from the external memory, and the test chip parses and executes the pattern data to output test vectors.

[0026] There are jump instructions in the process of parsing and executing pattern data. One embodiment of the present application is: the jump instruction includes jumping to a specified position and returning to the jump position. The jump instruction corresponds to a jump address of the external memory. The test chip uses the jump address as the starting point to move the pattern header data and stores it in the first storage area. The same method is used to move the pattern header data at the same position of all jump instructions (same position: a segment of pattern data of the first length starting from the jump address). The second storage area is used to store continuously moved pattern segments, so that the test chip can parse and execute the pattern data sequentially.

[0027] The second storage area is provided with a water level value for determining the memory usage, adjusting the operating parameters of the test chip so that the speed of pattern data transfer is greater than the speed of pattern data parsing and execution, and: the number of instruction lines transferred is greater than the number of instruction lines parsed in the same time. By judging whether the water level value of the second storage area is within the threshold interval, controlling whether the test chip transfers the pattern segment, so that the water level value of the second storage area is maintained within the threshold interval, the pattern data can be parsed and executed continuously and stably.

[0028] The process of Pattern parsing includes:

[0029] Step 1: construct a first storage area, obtain a jump address of a jump instruction, move a segment of pattern data of a first length starting from the jump address and store it in the first storage area, and use the same method to move pattern data at the same position of all jump instructions.

[0030] Starting from the jump address, the pattern data of the first length is the pattern header, and the pattern data of the second length is defined as the pattern segment. The test chip moves one pattern segment at a time. The first length is artificially set according to the operating parameters of the test chip, so that the time to parse and execute the pattern header is longer than the time to re-move multiple pattern segments in the second storage area, thereby improving the continuity of the test.

[0031] The first storage area includes an address table, which includes the jump instruction name and the storage address of the corresponding pattern header. The test chip quickly determines the location of the required pattern header by querying the address table, so as to continuously parse and execute and reduce the jump delay.

[0032] Step 2: construct and execute the second storage area, continuously transfer several segments of pattern data of the second length in the external memory and store them in the second storage area, parse and execute the pattern data in sequence according to the transfer order, and delete the executed pattern data.

[0033] The second length is artificially set according to the operating parameters of the test chip to adjust the transport frequency of the pattern segment. While the test chip continuously transports the pattern segment to the second storage area, the pattern data composed of the pattern segment is analyzed and executed in sequence according to the transport order of the pattern segment, and the analyzed pattern data is deleted. Since the transport speed of the pattern data is greater than the speed of parsing and executing the pattern data, the water level value of the second storage area can be kept within the threshold range.

[0034] Step 3, determine whether there is a jump instruction during the execution of step 2. If not, continue to execute step 2 until all pattern data are moved, parsed and executed. If yes, execute step 4.

[0035] During the process of parsing and executing the pattern data, it is continuously determined whether there is a jump instruction. The jump instruction includes jumping to a new location or returning to the original location before the jump. If there is no jump instruction, continue to execute step 2 to move, parse and execute the pattern data until all the pattern data are run; if there is a jump instruction, execute step 4.

[0036] Step 4, execute the first storage area, reconstruct the second storage area and jump to the first storage area according to the jump instruction, parse and execute the pattern data corresponding to the jump instruction, and then execute step 2.

[0037] When a jump instruction is encountered during the parsing and execution process, the address table is queried according to the name of the jump instruction to obtain the storage address of the corresponding pattern header, and the pattern header of the first storage area is parsed and executed to achieve continuous parsing of the pattern data and reduce the jump delay.

[0038] While the test chip parses the pattern header in the first storage area, it reconstructs the second storage area. The specific process is: clear all pattern data in the second storage area, obtain the jump address corresponding to the jump instruction, and after the pattern data of the first length of the jump address is separated, the pattern data of the second length is sequentially transferred and stored in the second storage area. After the test chip parses and executes the corresponding pattern header in the first storage area, it can continue to parse the pattern data just transferred in the second storage area to improve the continuity of the parsing.

[0039] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of this patent.

Claims

1. A test method for reducing chip test delay, characterized in that: It includes a test chip for parsing and executing pattern data and an external memory for storing pattern data, wherein a first storage area and a second storage area are set in the test chip to avoid jump delay; Step 1, constructing a first storage area, obtaining a jump address of a jump instruction, moving a segment of pattern data of a first length starting from the jump address and storing it in the first storage area, and using the same method to move pattern data at the same position of all jump instructions; Step 2, constructing and executing the second storage area, continuously transferring a plurality of pattern data of the second length in the external memory and storing them in the second storage area, parsing and executing the pattern data in sequence according to the transfer order, and deleting the executed pattern data; Step 3: determine whether there is a jump instruction during the execution of step 2. If not, continue to execute step 2 until all pattern data are moved, parsed and executed. If yes, execute step 4. Step 4, executing the first storage area, reconstructing the second storage area and jumping to the first storage area according to the jump instruction, parsing and executing the pattern data corresponding to the jump instruction, and then executing step 2; The reconstructing the second storage area includes: clearing all pattern data in the second storage area, obtaining a jump address corresponding to a jump instruction, sequentially moving pattern data of a second length after an interval of a first length of the jump address, and storing the pattern data in the second storage area; The first length is set according to the operating parameters of the test chip so that the time for parsing and executing the pattern header segment is longer than the time for the second storage area to re-transfer multiple pattern segments.

2. A test method for reducing chip test delay according to claim 1, characterized in that: The second storage area is provided with a water level value for determining the memory usage, and the transport speed of the pattern data is greater than the speed of parsing and executing the pattern data, so that the water level value of the second storage area is maintained in a stable range.

3. A test method for reducing chip test delay according to claim 1, characterized in that: The first storage area includes an address table, which includes a jump instruction name and address information of corresponding pattern data; the required pattern data is quickly located by a table lookup method.

4. A test method for reducing chip test delay according to claim 1, characterized in that: The jump instruction includes jumping to a specified location and returning to the jump location.

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