Memory termination resistor configuration method, electronic device and storage medium

Abstract

The present invention relates to the field of computer technology, and discloses a memory termination resistor configuration method, electronic device and storage medium, the method comprising: configuring a resistance parameter sequence to be tested to a product to be tested, and performing a stress test on the configured product to be tested; in the process of performing a stress test on the configured product to be tested, performing error information collection and test signal collection on the product to be tested, and screening a target resistance parameter in the resistance parameter sequence to be tested according to the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested, so as to perform memory termination resistor configuration according to the target resistance parameter. Before performing memory termination resistor configuration, a series of stress tests and analyses are performed on a plurality of optional resistance parameters to be tested, so as to screen the optimal target resistance parameter, thereby improving the accuracy of the memory termination resistor configuration result and laying a foundation for improving the performance and stability of memory.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory termination resistor configuration method, an electronic device, and a storage medium. Background Art

[0002] At present, as the demand for memory bandwidth of electronic devices such as servers continues to increase, the operating frequency of memory is also getting higher and higher. The increase in memory operating frequency also gradually increases the requirements for signal integrity on the board. Poor signal integrity will cause a large number of errors in the communication process between the main control chip and the memory, and seriously affect the stability of the operation of electronic equipment.

[0003] In related technologies, on-die termination technology (ODT) is usually used to build termination resistors inside the memory chip to solve the signal reflection problem, thereby improving the performance and stability of the memory.

[0004] However, since the configuration result of the termination resistor will directly affect the performance and stability of the memory, and the current configuration of the termination resistor still relies on manual work, there is a great deal of subjectivity, which reduces the accuracy of the configuration result of the termination resistor. Summary of the invention

[0005] The present application provides a memory termination resistor configuration method, an electronic device and a storage medium to solve the defects of the related art that the accuracy of the configuration result of the termination resistor is reduced.

[0006] The first aspect of the present application provides a memory termination resistor configuration method, comprising:

[0007] Obtain the resistance parameter sequence to be measured;

[0008] configuring the resistance parameter sequence to be tested to the product under test, and performing a stress test on the configured product under test;

[0009] In the process of stress testing the configured product under test, error information collection and test signal collection are performed on the product under test to obtain error information collection results and test signal collection results corresponding to each resistance parameter under test in the resistance parameter sequence under test;

[0010] According to the error information collection results and the test signal collection results corresponding to each resistance parameter to be measured in the resistance parameter sequence to be measured, a target resistance parameter is screened in the resistance parameter sequence to configure the memory termination resistance according to the target resistance parameter.

[0011] In an optional implementation, in the process of performing stress testing on the configured product under test, error information collection and test signal collection are performed on the product under test to obtain error information collection results and test signal collection results corresponding to each resistance parameter under test in the resistance parameter sequence under test, including:

[0012] During the stress test of the configured product under test, error information of the product under test is collected to determine the number of single-bit errors and the number of multi-bit errors corresponding to each resistance parameter under test in the resistance parameter sequence under test;

[0013] For any of the resistance parameters to be measured in the resistance parameter sequence to be measured, according to the number of single-bit errors and the number of multi-bit errors corresponding to the resistance parameter to be measured, determining an error information collection result corresponding to the resistance parameter to be measured;

[0014] During the process of stress testing the configured product under test, multiple test signal acquisitions are performed on the product under test to obtain multiple test signal waveform features corresponding to each resistance parameter under test in the resistance parameter sequence under test;

[0015] For any resistance parameter to be measured in the resistance parameter sequence to be measured, a test signal acquisition result corresponding to the resistance parameter to be measured is determined according to a plurality of test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured.

[0016] In an optional implementation, for any of the resistance parameters to be measured in the resistance parameter sequence to be measured, determining the test signal acquisition result corresponding to the resistance parameter to be measured according to a plurality of test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured, comprises:

[0017] For any of the resistance parameters to be measured in the resistance parameter sequence to be measured, according to a plurality of the test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured, determining the square wave similarity corresponding to the test signal obtained by each signal acquisition;

[0018] The test signal acquisition result corresponding to the resistance parameter to be measured is determined according to the square wave similarity corresponding to the test signal obtained by each signal acquisition.

[0019] In an optional implementation, determining the square wave similarity corresponding to the test signal obtained by each signal acquisition according to the plurality of test signal waveform characteristics and the standard square wave signal characteristics corresponding to the resistance parameter to be measured includes:

[0020] Based on the following formula, the square wave similarity corresponding to the test signal obtained from each signal acquisition is determined:

[0021]

[0022] in, represents the square wave similarity, represents the sequence length of the test signal waveform characteristics and the standard square wave signal characteristics, Indicates the first of the test signal waveform characteristics sequence values, Indicates the first characteristic of the standard square wave signal sequence values, , the test signal waveform characteristics and standard square wave signal characteristics include A sequence value.

[0023] In an optional implementation, determining the test signal acquisition result corresponding to the resistance parameter to be measured according to the square wave similarity corresponding to the test signal obtained by each signal acquisition includes:

[0024] According to the square wave similarity corresponding to the test signal obtained by each signal acquisition, the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured are determined;

[0025] The test signal acquisition result corresponding to the resistance parameter to be measured is determined according to the waveform characteristic mean and the waveform characteristic standard deviation corresponding to the resistance parameter to be measured.

[0026] In an optional implementation, determining the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured according to the square wave similarity corresponding to the test signal obtained by each signal acquisition includes:

[0027] Based on the following formula, determine the waveform characteristic mean value corresponding to the resistance parameter to be measured:

[0028]

[0029] in, represents the mean value of the waveform characteristics, Indicates the number of times the test signal is collected. Indicates The square wave similarity corresponding to the test signal obtained by the second signal acquisition.

[0030] In an optional implementation, determining the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured according to the square wave similarity corresponding to the test signal obtained by each signal acquisition includes:

[0031] Based on the following formula, determine the waveform characteristic standard deviation corresponding to the resistance parameter to be measured:

[0032]

[0033] in, represents the standard deviation of the waveform characteristics, Indicates the number of times the test signal is collected. Indicates The square wave similarity corresponding to the test signal obtained by the signal acquisition, Indicates the waveform characteristic mean value corresponding to the resistance parameter to be measured.

[0034] In an optional implementation, the step of screening a target resistance parameter in the resistance parameter sequence according to the error information collection results and the test signal collection results corresponding to each resistance parameter to be measured in the resistance parameter sequence to be measured comprises:

[0035] Determine the number of single-bit errors and the number of multi-bit errors corresponding to each resistance parameter to be measured in the resistance parameter sequence according to the error information collection result corresponding to each resistance parameter to be measured in the resistance parameter sequence;

[0036] The resistance parameter to be tested with a multi-bit error number of 0 and a minimum single-bit error number is used as the resistance parameter to be selected;

[0037] In the case that the candidate resistance parameters are not unique, the target resistance parameters are screened from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters.

[0038] In an optional implementation, when the candidate resistance parameters are not unique, screening the target resistance parameters from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters includes:

[0039] In the case that the resistance parameter to be selected is not unique, determining a first average distance between each of the resistance parameters to be selected and the resistance parameter to be measured whose number of multi-bit errors is not 0;

[0040] Taking the candidate resistance parameter with the largest first average distance as the candidate resistance parameter;

[0041] In the case that the candidate resistance parameters are not unique, the target resistance parameters are screened from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters.

[0042] In an optional implementation manner, determining a first average distance between each of the candidate resistance parameters and the resistance parameter to be measured whose number of multi-bit errors is not 0 includes:

[0043] Based on the following formula, a first average distance between each of the selected resistance parameters and the resistance parameter to be measured whose number of multi-bit errors is not 0 is determined:

[0044]

[0045] in, Indicates a first average distance between a candidate resistance parameter and the resistance parameter to be measured whose number of multi-bit errors is not 0, Indicates the number of resistance parameters to be tested whose number of multi-bit errors is not 0, represents the dimension of the resistor parameters to be selected, Indicates The first of the resistor parameters to be selected Dimension value, Indicates The resistance parameter to be tested whose number of multi-bit errors is not zero Dimension value.

[0046] In an optional implementation, when the candidate resistance parameters are not unique, screening the target resistance parameters from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters includes:

[0047] In the case where the candidate resistance parameters are not unique, determining a second average distance between each of the candidate resistance parameters and the resistance parameter to be measured having the second smallest number of single-bit errors;

[0048] taking the candidate resistance parameter with the largest second average distance as a candidate resistance parameter;

[0049] In the case that the candidate resistance parameters are not unique, a target resistance parameter is screened from the candidate resistance parameters according to test signal acquisition results corresponding to the candidate resistance parameters.

[0050] In an optional implementation, when the candidate resistance parameters are not unique, screening the target resistance parameters from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters includes:

[0051] In the case where the candidate resistance parameters are not unique, determining the waveform feature mean values ​​corresponding to the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters;

[0052] Taking the candidate resistance parameter with the smallest waveform feature mean as the target candidate resistance parameter;

[0053] When the target candidate resistance parameter is not unique, determining the waveform characteristic standard deviation corresponding to each target candidate resistance parameter according to the test signal acquisition result corresponding to each target candidate resistance parameter;

[0054] The target candidate resistance parameter with the smallest waveform characteristic standard deviation is used as the target resistance parameter.

[0055] In an optional implementation, after configuring the memory termination resistance according to the target resistance parameter, the method further includes:

[0056] Obtaining operation data of the product to be tested in which the memory termination resistor is deployed;

[0057] Determine, according to the operating data of the product to be tested, a mean value of a waveform characteristic to be tested and a standard deviation of a waveform characteristic to be tested represented by the target resistance parameter on the product to be tested;

[0058] The inspection result of the product to be tested is determined based on the size relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the size relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard.

[0059] In an optional implementation, the determining the inspection result of the product to be tested according to the size relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the size relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard includes:

[0060] When the magnitude relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the magnitude relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard satisfy the following expressions, the inspection result of the product to be tested is determined to be qualified:

[0061]

[0062]

[0063] in, Represents the mean value of the waveform characteristics to be measured, Indicates the waveform feature mean test standard, represents the first equalization parameter, Indicates the maximum value of the waveform characteristic mean corresponding to the resistance parameter to be tested when the number of multi-bit errors is 0, Indicates the mean value of the waveform characteristics corresponding to the target resistance parameter, Indicates the standard deviation of the waveform characteristics to be measured, Indicates the waveform characteristic standard deviation test standard, represents the second equalization parameter, Indicates the maximum value of the standard deviation of the waveform characteristics corresponding to the resistance parameter to be tested when the number of multi-bit errors is 0, Indicates the standard deviation of the waveform characteristics corresponding to the target resistance parameters.

[0064] A second aspect of the present application provides a memory termination resistor configuration device, comprising:

[0065] An acquisition module is used to acquire a parameter sequence of the resistance to be measured;

[0066] A test module, used to configure the resistance parameter sequence to be tested to the product under test, and perform a stress test on the configured product under test;

[0067] An acquisition module is used to acquire error information and test signals of the tested product during the process of performing stress testing on the configured tested product, and obtain error information acquisition results and test signal acquisition results corresponding to each tested resistance parameter in the tested resistance parameter sequence;

[0068] The configuration module is used to screen the target resistance parameter in the resistance parameter sequence to be tested according to the error information collection results and the test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested, so as to configure the memory termination resistance according to the target resistance parameter.

[0069] A third aspect of the present application provides an electronic device, comprising: at least one processor and a memory;

[0070] The memory stores computer-executable instructions;

[0071] The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the method described in the first aspect and various possible designs of the first aspect.

[0072] A fourth aspect of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When a processor executes the computer-executable instructions, the method described in the first aspect and various possible designs of the first aspect are implemented.

[0073] A fifth aspect of the present application provides a computer program product, including computer instructions, which are used to enable a computer to execute the method described in the first aspect and various possible designs of the first aspect.

[0074] The technical solution of this application has the following advantages:

[0075] The present application provides a memory termination resistor configuration method, electronic device and storage medium, the method comprising: obtaining a resistance parameter sequence to be tested; configuring the resistance parameter sequence to be tested to the product to be tested, and performing a stress test on the configured product to be tested; in the process of performing a stress test on the configured product to be tested, performing error information collection and test signal collection on the product to be tested, and obtaining the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested; according to the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested, screening the target resistance parameter in the resistance parameter sequence to be tested, so as to perform memory termination resistor configuration according to the target resistance parameter. The method provided by the above scheme performs a series of stress tests and analyses on a variety of optional resistance parameters to be tested before configuring the memory termination resistor configuration, so as to screen the optimal target resistance parameter, thereby improving the accuracy of the memory termination resistor configuration result and laying a foundation for improving the performance and stability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the following is a brief introduction to the drawings required for use in the embodiments or the related technical descriptions. Obviously, the drawings described below are some embodiments of the present application, and a person skilled in the art can also obtain other drawings based on these drawings.

[0077] Figure 1 A schematic diagram of the structure of a memory termination resistor configuration system based on an embodiment of the present application;

[0078] Figure 2 A schematic diagram of a flow chart of a memory termination resistor configuration method provided in an embodiment of the present application;

[0079] Figure 3 A schematic diagram of a flow chart of an exemplary memory termination resistor configuration method provided in an embodiment of the present application;

[0080] Figure 4 A schematic diagram of a reference waveform of a test signal provided in an embodiment of the present application;

[0081] Figure 5 A schematic diagram of a test signal waveform processing process provided in an embodiment of the present application;

[0082] Figure 6 A schematic diagram of a standard square wave signal processing process provided in an embodiment of the present application;

[0083] Figure 7 A schematic flow chart of another exemplary memory termination resistor configuration method provided in an embodiment of the present application;

[0084] Figure 8A schematic diagram of the structure of a memory termination resistor configuration device provided in an embodiment of the present application;

[0085] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0086] The above drawings have shown clear embodiments of the present application, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0087] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0088] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the following embodiments, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0089] In related technologies, DDR memory is a key electronic component in electronic devices such as desktop computers, servers, and mobile phones. It is used to store various codes, data, and other information during the operation of the device. As the demand for DDR bandwidth continues to increase, the operating frequency of DDR is also getting higher and higher. For the popular DDR4, the operating frequency has reached 1600MHz, and for the newer DDR5, the operating frequency is even as high as 2400MHz.

[0090] The increase in DDR operating frequency has gradually increased the requirements for on-board signal integrity. Poor signal integrity can cause a large number of errors in the communication process between the main control chip and DDR, and seriously affect the stability of electronic equipment operation. ODT technology is a mechanism used in DDR to reduce signal reflections caused by impedance mismatch on the transmission line. Since the matching resistor is integrated into the DDR and PHY, the number of DDR peripheral components and PCB area are effectively reduced. Therefore, ODT technology has been used from DDR2 to the latest generation of DDR5.

[0091] In ODT technology, the on-chip matching resistor module is configured according to factors such as transmission line characteristics and DDR chip process to improve the overall signal integrity. When configuring, it is necessary to design the matching resistor value according to the waveform of the actual signal, and then perform a transmission test to determine whether the configured parameter value is appropriate based on the transmission result. This is a cumbersome process, and there may be multiple feasible parameter groups that can achieve correct transmission. The specific set of parameters to be used is determined by the tester's evaluation of the quality of the signal waveform based on experience, which is highly subjective.

[0092] The determination of ODT is crucial to the signal integrity of DDR data transmission. Traditional methods for determining ODT include manual determination through signal waveform and trial-and-error determination through ODT value modification -> data transmission correctness test -> ODT value modification. The former is highly subjective and greatly affected by the personal ability of engineers; the latter has a relatively simple correctness judgment standard. When there are multiple ODT values ​​that can achieve correct data transmission, there is a problem of selecting the best one.

[0093] In response to the above problems, the embodiment of the present application provides a memory termination resistor configuration method, electronic device and storage medium, the method comprising: obtaining a resistance parameter sequence to be tested; configuring the resistance parameter sequence to be tested to the product to be tested, and performing a stress test on the configured product to be tested; in the process of performing a stress test on the configured product to be tested, performing error information collection and test signal collection on the product to be tested, and obtaining the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested; according to the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested, the target resistance parameter is screened in the resistance parameter sequence to be tested, so as to configure the memory termination resistor according to the target resistance parameter. The method provided by the above scheme performs a series of stress tests and analyses on a variety of optional resistance parameters to be tested before configuring the memory termination resistor, so as to screen the optimal target resistance parameter, thereby improving the accuracy of the memory termination resistor configuration result and laying a foundation for improving the performance and stability of the memory.

[0094] The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0095] First, the structure of the memory termination resistor configuration system on which this application is based is described:

[0096] The memory termination resistor configuration method, electronic device, and storage medium provided in the embodiments of the present application are suitable for parameter configuration of the memory termination resistor of electronic devices such as servers. Figure 1As shown, it is a structural schematic diagram of the memory termination resistor configuration system based on the embodiment of the present application, which mainly includes a product under test and a memory termination resistor configuration device, and the device includes a test control computer and a signal acquisition device. The test control computer is used to set the process control and data processing center of the device. On the one hand, it sends data such as configuration and control instructions to the product under test through a communication cable, and obtains the current working status information of the product under test to obtain the error information collection result; on the other hand, it configures the signal acquisition device through internal communication means, performs sampling control and other operations, and obtains digital collection results. The signal acquisition device is controlled by the test control computer, obtains the original analog signal from the DDR-related transmission line in the product under test through a probe and a corresponding cable, and performs analog-to-digital conversion on the original analog signal, and then transmits the digital test signal acquisition result to the test control computer. The test control computer determines the target resistance parameters based on all the data obtained, so as to configure the memory termination resistance based on the target resistance parameters.

[0097] The embodiment of the present application provides a memory termination resistor configuration method for configuring parameters of memory termination resistors of electronic devices such as servers. The execution subject of the embodiment of the present application is an electronic device, such as a server, a desktop computer, a laptop computer, a tablet computer, and other electronic devices that can be used for memory termination resistor configuration.

[0098] like Figure 2 FIG. 1 is a flow chart of a method for configuring a memory termination resistor provided in an embodiment of the present application, the method comprising:

[0099] Step 201, obtaining a parameter sequence of a resistor to be measured.

[0100] The resistance parameter sequence to be measured includes a plurality of groups of selectable resistance parameters to be measured.

[0101] Step 202, configuring the resistance parameter sequence to be tested to the product under test, and performing a stress test on the configured product under test.

[0102] Specifically, the ODT value (resistance parameter to be tested) is taken out from the ODT value sequence (resistance parameter sequence to be tested) in sequence and transmitted to the product under test. Here, the ODT value is a single value, corresponding to a certain pin of DDR involving ODT. A start stress test instruction is sent to the product under test to start the stress test. Here, the stress test includes but is not limited to random access test and block access test, etc. The specific stress test time is determined according to the stability requirements.

[0103] Step 203, during the process of stress testing the configured product under test, error information collection and test signal collection are performed on the product under test to obtain error information collection results and test signal collection results corresponding to each resistance parameter under test in the resistance parameter sequence under test.

[0104] Among them, the error information collection results can also be called stress test results. The error information of the product under test includes single-bit errors and multi-bit errors. The error information collection results include at least the number of single-bit errors and the number of multi-bit errors. The test signal collection includes at least the test signal waveform characteristic information of the product under test, etc.

[0105] Step 204 , according to the error information collection results and the test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested, the target resistance parameter is screened in the resistance parameter sequence to configure the memory termination resistance according to the target resistance parameter.

[0106] Specifically, by performing a series of analyses on the error information collection results and the test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested, the resistance parameter to be tested that performs the best performance is determined, and the resistance parameter to be tested is used as the target resistance parameter. Finally, the memory termination resistance is configured according to the target resistance parameter, wherein the target resistance parameter is the matching resistance value.

[0107] Based on the above embodiments, Figure 3 A flowchart of an exemplary memory termination resistor configuration method provided in an embodiment of the present application is provided. As an implementable manner, based on the above embodiment, in one embodiment, during the process of stress testing the configured product under test, error information collection and test signal collection are performed on the product under test to obtain error information collection results and test signal collection results corresponding to each resistance parameter under test in the resistance parameter sequence under test, including:

[0108] Step 2031, during the process of stress testing the configured product under test, error information of the product under test is collected to determine the number of single-bit errors and the number of multi-bit errors corresponding to each resistance parameter under test in the resistance parameter sequence under test;

[0109] Step 2032, for any resistance parameter to be measured in the resistance parameter sequence to be measured, according to the number of single-bit errors and the number of multi-bit errors corresponding to the resistance parameter to be measured, determining the error information collection result corresponding to the resistance parameter to be measured;

[0110] Step 2033, during the process of performing stress testing on the configured product under test, multiple test signal acquisitions are performed on the product under test to obtain multiple test signal waveform features corresponding to each resistance parameter under test in the resistance parameter sequence under test;

[0111] Step 2034 , for any resistance parameter to be measured in the resistance parameter sequence to be measured, according to a plurality of test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured, determine the test signal acquisition result corresponding to the resistance parameter to be measured.

[0112] Specifically, the memory termination resistor configuration system is first initialized, the status of the product under test and the signal acquisition device are obtained, and the test status is waited for. After that, the ODT value sequence and stress test mode to be tested are initialized, and the operating parameters of the signal acquisition device are initialized. The stress test mode includes at least random access test and block access test. After setting the current ODT value and transmitting it to the product under test, the product under test is controlled to start the stress test. During the stress test, the product under test collects error information, mainly including the number of single-bit errors and the number of multi-bit errors. After the stress test is completed, the stress test results (error information collection results) are read from the product under test, mainly including the number of single-bit errors and the number of multi-bit errors, and stored in the table corresponding to the current ODT value. During the stress test, the signal acquisition device is also controlled to perform sampling. When the product under test performs the last stress test, the signal sampling device is controlled to perform signal sampling. The stress test time is relatively long, usually measured in hours, and it is impractical and unnecessary to store all waveform information. In practice, a certain feature (such as the rising edge) of a typical signal (such as the DQS signal of DDR) is used as a trigger for sampling. Each sampling is a burst access cycle, and each stress test is sampled a fixed number of times. After the signal is sampled, the digitized sampling results are stored. After the stress test is completed, the sampled data is read from the signal sampling device and stored in the storage area corresponding to the current ODT value. If all ODT values ​​in the sequence have been tested, proceed to the next step; otherwise, select the next ODT value from the ODT sequence to repeat the above process, and finally perform data analysis to obtain the optimal ODT (target resistance parameter) and the corresponding waveform characteristic value, and then determine the product inspection standard.

[0113] Among them, Figure 4As shown, it is a reference waveform diagram of the test signal provided by the embodiment of the present application. The stress test mode mainly corresponds to different test data patterns, that is, any data line of DDR is serially outputted such as 0xFF, 0x0, 0x55, 0xCC, etc. Because the sampled waveform is to be compared with the continuous square wave waveform, it is necessary to know when the square wave waveform is generated so as to perform sampling at the corresponding time. The stress test that generates the square wave waveform is arranged at the end (the signal during the last stress test), so that the sampling operation can be performed after a certain time. In fact, the time of each stress test is not fixed, but the time can be roughly estimated, and the stress test item corresponding to the sampling is placed at the end, which is convenient for estimating the start time of sampling. The data line is serially outputted 0x55 to form a square wave. Here, only 5 continuous square waves need to be generated. In fact, when DDR is accessed in burst8 mode, 5 square waves are outputted. The first pulse is a leading pulse, which is invalid. Each edge of the last four square waves corresponds to one data, a total of 8 data, that is, one data line outputs 8 bits in one burst8, which is 0x55 here.

[0114] Specifically, in one embodiment, for any resistance parameter to be measured in the resistance parameter sequence to be measured, the square wave similarity corresponding to the test signal obtained in each signal acquisition can be determined based on multiple test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured; and the test signal acquisition result corresponding to the resistance parameter to be measured is determined based on the square wave similarity corresponding to the test signal obtained in each signal acquisition.

[0115] Specifically, Figure 5 As shown, it is a schematic diagram of the test signal waveform processing process provided in an embodiment of the present application. After completing all stress tests, the characteristic values ​​of the signal waveform corresponding to each ODT value are analyzed first. The characteristic values ​​are obtained by analyzing the signal FFT (Fast Fourier Transform) results. First, after the test signal is obtained by sampling, since the first signal cycle of the sampling is unstable, the sampling values ​​of the first cycle in the sampling sequence (test signal) are all modified to 0. In order to further ensure the accuracy of the characteristic analysis results, the sampling sequence is padded with zeros and extended, and the length of the extended sequence is 4 times the nearest integer power of 2 that is larger than the original length. For example, if the original sequence length is 1000, the nearest integer power of 2 that is larger than it is 1024, and 4 times 1024 is 4096, then the length of the extended sequence is 4096, of which the numbers from 1001 to 4096 are 0. The sampling sequence processing process is as follows Figure 5 As shown, N is the sampling sequence length and T is the signal period.

[0116] Accordingly, if Figure 6As shown, it is a schematic diagram of the standard square wave signal processing process provided in an embodiment of the present application. The starting phase of the standard square wave signal sequence is 0, the period is T, and the sequence length is N. For the specific processing process, refer to the processing process of the test signal. The principles of the two are the same and will not be repeated here.

[0117] Specifically, in one embodiment, FFT is performed on the expanded sampling sequence and the standard square wave sequence respectively to convert the sampling sequence (test signal) into a test signal waveform feature, and convert the standard square wave signal into a standard square wave signal feature. Further, the square wave similarity corresponding to the test signal obtained by each signal acquisition can be determined based on the following formula:

[0118]

[0119] in, represents the square wave similarity, The length of the sequence representing the waveform characteristics of the test signal and the characteristics of the standard square wave signal, Indicates the first sequence values, Indicates the characteristics of the standard square wave signal sequence values, , the test signal waveform characteristics and standard square wave signal characteristics include A sequence value.

[0120] It should be noted that the test signal waveform characteristics and standard square wave signal characteristics obtained by FFT are both sequence data, that is, the test signal waveform characteristics and standard square wave signal characteristics both include A sequence value.

[0121] Specifically, in one embodiment, the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured can be determined based on the square wave similarity corresponding to the test signal obtained in each signal acquisition; the test signal acquisition result corresponding to the resistance parameter to be measured can be determined based on the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured.

[0122] It should be noted that the waveform characteristics are used to characterize the amplitude, frequency, phase, etc. of the waveform. The overall performance of the resistance parameter to be measured is characterized by calculating the waveform characteristic mean, and the dispersion of the waveform characteristic value relative to the mean is characterized by calculating the waveform characteristic standard deviation.

[0123] Specifically, in one embodiment, the waveform characteristic mean value corresponding to the resistance parameter to be measured may be determined based on the following formula:

[0124]

[0125] in, represents the mean value of waveform characteristics, Indicates the number of times the test signal is collected. Indicates The square wave similarity corresponding to the test signal obtained by the second signal acquisition.

[0126] Specifically, in one embodiment, the waveform characteristic standard deviation corresponding to the resistance parameter to be measured may be determined based on the following formula:

[0127]

[0128] in, represents the standard deviation of waveform characteristics, Indicates the number of times the test signal is collected. Indicates The square wave similarity corresponding to the test signal obtained by the signal acquisition, Indicates the waveform characteristic mean value corresponding to the resistance parameter to be measured.

[0129] On the basis of the above embodiments, since the target resistance parameter can be screened by considering multiple aspects of performance, when the resistance parameter sequence to be measured includes many resistance parameters to be measured, in order to improve the accuracy of the target resistance parameter screening result, as an implementable method, on the basis of the above embodiments, in one embodiment, according to the error information collection results and the test signal collection results corresponding to each resistance parameter to be measured in the resistance parameter sequence to be measured, the target resistance parameter is screened in the resistance parameter sequence to be measured, including:

[0130] Step 2041, determining the number of single-bit errors and the number of multi-bit errors corresponding to each resistance parameter to be measured in the resistance parameter sequence according to the error information collection result corresponding to each resistance parameter to be measured in the resistance parameter sequence;

[0131] Step 2042, taking the resistance parameter to be tested with a multi-bit error number of 0 and a minimum single-bit error number as the resistance parameter to be selected;

[0132] Step 2043 , when the candidate resistance parameters are not unique, select the target resistance parameters from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters.

[0133] Among them, the number of multi-bit errors is 0, which indicates that the resistance parameter to be tested has no multi-bit errors during the test, and the number of single-bit errors is the smallest, which indicates that the resistance parameter to be tested has the least single-bit errors during the test. Therefore, when the number of resistance parameters to be selected is unique, the resistance parameter to be selected can be directly used as the target resistance parameter. If no resistance parameter to be selected exists after analysis, an error is reported, indicating that the sequence of resistance parameters to be tested is unreasonable and there is no suitable resistance parameter to be tested.

[0134] Specifically, in one embodiment, when the candidate resistance parameters are not unique, the first average distance between each candidate resistance parameter and the resistance parameter to be measured whose number of multi-bit errors is not 0 can be determined; the candidate resistance parameter with the largest first average distance is used as the candidate resistance parameter; when the candidate resistance parameters are not unique, the target resistance parameter is screened from the candidate resistance parameters based on the test signal acquisition results corresponding to each candidate resistance parameter.

[0135] Specifically, the first average distance represents the average difference between each candidate resistance parameter and several resistance parameters to be measured whose number of multi-bit errors is not zero. The larger the difference, the greater the difference between the resistance parameters to be measured and the resistance parameters whose number of bit errors is not zero. The distance between the two resistance parameters can be specifically represented by Euclidean distance, etc. Therefore, when the candidate resistance parameter is unique, the candidate resistance parameter can be directly used as the target resistance parameter.

[0136] Specifically, in one embodiment, the first average distance between each candidate resistance parameter and the resistance parameter to be measured whose number of multi-bit errors is not 0 may be determined based on the following formula:

[0137]

[0138] in, Indicates A first average distance between the candidate resistance parameters and the resistance parameters to be tested whose number of multi-bit errors is not 0, Indicates the number of resistance parameters to be tested whose number of multi-bit errors is not 0, represents the dimension of the resistor parameters to be selected, Indicates The first of the resistor parameters to be selected Dimension value, Indicates The resistance parameter to be tested whose number of multi-bit errors is not zero Dimension value.

[0139] It should be noted that a resistor parameter actually contains sub-parameters corresponding to multiple memory pins. dimensional vector.

[0140] Specifically, in one embodiment, when the candidate resistance parameters are not unique, the second average distance between each candidate resistance parameter and the resistance parameter to be measured with the second smallest number of single-bit errors can be determined; the candidate resistance parameter with the largest second average distance is used as the candidate resistance parameter; when the candidate resistance parameters are not unique, the target resistance parameter is screened from the candidate resistance parameters based on the test signal acquisition results corresponding to each candidate resistance parameter.

[0141] The calculation principle of the second average distance is the same as the calculation principle of the first average distance, which will not be described in detail here.

[0142] Accordingly, when the candidate resistance parameter is unique, the candidate resistance parameter is directly used as the target resistance parameter.

[0143] Specifically, in one embodiment, when the candidate resistance parameters are not unique, the mean of the waveform characteristics corresponding to each candidate resistance parameter can be determined based on the test signal acquisition results corresponding to each candidate resistance parameter; the candidate resistance parameter with the smallest mean of the waveform characteristics is used as the target candidate resistance parameter; when the target candidate resistance parameter is not unique, the standard deviation of the waveform characteristics corresponding to each target candidate resistance parameter can be determined based on the test signal acquisition results corresponding to each target candidate resistance parameter; the target candidate resistance parameter with the smallest standard deviation of the waveform characteristics is used as the target resistance parameter.

[0144] When the target candidate resistance parameter with the smallest waveform characteristic standard deviation is not unique, any target candidate resistance parameter with the smallest waveform characteristic standard deviation may be used as the target resistance parameter.

[0145] Accordingly, when the target candidate resistance parameter is unique, the target candidate resistance parameter is directly used as the target resistance parameter.

[0146] Specifically, the present application undergoes multi-level screening to ensure that the target resistance parameters finally screened are the optimal resistance parameters.

[0147] Specifically, in one embodiment, when the target candidate resistor parameter with the smallest waveform characteristic standard deviation is not unique, considering that the resistance value of the resistor will change with temperature, the smaller the temperature coefficient, the better the stability of the resistor. Therefore, the target resistor parameter can be screened from several target candidate resistor parameters with the smallest waveform characteristic standard deviation according to the temperature coefficient of the resistor. The change in the resistance value of the resistor during long-term use will also affect the performance of the circuit. Therefore, the target resistor parameter can also be screened from several target candidate resistor parameters with the smallest waveform characteristic standard deviation according to the stability of the resistor.

[0148] On the basis of the above-mentioned embodiments, due to the lack of an automatic correction mechanism for the ODT value, after the product is designed, the ODT value determined by various tests will no longer be modified during the subsequent normal life cycle of the product. In the production process, the same ODT is used for products from the same batch or even different batches. In practice, even for products from the same batch, there are always many differences that are inevitable due to the existence of various random factors in the production process. For products with poor signal integrity design or working in harsh environments, they are more sensitive to such differences. At this time, it is necessary to quickly identify those individuals that have become defective products due to the use of common ODT values ​​and perform personalized configuration of ODT. Manual one-by-one checking is inefficient and there are subjective differences, and the read-write stress test takes a long time. A method that can quickly evaluate whether the ODT configuration of each product is optimal is needed to solve this problem. As an implementable method, on the basis of the above-mentioned embodiments, in one embodiment, after configuring the memory termination resistance according to the target resistance parameters, the method also includes:

[0149] Step 301, obtaining operation data of a product to be tested that deploys a memory termination resistor;

[0150] Step 303, determining the mean value and standard deviation of the waveform characteristics of the target resistance parameter on the product to be tested according to the operating data of the product to be tested;

[0151] Step 304, determining the inspection result of the product to be tested according to the size relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the size relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard.

[0152] Specifically, Figure 7 As shown, it is a flow chart of another exemplary memory termination resistor configuration method provided in an embodiment of the present application. The batch products on the production line will be configured using the parameters determined in the research and development stage, and then the corresponding indicators will be determined to be qualified according to the evaluation criteria. The same is true for ODT configuration. During production, the optimal ODT value determined in the research and development stage will be directly configured to each product. However, each product has certain differences to a greater or lesser extent, and there is always a certain probability that the optimal ODT value is not suitable for certain individual products. If the stress test results are used to determine whether the optimal ODT value is suitable for individual products, the cost is huge, which requires a rapid detection method to evaluate the adaptability of ODT.

[0153] Specifically, the optimal ODT value (target resistance parameter) is transmitted to the product under test, that is, the individual product is configured accordingly. The product under test is controlled to start the test program, which is a test program for cooperating with the signal acquisition device to sample the signal waveform. The signal acquisition device is controlled to sample the test signal, which is equivalent to only the configured optimal ODT value. The sampling data is obtained from the signal acquisition device and stored. The waveform characteristic value is calculated to obtain the mean value of the waveform characteristic to be tested and the standard deviation of the waveform characteristic to be tested. Determine whether the ODT value is adapted. If it is adapted, it is determined to be qualified, otherwise it is unqualified.

[0154] Specifically, in one embodiment, when the magnitude relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the magnitude relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard satisfy the following expressions, it is determined that the inspection result of the product to be tested is qualified:

[0155]

[0156]

[0157] in, Represents the mean value of the waveform characteristics to be measured, Indicates the waveform feature mean test standard, represents the first equalization parameter, Indicates the maximum value of the waveform characteristic mean corresponding to the resistance parameter to be tested when the number of multi-bit errors is 0, Indicates the mean value of the waveform characteristics corresponding to the target resistance parameter, Indicates the standard deviation of the waveform characteristics to be measured, Indicates the waveform characteristic standard deviation test standard, represents the second equalization parameter, Indicates the maximum value of the standard deviation of the waveform characteristics corresponding to the resistance parameter to be tested when the number of multi-bit errors is 0, Indicates the waveform characteristic standard deviation corresponding to the target resistance parameter. The first balance parameter and the second balance parameter are between 1 and 2.

[0158] The memory termination resistor configuration method provided in the embodiment of the present application is obtained by obtaining a sequence of resistance parameters to be tested; configuring the sequence of resistance parameters to be tested to the product to be tested, and performing a stress test on the configured product to be tested; in the process of stress testing the configured product to be tested, error information collection and test signal collection are performed on the product to be tested, and the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the sequence of resistance parameters to be tested and the corresponding error information collection results and test signal collection results are obtained; according to the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the sequence of resistance parameters to be tested, the target resistance parameters are screened in the sequence of resistance parameters to be tested, so as to configure the memory termination resistor according to the target resistance parameters. The method provided by the above scheme performs a series of stress tests and analyses on a variety of optional resistance parameters to be tested before configuring the memory termination resistor configuration, so as to screen the optimal target resistance parameters, thereby improving the accuracy of the memory termination resistor configuration results and laying a foundation for improving the performance and stability of the memory. Moreover, based on the corresponding equipment and automation program, the optimal ODT value can be automatically obtained according to the algorithm. On the one hand, this reduces manual intervention, reduces human resource consumption, and avoids subjective factors in judging the optimal ODT value; on the other hand, the optimal ODT value is selected based on comparisons in more dimensions, and the results are more reliable. A rapid detection method for the optimal ODT value for individual product adaptability is proposed, which does not require time-consuming stress testing and shortens the product inspection time. At the same time, judging the adaptability of the ODT value through the signal waveform, compared with stress testing, not only does it greatly shorten the inspection time, but the method is more direct and the results are more reliable.

[0159] An embodiment of the present application provides a memory termination resistor configuration device, which is used to execute the memory termination resistor configuration method provided in the above embodiment.

[0160] like Figure 8 , which is a schematic diagram of the structure of a memory termination resistor configuration device provided in an embodiment of the present application. The memory termination resistor configuration device 80 comprises: an acquisition module 801 , a test module 802 , a collection module 803 and a configuration module 804 .

[0161] Among them, the acquisition module is used to obtain the resistance parameter sequence to be tested; the test module is used to configure the resistance parameter sequence to be tested to the product to be tested, and to perform stress testing on the configured product to be tested; the acquisition module is used to collect error information and test signals of the product to be tested during the stress testing of the configured product to be tested, and obtain the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested; the configuration module is used to screen the target resistance parameters in the resistance parameter sequence to be tested according to the error information collection results and test signal collection results corresponding to each resistance parameter to be tested in the resistance parameter sequence to be tested, so as to configure the memory termination resistance according to the target resistance parameters.

[0162] Regarding the memory termination resistor configuration device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0163] The memory termination resistor configuration device provided in the embodiment of the present application is used to execute the memory termination resistor configuration method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0164] An embodiment of the present application provides an electronic device for executing the memory termination resistor configuration method provided in the above embodiment.

[0165] like Fig. 9 FIG. 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 90 includes: at least one processor 91 and a memory 92.

[0166] The memory stores computer-executable instructions; at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the memory termination resistor configuration method provided in the above embodiment.

[0167] The electronic device provided in the embodiment of the present application is used to execute the memory termination resistor configuration method provided in the above embodiment. Its implementation method and principle are the same and will not be repeated here.

[0168] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the memory termination resistor configuration method provided in any of the above embodiments is implemented.

[0169] The storage medium containing computer executable instructions provided in the embodiment of the present application can be used to store computer executable instructions of the memory termination resistor configuration method provided in the aforementioned embodiment. Its implementation method and principle are the same and will not be repeated here.

[0170] An embodiment of the present application provides a computer program product, including computer instructions, which are used to enable a computer to execute the memory termination resistor configuration method provided in the aforementioned embodiment.

[0171] The embodiments of the present application provide a computer program product that can be used to execute computer instructions of the memory termination resistor configuration method provided in the aforementioned embodiments. The implementation method and principle are the same and will not be repeated here.

[0172] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0173] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0174] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0175] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0176] A part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0177] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0178] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory termination resistor configuration method, characterized in that: include: Obtain the resistance parameter sequence to be measured; configuring the resistance parameter sequence to be tested to the product under test, and performing a stress test on the configured product under test; In the process of stress testing the configured product under test, error information collection and test signal collection are performed on the product under test to obtain error information collection results and test signal collection results corresponding to each resistance parameter under test in the resistance parameter sequence under test; According to the error information collection results and the test signal collection results corresponding to each resistance parameter to be measured in the resistance parameter sequence to be measured, a target resistance parameter is selected in the resistance parameter sequence to perform memory termination resistance configuration according to the target resistance parameter; The step of screening a target resistance parameter in the resistance parameter sequence according to the error information collection results and the test signal collection results corresponding to each resistance parameter to be measured in the resistance parameter sequence to be measured comprises: Determine the number of single-bit errors and the number of multi-bit errors corresponding to each resistance parameter to be measured in the resistance parameter sequence according to the error information collection result corresponding to each resistance parameter to be measured in the resistance parameter sequence; The resistance parameter to be tested with a multi-bit error number of 0 and a minimum single-bit error number is used as the resistance parameter to be selected; In the case that the candidate resistance parameters are not unique, selecting a target resistance parameter from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters; When the candidate resistance parameters are not unique, screening the target resistance parameters from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters includes: In the case that the resistance parameter to be selected is not unique, determining a first average distance between each of the resistance parameters to be selected and the resistance parameter to be measured whose number of multi-bit errors is not 0; Taking the candidate resistance parameter with the largest first average distance as the candidate resistance parameter; In the case that the candidate resistance parameters are not unique, selecting a target resistance parameter from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters; When the candidate resistance parameters are not unique, screening the target resistance parameters from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters includes: In the case where the candidate resistance parameters are not unique, determining a second average distance between each of the candidate resistance parameters and the resistance parameter to be measured having the second smallest number of single-bit errors; taking the candidate resistance parameter with the largest second average distance as a candidate resistance parameter; In the case that the candidate resistance parameters are not unique, selecting a target resistance parameter from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters; When the candidate resistance parameters are not unique, screening the target resistance parameters from the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters includes: In the case where the candidate resistance parameters are not unique, determining the waveform feature mean values ​​corresponding to the candidate resistance parameters according to the test signal acquisition results corresponding to the candidate resistance parameters; Taking the candidate resistance parameter with the smallest waveform feature mean as the target candidate resistance parameter; When the target candidate resistance parameter is not unique, determining the waveform characteristic standard deviation corresponding to each target candidate resistance parameter according to the test signal acquisition result corresponding to each target candidate resistance parameter; The target candidate resistance parameter with the smallest waveform characteristic standard deviation is used as the target resistance parameter.

2. The method according to claim 1, characterized in that In the process of performing stress testing on the configured product under test, error information collection and test signal collection are performed on the product under test to obtain error information collection results and test signal collection results corresponding to each resistance parameter under test in the resistance parameter sequence under test, including: During the stress test of the configured product under test, error information of the product under test is collected to determine the number of single-bit errors and the number of multi-bit errors corresponding to each resistance parameter under test in the resistance parameter sequence under test; For any of the resistance parameters to be measured in the resistance parameter sequence to be measured, according to the number of single-bit errors and the number of multi-bit errors corresponding to the resistance parameter to be measured, determining an error information collection result corresponding to the resistance parameter to be measured; During the process of stress testing the configured product under test, multiple test signal acquisitions are performed on the product under test to obtain multiple test signal waveform features corresponding to each resistance parameter under test in the resistance parameter sequence under test; For any resistance parameter to be measured in the resistance parameter sequence to be measured, a test signal acquisition result corresponding to the resistance parameter to be measured is determined according to a plurality of test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured.

3. The method according to claim 2, characterized in that The step of determining, for any resistance parameter to be measured in the resistance parameter sequence, a test signal acquisition result corresponding to the resistance parameter to be measured according to a plurality of test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured, comprises: For any of the resistance parameters to be measured in the resistance parameter sequence to be measured, according to a plurality of the test signal waveform characteristics and standard square wave signal characteristics corresponding to the resistance parameter to be measured, determine the square wave similarity corresponding to the test signal obtained by each signal acquisition; The test signal acquisition result corresponding to the resistance parameter to be measured is determined according to the square wave similarity corresponding to the test signal obtained by each signal acquisition.

4. The method according to claim 3, characterized in that Determining the square wave similarity corresponding to the test signal obtained by each signal acquisition according to the plurality of test signal waveform characteristics and the standard square wave signal characteristics corresponding to the resistance parameter to be measured includes: Based on the following formula, the square wave similarity corresponding to the test signal obtained from each signal acquisition is determined: in, represents the square wave similarity, represents the sequence length of the test signal waveform characteristics and the standard square wave signal characteristics, Indicates the first of the test signal waveform characteristics sequence values, Indicates the first characteristic of the standard square wave signal sequence values, , the test signal waveform characteristics and standard square wave signal characteristics include A sequence value.

5. The method according to claim 3, characterized in that: According to the square wave similarity corresponding to the test signal obtained by each signal acquisition, the test signal acquisition result corresponding to the resistance parameter to be measured is determined, including: According to the square wave similarity corresponding to the test signal obtained by each signal acquisition, the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured are determined; The test signal acquisition result corresponding to the resistance parameter to be measured is determined according to the waveform characteristic mean and the waveform characteristic standard deviation corresponding to the resistance parameter to be measured.

6. The method according to claim 5, characterized in that The method of determining the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured according to the square wave similarity corresponding to the test signal obtained by each signal acquisition includes: Based on the following formula, determine the waveform characteristic mean value corresponding to the resistance parameter to be measured: in, represents the mean value of the waveform characteristics, Indicates the number of times the test signal is collected. Indicates The square wave similarity corresponding to the test signal obtained by the secondary signal acquisition.

7. The method according to claim 5, characterized in that The method of determining the waveform characteristic mean and waveform characteristic standard deviation corresponding to the resistance parameter to be measured according to the square wave similarity corresponding to the test signal obtained by each signal acquisition includes: Based on the following formula, determine the waveform characteristic standard deviation corresponding to the resistance parameter to be measured: in, represents the standard deviation of the waveform characteristics, Indicates the number of times the test signal is collected. Indicates The square wave similarity corresponding to the test signal obtained by the signal acquisition, Indicates the waveform characteristic mean value corresponding to the resistance parameter to be measured.

8. The method according to claim 1, characterized in that The determining a first average distance between each of the candidate resistance parameters and the resistance parameter to be measured whose number of multi-bit errors is not 0 includes: Based on the following formula, a first average distance between each of the selected resistance parameters and the resistance parameter to be measured whose number of multi-bit errors is not 0 is determined: in, Indicates a first average distance between a candidate resistance parameter and the resistance parameter to be measured whose number of multi-bit errors is not 0, Indicates the number of resistance parameters to be tested whose number of multi-bit errors is not 0, represents the dimension of the resistor parameters to be selected, Indicates The first of the resistor parameters to be selected Dimension value, Indicates The resistance parameter to be tested whose number of multi-bit errors is not zero Dimension value.

9. The method according to claim 1, characterized in that: After configuring the memory termination resistance according to the target resistance parameter, the method further includes: Obtaining operation data of the product to be tested in which the memory termination resistor is deployed; Determine, according to the operating data of the product to be tested, a mean value of a waveform characteristic to be tested and a standard deviation of a waveform characteristic to be tested represented by the target resistance parameter on the product to be tested; The inspection result of the product to be tested is determined based on the size relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the size relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard.

10. The method according to claim 9, characterized in that Determining the inspection result of the product to be tested according to the size relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the size relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard includes: When the magnitude relationship between the waveform feature mean to be tested and the waveform feature mean inspection standard and the magnitude relationship between the waveform feature standard deviation to be tested and the waveform feature standard deviation inspection standard satisfy the following expressions, the inspection result of the product to be tested is determined to be qualified: in, Represents the mean value of the waveform characteristics to be measured, Indicates the waveform feature mean test standard, represents the first equalization parameter, Indicates the maximum value of the waveform characteristic mean corresponding to the resistance parameter to be tested when the number of multi-bit errors is 0, Indicates the mean value of the waveform characteristics corresponding to the target resistance parameter, Indicates the standard deviation of the waveform characteristics to be measured, Indicates the waveform characteristic standard deviation test standard, represents the second equalization parameter, Indicates the maximum value of the standard deviation of the waveform characteristics corresponding to the resistance parameter to be tested when the number of multi-bit errors is 0, Indicates the standard deviation of the waveform characteristics corresponding to the target resistance parameters.

11. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the method according to any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the method according to any one of claims 1 to 10 is implemented.

13. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the method according to any one of claims 1 to 10.

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