A process method for simplifying rewire of interconnect structures

Abstract

The application discloses a kind of process methods of simplifying interconnection structure rewiring, comprising the following steps: step one: preparing metal layer on chip;Step two: a plurality of step one obtained chip is covered to form a whole;Step three: additional insulating layer I is formed on the surface of semi-finished product obtained in step two;Step four: conductive layer is formed on the surface of insulating layer I;Step five: first layer RDL pattern is formed on the surface of conductive layer;Step six: RDL pattern layer is formed;Step seven: insulating layer II is formed on the surface of RDL pattern layer;Step eight: chip pad and / or RDL pattern layer are exposed;Step nine: on the basis of step eight, RDL layering process is carried out, and rewiring layer is formed, and the conduction between each RDL layer is realized by penetrating multiple metal layers at a time.The application realizes the conduction between each RDL layer by penetrating multiple metal layers at a time, realizes interconnection with each chip, realizes multilayer RDL wiring, and can effectively reduce process cost.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a process method for simplifying the redistribution of an interconnection structure. BACKGROUND

[0002] The preparation method of the normal RDL redistribution line comprises the following steps: using a sputtering seed layer technology and a photoetching technology to expose a photoresist layer on a substrate, modifying the pattern of the remaining bottom photoresist layer by means of drilling or etching, and finally performing metal plating to form an RDL wiring layer. The multilayer RDL redistribution line is operated in a repeated and stacked manner. This manufacturing method is a standard process flow in the packaging field, but the details of the preparation result in a high process cost of the redistribution layer. SUMMARY

[0003] To solve the technical problems in the prior art, the purpose of the application is to provide a process method for simplifying the redistribution of an interconnection structure.

[0004] To achieve the above purposes and achieve the above technical effects, the technical solution adopted by the application is as follows:

[0005] A process method for simplifying the redistribution of an interconnection structure, comprising the following steps:

[0006] Step one: preparing a metal layer on a chip;

[0007] Step two: covering a plurality of chips obtained in step one to form a whole, so that the plurality of chips are in the same plane;

[0008] Step three: adding an insulating layer I on the surface of the semi-finished product obtained in step two;

[0009] Step four: forming a conductive layer on the surface of the insulating layer I;

[0010] Step five: forming a first layer of RDL pattern on the surface of the conductive layer;

[0011] Step six: forming an RDL pattern layer;

[0012] Step seven: forming an insulating layer II on the surface of the RDL pattern layer;

[0013] Step eight: exposing the chip pad and / or the RDL pattern layer;

[0014] Step nine: based on step eight, performing an RDL layer adding process to form a redistribution layer, and realizing the conduction between the RDL layers by penetrating a plurality of metal layers at one time.

[0015] Further, in step one, the thickness of the metal layer is greater than 3 microns.

[0016] Further, in step two, the multiple chips obtained in step one are covered to form a whole by means of plastic sealing or sticking of an insulating film.

[0017] Further, in step three, the thickness of the insulating layer I is greater than 5 microns.

[0018] Further, in step four, the step of forming the conductive layer on the surface of the insulating layer I comprises:

[0019] First, a seed layer is formed on the surface of the insulating layer I, and then a conductive layer is formed on the seed layer by means of electroplating.

[0020] Further, the seed layer is made of Cu or Ti / Cu.

[0021] Further, in step five, the step of forming the first RDL pattern on the surface of the conductive layer comprises:

[0022] A process adhesive film is stuck on the surface of the conductive layer, the process adhesive film is a photoresist film, and then the first RDL pattern is formed by means of exposure and development, and the process adhesive film is removed in step six.

[0023] Further, in step six, the RDL pattern layer is formed by means of etching.

[0024] Further, in step eight, different kinds of interconnection layers are made by means of UV&CO2 opening, in combination with specific design and various collocations, so that the chip pad is exposed and / or the RDL pattern layer is exposed.

[0025] Compared with the prior art, the present application has the following beneficial effects:

[0026] The present application discloses a process method for simplifying the re-distribution of the interconnection structure, realizes the conduction between the RDL layers by penetrating multiple metal layers at one time, realizes the interconnection with the chips, realizes the multi-layer RDL wiring, and can effectively reduce the process cost. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The figure is a structural schematic diagram of step one of the present application.

[0028] Figure 2 The figure is a structural schematic diagram of step two of the present application.

[0029] Figure 3 The figure is a structural schematic diagram of step three of the present application.

[0030] Figure 4 The figure is a structural schematic diagram of step four of the present application.

[0031] Figure 5 The figure is a structural schematic diagram of step five of the present application.

[0032] Figure 6 Structure diagram of step six of the present application;

[0033] Figure 7 Structure diagram of step seven of the present application;

[0034] Figure 8 Structure diagram of step eight of embodiment 1 of the present application;

[0035] Figure 9 Structure diagram of step nine of embodiment 1 of the present application;

[0036] Figure 10 Structure diagram of step eight of embodiment 2 of the present application;

[0037] Figure 11 Structure diagram of step nine of embodiment 2 of the present application. DETAILED DESCRIPTION

[0038] The present application will be described in detail below so that the advantages and features of the present application can be more easily understood by those skilled in the art, and the scope of protection of the present application can be more clearly defined.

[0039] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0040] As shown in Figures 1-11 , the present application discloses a process method for simplifying the re-wiring of an interconnected structure, comprising the following steps:

[0041] Step one: as shown in Figure 1 , a metal layer 101 is prepared on a chip 100, with a thickness of 3 microns or more, and without damaging the functional layer of the chip body.

[0042] Step two: as shown in Figure 2 , a plurality of chips 100 obtained in step one are covered to form a whole by means of plastic encapsulation 200 or by pasting an insulating film, which is a multi-chip integration, without limitation on the thickness, so that the plurality of chips 100 are in the same plane, and the plastic encapsulation 200 is made of an insulating material.

[0043] Step three: as shown in Figure 3As shown, an insulating layer 1300 is added to the surface of the semi-finished product obtained in step two. The insulating layer 1300 can be added by rolling, spraying, spin coating, pressure bonding or a combination of one or more of the above. The insulating layer 1300 can be a photoresist film or a non-photoresist film, with a thickness greater than 5 microns, which can withstand interlayer insulation, ensure 100% coverage of the packaging effective area, and ensure the bonding force with the plastic packaging material 200.

[0044] Step four: as shown in Figure 4 , a seed layer is formed on the surface of the insulating layer 1300. The seed layer can be formed by chemical copper deposition or physical sputtering, and the material can be Cu, Ti / Cu, etc. A conductive layer 400 is then formed on the seed layer by electroplating process. The process is a full-surface copper electroplating process, and the thickness is determined according to the current density that the customer can bear.

[0045] Step five: as shown in Figure 5 , a process film 500 is attached to the surface of the conductive layer 400. The film is a photoresist film, and the first RDL pattern is formed by exposure and development.

[0046] Step six: as shown in Figure 6 , the RDL pattern layer 401 is formed by etching, and the process film 500 is removed by degumming, so that each chip is independent and not interconnected.

[0047] Step seven: as shown in Figure 7 , an insulating layer 2600 is formed on the surface of the RDL pattern layer 401. The insulating layer 2600 can be combined with the rewiring by coating or pressure bonding.

[0048] Step eight: as shown in Figure 8 or Figure 10 , different types of interconnection layers are made by UV&CO2 opening (the aperture is determined according to the size of the surface metal layer 101, and cannot be larger than the size of the surface metal layer 101), combined with specific design, various combinations, to make different types of interconnection layers, so that the chip pad is exposed and / or the RDL pattern layer 401 is exposed.

[0049] Step nine: based on step eight, the RDL layer increasing process is performed to form a rewiring layer 700, as shown in Figure 9 or 11. The RDL layers are connected by penetrating the multi-layer metal layer at one time, and the multi-layer RDL wiring is realized.

[0050] Embodiment 1

[0051] As shown in Figures 1-9 , a process for simplifying the rewiring of the interconnection structure includes the following steps:

[0052] Step 1: As Figure 1 As shown, a metal layer 101 is fabricated on the chip 100 without damaging the functional layers of the chip body. The metal layer 101 is made of copper.

[0053] Step Two: As Figure 2 As shown, multiple chips 100 obtained in step one are encapsulated using molding compound 200 to form a whole. This is multi-chip integration, and the thickness is not limited, so that multiple chips 100 are on the same plane.

[0054] Step 3: As Figure 3 As shown, an insulating layer I300 is formed on the surface of the semi-finished product obtained in step two by spraying. The insulating layer I300 is a photolithographic film with a thickness of 7 micrometers. The thickness must be able to withstand the interlayer isolation effect to ensure 100% coverage of the effective encapsulation area and to ensure the adhesion with the molding compound 200.

[0055] Step Four: As Figure 4 As shown, a seed layer is formed on the surface of insulating layer I300 by chemical copper plating, and a conductive layer 400 is formed on top of the seed layer by electroplating copper.

[0056] Step 5: As Figure 5 As shown, a process adhesive film 500 is attached to the surface of the conductive layer 400. This adhesive film is a photoresist film, and the first RDL pattern is formed by exposure and development.

[0057] Step Six: As Figure 6 As shown, the RDL pattern layer 401 is formed by etching, and the process adhesive film 500 is removed by stripping, so that each chip is independent, not interconnected, and rewired.

[0058] Step Seven: As Figure 7 As shown, an insulating layer II 600 is formed on the surface of the RDL pattern layer 401. The insulating layer II 600 is combined with the redistribution line by coating.

[0059] Step 8: As Figure 8 As shown, the interconnect layer is fabricated by UV & CO2 opening, which exposes the chip pad and the RDL pattern layer 401.

[0060] Step Nine: Based on Step Eight, perform the RDL layer addition process to form the redistribution layer 700, such as... Figure 9 As shown, the interconnection between each RDL layer is achieved by penetrating multiple metal layers in one go, realizing interconnection with each chip 100 at the bottom, and realizing multi-layer RDL wiring.

[0061] Example 2

[0062] like Figures 1-7A process method for simplifying the redistribution of the interconnection structure is shown in FIGS. 10-11, comprising the following steps:

[0063] Step one: as shown in FIG. 1, a metal layer 101 is prepared on the chip 100, which cannot harm the functional layer of the chip body, and the metal layer 101 is made of copper. Figure 1

[0064] Step two: as shown in FIG. 2, a plurality of chips 100 obtained in step one are covered to form a whole by using a plastic sealing material 200, which is a multi-chip integration, and the thickness is not limited, so that the plurality of chips 100 are in the same plane. Figure 2

[0065] Step three: as shown in FIG. 3, an insulating layer I 300 is formed on the surface of the semi-finished product obtained in step two by coating. Figure 3

[0066] Step four: as shown in FIG. 4, a seed layer is formed on the surface of the insulating layer I 300, and a conductive layer 400 is formed above the seed layer by using an electroplating process. Figure 4

[0067] Step five: as shown in FIG. 5, a process adhesive film 500 is attached to the surface of the conductive layer 400, which is a photoresist film, and a first RDL pattern is formed by exposure and development. Figure 5

[0068] Step six: as shown in FIG. 6, an RDL pattern layer 401 is formed by etching, and the process adhesive film 500 is removed by degumming, so that each chip is independent, not interconnected, and the redistribution is formed. Figure 6

[0069] Step seven: as shown in FIG. 7, an insulating layer II 600 is formed on the surface of the RDL pattern layer 401, and the insulating layer II 600 is combined with the redistribution by coating. Figure 7

[0070] Step eight: as shown in FIG. 8, an interconnection layer is made by UV&CO2 opening, so that the chip pad is exposed and the RDL pattern layer 401 is exposed. Figure 10

[0071] Step nine: based on step eight, an RDL layer increasing process is performed to form a redistribution layer 700, as shown in FIG. 9. The through-penetration of multiple metal layers is realized to realize the conduction between the RDL layers, realize the interconnection with the bottom chips 100, and realize the multi-layer RDL wiring. Figure 11

[0072] The remaining steps are the same as in example 1.

[0073] The parts or structures not specifically described in the present application can use existing technology or existing products, which are not described here.​​​​​​​​​

[0074] The above merely illustrates the embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process conversion, or direct or indirect application in other related technical fields, made by using the content of the present application, are also included in the patent protection scope of the present application.

Claims

1. A process for simplifying the re-routing of an interconnect structure, characterized by, The method comprises the following steps: Step 1: preparing a metal layer on a chip, wherein the thickness of the metal layer is greater than 3 microns; Step 2: covering the chips obtained in step 1 into a whole by means of plastic packaging or pasting an insulating film, so that the chips are in the same plane; Step 3: adding an insulating layer I on the surface of the semi-finished product obtained in step 2, wherein the thickness of the insulating layer I is greater than 5 microns; Step 4: forming a conductive layer on the surface of the insulating layer I; Step 5: forming a first layer of RDL pattern on the surface of the conductive layer; Step 6: forming an RDL pattern layer by etching; Step 7: forming an insulating layer II on the surface of the RDL pattern layer; Step 8: exposing the chip pad and the RDL pattern layer; Step 9: based on step 8, performing an RDL layering process to form a redistribution layer, and realizing the conduction among the metal layer, the RDL pattern layer and the redistribution layer by penetrating the metal layer and the RDL pattern layer at one time; In step 4, the step of forming the conductive layer on the surface of the insulating layer I comprises: firstly forming a seed layer on the surface of the insulating layer I, and then forming the conductive layer on the seed layer by electroplating; In step 5, the step of forming the first layer of RDL pattern on the surface of the conductive layer comprises: pasting a process adhesive film on the surface of the conductive layer, the process adhesive film being a photoresist film, and then forming the first layer of RDL pattern by exposure and development, wherein the process adhesive film is removed in step 6; In step 8, by means of UV&CO2 opening, combined with specific design and various collocations, different kinds of interconnection layers are made to expose the chip pad and the RDL pattern layer.

2. The process for re- routing of a simplified interconnect structure according to claim 1, wherein, The seed layer is made of Cu or Ti / Cu.

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