A semiconductor mask data graphics optimization method and system

Abstract

The present invention provides a semiconductor mask data graphics optimization method and system, which relates to the field of data processing technology. The method includes: obtaining semiconductor mask data, the semiconductor mask data includes a design graphic to be processed; constructing a photolithography imaging model; performing preliminary segmentation on the design graphic to be processed; inputting the design graphic after preliminary segmentation into the photolithography imaging model, and outputting the actual graphic after photolithography processing; calculating the EPE sensitivity of each segment of the graphic based on the difference between the design graphic and the actual graphic; performing fine segmentation on the design graphic after preliminary segmentation based on the EPE sensitivity; sensing the EPE, PV band area and CPU running time of the process variation of each segment of the graphic, controlling the movement of each segment of the graphic after fine segmentation, and performing graphic optimization on the design graphic. The present invention can improve the geometric accuracy of the pattern, improve the efficiency of graphic optimization, and reduce the difficulty of graphic optimization.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a semiconductor mask data graphic optimization method and system. Background Art

[0002] Mask lithography technology is a key process used to transfer tiny patterns onto wafers during semiconductor manufacturing. It uses an optical system to project the pattern on the mask onto the surface of the wafer coated with photoresist, and achieves pattern transfer through steps such as exposure, development, and etching.

[0003] However, in actual applications, due to the influence of optical proximity effects (OPE), graphic deformation and distortion often occur.

[0004] In the face of this problem, the commonly used method for optimizing mask patterns is the SRAF insertion method, i.e., sub-resolution auxiliary features. By adding auxiliary patterns (SRAFs), the resolution and process tolerance of the lithography pattern can be improved, thereby improving the deformation and distortion of the final wafer pattern.

[0005] However, the SRAF insertion method adds auxiliary graphics on the basis of the original mask graphics, which may further lead to an increase in edge placement errors. Adding auxiliary graphics without increasing the edge placement error requires a large amount of calculations, which takes too long to run, and has low graphics optimization efficiency. Sometimes, even after a large amount of calculations, it is difficult to find a suitable position to add auxiliary graphics without increasing the edge placement error, making optimization difficult. Summary of the invention

[0006] In order to solve the technical problems of the prior art, such as long running time, low graphics optimization efficiency and great optimization difficulty, the present invention provides a semiconductor mask data graphics optimization method and system.

[0007] The technical solution provided by the embodiment of the present invention is as follows:

[0008] First aspect:

[0009] An embodiment of the present invention provides a semiconductor mask data pattern optimization method, comprising:

[0010] S1: Acquire semiconductor mask data, wherein the semiconductor mask data includes a design pattern to be processed;

[0011] S2: build lithography imaging model;

[0012] S3: preliminary segmentation of the design graphics to be processed;

[0013] S4: inputting the design graphics after preliminary segmentation into the photolithography imaging model, and outputting the actual graphics after photolithography processing;

[0014] S5: Calculating the EPE sensitivity of each segment of the graphic based on the difference between the design graphic and the actual graphic;

[0015] S6: Based on the EPE sensitivity, finely segment the design graphics after the preliminary segmentation;

[0016] S7: Based on the process variation perception EPE of each segment of the graphics, the area of ​​the PV band region and the CPU running time, the movement of each segment of the graphics after fine segmentation is controlled to optimize the design graphics.

[0017] Second aspect:

[0018] An embodiment of the present invention provides a semiconductor mask data pattern optimization system, comprising:

[0019] processor;

[0020] A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the semiconductor mask data graphic optimization method as described in the first aspect is implemented.

[0021] The third aspect:

[0022] An embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the semiconductor mask data graphic optimization method as described in the first aspect is implemented.

[0023] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0024] In the present invention, the mask pattern is optimized by precisely adjusting the position of each segment of the pattern, which can reduce the process variation perception EPE, PV band area and CPU running time, improve the geometric accuracy of the pattern, enhance the efficiency of pattern optimization, and reduce the difficulty of pattern optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic flow chart of a semiconductor mask data pattern optimization method provided by an embodiment of the present invention;

[0027] Figure 2 A schematic structural diagram of a semiconductor mask data pattern optimization system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0029] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0030] In the embodiments of the present invention, "image" and "picture" can sometimes be used interchangeably. It should be noted that when the difference between them is not emphasized, the meanings they intend to express are the same. "of", "corresponding, relevant" and "corresponding" can sometimes be used interchangeably. It should be noted that when the difference between them is not emphasized, the meanings they intend to express are the same.

[0031] In the embodiments of the present invention, sometimes a subscript such as W1 may be written as a non-subscript such as W1. When the difference is not emphasized, the meanings to be expressed are the same.

[0032] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0033] Reference Manual Attached Figure 1 , showing a schematic flow chart of a semiconductor mask data graphic optimization method provided by an embodiment of the present invention.

[0034] The embodiment of the present invention provides a semiconductor mask data pattern optimization method, which can be implemented by a semiconductor mask data pattern optimization device, and the semiconductor mask data pattern optimization device can be a terminal or a server. The processing flow of the semiconductor mask data pattern optimization method can include the following steps:

[0035] S1: Obtain semiconductor mask data.

[0036] Among them, the semiconductor mask data includes the design graphics to be processed.

[0037] S2: Build a lithography imaging model.

[0038] In a possible implementation, the photolithography imaging model is specifically:

[0039]

[0040] Among them, I represents the actual graph, (x s ,y s ) represents the normalized spatial coordinate in the light source plane, J(x s ,y s ) means (x s ,y s ) at a certain point, H(x s ,y s ) means (x s ,y s ) is the point spread function of the lithography system, B(x s ,y s ) represents the mask diffraction function calculated based on the constant scattering coefficient assumption, M represents the design pattern, ⊙ represents the element-by-element multiplication operation, represents the convolution operation, J sum Indicates the total light intensity of the light source.

[0041] In the present invention, the light intensity distribution and system response in the actual lithography process can be accurately simulated through the lithography imaging model, the difference between the actual pattern and the designed pattern can be more accurately predicted and optimized, the edge placement error (EPE) and PV band can be more accurately determined, and the actual pattern can be ensured to be closer to the designed pattern.

[0042] Among them, edge placement error (EPE) refers to the deviation between the actual pattern edge formed and the designed target edge during the lithography process. EPE is a key indicator for measuring the accuracy of lithography patterns and has a direct impact on the final chip performance and manufacturing yield.

[0043] The PV band refers to the fluctuation range of the pattern edge position caused by process changes (such as exposure dose and focal length changes) during the photolithography process. The PV band reflects the stability and consistency of the pattern under different process conditions.

[0044] The specific calculation of edge placement error (EPE) and PV tape will be introduced in detail later.

[0045] S3: Perform preliminary segmentation on the design graphics to be processed.

[0046] In a possible implementation, S3 specifically includes sub-steps S301 to S303:

[0047] S301: Evenly segment the design graphics.

[0048] S302: further segmenting the graphic segments at the edge positions.

[0049] Optionally, a further segmentation method may be to divide the graphic segments evenly again.

[0050] It should be noted that the edge position is often the area with large errors in the photolithography process. Further segmentation of these areas helps to more finely control and optimize the edge position and improve the accuracy of the pattern.

[0051] S303: further segmenting the graphic segments whose distances to other graphics are less than a preset distance.

[0052] It should be noted that when the distance between patterns is close, the optical proximity effect will significantly affect the imaging quality of the pattern. By further segmenting, these areas can be controlled more finely to reduce the impact of the proximity effect.

[0053] In the present invention, the design pattern to be processed is preliminarily segmented, and multi-level optimization processing can be achieved through uniform segmentation, further segmentation of edge positions, and further segmentation of close-range patterns. This method not only simplifies the processing process and improves calculation efficiency, but also enhances the accuracy and consistency of the pattern, reduces manufacturing defects, and ultimately improves the overall photolithography pattern quality and manufacturing yield.

[0054] S4: Input the design graphics after preliminary segmentation into the photolithography imaging model, and output the actual graphics after photolithography processing.

[0055] S5: Based on the difference between the design pattern and the actual pattern, the EPE sensitivity of each segment of the pattern is calculated. In a possible implementation, the specific calculation method of the EPE sensitivity is:

[0056] δ i =e i -e i '

[0057] Among them, δ i represents the edge placement sensitivity, e i represents the geometric EPE of the i-th segment of the figure, e i ' j Represents the geometric EPE of the i-th segment of the graphic after it is offset outward by a preset distance.

[0058] Among them, those skilled in the art can set the size of the preset distance according to actual conditions, and the present invention does not limit it.

[0059] It should be noted that the sensitivity of each segment of the graphic to the edge placement error is determined by calculating the difference between the geometric EPE of the graphic after the offset and the original geometric EPE.

[0060] In the present invention, by calculating the EPE sensitivity of each segment of the graph, the areas most sensitive to EPE changes can be accurately identified. By focusing on optimizing these sensitive areas, the overall EPE can be significantly reduced.

[0061] Optionally, the geometric EPE is calculated as follows:

[0062]

[0063] Among them, e i represents the geometric EPE of the i-th segment of the graph, Indicates the actual edge position of the i-th segment of the graphic when the standard process parameters are used. Indicates the design graphic edge position of the i-th segment of the graphic when standard process parameters are used.

[0064] It should be noted that the geometric error of each segment of the graphic is determined by calculating the distance between the actual graphic edge position and the designed graphic edge position.

[0065] S6: Based on the EPE sensitivity, the design graphics after preliminary segmentation are finely segmented.

[0066] In a possible implementation, S6 specifically includes: further segmenting the graphic segments whose EPE sensitivity is greater than the preset sensitivity.

[0067] Among them, those skilled in the art can set the preset sensitivity according to actual conditions, and the present invention does not limit it.

[0068] In the present invention, the graphic segments that are most sensitive to edge placement errors can be identified through EPE sensitivity, and these areas often have the greatest impact on the overall pattern accuracy. These highly sensitive graphic segments are further segmented to make the optimization process more targeted, and resources can be concentrated to fine-tune key areas. At the same time, the graphic segments with high EPE sensitivity are refined and segmented, and the position and shape of each small segment can be adjusted more accurately, further reducing EPE and improving the overall accuracy of the pattern. Fine segmentation can effectively reduce the cumulative effect of errors in large segments of graphics, making the adjustment of each small segment more accurate, and ultimately reducing the overall error.

[0069] S7: Based on the process variation of each segment of the graphics, the EPE, PV band area and CPU running time are sensed, and the movement of each segment of the graphics after fine segmentation is controlled to optimize the design graphics.

[0070] In the present invention, the mask pattern is optimized by precisely adjusting the position of each segment of the pattern, which can reduce the process variation perception EPE, PV band area and CPU running time, improve the geometric accuracy of the pattern, enhance the efficiency of pattern optimization, and reduce the difficulty of pattern optimization.

[0071] In a possible implementation, S7 specifically includes sub-steps S701 and S702:

[0072] S701: Construct a graph movement objective function based on the process variation perception EPE, PV band area, number of violations, and CPU running time of each segment of the graph.

[0073] Optionally, the graphics movement objective function is specifically:

[0074] f=μ1E+μ2PV+μ3T

[0075] Among them, f represents the graph moving objective function, E represents the process variation perception EPE, PV represents the PV belt area, T represents the CPU running time, μ1 represents the weight coefficient of the process variation perception EPE, μ2 represents the weight coefficient of the PV belt area, and μ3 represents the weight coefficient of the CPU running time.

[0076] Among them, those skilled in the art can set the weight coefficient μ1 of process variation perception EPE, the weight coefficient μ2 of PV band area, and the weight coefficient μ3 of CPU running time according to actual conditions, and the present invention does not limit this.

[0077] In the present invention, the process variation perception EPE, PV band area, and CPU running time are integrated into one objective function, which can consider multiple optimization objectives at the same time, ensure the balance of various aspects, improve pattern accuracy and stability, enhance computing efficiency and manufacturing yield, and achieve precise adjustment.

[0078] Among them, process variation perception EPE refers to the geometric error between the edge of the actually formed pattern and the edge of the designed target, taking into account the influence of various process variations in the lithography process (such as exposure dose, focal length change, etc.). This EPE calculation method comprehensively evaluates the errors under different process conditions to more comprehensively reflect the accuracy and stability of the pattern in the actual manufacturing process.

[0079] Optionally, the process variation aware EPE is calculated as follows:

[0080]

[0081] Among them, E represents process variation perception EPE, e ij represents the geometric EPE of the i-th segment of the graph when the j-th process parameters are used, λ j It represents the weight coefficient of the jth process parameter, n represents the total number of graph segments, and m represents the total number of process parameters.

[0082] The weight coefficients of the process parameters are as follows:

[0083]

[0084] Among them, the weight coefficient is dynamically allocated according to the contribution of each process parameter to the total EPE, which can reflect the actual influence of each process condition.

[0085] In the present invention, by calculating the process variation perception EPE, the impact of process variation on the pattern can be more accurately reflected, and the optimization resources can be reasonably allocated to improve the optimization efficiency and effect. The dynamic adjustment of the weight coefficient ensures that the focus of the optimization process is clear, which helps to improve the accuracy and stability of the pattern, enhance the process robustness, and improve the manufacturing yield. This method provides a scientific, reasonable and effective solution for semiconductor pattern optimization.

[0086] The specific calculation method of the geometric EPE of the i-th segment of the graph when the j-th process parameters are used is:

[0087] Get the actual graphics when using the jth process parameter.

[0088] When the jth process parameter is used and the i-th segment of the actual graph exists, the calculation is performed in the following way:

[0089]

[0090] Among them, min means taking the minimum value, It represents the actual edge position of the i-th segment of the graphic when the j-th process parameters are used. represents the edge position of the design pattern of the i-th segment of the pattern when the j-th process parameters are used, e max Indicates the maximum geometric EPE.

[0091] In the present invention, by taking the minimum function, it can be ensured that the error value will not exceed the preset maximum geometric EPE, preventing individual excessive errors from affecting the overall evaluation.

[0092] When the jth process parameter is used and the i-th segment of the graph does not exist in the actual graph, the calculation is performed in the following way:

[0093] e ij =α j h i

[0094] Among them, α j represents the conversion coefficient of the jth process parameter, h i Indicates the minimum spacing between the i-th segment of the design graphic and other graphics.

[0095] In the present invention, when the i-th segment of the graphic does not exist in the actual graphic, the error is indirectly evaluated by calculating the minimum spacing between the segment of the graphic and other graphics multiplied by the conversion coefficient. The relative position of the graphic segment in the design graphic is taken into consideration, and a reasonable alternative evaluation method is provided to ensure the rationality and continuity of the evaluation result, making the optimization result more accurate.

[0096] Optionally, the PV band area is calculated as follows:

[0097] Get the actual pattern edge position under various process parameters.

[0098] The actual graphic edge positions under various process parameters are summarized to form the PV band area.

[0099] Calculate the PV band area by calculus.

[0100] In the present invention, by summarizing the edge positions under various process conditions to form a complete PV band area, the impact of process changes is fully reflected, and the calculus method is used to calculate the PV band area, which can accurately quantify the fluctuation range of the edge position and provide accurate evaluation indicators.

[0101] S702: With the goal of minimizing the graphic movement objective function, the moving direction and moving distance of each segment of the graphic are determined by a particle swarm optimization algorithm, and the design graphic is optimized.

[0102] Among them, Particle Swarm Optimization (PSO) is a global optimization algorithm based on swarm intelligence, which simulates the group behavior of bird flocks or fish schools, and finds the optimal solution to the problem through information sharing among individuals in the group.

[0103] Specifically, the inverse of the graph movement objective function is used as the fitness function of the particle swarm optimization algorithm.

[0104] Initialize the population, which contains multiple particles. Each particle represents a feasible graphic movement plan, which includes the movement direction and movement distance of each graphic segment.

[0105] Calculate the fitness of each particle.

[0106] Determine the individual optimal position and the global optimal position.

[0107]

[0108] Among them, V i t+1 represents the velocity of the ith particle at the t+1th iteration, V i trepresents the velocity of the i-th particle at the t-th iteration, ω represents the inertia weight factor, c1 represents the individual learning factor, c2 represents the global learning factor, r1 and r2 both represent random numbers between 0 and 1, P i t represents the individual optimal position of the i-th particle at the t-th iteration, represents the global optimal position of the i-th particle at the t-th iteration, represents the position of the i-th particle at the t-th iteration, represents the position of the i-th particle at the t+1th iteration.

[0109] It should be noted that by calculating the speed and position of the particles and combining the guidance of the individual optimal position and the global optimal position, it is possible to effectively balance the global search and the local search and quickly approach the optimal solution.

[0110] Optionally, the inertia weight factor ω is specifically:

[0111]

[0112] in, represents the inertia weight factor of the i-th particle at the t-th iteration, ω max Represents the maximum value of the inertia weight factor, ω min represents the minimum value of the inertia weight factor, e represents a natural constant, η represents a scaling parameter, and r3 represents a random number between 0 and 1. Represents the fitness change parameter of the i-th particle at the t-th iteration.

[0113] Among them, those skilled in the art can set the size of the scaling parameter η according to actual conditions, and the present invention does not limit it.

[0114] Furthermore, the fitness change parameter is specifically:

[0115]

[0116] in, represents the fitness change of the i-th particle at the t-th iteration, represents the fitness value of the i-th particle at the t-th iteration, Represents the fitness value of the i-th particle at the t-1th iteration.

[0117] In the present invention, the inertia weight factor gradually decreases with the increase of the number of iterations, so that the algorithm is more inclined to global search in the early stage and more inclined to local search in the later stage, which is helpful to find the global optimal solution and refine the local solution at the same time. At the same time, by introducing the fitness change parameter, the inertia weight factor can be dynamically adjusted according to the change of particle fitness, thereby improving the flexibility and adaptability of the algorithm. In the optimization process, it can more flexibly adapt to different optimization requirements, balance global search and local search, and improve the optimization effect and calculation efficiency.

[0118] Recalculate the fitness of each particle.

[0119] When the fitness of the current particle is better than the individual optimal solution of the particle itself, the individual optimal solution of the particle itself is updated. When the fitness of the current particle is worse than the individual optimal solution of the particle itself, the individual optimal solution of the particle itself is updated with a certain replacement probability. When the fitness of the current particle is better than the global optimal solution, the global optimal solution is updated.

[0120] It should be noted that when the fitness of the current particle is better than the individual optimal solution of the particle itself, the individual optimal solution is directly updated. This adaptive update mechanism can ensure that the particle swarm promptly follows the better solution found in the search process and improve the convergence speed of the algorithm. When the fitness of the current particle is worse than the individual optimal solution of the particle itself, the individual optimal solution is updated with a certain replacement probability. This mechanism introduces a certain degree of randomness to prevent the individual optimal solution from falling into the local optimum, thereby enhancing the global exploration capability.

[0121] Determine whether the maximum number of iterations has been reached. If so, output the lamp installation solution represented by the particle with the highest fitness value as the optimal lamp installation solution. Otherwise, return to continue iterating.

[0122] Among them, the replacement probability is specifically:

[0123]

[0124] Among them, P represents the replacement probability, e represents the natural constant, δ() represents the fitness function, and C t represents the temperature at the tth iteration.

[0125] Among them, the temperature is updated according to the following formula:

[0126] T i+1 =εT i

[0127] Where ε represents the temperature drop coefficient, T i+1 represents the temperature at the i+1th iteration, T i represents the temperature at the i-th iteration.

[0128] It should be noted that when the temperature is higher, it is easier to accept worse solutions, thereby increasing the chance of escaping the local optimum. As the number of iterations increases, the temperature gradually decreases, allowing the algorithm to perform more global searches in the early stages and gradually focus on local searches in the later stages, thereby improving the optimization effect.

[0129] The specific temperature reduction coefficient is:

[0130]

[0131] Among them, A1 represents the cooling oscillation factor of the first half cycle, B1 represents the cooling floating factor of the first half cycle, A2 represents the cooling oscillation factor of the second half cycle, and B2 represents the cooling floating factor of the second half cycle.

[0132] It should be noted that by dividing the cooling process into two cycles, the temperature changes in different stages can be finely controlled to adapt to different optimization requirements and search strategies. In each cycle, the temperature change not only considers exponential decay, but also combines sinusoidal oscillation and floating factors to make the temperature change smoother and more flexible. At the same time, the sinusoidal oscillation characteristics introduce a certain temperature fluctuation, avoiding premature convergence, increasing the diversity of the solution space, and reducing the risk of falling into the local optimum.

[0133] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0134] In the present invention, the mask pattern is optimized by precisely adjusting the position of each segment of the pattern, which can reduce the process variation perception EPE, PV band area and CPU running time, improve the geometric accuracy of the pattern, enhance the efficiency of pattern optimization, and reduce the difficulty of pattern optimization.

[0135] Reference Manual Attached Figure 2 , showing a schematic structural diagram of a semiconductor mask data graphic optimization system provided by the present invention.

[0136] The present invention further provides a semiconductor mask data pattern optimization system 20, which is applied to the semiconductor mask data pattern optimization method described above, and comprises:

[0137] Processor 201;

[0138] The memory 202 stores computer-readable instructions, and when the computer-readable instructions are executed by the processor 201, the semiconductor mask data pattern optimization method described in the method embodiment is implemented.

[0139] The semiconductor mask data pattern optimization system 20 provided by the present invention can execute the above-mentioned semiconductor mask data pattern optimization method and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate on it.

[0140] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0141] In the present invention, the mask pattern is optimized by precisely adjusting the position of each segment of the pattern, which can reduce the process variation perception EPE, PV band area and CPU running time, improve the geometric accuracy of the pattern, enhance the efficiency of pattern optimization, and reduce the difficulty of pattern optimization.

[0142] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0143] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0144] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0145] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0146] In the present invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0147] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0148] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0149] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0150] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0151] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0152] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0153] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0154] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the semiconductor mask data graphic optimization method as described in the method embodiment.

[0155] A computer-readable storage medium provided by the present invention can implement the steps and effects of the semiconductor mask data graphic optimization method of the above method embodiment. To avoid repetition, the present invention will not go into details.

[0156] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0157] In the present invention, the mask pattern is optimized by precisely adjusting the position of each segment of the pattern, which can reduce the process variation perception EPE, PV band area and CPU running time, improve the geometric accuracy of the pattern, enhance the efficiency of pattern optimization, and reduce the difficulty of pattern optimization.

[0158] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0159] There are a few points to note:

[0160] (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention, and other structures may refer to the general design.

[0161] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of the layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0162] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0163] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A semiconductor mask data pattern optimization method, characterized in that: include: S1: Acquire semiconductor mask data, wherein the semiconductor mask data includes a design pattern to be processed; S2: build lithography imaging model; S3: preliminary segmentation of the design graphics to be processed; S4: inputting the design graphics after preliminary segmentation into the photolithography imaging model, and outputting the actual graphics after photolithography processing; S5: Calculating the EPE sensitivity of each segment of the graphic based on the difference between the design graphic and the actual graphic; S6: Based on the EPE sensitivity, finely segment the design graphics after the preliminary segmentation; S7: Based on the process variation perception EPE of each segment of the graphics, the area of ​​the PV band region and the CPU running time, the movement of each segment of the graphics after fine segmentation is controlled to optimize the design graphics.

2. The semiconductor mask data pattern optimization method according to claim 1, characterized in that: The photolithography imaging model is specifically: Among them, I represents the actual graph, (x s ,y s ) represents the normalized spatial coordinate in the light source plane, J(x s ,y s ) means (x s ,y s ) at a certain point, H(x s ,y s ) means (x s ,y s ) is the point spread function of the lithography system, B(x s ,y s ) represents the mask diffraction function calculated based on the constant scattering coefficient assumption, M represents the design pattern, ⊙ represents the element-by-element multiplication operation, represents the convolution operation, J sum Indicates the total light intensity of the light source.

3. The semiconductor mask data pattern optimization method according to claim 1, characterized in that: The S3 specifically includes: S301: Evenly segmenting the design pattern; S302: further segmenting the graphic segments at the edge positions; S303: further segmenting the graphic segments whose distances to other graphics are less than a preset distance.

4. The semiconductor mask data pattern optimization method according to claim 1, characterized in that: The specific calculation method of the EPE sensitivity is: δ i =and i -And i ' Among them, δ i represents the edge placement sensitivity, e i represents the geometric EPE of the i-th segment of the figure, e i ' j It represents the geometric EPE after the i-th segment of the graphic is offset outward by a preset distance; The geometric EPE is calculated as follows: Among them, e i represents the geometric EPE of the i-th segment of the graph, Indicates the actual edge position of the i-th segment of the graphic when the standard process parameters are used. Indicates the design graphic edge position of the i-th segment of the graphic when standard process parameters are used.

5. The semiconductor mask data pattern optimization method according to claim 1, characterized in that: The S6 is specifically: The graphic segments whose EPE sensitivity is greater than the preset sensitivity are further segmented.

6. The semiconductor mask data pattern optimization method according to claim 1, characterized in that: The S7 specifically includes: S701: constructing a graph movement objective function based on the process variation perception EPE, PV band area, violation count, and CPU running time of each segment of the graph; S702: With the goal of minimizing the graphic movement objective function, the moving direction and moving distance of each segment of the graphic are determined by a particle swarm optimization algorithm, and the graphic of the designed graphic is optimized.

7. The semiconductor mask data pattern optimization method according to claim 6, characterized in that: The graphics movement objective function is specifically: f=μ1E+μ2PV+μ3T Among them, f represents the graph moving objective function, E represents the process variation perception EPE, PV represents the PV belt area, T represents the CPU running time, μ1 represents the weight coefficient of the process variation perception EPE, μ2 represents the weight coefficient of the PV belt area, and μ3 represents the weight coefficient of the CPU running time.

8. The semiconductor mask data pattern optimization method according to claim 7, characterized in that: The specific calculation method of the process variation perception EPE is as follows: Among them, E represents the process variation perception EPE, e ij represents the geometric EPE of the i-th segment of the graph when the j-th process parameters are used, λ j represents the weight coefficient of the jth process parameter, n represents the total number of graph segments, and m represents the total number of process parameters; The weight coefficients of the process parameters are specifically: The specific calculation method of the geometric EPE of the i-th segment of the graph when the j-th process parameter is adopted is: Obtain the actual graphics when the jth process parameter is adopted; When the jth process parameter is used and the i-th segment of the actual graph exists, the calculation is performed in the following way: Among them, min means taking the minimum value, It represents the actual edge position of the i-th segment of the graphic when the j-th process parameters are used. represents the edge position of the design pattern of the i-th segment of the pattern when the j-th process parameters are used, e max Indicates the maximum geometric EPE; When the jth process parameter is used and the i-th segment of the graph does not exist in the actual graph, the calculation is performed in the following way: e ij =a j h i Among them, α j represents the conversion coefficient of the jth process parameter, h i Indicates the minimum spacing between the i-th segment of the design graphic and other graphics.

9. The semiconductor mask data pattern optimization method according to claim 6, characterized in that: The calculation method of the PV band area is specifically as follows: Obtain the actual pattern edge position under various process parameters; The actual pattern edge positions under various process parameters are summarized to form the PV band area; Calculate the PV band area by calculus.

10. A semiconductor mask data pattern optimization system, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the semiconductor mask data graphic optimization method according to any one of claims 1 to 9 is implemented.

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