Multifunctional programmable data management system and electronic equipment

Abstract

The present application provides a multifunctional programmable data management system and electronic device, the data management system includes: an AHB bus, a main core unit, a ROM unit and a secondary core unit. The main core unit is connected to the AHB bus; the ROM unit is connected to the AHB bus, the ROM unit stores the main core program and the secondary core program, the secondary core program is stored at a preset designated address on the ROM unit; the secondary core unit is connected to the AHB bus, and the secondary core unit stores a preset designated address. The secondary core unit reads the ROM unit through the AHB bus, reads and caches the secondary core program according to the preset designated address, and executes data transmission or data processing functions according to the secondary core program.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a multifunctional programmable data management system and electronic equipment. Background Art

[0002] At present, in embedded systems, the Direct Memory Access (DMA) module is a core component responsible for efficiently transferring data between different memories without CPU intervention, thereby significantly improving the overall performance and efficiency of the system. However, the traditional DMA design has obvious limitations, especially in the application of microcontroller units (MCUs). Although the DMA module can effectively reduce the CPU burden and increase the data transmission speed, it occupies a relatively large area on the MCU chip, which not only limits the further improvement of MCU integration, but also increases the cost. At the same time, the function of traditional DMA is too single, limited to data handling, and lacks the ability to process data in real time. Summary of the invention

[0003] The present application provides a multifunctional programmable data management system and electronic device, which are used to replace DMA and realize data transmission function and data processing function at the same time.

[0004] In a first aspect, an embodiment of the present application provides a multifunctional programmable data management system, the data management system comprising:

[0005] AHB (Advanced High performance Bus, AHB) bus;

[0006] A main core unit, the main core unit is connected to the AHB bus;

[0007] A ROM unit, wherein the ROM unit is connected to the AHB bus, the ROM unit stores a main core program and a secondary core program, and the secondary core program is stored at a preset designated address on the ROM unit;

[0008] A secondary core unit, the secondary core unit is connected to the AHB bus, and the secondary core unit stores the preset designated address;

[0009] The sub-core unit performs a read operation on the ROM unit through the AHB bus, reads and caches the sub-core program according to the preset designated address, and executes data transmission or data processing functions according to the sub-core program.

[0010] In some embodiments, the sub-core unit comprises:

[0011] a first buffer memory, wherein a first end of the first buffer memory is connected to the AHB bus, and the first buffer memory is used to cache the secondary core program;

[0012] A secondary core, wherein a first end of the secondary core is connected to a second end of the first buffer memory, the secondary core is used to read and execute the secondary core program cached in the first buffer memory, a second end of the secondary core is connected to the AHB bus, and the second end of the secondary core is an output end;

[0013] A first function register, wherein a first end of the first function register is connected to the secondary core, a second end of the first function register is connected to the AHB bus, and the first function register is used to provide a clock variable and an address variable to the secondary core, wherein the address variable is a variable of the specified address.

[0014] In some embodiments, the number of bits of the AHB bus is a first number, the number of bits of the first end of the secondary core is a second number, and the number of bits of the second end of the secondary core is expanded to the first number;

[0015] The number of bits at the first end of the first buffer memory is the first number of bits, and the number of bits at the second end of the first buffer memory is the second number of bits.

[0016] In some embodiments, the main core unit includes:

[0017] a second buffer memory, wherein a first end of the second buffer memory is connected to the AHB bus;

[0018] A main core, a first end of the main core is connected to a second end of the second buffer memory, and a second end of the main core is connected to the AHB bus.

[0019] In some embodiments, the data management system further includes: a slave unit and a RAM unit, and the slave unit includes: an IAP unit, an I / O unit, other peripheral units and a second function register.

[0020] In some embodiments, the main core unit and the secondary core unit perform data exchange by reading and writing the RAM unit or the second function register.

[0021] In a second aspect, an embodiment of the present application provides a chip, which includes a multifunctional programmable data management system as described in any one of the embodiments of the present application.

[0022] The embodiment of the present application provides a multifunctional programmable data management system, which includes: an AHB bus, a main core unit, a ROM unit, and a secondary core unit. The main core unit is connected to the AHB bus; the ROM unit is connected to the AHB bus, the ROM unit stores the main core program and the secondary core program, and the secondary core program is stored at a preset designated address on the ROM unit; the secondary core unit is connected to the AHB bus, and the secondary core unit stores a preset designated address; wherein the secondary core unit reads the ROM unit through the AHB bus, reads and caches the secondary core program according to the preset designated address, and executes data transmission or data processing functions according to the secondary core program. In the above data management system, the main core unit reads the main core program normally, and the secondary core unit only reads the secondary core program at the preset designated address of the ROM unit. The secondary core unit can read and cache the secondary core program, so that when the main core unit and the secondary core unit access the ROM unit, the competition generated on the AHB bus is reduced, thereby achieving the execution efficiency of the main core program without slowing down. At the same time, the secondary core unit can also realize the data transmission function and the data processing function respectively by executing the secondary core program. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0024] Figure 1 A schematic block diagram of a first data management system provided in an embodiment of the present application;

[0025] Figure 2 A schematic block diagram of a second data management system provided in an embodiment of the present application;

[0026] Figure 3 A schematic flow chart of a data processing method provided in an embodiment of the present application.

[0027] Description of reference numerals:

[0028] 100. Data management system; 11. AHB bus; 12. Main core unit; 121. Second buffer memory; 122. Main core; 13. ROM unit; 14. Sub-core unit; 141. First buffer memory; 142. Sub-core; 143. First function register; 15. Slave unit; 151. IAP unit; 152. I / O unit; 153. Other peripheral units; 154. Second function register; 16. RAM unit. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0031] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0032] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] See also Figure 1 , Figure 1 is a schematic block diagram of a first data management system provided by an embodiment of the present application. Figure 1 As shown, the data management system 100 includes: an AHB bus 11 , a main core unit 12 , a ROM unit 13 and a sub-core unit 14 .

[0034] The main core unit 12 is connected to the AHB bus 11. The ROM unit 13 is connected to the AHB bus 11. The ROM unit 13 stores the main core program and the secondary core program. The secondary core program is stored at a preset designated address on the ROM unit 13. The secondary core unit 14 is connected to the AHB bus 11. The secondary core unit 14 stores a preset designated address. The secondary core unit 14 performs a read operation on the ROM unit 13 through the AHB bus 11, reads and caches the secondary core program according to the preset designated address, and executes data transmission or data processing functions according to the secondary core program.

[0035] Exemplarily, the AHB bus 11 includes a master end and a slave end, and the main core unit 12 and the secondary core unit 14 in the embodiment of the present application are both arranged at the master end. The main core unit 12 reads the program instructions of the main core program from the ROM unit 13 through the AHB bus 11, and then outputs the control AHB bus 11 to operate other units of each slave end. The secondary core unit 14 needs to be modified in bit number to adapt to the AHB bus 11.

[0036] Based on the original ARM MCU architecture, the area occupied by the sub-core unit 14 is not much different from that occupied by DMA. The sub-core unit 14 can completely replace DMA to realize the data transfer function of DMA, and can also process the data.

[0037] The sub-core program includes a first program, a second program, and a third program. The first program is used to implement data transmission, the second program is used to implement data processing, and the third program is used to implement peripheral control. The sub-core unit 14 executes different programs to implement different functions. Therefore, the sub-core unit 14 can replace DMA and increase the function of data processing.

[0038] When storing the secondary core program, the ROM unit 13 uses a specially designated storage area for storage, and the storage address of the area is a preset designated address, for example, the storage address of the last 2Kb of the ROM unit 13. The secondary core program is written in C language or assembly language.

[0039] The embodiment of the present application provides a multifunctional programmable data management system, which includes: an AHB bus, a main core unit, a ROM unit, and a secondary core unit. The main core unit is connected to the AHB bus; the ROM unit is connected to the AHB bus, the ROM unit stores the main core program and the secondary core program, and the secondary core program is stored at a preset designated address on the ROM unit; the secondary core unit is connected to the AHB bus, and the secondary core unit stores a preset designated address; wherein the secondary core unit reads the ROM unit through the AHB bus, reads and caches the secondary core program according to the preset designated address, and executes data transmission or data processing functions according to the secondary core program. In the above data management system, the main core unit reads the main core program normally, and the secondary core unit only reads the secondary core program at the preset designated address of the ROM unit. The secondary core unit can read and cache the secondary core program, so that when the main core unit and the secondary core unit access the ROM unit, the competition generated on the AHB bus is reduced, thereby achieving the execution efficiency of the main core program without slowing down. At the same time, the secondary core unit can also realize the data transmission function and the data processing function respectively by executing the secondary core program.

[0040] In order to more clearly introduce the technical solution of the present application, the technical solution of the present application will be introduced through specific embodiments below. It should be noted that the specific embodiments are used to expand the technical solution of the present application, but are not intended to limit the present application.

[0041] In some embodiments, for example, see Figure 2 , Figure 2 FIG. 1 shows a schematic block diagram of a second data management system provided in an embodiment of the present application. Figure 2 As shown, the sub-core unit 14 includes: a first buffer memory 141, a sub-core 142 and a first function register 143. The first end of the first buffer memory 141 is connected to the AHB bus 11, and the first buffer memory 141 is used to cache the sub-core program. The first end of the sub-core 142 is connected to the second end of the first buffer memory 141, and the sub-core 142 is used to read and execute the sub-core program cached in the first buffer memory 141. The second end of the sub-core 142 is connected to the AHB bus 11, and the second end of the sub-core 142 is an output end. The first end of the first function register 143 is connected to the sub-core 142, and the second end of the first function register 143 is connected to the AHB bus 11. The first function register 143 is used to provide clock variables and address variables to the sub-core 142, and the address variable is a variable of a specified address.

[0042] Exemplarily, the secondary core 142 is a small-scale core, specifically a small-scale core (16 / 8 / 4-bit core) that has been modified by bit expansion, for example, an 8051 core. The 8051 core needs to be modified to expand the control lines of the 8051 core to 32 bits to adapt to the 32-bit AHB bus 11.

[0043] The first buffer memory 141 is a 32-bit input and 16 / 8 / 4-bit output cache (high-speed cache memory). The main function of the first buffer memory 141 is to collect and save program data from the ROM, and then convert it into 8-bit data from the output port to the 8051 core as an instruction.

[0044] The first function register 143 is a Special Function Register (SFR) for providing various parameters to the sub-core unit 14. The first function register 143 provides clock variables, address variables, etc. to the 8051 core.

[0045] By using the cache program, when the main core unit 12 and the secondary core unit 14 access the ROM, the competition on the AHB bus 11 is reduced, so that the execution efficiency of the main core unit 12 executing the main core program is not slowed down.

[0046] In some embodiments, the number of bits of the AHB bus 11 is the first number, the number of bits of the first end of the sub-core 142 is the second number, and the number of bits of the second end of the sub-core 142 is expanded to the first number; the number of bits of the first end of the first buffer memory 141 is the first number, and the number of bits of the second end of the first buffer memory 141 is the second number.

[0047] Exemplarily, the first digit is 32 bits and the second digit is 8 bits.

[0048] In some embodiments, Figure 2 As shown, the main core unit 12 includes: a second buffer memory 121 and a main core 122. The first end of the second buffer memory 121 is connected to the AHB bus 11. The first end of the main core 122 is connected to the second end of the second buffer memory 121, and the second end of the main core 122 is connected to the AHB bus 11.

[0049] Exemplarily, the main core 122 is an ARM core, and the second buffer memory 121 is a Cache. The ARM core reads program instructions from the ROM unit 13 through the second buffer memory 121, and then outputs the AHB bus 11 to operate other modules on each AHB bus 11.

[0050] In some embodiments, Figure 2 As shown, the data management system 100 further includes: a slave unit 15 and a RAM unit 16 , and the slave unit 15 includes: an IAP unit 151 , an I / O unit 152 , other peripheral units 153 and a second function register 154 .

[0051] In some embodiments, the main core unit 12 and the secondary core unit 14 perform data exchange by reading and writing the RAM unit 16 or the second function register 154 .

[0052] Exemplarily, the secondary core unit 14 can read and write the slave units 15 of each AHB bus 11 through the AHB bus 11 to implement the data transfer function of DMA, and can realize the function of simulating peripherals by controlling the flipping of the I / O unit 152 .

[0053] Specifically, the main core unit 12 writes the control instruction into the RAM or the second function register 154 through the AHB bus 11. The sub-core unit 14 reads the control instruction written into the RAM or the second function register 154, and controls the input and output of the I / O unit 152 according to the control instruction, thereby realizing the functions of simulating peripherals such as UART and SPI.

[0054] See also Figure 3 , Figure 3 A schematic flow chart of a data processing method provided in an embodiment of the present application. Figure 3As shown, the data processing method is applied to the sub-kernel 142, and the specific steps of the data processing method include: S101-S106.

[0055] S101 . According to a preset block specification, a database to be transmitted is divided into blocks to obtain a plurality of data blocks.

[0056] Exemplarily, the data to be processed is divided according to a predetermined block size, for example, the block size is 1 Mb, to obtain multiple data blocks, each of which is an independent processing unit for subsequent compression and encryption processing.

[0057] S102, performing redundancy analysis on each data block to obtain a redundancy value corresponding to each data block, and performing entropy calculation on each data block to obtain an entropy value.

[0058] Exemplarily, entropy calculation is performed on the data block first. In the process of entropy calculation, it is necessary to count the symbol type and occurrence probability of the symbols in the data block, and determine the entropy value according to the symbol type, occurrence probability and a preset entropy calculation formula. The preset entropy calculation formula is specifically:

[0059] ;

[0060] in, is the entropy value of the ith data block, is the probability of occurrence of the kth symbol type in the ith data block, and is the number of symbol types.

[0061] For m types of symbols, the maximum entropy of the data block is Occurs when all symbols have equal probability of appearing. This means that the data blocks are completely random and have no redundancy. The redundancy value can be calculated using the following formula:

[0062] ;

[0063] in, is the redundancy value of the i-th data block.

[0064] S103: When the redundancy value is greater than a preset first threshold value and the entropy value is greater than a preset second threshold value, compress each data block using a preset dictionary compression algorithm to obtain a compressed block.

[0065] For example, if the redundancy value of the data block is high, a dictionary-based compression algorithm (such as LZW) is selected; if the entropy value of the data block is low, an entropy coding algorithm (such as Huffman coding) is selected. When the redundancy value of the data block is high and the entropy value is also high, the preset dictionary compression algorithm is used to compress each data block.

[0066] Through the above settings, the main core unit has more time to do other things and has a faster running speed. At the same time, the number of peripherals can be reduced, and the problems of difficult use, high system complexity, large area and uneconomical use of dual main cores can be avoided.

[0067] The embodiment of the present application provides a preset dictionary compression algorithm, and the preset dictionary compression algorithm includes: S1031-S1036.

[0068] S1031. Count the occurrence frequency of each symbol type in the data block, encode the symbol type according to the occurrence frequency to obtain the symbol code, and hierarchically process the first compression dictionary according to the occurrence frequency to obtain a high-frequency symbol set and a low-frequency symbol set.

[0069] First, the frequency of occurrence of symbol types is counted for each data block to generate the first compression dictionary. The first compression dictionary contains all symbol types and their corresponding symbol codes that appear in the data block. At the same time, according to the frequency of occurrence of the symbol type, the first compression dictionary is divided into a high-frequency symbol set and a low-frequency symbol set. The high-frequency symbol set contains those symbols that appear more frequently in the data block, while the low-frequency symbol set contains symbols that appear less frequently. This step provides the basis for subsequent multi-level compression and enables the compression process to more effectively process data of different frequencies.

[0070] S1032: Use a high-frequency symbol set to replace the data block to obtain first compressed data.

[0071] Exemplarily, after the first compression dictionary is generated, the high-frequency symbol set therein is used to perform the first stage of compression processing on the data block. In this stage, all symbol types belonging to the high-frequency symbol set will be replaced with their corresponding codes to generate the first compressed data. This step reduces the size of the data block by replacing the high-frequency symbols that occupy a larger data space with shorter codes, forming a compressed data block, laying the foundation for subsequent deeper compression.

[0072] S1033, counting the types of low-frequency symbols that have not been replaced or compressed in the first compressed data, updating the first compression dictionary according to the types of low-frequency symbols, generating a second compression dictionary, and performing secondary compression and replacement processing on the first compressed data using the second compression dictionary to obtain second compressed data.

[0073] Exemplarily, the first compressed data is analyzed, low-frequency symbols that are not replaced or compressed are counted, and the initial dictionary is updated and a new dictionary is generated according to the occurrence of these low-frequency symbols. Then, the first compressed data is subjected to secondary compression processing using the updated dictionary to generate secondary compressed data. In this step, the dynamic adjustment of the dictionary ensures that the compression process can adapt to new features in the data block, further reducing the size of the data.

[0074] S1034, loop step S1033 to obtain the Nth compression dictionary and the Nth compressed data, where N is the number of loops.

[0075] Exemplarily, the second compressed data is further recursively compressed in multiple stages. According to the data characteristics of the second compressed data, the second compression dictionary is continuously updated to generate a new dictionary, and the updated dictionaries are sequentially applied to further compress the data. The size of the data block after each recursive compression works together with the previous dictionary to ensure the improvement of the compression rate and the adaptability of the dictionary. Through this recursive method, the algorithm can handle complex structures in the data and improve the compression efficiency.

[0076] S1035 , merging the first compressed data into the Nth compression dictionary to generate a final compression dictionary, and using the final compression dictionary to process the Nth compressed data to generate final compressed data.

[0077] After multi-level recursive compression, all generated dictionaries are globally optimized, and the first, second to Nth dictionaries are merged to generate the final compressed dictionary. By eliminating redundant symbols and optimizing the encoding length, the final dictionary further improves the effectiveness of data compression while maintaining the compression rate. The final optimized dictionary is used to perform the final compression on the data block after multi-level recursive compression to generate the final compressed data.

[0078] S1036: Pack the final compression dictionary and the final compressed data to generate a compression block.

[0079] The final compressed data is encapsulated with the final compression dictionary to form a complete data compression package. This compression package contains all the necessary information and can be decompressed and restored when needed. During the data recovery process, the compressed data is decompressed step by step by reversely applying the final compression dictionary to restore the original data. This mechanism ensures the integrity of the data and the reversibility of the compression algorithm, so that the original data can be accurately restored.

[0080] By introducing dynamic dictionary update, multi-level compression and global optimization mechanisms, the efficiency and adaptability of data compression are significantly improved.

[0081] S104: Determine a data compression rate according to the compression block and the corresponding data block.

[0082] S105: Encrypt the compressed block to obtain an encrypted block, and record the encryption duration of the compression process.

[0083] Exemplarily, the data block is encrypted while being compressed. The choice of encryption algorithm can also be adjusted according to the sensitivity and real-time requirements of the data. It is recommended to use a lightweight encryption algorithm, such as a stream-based encryption algorithm (such as RC4) or a block encryption algorithm (such as AES) for data encryption.

[0084] S106. Determine the transmission order of the encrypted blocks according to the data compression rate and the encryption duration, and transmit the encrypted blocks according to the transmission order.

[0085] Exemplarily, the sub-kernel 142 will dynamically adjust the transmission order of data blocks according to the bandwidth and latency characteristics of the transmission channel. Prioritize the transmission of data blocks with high compression ratio and moderate encryption strength to ensure maximum transmission efficiency and security under limited bandwidth. The specific calculation formula for the transmission order is:

[0086] ;

[0087] Where L represents the transmission order of the i-th data block, represents the data compression rate of the i-th data block, Indicates the encryption duration of the i-th data block.

[0088] The sub-kernel 142 optimizes the transmission order of multiple encrypted data blocks, calculates the transmission priority of each data block according to the compression rate and encryption time of the data block, determines the transmission order of the data blocks according to the calculated transmission priority, and obtains an optimized transmission data sequence.

[0089] During the transmission process, the sub-kernel 142 will also monitor the effect of data transmission in real time, and dynamically adjust the parameters of the compression algorithm and the encryption strength according to the bandwidth usage, error rate, decryption time and other information fed back during the transmission process. This step ensures that the algorithm can be optimized and adjusted according to the real-time situation to cope with changes in network conditions.

[0090] Based on the above process, the data management system 100 can realize the functions of data compression and data encryption during data transmission, and can be applied to hardware systems that require data confidentiality, thereby ensuring that the hardware system can perform efficient data transmission and improving the data security of the hardware system.

[0091] An embodiment of the present application also provides a chip, which includes a multifunctional programmable data management system as described in any one of the embodiments of the present application.

[0092] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A multifunctional programmable data management system, characterized in that: The data management system comprises: AHB bus; A main core unit, the main core unit is connected to the AHB bus; A ROM unit, wherein the ROM unit is connected to the AHB bus, the ROM unit stores a main core program and a secondary core program, and the secondary core program is stored at a preset designated address on the ROM unit; A sub-core unit, the sub-core unit comprising: a first buffer memory, a sub-core and a first function register, wherein a first end of the first buffer memory is connected to the AHB bus, and the first buffer memory is used to cache the sub-core program; a first end of the sub-core is connected to a second end of the first buffer memory, and the sub-core is used to read and execute the sub-core program cached in the first buffer memory, and a second end of the sub-core is connected to the AHB bus, and the second end of the sub-core is an output end; a first end of the first function register is connected to the sub-core, and a second end of the first function register is connected to the AHB bus, and the first function register is used to provide a clock variable and an address variable to the sub-core, and the address variable is a variable of the preset designated address; The sub-core unit performs a read operation on the ROM unit through the AHB bus, reads and caches the sub-core program according to the preset designated address, and executes data transmission or data processing functions according to the sub-core program.

2. The multifunctional programmable data management system according to claim 1, characterized in that: The number of bits of the AHB bus is a first number, the number of bits of the first end of the secondary core is a second number, and the number of bits of the second end of the secondary core is expanded to the first number; The number of bits at the first end of the first buffer memory is the first number of bits, and the number of bits at the second end of the first buffer memory is the second number of bits.

3. The multifunctional programmable data management system according to claim 1, characterized in that: The main core unit comprises: a second buffer memory, wherein a first end of the second buffer memory is connected to the AHB bus; A main core, a first end of the main core is connected to a second end of the second buffer memory, and a second end of the main core is connected to the AHB bus.

4. The multifunctional programmable data management system according to claim 1, characterized in that: The data management system further comprises: a slave unit and a RAM unit, wherein the slave unit comprises: an IAP unit, an I / O unit, other peripheral units and a second function register.

5. The multifunctional programmable data management system according to claim 4, characterized in that: The main core unit and the secondary core unit perform data exchange by reading and writing the RAM unit or the second function register.

6. A chip, characterized in that: The chip includes a multifunctional programmable data management system as described in any one of claims 1-5.

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