A programmable gain amplifier for sensor signal conditioning circuit

Abstract

The invention discloses a programmable gain amplifier for a sensor signal conditioning circuit, relates to the technical field of integrated circuits, and solves the technical problem that the resistance matching of a three-op-amp amplifier has a great influence on the total mode rejection ratio of the circuit. The key points of the technical solution are that the programmable gain amplifier comprises a chopper circuit and a two-stage op-amp circuit, and the 1 / f noise and offset of the circuit are reduced by the chopper circuit; the accuracy of the PGA is improved by a high-gain op-amp structure, so that the PGA has the characteristics of high gain, low noise and low offset.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a programmable gain amplifier for a sensor signal conditioning circuit. Background Art

[0002] With the continuous development of the electronics industry, the Internet of Things (IoT) has become one of the important growth engines in the past decade. Sensors, as a bridge between the physical world and the information world, can convert physical quantities such as temperature, humidity, and pressure into electrical signals such as voltage and current. Therefore, sensors are important devices for sensing the physical world in IoT applications. With the continuous development of the IoT industry, the research on sensors and sensor integrated interface circuits has become increasingly important.

[0003] With the rapid development of Micro Electro Mechanical System (MEMS) sensors, they are widely used in biomedical equipment, automotive parts, national defense, communications, avionics and household appliances. MEMS piezoresistive pressure sensors are widely used due to their linear output response, easy manufacturing, low cost and durability. At present, MEMS piezoresistive pressure sensors are mainly developed in the direction of high reliability, low power consumption, integration, intelligence, miniaturization and low cost.

[0004] In order to pursue high-precision and high-stability sensors, the design of sensor interface circuits has become one of the key technologies. The designed interface circuit includes functions such as amplification and analog-to-digital conversion. The programmable gain amplifier (PGA) is mainly used to amplify the output signal of the sensor.

[0005] The circuit structure of the existing three-op-amp instrumentation amplifier is as follows Figure 1 As shown in the figure, it consists of two stages. Among them, A1 and A2 form the first stage differential structure amplifier circuit, which improves the common mode rejection ratio of the circuit, and A3 forms the second stage amplifier circuit to further improve the gain of the operational amplifier. Since the input of the three op amps is directly connected to the gates of A1 and A2, the input resistance of the three op amp instrumentation amplifier is very large. According to Figure 1 , the gain of the first-stage amplifier circuit can be calculated as:

[0006] (1)

[0007] If R4=R6, R5=R7, the total gain of the three-op-amp instrumentation amplifier is:

[0008] (2)

[0009] According to formula (2), the gain of the three-op-amp instrumentation amplifier is determined by the feedback resistor, and the total common mode rejection ratio (CMRR) of the circuit is mainly the product of the CMRR of the first gain stage and the second gain stage. Therefore, the resistance matching of the three-op-amp instrumentation amplifier will affect the CMRR of the circuit, thereby affecting the gain of the three-op-amp instrumentation amplifier. Summary of the invention

[0010] The present application provides a programmable gain amplifier for a sensor signal conditioning circuit, the technical purpose of which is to increase the gain of an operational amplifier structure, thereby improving the accuracy of a PGA (Programmable Gain Amplifier).

[0011] The above technical objectives of this application are achieved through the following technical solutions:

[0012] A programmable gain amplifier for a sensor signal conditioning circuit comprises a first chopper circuit, a first-stage operational amplifier circuit, a second-stage operational amplifier circuit and a second chopper circuit, wherein the first-stage operational amplifier circuit comprises a first amplifier and a second amplifier, and the second-stage operational amplifier circuit comprises a third amplifier, an input signal is input from two input terminals of the first chopper circuit, two output terminals of the first chopper circuit are respectively connected to a non-inverting input terminal of the first amplifier and a non-inverting input terminal of the second amplifier, a first resistor is connected between an inverting input terminal of the first amplifier and an output terminal thereof, a third resistor is connected between an inverting input terminal of the second amplifier and an output terminal thereof, a second resistor is connected between an inverting input terminal of the first amplifier and an inverting input terminal of the second amplifier, a fourth resistor is connected between an output terminal of the first amplifier and a non-inverting input terminal of the third amplifier, a sixth resistor is connected between an output terminal of the second amplifier and an inverting input terminal of the third amplifier, a fifth resistor is connected between a non-inverting input terminal of the third amplifier and a negative output terminal thereof, a seventh resistor is connected between an inverting input terminal of the third amplifier and a positive output terminal thereof, and two output terminals of the third amplifier are respectively connected to two input terminals of the second chopper circuit.

[0013] Furthermore, the second resistor includes two resistance adjustment units and four basic resistors connected in series, each of the resistance adjustment units includes multiple switch resistors connected in parallel, when the switch is closed, the switch resistor is connected in parallel with the basic resistor; when the switch is open, the switch resistor is connected in series with the basic resistor; wherein the resistance value of the switch resistor is 2 times the resistance value of the basic resistor.

[0014] Further, the fifth resistor and the seventh resistor each include a resistance adjustment unit and a basic resistor connected in series, the resistance adjustment unit includes a plurality of switch resistors connected in parallel, when the switch is closed, the switch resistor is connected in parallel with the basic resistor; when the switch is opened, the switch resistor is connected in series with the basic resistor; the resistance values ​​of the fourth resistor and the sixth resistor are both equal to the resistance value of the basic resistor; wherein the resistance value of one switch resistor is equal to the resistance value of the basic resistor, and the resistance values ​​of the other switch resistors are times the power of 2 of the resistance value of the basic resistor;

[0015] The input signals are connected to the non-inverting input terminal and the inverting input terminal of the third amplifier respectively through the basic resistor and the switch.

[0016] Furthermore, the first amplifier, the second amplifier and the third amplifier all include a two-stage operational amplifier structure, the output end of the first stage operational amplifier structure is connected to the output end of the second stage operational amplifier structure, and a Miller compensation capacitor is connected between the input end and the output end of the second stage operational amplifier structure. Then, the capacitance of the input end of the second stage operational amplifier structure is expressed as , the capacitance at the output of the second stage op amp structure is expressed as ;in, Represents the second-stage op amp structure, Represents the capacitance of the Miller compensation capacitor.

[0017] Furthermore, the amplification factor of the first-stage operational amplifier circuit includes 1 times, 2 times, 4 times, 8 times and 16 times, and the amplification factor of the second-stage operational amplifier circuit includes 1 times, 2 times, 4 times and 8 times.

[0018] Further, the first chopping circuit and the second chopping circuit both include a first second-order low-pass filter, a second second-order low-pass filter, a third second-order low-pass filter, a fourth second-order low-pass filter, a third capacitor and a fourth capacitor; the negative output end of the first second-order low-pass filter, the inverting input end of the second second-order low-pass filter, the positive output end of the second second-order low-pass filter, the inverting input end of the third second-order low-pass filter, the non-inverting input end of the fourth second-order low-pass filter and one end of the third capacitor are all connected, and the positive output end of the first second-order low-pass filter, the non-inverting input end of the second second-order low-pass filter, the negative output end of the second second-order low-pass filter, the non-inverting input end of the third second-order low-pass filter, the inverting input end of the fourth second-order low-pass filter and the other end of the third capacitor are all connected; the positive output end of the fourth second-order low-pass filter, the positive output end of the third second-order low-pass filter and one end of the fourth capacitor are all connected; the negative output end of the fourth second-order low-pass filter, the negative output end of the third second-order low-pass filter and the other end of the fourth capacitor are all connected.

[0019] Further, the transfer functions of the first second-order low-pass filter, the second second-order low-pass filter, the third second-order low-pass filter and the fourth second-order low-pass filter are expressed as:

[0020] ;

[0021] in, ~ denote the transconductance of the first second-order low-pass filter, the second second-order low-pass filter, the third second-order low-pass filter, and the fourth second-order low-pass filter, respectively, and = = , = , represents the third capacitor, represents the fourth capacitor;

[0022] According to the transfer function Get the cutoff frequencies of the first second-order low-pass filter, the second second-order low-pass filter, the third second-order low-pass filter, and the fourth second-order low-pass filter and The values ​​are expressed as:

[0023] ;

[0024] ;

[0025] ;

[0026] ;

[0027] ;

[0028] ;

[0029] ;

[0030] ;

[0031] in, and Represent the cutoff frequency of the first and second order low pass filters respectively. value, and Represent the cutoff frequency and value, and Represent the cutoff frequency and value, and Represent the cutoff frequency and value, .

[0032] The beneficial effects of the present application are as follows: the programmable gain amplifier for the sensor signal conditioning circuit described in the present application includes a chopper circuit and a two-stage operational amplifier circuit, and the 1 / f noise and offset of the circuit are reduced by the chopper circuit; the accuracy of the PGA is improved by a high-gain operational amplifier structure, so that the PGA has the characteristics of high gain, low noise and low offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The circuit structure diagram of the existing three-op-amp instrumentation amplifier is shown in FIG.

[0034] Figure 2 A system framework diagram of a programmable gain amplifier in an embodiment of the present application;

[0035] Figure 3a This is a structural diagram of the first-stage operational amplifier circuit in an embodiment of the present application;

[0036] Figure 3b This is a structural diagram of the second-stage operational amplifier circuit in an embodiment of the present application;

[0037] Figure 4 This is a structural diagram of the first amplifier, the second amplifier and the third amplifier in the embodiment of the present application;

[0038] Figure 5 A circuit diagram of a first amplifier and a second amplifier in an embodiment of the present application;

[0039] Figure 6 Graph showing simulation results of the first-stage PGA operational amplifier circuit in an embodiment of the present application;

[0040] Figure 7 is a circuit diagram of a third amplifier in an embodiment of the present application;

[0041] Figure 8 1 is a simulation result diagram of the PGA second-stage operational amplifier circuit in an embodiment of the present application;

[0042] Fig. 9 This is the schematic diagram of the chopping technique;

[0043] Fig.10 A structural diagram of a first chopping circuit and a second chopping circuit in an embodiment of the present application;

[0044] Fig.11 is a circuit diagram of a second-order low-pass filter in a chopper circuit in an embodiment of the present application;

[0045] Fig.12 Schematic diagram of the frequency domain characteristic curve of the low-pass filter in the embodiment of the present application;

[0046] Fig.13A schematic diagram of transient simulation results of a PGA amplifier circuit of a chopper switch in an embodiment of the present application; Fig.13 In the figure, from top to bottom are the PGA input signal, the chopped signal, and the demodulated signal after passing through the low-pass filter;

[0047] Fig.14a Schematic diagram of noise simulation results of a non-chopper PGA in an embodiment of the present application;

[0048] Fig.14b A schematic diagram of noise simulation results of a chopped PGA in an embodiment of the present application;

[0049] Fig.15 This is a graph of the PGA gain error results in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0051] The system framework diagram of the programmable gain amplifier for the sensor signal conditioning circuit described in this application is as follows: Figure 2 As shown, the PGA is divided into two stages. The first stage op amp circuit uses two high-gain operational amplifiers to form differential input and differential output, and the second stage op amp circuit uses a fully differential op amp. In order to realize an amplifier with adjustable gain, Figure 2 R1, R2, R3, R4, R5, R6, R7, etc. are all adjustable resistors. PGA achieves the purpose of variable gain by changing the resistance value of the resistor. The maximum closed-loop gain in this application is 128 times. If only the first-stage op amp circuit is used for amplification, it is not easy to achieve when the accuracy requirement is relatively high. Therefore, the first-stage op amp circuit is designed to amplify 16 times and the second-stage op amp circuit is designed to amplify 8 times. At the same time, CH1 and CH2 are chopper switches, which can reduce the 1 / f noise and offset of the circuit.

[0052] The first stage op amp circuit (A1 and A2) and the second stage op amp circuit (A3) of PGA are as follows: Figure 3a and Figure 3b As shown by Figure 3a It can be seen that the amplification factor of the PGA first-stage operational amplifier circuit can be set to 1x, 2x, 4x, 8x and 16x by adjusting the switches SW_A0~SW_A4. Figure 3b The amplification factors of the second-stage op amp circuit are 1, 2, 4 and 8. The PGA can obtain amplification factors of 1 to 128 by multiplying the amplification factor of the first-stage op amp circuit by the amplification factor of the second-stage op amp circuit.

[0053] Specifically, the present application adopts a transmission gate structure as a switch. Compared with a single MOS device switch, the linear on-resistance of the switch can be reduced. However, it still affects the gain value of the PGA. In order to minimize the effect of the switch on the gain value of the PGA, the present application Figure 3b Two normally open switches are added to the input end of the PGA, so the gain of the second stage op amp circuit can be expressed as:

[0054] (3)

[0055] in, Indicates the magnification factor required. Represents the equivalent resistance of the switch.

[0056] In order to obtain a high-precision sensor output signal, the PGA must have high gain, low noise, and low offset characteristics. In order not to affect the accuracy of the entire system, the open-loop gain of the op amp must be as high as possible. Therefore, a high-gain op amp structure is used in this application to achieve the purpose of improving the accuracy of the PGA.

[0057] In the embodiment of the present application, each single-stage operational amplifier (the first amplifier A1, the second amplifier A2 and the third amplifier A3) adopts Figure 4 The op amp structure shown can achieve higher gain. Figure 4 The op amp structure shown includes and Two-stage op amp, because there are two poles in the two-stage op amp, if the two poles are close to each other, the phase shift exceeds 180° when the gain is equal to 0dB, which will cause the circuit to self-oscillate. In this application, the Miller compensation method is used to add Miller compensation capacitor separates the two poles.

[0058] like Figure 4 As shown, Miller compensation capacitors are connected across the input and output terminals of the second-stage op amp. , the purpose of which is to create a large capacitor at point x, whose value is equal to , push the first pole toward the origin; at the same time, establish a small capacitor at point y, whose value is equal to , the load capacitance remains almost unchanged, but due to the high frequency, Between input and output Providing a low impedance will move the output pole away from the origin. Therefore, Miller compensation separates the two poles to achieve the compensation effect.

[0059] In the embodiment of the present application, the circuit diagram of the first amplifier and the second amplifier in the PGA amplifier is as follows: Figure 5 As shown, the first stage of the circuit adopts a folded common source and common gate structure, and the second stage adopts a common source structure.

[0060] Depend on Figure 5 It can be known that the first amplifier and the second amplifier both include a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube and a Miller compensation capacitor; the positive electrode of the input signal is connected to the gates of the first MOS tube and the third MOS tube, the source of the first MOS tube, the source of the second MOS tube and the drain of the third MOS tube are all connected, the drain of the first MOS tube, the source of the eighth MOS tube and the drain of the tenth MOS tube are all connected; the drain of the second MOS tube, the source of the ninth MOS tube and the drain of the eleventh MOS tube are all connected, and the gate of the second MOS tube is connected to the negative electrode of the input signal; the source of the third MOS tube, the source of the fourth MOS tube, the source of the fifth MOS tube and the drain of the thirteenth MOS tube are connected. The sources of the OS tubes are all connected to the power supply voltage; the drain of the fourth MOS tube is connected to the source of the sixth MOS tube, and the gate of the fourth MOS tube, the gate of the fifth MOS tube, the drain of the sixth MOS tube and the drain of the eighth MOS tube are all connected; the drain of the fifth MOS tube is connected to the source of the seventh MOS tube; the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube; the drain of the seventh MOS tube, the drain of the ninth MOS tube, the gate of the thirteenth MOS tube and one end of the Miller compensation capacitor are all connected; the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube; the gate of the tenth MOS tube, the gate of the eleventh MOS tube and the gate of the twelfth MOS tube are all connected, and the source of the tenth MOS tube, the source of the eleventh MOS tube and the source of the twelfth MOS tube are all grounded; the drain of the twelfth MOS tube, the drain of the thirteenth MOS tube, the Miller compensation capacitor and the signal output end are all connected.

[0061] Since the output impedance of the folded cascode structure is high, the gain of the circuit can be improved; at the same time, because the operating voltage of the sensor is lower than the operating voltage of the PGA, and the common-mode level of the sensor is half of the sensor operating voltage, it is more appropriate to choose a PMOS tube as the amplifier tube of the op amp. Figure 5 The simulation results of the circuit shown are as follows Figure 6 As shown, it can be seen that the gain of the first stage is 139 dB, the GBW is 15.2 MHz, and the phase margin is 56°.

[0062] The circuit diagram of the third amplifier in the PGA amplifier is as follows Figure 7 As shown, Figure 7 A fully differential class AB structure with differential input and differential output is adopted. Compared with the class A amplifier, the class AB amplifier has a stronger driving capability and can effectively reduce the intermodulation distortion. At the same time, the quiescent current of the output stage is small.

[0063] Depend on Figure 7It can be known that the third amplifier includes a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a twenty-seventh MOS tube, a twenty-eighth MOS tube, a twenty-ninth MOS tube, a thirtieth MOS tube, a thirty-first MOS tube, a thirty-second MOS tube, a thirty-third MOS tube, a thirty-fourth MOS tube, a thirty-fifth MOS tube, a thirty-sixth MOS tube, a thirty-seventh MOS tube, a thirty-eighth MOS tube, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor The gate of the fourteenth MOS tube serves as the in-phase input terminal, the drain of the fourteenth MOS tube, the drain of the eighteenth MOS tube, the drain of the nineteenth MOS tube, the gate of the twenty-sixth MOS tube, the gate of the twenty-seventh MOS tube and one end of the first capacitor are all connected, and the source of the fourteenth MOS tube, the source of the fifteenth MOS tube and the drain of the sixteenth MOS tube are all connected; the gate of the fifteenth MOS tube serves as the inverting input terminal, the drain of the fifteenth MOS tube, the drain of the twenty-second MOS tube, the drain of the twenty-third MOS tube, the gate of the thirty-first MOS tube, the gate of the thirty-third MOS tube and one end of the second capacitor are all connected; the gate of the sixteenth MOS tube, the gate of the seventeenth MOS tube, the gate of the The gate of the twenty-fourth MOS tube, the gate of the twenty-fifth MOS tube, the gate of the twenty-ninth MOS tube, the gate of the thirtieth MOS tube, the drain of the thirtieth MOS tube, the gate of the thirty-second MOS tube, the gate of the thirty-fourth MOS tube and the source of the thirty-first MOS tube are all connected; the source of the sixteenth MOS tube, the source of the seventeenth MOS tube, the source of the twenty-fourth MOS tube, the source of the twenty-fifth MOS tube, the source of the twenty-eighth MOS tube, the source of the twenty-ninth MOS tube, the source of the thirtieth MOS tube, the source of the thirty-second MOS tube and the source of the thirty-fourth MOS tube are all connected to the power supply voltage; the drain of the seventeenth MOS tube is connected to the source of the eighteenth MOS tube; the gate of the eighteenth MOS tube is connected to the twentieth MOS tube The gates of the three MOS tubes are connected; the gate of the nineteenth MOS tube is connected to the gate of the twenty-second MOS tube; the source of the nineteenth MOS tube is connected to the drain of the twentieth MOS tube; the gate of the twentieth MOS tube, the gate of the twenty-first MOS tube, the drain of the thirty-fifth MOS tube, the gate of the thirty-seventh MOS tube and the drain of the thirty-seventh MOS tube are all connected; the source of the twentieth MOS tube, the source of the twenty-first MOS tube, the drain of the twenty-sixth MOS tube, the source of the twenty-seventh MOS tube, the drain of the thirty-first MOS tube, the source of the thirty-third MOS tube, the source of the thirty-seventh MOS tube and the source of the thirty-eighth MOS tube are all grounded; the drain of the twenty-first MOS tube is connected to the source of the twenty-second MOS tube;The source of the twenty-third MOS tube is connected to the drain of the twenty-fourth MOS tube; the drain of the twenty-fifth MOS tube, the source of the twenty-sixth MOS tube and the gate of the twenty-eighth MOS tube are all connected; the drain of the twenty-seventh MOS tube, the drain of the twenty-eighth MOS tube, one end of the eleventh resistor, one end of the eighth resistor and the positive output end are all connected; the drain of the twenty-ninth MOS tube is connected to a bias current; the drain of the thirty-second MOS tube, the drain of the thirty-third MOS tube, one end of the ninth resistor, one end of the tenth resistor and the negative output end are all connected; the drain of the thirty-fourth MOS tube, the source of the thirty-fifth MOS tube and the source of the thirty-sixth MOS tube are all connected; the gate of the thirty-fifth MOS tube, the other end of the eighth resistor and the other end of the ninth resistor are all connected; the gate of the thirty-sixth MOS tube is connected to a common mode voltage; the drain of the thirty-sixth MOS tube, the gate of the thirty-eighth MOS tube and the drain of the thirty-eighth MOS tube are all connected; the other end of the first capacitor is connected to the other end of the eleventh resistor; the other end of the second capacitor is connected to the other end of the tenth resistor. ;

[0064] The fully differential class AB op amp used in this application is a two-stage amplifier circuit, the first stage is a folded common source and common gate structure, which can improve the gain of the circuit; the second stage is a fully differential structure of the class AB output stage. When the circuit is working, the current biased by M17 and M24 is easily mismatched with the current biased by M20 and M21. In order to match the current, the MOS tube will enter the linear region, so a common mode feedback circuit is needed to stabilize the voltage at the output point. The input control voltage Vcm of the M36 tube controls the output common mode voltage point, and M35 checks the output level of the op amp through resistors R8 and R9. If the common mode level increases, the common mode feedback circuit outputs a low level, and the current of M20 and M21 will decrease, thereby adjusting the tail current source to lower the common mode level, and vice versa. The circuit uses a source follower to realize DC level shifting, thereby realizing class AB output. At the same time, the circuit uses Miller compensation to stabilize the circuit and add a zero adjustment resistor.

[0065] Figure 7 The simulation results of the second stage op amp circuit of the PGA shown in Figure 8 As shown, it can be seen that the gain of the second-stage op amp circuit is 133 dB, the GBW is 27 MHz, and the phase margin is 83°.

[0066] Due to the existence of factors such as the 1 / f noise and offset voltage of the operational amplifier, the accuracy of the entire system will be limited. In this application, chopper stabilization technology is used to suppress the 1 / f noise and offset voltage of the operational amplifier. Chopping can be regarded as a frequency domain technology. It first modulates the input signal to a high frequency after passing through a chopper, and then demodulates it back to the base frequency after passing through the chopper; while the 1 / f noise and offset of the operational amplifier are only demodulated once and moved to a high frequency, and then filtered out by a low-pass filter.

[0067] The basic principle of chopping technology is as follows Fig. 9 As shown in the figure, after the input signal passes through the first set of chopping switches, its spectrum is moved to the odd harmonic components of the chopping frequency, and then superimposed with the low-frequency noise and offset voltage at the input end and amplified by the amplifier. After the signal passes through the second set of chopping switches, it is demodulated back to the baseband and even harmonic components, while the noise and offset voltage of the amplifier are modulated by the chopping switch only once, and all noise and offset are modulated to the odd harmonics. Finally, the noise and offset at the high frequency are filtered out by a low-pass filter, thereby improving the accuracy of the entire system.

[0068] Therefore, the chopping technology in the PGA circuit requires the use of a low-pass filter to filter out the circuit's offset and noise. This application uses a gm-c low-pass filter, and its circuit structure is as follows Fig.10 as shown, to make the transition zone steeper.

[0069] according to Fig.10 It can be seen that the transfer function of the gm-c second-order low-pass filter is:

[0070] (4)

[0071] in, ~ Respectively represent the transconductance of transconductance units Gm1 to Gm4, and = = , = , represents the third capacitor, Represents the fourth capacitor.

[0072] According to formula (4), the cut-off frequency can be obtained and The values ​​are expressed as:

[0073] (5)

[0074] (6)

[0075] in, represents the transconductance of four gm-c second-order low-pass filters ~ , represents the capacitance between the transconductors, According to formula (5), if the cutoff frequency of the system is relatively low, the capacitance value of the filter should be large and the transconductance unit value gm should be small. The capacitor structure can adopt the form of differential capacitor, that is, the two ends of the capacitor are connected to the in-phase output terminal and the inverting output terminal of the transconductance unit respectively, such as Fig.10As shown, this connection method can reduce the capacitance value by half compared to the connection method of the capacitor to ground.

[0076] The transconductance unit design to achieve low transconductance value can adopt source negative feedback technology and current shunt technology, then the circuit structure adopted by Gm1~Gm4 is as follows Fig.11 As shown. Fig.11, the first second-order low-pass filter, the second second-order low-pass filter, the third second-order low-pass filter and the fourth second-order low-pass filter all include a first composite transistor, a second composite transistor, a forty-first MOS tube, a forty-second MOS tube, a forty-third MOS tube, a forty-fourth MOS tube, a forty-fifth MOS tube, a forty-sixth MOS tube, a forty-seventh MOS tube, a forty-eighth MOS tube, a forty-ninth MOS tube, a fifty-first MOS tube, a fifty-second MOS tube, a fifty-third MOS tube and a fifty-fourth MOS tube, the first composite transistor includes a thirty-ninth MOS tube and a fiftieth MOS tube, and the second composite transistor includes a fortieth MOS tube and a fifty-fifth MOS tube; The in-phase input signal is input from the gate of the 50th MOS tube, and the gate of the 50th MOS tube is connected to the gate of the 39th MOS tube; the drain of the 50th MOS tube, the source of the 47th MOS tube, the source of the 48th MOS tube, the source of the 49th MOS tube, the source of the 51st MOS tube, the source of the 52nd MOS tube and the drain of the 55th MOS tube are all grounded; the source of the 50th MOS tube, the source of the 39th MOS tube, the drain of the 41st MOS tube and the drain of the 44th MOS tube are all connected; the drain of the 39th MOS tube, the drain of the 48th MOS tube, the gate of the 48th MOS tube and the gate of the 51st MOS tube are all connected; the inverting input signal The gate of the fifty-fifth MOS tube is input, the gate of the fifty-fifth MOS tube is connected to the gate of the fortieth MOS tube; the source of the fifty-fifth MOS tube, the source of the fortieth MOS tube, the drain of the forty-third MOS tube and the source of the forty-fifth MOS tube are all connected; the drain of the fortieth MOS tube, the drain of the forty-ninth MOS tube, the gate of the forty-ninth MOS tube and the gate of the fifty-second MOS tube are all connected; the gate of the forty-first MOS tube, the gate of the forty-second MOS tube and the gate of the forty-third MOS tube are all connected with the base voltage; the source of the forty-first MOS tube, the source of the forty-second MOS tube, the source of the forty-third MOS tube, the source of the fifty-third MOS tube and the fifty-fourth MOS tube are connected. The sources of the OS tubes are all connected to the power supply voltage; the drain of the 42nd MOS tube is connected to the source of the 46th MOS tube; the gate of the 44th MOS tube, the gate of the 45th MOS tube, the gate of the 46th MOS tube, the drain of the 46th MOS tube and the drain of the 47th MOS tube are all connected; the source of the 44th MOS tube is connected to the drain of the 45th MOS tube; the gate of the 47th MOS tube is connected to the base voltage; the drain of the 51st MOS tube and the drain of the 54th MOS tube are both connected to the positive output terminal; the drain of the 52nd MOS tube and the drain of the 53rd MOS tube are both connected to the negative output terminal; the gate of the 53rd MOS tube and the gate of the 54th MOS tube are both suspended.

[0077] Fig.11In the figure, M44 and M45 act as source negative feedback resistors of input transistors M39, M50, M40, and M55 to reduce the final equivalent output transconductance of M39, M50, M40, and M55. Input transistors M39, M50, M40, and M55 use current shunting technology to set the size ratio of input transistors to M:1, and the equivalent transconductance obtained is:

[0078] (7)

[0079] in Represents a composite transistor (before splitting), through which both technologies can realize a transconductance cell with low transconductance.

[0080] At the same time, according to formula (7), by adjusting the second-stage transconductance value, the Q value of the filter can be made less than 0.707, so that the frequency curve of the filter will be smoother and no peak will appear near the cutoff frequency.

[0081] The frequency domain characteristics of the designed low-pass filter are analyzed, and the analysis results are as follows: Fig.12 As shown, the slope of the low-pass filter is -40 dB / decade, and the cut-off frequency is about 250 Hz. The second-order low-pass filter designed in this application can basically meet the system requirements.

[0082] In summary, the PGA designed in this application is simulated. The input signal of the PGA is set to 1 mV, an AC signal with a frequency of 100 Hz, and the chopping frequency is set to be more than twice the input signal frequency. The transient simulation of the PGA amplifier circuit including the chopping switch is shown in the figure. Fig.13 As shown in the figure, from top to bottom are the input signal of PGA, the signal after chopped and the signal after demodulation and passing through the low-pass filter. It can be seen that the designed chopper switch and low-pass filter can work normally.

[0083] Since noise can distort the output signal of the op amp, thus affecting the signal-to-noise ratio and resolution of the entire ADC, a chopper switch is added when designing the PGA to reduce the noise of the PGA. Fig.14a and Fig.14b As shown in the figure, by comparing the noise simulation results of the PGA with and without chopping, it can be seen that the equivalent input noise at a frequency of 1 Hz without chopping is 12.9218 μV / aqrt(Hz) (as shown in the figure). Fig.14a After chopping, the equivalent input noise at 1 Hz is reduced to 81.36 nV / aqrt(Hz) (as shown in Fig.14b As shown in the figure, it can be seen that the equivalent noise has been significantly reduced.

[0084] Fig.15From the gain error analysis of the PGA, it can be seen that the gain error of the PGA designed in this application is very small, with a maximum error of 0.023‰, which meets the design requirements.

[0085] The above are exemplary embodiments of the present application, and the protection scope of the present application is defined by the claims and their equivalents.

Claims

1. A programmable gain amplifier for a sensor signal conditioning circuit, characterized in that: The invention comprises a first chopping circuit, a first-stage operational amplifier circuit, a second-stage operational amplifier circuit and a second chopping circuit, wherein the first-stage operational amplifier circuit comprises a first amplifier and a second amplifier, and the second-stage operational amplifier circuit comprises a third amplifier. An input signal is input from two input terminals of the first chopping circuit, and two output terminals of the first chopping circuit are respectively connected to the in-phase input terminal of the first amplifier and the in-phase input terminal of the second amplifier, a first resistor is connected between the inverting input terminal of the first amplifier and its output terminal, a third resistor is connected between the inverting input terminal of the second amplifier and its output terminal, a second resistor is connected between the inverting input terminal of the first amplifier and the inverting input terminal of the second amplifier, a fourth resistor is connected between the output terminal of the first amplifier and the in-phase input terminal of the third amplifier, a sixth resistor is connected between the output terminal of the second amplifier and the inverting input terminal of the third amplifier, a fifth resistor is connected between the in-phase input terminal of the third amplifier and its negative output terminal, a seventh resistor is connected between the inverting input terminal of the third amplifier and its positive output terminal, and two output terminals of the third amplifier are respectively connected to two input terminals of the second chopping circuit; The first chopping circuit and the second chopping circuit both include a first second-order low-pass filter, a second second-order low-pass filter, a third second-order low-pass filter, a fourth second-order low-pass filter, a third capacitor and a fourth capacitor; the negative output end of the first second-order low-pass filter, the inverting input end of the second second-order low-pass filter, the positive output end of the second second-order low-pass filter, the inverting input end of the third second-order low-pass filter, the non-inverting input end of the fourth second-order low-pass filter and one end of the third capacitor are all connected, the positive output end of the first second-order low-pass filter, the non-inverting input end of the second second-order low-pass filter, the negative output end of the second second-order low-pass filter, the non-inverting input end of the third second-order low-pass filter, the inverting input end of the fourth second-order low-pass filter and the other end of the third capacitor are all connected; the positive output end of the fourth second-order low-pass filter, the positive output end of the third second-order low-pass filter and one end of the fourth capacitor are all connected; the negative output end of the fourth second-order low-pass filter, the negative output end of the third second-order low-pass filter and the other end of the fourth capacitor are all connected.

2. The programmable gain amplifier according to claim 1, wherein: The second resistor includes two resistance adjustment units and four basic resistors connected in series, each of the resistance adjustment units includes multiple switch resistors connected in parallel, when the switch is closed, the switch resistor is connected in parallel with the basic resistor; when the switch is open, the switch resistor is connected in series with the basic resistor; wherein the resistance value of the switch resistor is 2 times the resistance value of the basic resistor.

3. The programmable gain amplifier according to claim 2, wherein: The fifth resistor and the seventh resistor each include a resistance adjustment unit and a basic resistor connected in series, the resistance adjustment unit includes a plurality of switch resistors connected in parallel, when the switch is closed, the switch resistor is connected in parallel with the basic resistor; when the switch is opened, the switch resistor is connected in series with the basic resistor; the resistance values ​​of the fourth resistor and the sixth resistor are both equal to the resistance value of the basic resistor; wherein the resistance value of one switch resistor is equal to the resistance value of the basic resistor, and the resistance values ​​of the other switch resistors are times the power of 2 of the resistance value of the basic resistor; The input signals are connected to the non-inverting input terminal and the inverting input terminal of the third amplifier respectively through the basic resistor and the switch.

4. The programmable gain amplifier according to claim 1, wherein: The first amplifier, the second amplifier and the third amplifier all include a two-stage operational amplifier structure, the output end of the first stage operational amplifier structure is connected to the input end of the second stage operational amplifier structure, and a Miller compensation capacitor is connected between the input end and the output end of the second stage operational amplifier structure. Then, the capacitance of the input end of the second stage operational amplifier structure is expressed as , the capacitance at the output of the second stage op amp structure is expressed as ;in, Represents the second-stage op amp structure, Represents the capacitance of the Miller compensation capacitor.

5. The programmable gain amplifier according to claim 1, wherein: The amplification factors of the first-stage operational amplifier circuit include 1 times, 2 times, 4 times, 8 times and 16 times, and the amplification factors of the second-stage operational amplifier circuit include 1 times, 2 times, 4 times and 8 times.

6. The programmable gain amplifier according to claim 1, wherein: The transfer functions of the first second-order low-pass filter, the second second-order low-pass filter, the third second-order low-pass filter and the fourth second-order low-pass filter are expressed as: ； in, ~ denote the transconductance of the first second-order low-pass filter, the second second-order low-pass filter, the third second-order low-pass filter, and the fourth second-order low-pass filter, respectively, and = = , = , represents the third capacitor, represents the fourth capacitor; According to the transfer function Get the cutoff frequencies of the first second-order low-pass filter, the second second-order low-pass filter, the third second-order low-pass filter, and the fourth second-order low-pass filter and The values ​​are expressed as: ； ； ； ； ； ； ； ； in, and Represent the cutoff frequency of the first and second order low pass filters respectively. value, and Represent the cutoff frequency and value, and Represent the cutoff frequency and value, and Represent the cutoff frequency and value, .

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