CAN transceiver circuit

Abstract

The present application provides a CAN transceiver, which includes a transmission data port for receiving a transmission data signal; a control port for receiving a mode control signal; a high-side bus port for outputting a high-side signal; a low-side bus port for outputting a low-side signal; when the mode control signal is in the first state and the transmission data signal is at a logical low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V; when the mode control signal is in the first state and the transmission data signal is at a logical high potential, the difference is between -1.8V and -3.3V; when the mode control signal is in the second state and the transmission data signal is at a logical low potential, the difference is between 1.8V and 3.3V; when the mode control signal is in the second state and the transmission data signal is at a logical high potential, the difference is between -300mV and 300mV. The present application can adjust the characteristics of the differential signal output by the CAN transceiver to the bus, avoiding interference with data transmission caused by signal reflection and oscillation.

Description

Technical Field

[0001] This application relates to the technical field of CAN bus, and particularly to a CAN transceiver circuit. Background Art

[0002] As an interface between a CAN controller and a CAN bus, on the one hand, the CAN transceiver receives the transmission data signal TX sent by the CAN controller and converts it into a high-side signal VH and a low-side signal VL to the CAN bus. On the other hand, the CAN transceiver generates a received data signal RX according to the high-side signal VH and the low-side signal VL on the CAN bus and transmits the received data signal RX to the CAN controller. When the transmission data signal TX jumps from a logical low potential to a logical high potential, due to the sudden change of the output resistance of the CAN controller, the high-side signal VH and the low-side signal VL are prone to oscillation, resulting in an incorrect output of the received data signal RX, thus affecting the reliability and stability of the entire CAN transmission system. Usually, reducing the transmission rate of the CAN bus can avoid the incorrect output of the received data signal RX, but this will reduce the signal transmission efficiency of the CAN bus.

[0003] Therefore, a CAN transceiver is needed that has both a high transmission rate and high reliability. Summary of the Invention

[0004] The present invention provides a CAN transceiver to solve the problems of signal reflection and oscillation when the CAN transceiver switches between a dominant frame and a recessive frame, so as to reduce the error rate and improve the transmission rate.

[0005] According to a first aspect of the present invention, there is provided a CAN transceiver, including: a transmission data port for receiving a transmission data signal; a control port for receiving a mode control signal; a high-side bus port for outputting a high-side signal; and a low-side bus port for outputting a low-side signal; wherein when the mode control signal is in a first state and the transmission data signal is at a logical low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V; when the mode control signal is in the first state and the transmission data signal is at a logical high potential, the difference between the high-side signal and the low-side signal is between -1.8V and -3.3V; when the mode control signal is in a second state and the transmission data signal is at a logical low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V; when the mode control signal is in the second state and the transmission data signal is at a logical high potential, the difference between the high-side signal and the low-side signal is between -300mV and 300mV.

[0006] According to a second aspect of the present invention, the present invention provides a CAN transceiver, including: a transmit data port for receiving a transmit data signal; a high-side bus port for outputting a high-side signal; and a low-side bus port for outputting a low-side signal; wherein, when the transmit data signal is at a logic low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V, and when the transmit data signal is at a logic high potential, the difference between the high-side signal and the low-side signal is between -1.8V and -3.3V.

[0007] According to a third aspect of the present invention, the present invention provides a CAN transceiver, including: a transmit data port for receiving a transmit data signal; a high-side bus port for outputting a high-side signal; a low-side bus port for outputting a low-side signal; a high-side power transistor having a first end, a second end and a control end, wherein the first end receives a supply voltage and the control end receives the transmit data signal; a first high-side switch having a first end, a second end and a control end, wherein the first end is coupled to the second end of the high-side power transistor, the second end is coupled to the high-side bus port, and the control end receives a first high-side control signal; a second high-side switch having a first end, a second end and a control end, wherein the first end is coupled to the second end of the first high-side switch and the control end receives a second high-side control signal; a third high-side switch having a first end, a second end and a control end, wherein the first end is coupled to the second end of the second high-side switch, the second end is coupled to a first preset voltage VS1, and the control end receives a third high-side control signal; a first low-side switch having a first end, a second end and a control end, wherein the first end is coupled to the low-side bus port and the control end receives a first low-side control signal; a low-side power transistor having a first end, a second end and a control end, wherein the first end is coupled to the second end of the first low-side switch, the second end is coupled to a reference ground, and the control end receives a transmit data non-signal, wherein the transmit data non-signal and the transmit data signal are complementary signals; a second low-side switch having a first end, a second end and a control end, wherein the first end is coupled to the low-side bus port and the control end receives a second low-side control signal; and a third low-side switch having a first end, a second end and a control end, wherein the first end receives a second preset voltage, the second end is coupled to the second end of the second low-side switch, and the control end receives a third low-side control signal; wherein, when the transmit data signal is at a logic low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V, and when the transmit data signal is at a logic high potential, the difference between the high-side signal and the low-side signal is between -300mV and 300mV.

[0008] Through one or more embodiments of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0009] The CAN transceiver controls the voltage values of the high-side bus and the low-side bus when the CAN transceiver is in the dominant bit and the recessive bit according to the state of the mode control signal and the high and low potentials of the transmitted data signal, so that the difference between the high-side bus and the low-side bus is within a preset threshold range. By precisely controlling the difference between the high-side bus and the low-side bus, the characteristics of the differential signal output by the CAN transceiver to the bus are effectively adjusted, avoiding interference to data transmission caused by signal reflection and oscillation, thereby reducing the bit error rate and improving the transmission rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 The structural schematic diagram of the existing CAN transceiver is given;

[0012] Figure 2 The signal waveform diagrams of the output stage and the input stage of the existing CAN transceiver are given;

[0013] Figure 3 The structural schematic diagram of the CAN transceiver according to an embodiment of the present invention is given;

[0014] Figure 4 The circuit structural schematic diagram of the CAN transceiver according to an embodiment of the present invention is given;

[0015] Figure 5 Given Figure 4 The waveform diagrams of the signals in the CAN transceiver shown;

[0016] Figure 6 The circuit structural schematic diagram of the CAN transceiver according to an embodiment of the present invention is given;

[0017] Figure 7 The structural schematic diagram of the CAN transceiver according to an embodiment of the present invention is given;

[0018] Figure 8 The circuit structural schematic diagram of the CAN transceiver according to an embodiment of the present invention is given;

[0019] Figure 9 Given Figure 8 The waveform diagrams of the signals in the CAN transceiver shown;

[0020] Figure 10 The circuit structural schematic diagram of the CAN transceiver according to an embodiment of the present invention is given;

[0021] Figure 11 shows Figure 10 the waveform diagrams of the signals in the CAN transceiver shown in the figure. Specific embodiments

[0022] In the description of the present invention, it should be noted that throughout the specification and claims, the term "coupled" is defined as directly or indirectly connecting in an electrical or non-electrical manner. When an element is described as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be one or more intermediate elements. In contrast, when an element is described as "directly connected" or "directly coupled" to another element, there are no intermediate elements. Throughout the specification, the reference to "one embodiment", "an embodiment", "one example" or "an example" means that the specific features, structures or characteristics described in connection with that embodiment or example are included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment", "in an embodiment", "one example" or "an example" appearing throughout the specification do not necessarily all refer to the same embodiment or example. Additionally, the specific features, structures or characteristics can be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. Identical reference numerals indicate identical devices. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0023] Figure 1 shows the structural schematic diagram of the existing CAN transceiver.

[0024] The CAN transceiver includes two main parts: the CAN transceiver input stage and the CAN transceiver output stage. The CAN transceiver includes a transmit data port TXD and a receive data port RXD. The CAN transceiver input stage is used to receive the transmit data signal TX generated by the CAN controller and convert it into a high-side signal VH and a low-side signal VL that conform to the CAN bus signal specification for transmission on the CAN bus. In the input stage, the transmit data signal TX is encoded and shaped, and then the drive signal is sent to the CAN bus. The CAN transceiver output stage is used to demodulate, amplify and convert the high-side signal VH and the low-side signal VL received from the CAN bus into a receive data signal RX, and the CAN transceiver outputs the receive data signal RX from its receive data port RXD to the CAN controller.

[0025] Figure 1Multiple CAN transceivers in it are connected in a star topology. A star topology is a network connection method in which all nodes are directly connected to a central hub or switch. In a CAN bus system, the star topology usually means that all CAN nodes are directly connected to the central CAN bus hub. Such a connection method enables all nodes to exchange data and communicate through the hub, which can reduce the wiring distance, thus saving the bus wiring cost and connecting more CAN transceivers at the same time.

[0026] The CAN bus uses differential signals to transmit data, where the high-side signal VH and the low-side signal VL are a pair of differential signal lines on the CAN bus. When the transmitted data signal TX is at a logic low potential, the differential level between the high-side signal VH and the low-side signal VL is high, that is, there is a voltage difference between the high-side signal VH and the low-side signal VL, and the received data signal RX is at a logic high potential. When the transmitted data signal TX is at a logic high potential, the differential level between the high-side signal VH and the low-side signal VL is low, that is, the potentials of the high-side signal VH and the low-side signal VL are equal, and the received data signal RX is at a logic low potential.

[0027] In CAN bus communication, different data bits (dominant or recessive) are represented by changing the level difference between the high-side signal VH and the low-side signal VL, so as to realize the transmission and reception of data. The switching between the dominant bit and the recessive bit determines the differential level state on the CAN bus. In the dominant bit, the voltage difference between the high-side signal VH and the low-side signal VL is large; in the recessive bit, the voltage difference between the high-side signal VH and the low-side signal VL is small. The receiving party can interpret the data bit information transmitted by the sending party by identifying the voltage difference between the high-side signal VH and the low-side signal VL.

[0028] Figure 2 Waveform diagrams of each signal of the existing CAN transceiver output stage and input stage are given. As Figure 2As shown, when the existing CAN transceiver switches from dominant to recessive in the bus output, signal reflection occurs due to the sudden increase in the output impedance at the connection with the CAN bus, resulting in signal oscillation, causing the received data signal RX to oscillate, and ultimately leading to the CAN transceiver sending an incorrect signal. In CAN bus communication, the received data signal RX jumps from a logical low to a logical high potential according to the level difference defined by the CAN protocol. During the jump process, due to the sudden change in current and impedance mismatch on the transmission line, signal reflection occurs. If the output impedance of the CAN transceiver is too high or there is a large current change, this reflection will be more significant, resulting in distortion of the voltage waveform on the transmission line and even signal oscillation. The transceiver will receive an incorrect signal caused by waveform distortion, thus affecting the correct reception and transmission of data. The increase in this error rate will lead to reliability problems in the system during high-speed and long-distance transmissions.

[0029] Figure 3 The structural schematic diagram of a CAN transceiver according to an embodiment of the present invention is given. The CAN transceiver includes a transmit data port TXD, a receive data port RXD, a control port, a high-side bus port CANH, and a low-side bus port CANL. Among them, the transmit data port TXD receives the transmit data signal TX, the receive data port RXD outputs the received data signal RX, the control port receives the mode control signal MODE, the high-side bus port CANH outputs the high-side signal VH, and the low-side bus port CANL outputs the low-side signal VL.

[0030] When the mode control signal MODE is in the first state and the transmit data signal TX is at a logical low potential, the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V. When the mode control signal MODE is in the first state and the transmit data signal TX is at a logical high potential, the difference between the high-side signal VH and the low-side signal VL is between -1.8V and -3.3V. When the mode control signal MODE is in the second state and the transmit data signal TX is at a logical low potential, the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V. When the mode control signal MODE is in the second state and the transmit data signal TX is at a logical high potential, the difference between the high-side signal VH and the low-side signal VL is between -300mV and 300mV. In one embodiment, when the mode control signal MODE is in the first state, the mode control signal MODE is at a logical high potential, and when the mode control signal MODE is in the second state, the mode control signal MODE is at a logical low potential.

[0031] In Figure 3In the illustrated embodiment, the CAN transceiver further includes a received data port RXD to output a received data signal RX, wherein when the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V, the received data signal RX is at a logic low level, and when the difference between the high-side signal VH and the low-side signal VL is between -1.8V and -3.3V or between -300mV and 300mV, the received data signal RX is at a logic high level. In one embodiment, the CAN transceiver further includes a received data port RXD to output a received data signal RX, wherein when the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V, the received data signal RX is at a logic low level, and when the difference between the high-side signal VH and the low-side signal VL is between -1.8V and -3.3V, the received data signal RX is at a logic high level.

[0032] Figure 4 FIG. 4 shows a schematic circuit diagram of a CAN transceiver according to an embodiment of the present invention. The CAN transceiver further includes a high-side power transistor MH0, a first high-side switch SH1, a second high-side switch SH2, a third high-side switch SH3, a fourth high-side switch SH4, a first low-side switch SL1, a second low-side switch SL2, a third low-side switch SL3, a fourth low-side switch SL4, and a low-side power transistor ML0. The high-side power transistor MH0 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a supply voltage VCC, and the control terminal receives a transmitted data signal TX. It should be noted that the control terminal of the high-side power transistor MH0 receiving the transmitted data signal TX only indicates that the high-side power transistor MH0 is turned on or off under the control of the transmitted data signal TX. In one embodiment, the control terminal of the high-side power transistor MH0 receives a high-side power transistor control signal generated according to the transmitted data signal TX, and the high-side power transistor control signal may be an analog signal, and its voltage value may be set according to the requirements of circuit design. The first high-side switch SH1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor MH0, the second terminal is coupled to a high-side bus port CANH, and the control terminal receives a first high-side control signal TH1. The second high-side switch SH2 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the high-side bus port CANH, and the control terminal receives a second high-side control signal TH2. The third high-side switch SH3 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch SH2, the second terminal receives a first voltage V1, and the control terminal receives a third high-side control signal TH3. The fourth high-side switch SH4 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch SH2, the second terminal receives a second voltage V2, and the control terminal receives a fourth high-side control signal TH4.

[0033] The first low-side switch SL1 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the low-side bus port CANL, and the control terminal receives the first low-side control signal TL1. The second low-side switch SL2 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the low-side bus port CANL, and the control terminal receives the second low-side control signal TL2. The third low-side switch SL3 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the second terminal of the second low-side switch SL2, the second terminal receives the third voltage V3, and the control terminal receives the third low-side control signal TL3. The fourth low-side switch SL4 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the second terminal of the second low-side switch SL2, the second terminal receives the fourth voltage V4, and the control terminal receives the fourth low-side control signal TL4. The low-side power transistor ML0 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the second terminal of the first low-side switch SL1, the second terminal is coupled to the reference ground GND, and the control terminal receives the transmit data non-signal TX1, where the transmit data non-signal TX1 is the complementary signal of the transmit data signal TX. It should be noted that the control terminal of the low-side power transistor ML0 receiving the transmit data non-signal TX1 only indicates that the low-side power transistor ML0 is turned on or off under the control of the transmit data non-signal TX1. In one embodiment, the control terminal of the low-side power transistor ML0 receives a low-side power transistor control signal generated according to the transmit data non-signal TX1. This low-side power transistor control signal can be an analog signal, and its voltage value can be set according to the requirements of the circuit design. In Figure 4 , a load resistor RL is coupled between the high-side bus port CANH and the low-side bus port CANL, and the voltage across the load resistor RL is the load voltage Vdiff.

[0034] When the mode control signal MODE is in different states, each high-side control signal and low-side control signal are at their respective logic potentials to control the conduction and turn-off of their corresponding high-side switches and low-side switches. Exemplarily, the high-side control signal and the low-side control signal both include a logic low potential and a logic high potential. When the logic potential of the control signal changes, the conduction situation of the corresponding switch also changes.

[0035] When the mode control signal MODE is in the first state and the transmit data signal TX is at a logic low level, the high-side power transistor MH0, the first high-side switch SH1, the first low-side switch SL1, and the low-side power transistor ML0 are turned on, and the second high-side switch SH2, the third high-side switch SH3, the fourth high-side switch SH4, the second low-side switch SL2, the third low-side switch SL3, and the fourth low-side switch SL4 are turned off. The high-side power transistor MH0 and the first high-side switch SH1 are turned on, forming a path between the high-side bus port CANH and the supply voltage VCC. The low-side power transistor ML0 and the first low-side switch SL1 are turned on, forming a path between the low-side bus port CANL and the reference ground GND. The current flows from the supply voltage VCC through the load resistor RL to the reference ground GND, and the load voltage Vdiff is between 1.8V and 3.3V. In one embodiment, the value of the load voltage Vdiff is related to the supply voltage VCC, the load resistor RL, and the impedances of the components in the series path. In one embodiment, the load voltage Vdiff is equal to 2.2V.

[0036] When the mode control signal MODE is in the first state and the transmit data signal TX is at a logic high level, the second high-side switch SH2, the fourth high-side switch SH4, the second low-side switch SL2, and the fourth low-side switch SL4 are turned on, and the high-side power transistor MH0, the first high-side switch SH1, the third high-side switch SH3, the first low-side switch SL1, the third low-side switch SL3, and the low-side power transistor ML0 are turned off. The first high-side switch SH1 is turned off, and the line between the high-side bus port CANH and the supply voltage VCC is turned off. At this time, the second high-side switch SH2 and the fourth high-side switch SH4 are turned on, and the high-side bus port CANH receives the first voltage V1. The first low-side switch SL1 is turned off, and the line between the low-side bus port CANL and the reference ground GND is turned off. At this time, the second low-side switch SL2 and the fourth low-side switch SL4 are turned on, and the line between the low-side bus port CANL and the fourth voltage V4 is turned on. In Figure 4 the embodiment, the first voltage V1 is the reference ground GND, the fourth voltage V4 is the supply voltage VCC, and the current flows from the fourth voltage V4 through the load resistor RL to the reference ground GND. At this time, the load voltage Vdiff is between -1.8V and -3.3V. In one embodiment, the value of the load voltage Vdiff is related to the fourth voltage V4, the first voltage V1, the load resistor RL, and the impedances of the components in the series path. In one embodiment, the load voltage Vdiff is -2.2V.

[0037] When the mode control signal MODE is in the second state and the transmit data signal TX is at a logic low level, the high-side power transistor MH0, the first high-side switch SH1, the first low-side switch SL1, and the low-side power transistor ML0 are turned on, and the second high-side switch SH2, the third high-side switch SH3, the fourth high-side switch SH4, the second low-side switch SL2, the third low-side switch SL3, and the fourth low-side switch SL4 are turned off. The current flows from the supply voltage VCC through the load resistor RL to the reference ground GND, and the load voltage Vdiff is between 1.8V and 3.3V. In one embodiment, the value of the load voltage Vdiff is related to the supply voltage VCC and the impedances of the devices in the series path. In one embodiment, the load voltage Vdiff is equal to 2.2V.

[0038] When the mode control signal MODE is in the second state and the transmit data signal TX is at a logic high level, in the first working cycle, the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are turned on, and the high-side power transistor MH0, the first high-side switch SH1, the fourth high-side switch SH4, the first low-side switch SL1, the fourth low-side switch SL4, and the low-side power transistor ML0 are turned off. The high-side signal VH is equal to the low-side signal VL, and the load voltage Vdiff is between -300mV and 300mV. In one embodiment, the load voltage Vdiff is 0V. In the second working cycle, the high-side power transistor MH0, the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the fourth high-side switch SH4, the first low-side switch SL1, the second low-side switch SL2, the third low-side switch SL3, the fourth low-side switch SL4, and the low-side power transistor ML0 are all turned off. The load voltage Vdiff is between -300mV and 300mV. In one embodiment, the load voltage Vdiff is 0V.

[0039] In Figure 4 In the illustrated embodiment, the high-side power transistor MH0 is a P-type field effect transistor, and the low-side power transistor ML0 is an N-type field effect transistor. In one embodiment, the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the fourth high-side switch SH4, the first low-side switch SL1, the second low-side switch SL2, the third low-side switch SL3, and the fourth low-side switch SL4 are N-type field effect transistors.

[0040] In Figure 4In the illustrated embodiment, the CAN transceiver further includes a receive data port RXD to output a receive data signal RX, wherein when the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V, the receive data signal RX is at a logic low level, and when the difference between the high-side signal VH and the low-side signal VL is between -1.8V and -3.3V or between -300mV and 300mV, the receive data signal RX is at a logic high level.

[0041] In one embodiment, the first voltage V1 is between 3.5V - 5.5V, the second voltage V2 is between -1V and 1V, the third voltage V3 is between 3.5V - 5.5V, and the fourth voltage V4 is between 4.5V - 5.5V. In one embodiment, wherein the first voltage V1 and the third voltage V3 are equal to half of the supply voltage VCC, the second voltage V2 is equal to the voltage of the reference ground GND, and the fourth voltage V4 is equal to the supply voltage VCC.

[0042] Figure 5 A Figure 4 waveform diagram of each signal in the illustrated CAN transceiver is given, with reference to Figure 4 the CAN transceiver structure shown in Figure 5 to illustrate the waveforms of each signal in Figure 4 . It should be noted that for Figure 5 the CAN transceiver structure shown, the control logic and waveform conditions of the first low-side control signal TL1 to the fourth low-side control signal TL4 are the same as those of the first high-side control signal TH1 to the fourth high-side control signal TH4. Therefore

[0043] During the time from time t0 to time t1, the mode control signal MODE is in the first state, the transmit data signal TX is at a logic low level. At this time, the first high-side control signal TH1 and the first low-side control signal TL1 are at a logic high level, the second high-side control signal TH2 and the second low-side control signal TL2 are at a logic low level, the third high-side control signal TH3 and the third low-side control signal TL3 are at a logic low level, and the fourth high-side control signal TH4 and the fourth low-side control signal TL4 are at a logic low level. Since the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the fourth high-side switch SH4, the first low-side switch SL1, the second low-side switch SL2, the third low-side switch SL3, and the fourth low-side switch SL4 are all N-type field effect transistors, during the time from time t0 to time t1, the high-side power transistor MH0, the first high-side switch SH1, the first low-side switch SL1, and the low-side power transistor ML0 are conducting, and the second high-side switch SH2, the third high-side switch SH3, the fourth high-side switch SH4, the second low-side switch SL2, the third low-side switch SL3, and the fourth low-side switch SL4 are turned off. During the time from time t0 to time t1, the load voltage Vdiff is 2.2V.

[0044] During the time from time t1 to time t2, the mode control signal MODE is in the first state, the transmit data signal TX is at a logic high level, the first high-side control signal TH1 and the first low-side control signal TL1 are at a logic low level, the second high-side control signal TH2 and the second low-side control signal TL2 are at a logic high level, the third high-side control signal TH3 and the third low-side control signal TL3 are at a logic low level, and the fourth high-side control signal TH4 and the fourth low-side control signal TL4 are at a logic high level. Therefore, during the time from time t1 to time t2, the second high-side switch SH2, the fourth high-side switch SH4, the second low-side switch SL2, and the fourth low-side switch SL4 are conducting, and the high-side power transistor MH0, the first high-side switch SH1, the third high-side switch SH3, the first low-side switch SL1, the third low-side switch SL3, and the low-side power transistor ML0 are turned off. During the time from time t1 to time t2, the load voltage Vdiff is -2.2V.

[0045] During the period from time t2 to time t3, the mode control signal MODE is in the second state, the transmit data signal TX is at a logic low level, the first high-side control signal TH1 and the first low-side control signal TL1 are at logic high levels, the second high-side control signal TH2 and the second low-side control signal TL2 are at logic low levels, the third high-side control signal TH3 and the third low-side control signal TL3 are at logic low levels, and the fourth high-side control signal TH4 and the fourth low-side control signal TL4 are at logic low levels. Therefore, during the period from time t2 to time t3, the high-side power transistor MH0, the first high-side switch SH1, and the first low-side switch SL1 are turned on, and the second high-side switch SH2, the third high-side switch SH3, the fourth high-side switch SH4, the second low-side switch SL2, the third low-side switch SL3, the fourth low-side switch SL4, and the low-side power transistor ML0 are turned off. During the period from time t2 to time t3, the load voltage Vdiff is 2.2V.

[0046] During the period from time t3 to time t4 (the first working cycle), the mode control signal MODE is in the second state, the transmit data signal TX is at a logic high level, the first high-side control signal TH1 and the first low-side control signal TL1 are at logic low levels, the second high-side control signal TH2 and the second low-side control signal TL2 are at logic high levels, the third high-side control signal TH3 and the third low-side control signal TL3 are at logic high levels, and the fourth high-side control signal TH4 and the fourth low-side control signal TL4 are at logic low levels. The high-side power transistor MH0, the first high-side switch SH1, the fourth high-side switch SH4, the low-side power transistor ML0, the first low-side switch SL1, and the fourth low-side switch SL4 are turned off, and the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are turned on. During the period from time t3 to time t4, the load voltage Vdiff is 2.2V.

[0047] During the period from time t4 to time t5 (the second working cycle), the first high-side control signal TH1 and the first low-side control signal TL1 are at logic low levels, the second high-side control signal TH2 and the second low-side control signal TL2 are at logic low levels, the third high-side control signal TH3 and the third low-side control signal TL3 are at logic low levels, and the fourth high-side control signal TH4 and the fourth low-side control signal TL4 are at logic low levels. During the period from time t4 to time t5, the high-side power transistor MH0, the first high-side switch SH1, the fourth high-side switch SH4, the low-side power transistor ML0, the first low-side switch SL1, the fourth low-side switch SL4, the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are all turned off. During the period from time t4 to time t4, the load voltage Vdiff is 2.2V.

[0048] Figure 6 The schematic circuit diagram of a CAN transceiver according to an embodiment of the present invention is given. And Figure 4 Compared with the CAN transceiver shown, the CAN transceiver in this embodiment further includes a high-side withstand voltage circuit 61 and a low-side withstand voltage circuit 62.

[0049] The high-side power transistor MH0 has a first terminal, a second terminal, and a control terminal, wherein the first terminal receives the supply voltage VCC, and the control terminal receives the transmission data signal TX. The first high-side switch SH1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor MH0, and the control terminal receives the first high-side control signal TH1. The high-side withstand voltage circuit 61 has a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor MH0, and the second terminal is coupled to the high-side bus port CANH. The second high-side switch SH2 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first power transistor MH1, and the control terminal receives the second high-side control signal TH2. The third high-side switch SH3 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch SH2, the second terminal is coupled to the first voltage V1, and the control terminal receives the third high-side control signal TH3. The fourth high-side switch SH4 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch SH2, the second terminal is coupled to the second voltage V2, and the control terminal receives the fourth high-side control signal TH4.

[0050] The low-side withstand voltage circuit 62 has a first terminal and a second terminal, wherein the first terminal is coupled to the low-side bus port CANL. The first low-side switch SL1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the low-side withstand voltage circuit 62, and the control terminal receives the first low-side control signal TL1. The second low-side switch SL2 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the low-side withstand voltage circuit 62, and the control terminal receives the second low-side control signal TL2. The third low-side switch SL3 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second low-side switch SL2, the second terminal receives the third voltage V3, and the control terminal receives the third low-side control signal TL3. And the fourth low-side switch SL4 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second low-side switch SL2, the second terminal receives the fourth voltage V4, and the control terminal receives the fourth low-side control signal TL4.

[0051] In Figure 6In the illustrated embodiment, the high-side voltage withstand circuit 61 includes a first power transistor MH1 and a second power transistor MH2, and the low-side voltage withstand circuit 62 includes a third power transistor ML1 and a fourth power transistor ML2. The first power transistor MH1 has a first end, a second end, and a control end, wherein the first end is coupled to the second end of the first high-side switch SH1, and the control end is coupled to the supply voltage VCC. The second power transistor MH2 has a first end, a second end, and a control end, wherein the first end is coupled to the second end of the first power transistor MH1, the second end is coupled to the high-side bus port CANH, and the control end is coupled to the reference ground GND. The third power transistor ML1 has a first end and a second end, wherein the first end is coupled to the low-side bus port CANL, and the control end is coupled to the reference ground GND. The fourth power transistor ML2 has a first end, a second end, and a control end, wherein the first end is coupled to the second end of the third power transistor ML1, and the control end receives the supply voltage VCC.

[0052] In Figure 6 the illustrated embodiment, the first power transistor MH1 and the fourth power transistor ML2 are N-type field effect transistors, and the second power transistor MH2 and the third power transistor ML1 are P-type field effect transistors. Compared with Figure 4 the illustrated embodiment, by adding a high-side voltage withstand circuit composed of the first power transistor MH1 and the second power transistor MH2, and a low-side voltage withstand circuit composed of the third power transistor ML1 and the fourth power transistor ML2, Figure 6 the illustrated CAN transceiver obtains better voltage withstand ability. It should be noted that the high-side voltage withstand circuit 61 composed of the first power transistor MH1 and the second power transistor MH2, and the low-side voltage withstand circuit 62 composed of the third power transistor ML1 and the fourth power transistor ML2 are only illustrative examples, and any circuit structure that can implement the functions of the high-side voltage withstand circuit 61 and the low-side voltage withstand circuit 62 is included in this application.

[0053] Figure 7 FIG. shows a schematic structural diagram of a CAN transceiver according to an embodiment of the present invention. The CAN transceiver includes a transmit data port, a high-side bus port CANH, and a low-side bus port CANL. The transmit data port TXD receives a transmit data signal TX, the high-side bus port CANH outputs a high-side signal VH, and the low-side bus port CANL outputs a low-side signal VL. Wherein, when the transmit data signal TX is at a logic low potential, the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V, and when the transmit data signal TX is at a logic high potential, the difference between the high-side signal VH and the low-side signal VL is between -1.8V and -3.3V.

[0054] In Figure 7In the illustrated embodiment, the CAN transceiver further includes a receive data port RXD to output a receive data signal RX, wherein when the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V, the receive data signal RX is at a logic low level, and when the difference between the high-side signal VH and the low-side signal VL is between -1.8V and -3.3V, the receive data signal RX is at a logic high level.

[0055] Figure 8 FIG. 4 shows a schematic circuit diagram of a CAN transceiver according to an embodiment of the present invention. The high-side power transistor MH0 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a supply voltage VCC, and the control terminal receives a transmit data signal TX. The first high-side switch SH1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor MH0, and the control terminal receives a first high-side control signal TH1. The second high-side switch SH2 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the first high-side switch SH1, and the control terminal receives a second high-side control signal TH2. The third high-side switch SH3 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch SH2, the second terminal is coupled to a first reference voltage VE1, and the control terminal receives a third high-side control signal TH3. The first low-side switch SL1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a low-side bus port CANL, and the control terminal receives a first low-side control signal TL1.

[0056] The low-side power transistor ML0 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the first low-side switch SL1, the second terminal is coupled to a reference ground GND, and the control terminal receives a transmit data not signal TX1, wherein the transmit data not signal TX1 and the transmit data signal TX are complementary signals. The second low-side switch SL2 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first low-side switch SL1, and the control terminal receives a second low-side control signal TL2. The third low-side switch SL3 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second low-side switch SL2, the second terminal receives a second reference voltage VE2, and the control terminal receives a third low-side control signal TL3.

[0057] In Figure 8In the illustrated embodiment, when the transmitted data signal TX is at a logic low potential, the high-side power transistor MH0, the first high-side switch SH1, the first low-side switch SL1, and the low-side power transistor ML0 are turned on, and the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are all turned off, such that the line between the high-side bus port CANH and the supply voltage VCC is turned on, and the line between the low-side bus port CANL and the reference ground GND is turned on. The current flows through the load resistor RL, and the load voltage Vdiff is between 1.8V and 3.3V. When the transmitted data signal TX is at a logic high, the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are all turned on, such that the line between the high-side bus port CANH and the first reference voltage VE1 is turned on, and the line between the low-side bus port CANL and the second reference voltage VE2 is turned on. The high-side power transistor MH0, the first high-side switch SH1, the first low-side switch SL1, and the low-side power transistor ML0 are turned off, such that the line between the high-side bus port CANH and the supply voltage VCC is turned off, and the line between the low-side bus port CANL and the reference ground GND is turned off. In Figure 8 In the illustrated embodiment, the first reference voltage VE1 is the voltage of the reference ground, the second reference voltage VE2 is the supply voltage VCC, and the load voltage Vdiff is between -1.8V and -3.3V.

[0058] In Figure 8 In the illustrated embodiment, the high-side power transistor MH0 is a P-type field effect transistor, and the low-side power transistor ML0 is an N-type field effect transistor. In Figure 8 In the illustrated embodiment, the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the first low-side switch SL1, the second low-side switch SL2, and the third low-side switch SL3 are N-type field effect transistors. In Figure 8 In the illustrated embodiment, the voltage value of the supply voltage VCC is between 4.5V - 5.5V. The voltage value of the first reference voltage VE1 is between -1V and 1V, and the voltage value of the second reference voltage VE2 is between 3.5V - 5.5V. In Figure 8 In the illustrated embodiment, the CAN transceiver further includes a received data port RXD to output a received data signal RX, wherein when the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V, the received data signal RX is at a logic low potential, and when the difference between the high-side signal VH and the low-side signal VL is between -1.8V and -3.3V, the received data signal RX is at a logic high potential. In Figure 8 In, the CAN transceiver further has an output resistance Rdiff, and the output resistance Rdiff is the resistance between the high-side bus port CANH and the low-side bus port CANL of the CAN transceiver. For example, in Figure 8In the illustrated embodiment, when the transmission data signal TX is at a logic low level, the high-side power transistor MH0, the first high-side switch SH1, the first low-side switch SL1, and the low-side power transistor ML0 are all turned on. At this time, the output resistance Rdiff is the sum of the on-resistances of the high-side power transistor MH0, the first high-side switch SH1, the first low-side switch SL1, and the low-side power transistor ML0. In one embodiment, when the transmission data signal TX is at a logic low level, the output resistance Rdiff is 40Ω. When the transmission data signal TX is at a logic high level, the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are all turned on. At this time, the output resistance Rdiff is the sum of the on-resistances of the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3. In one embodiment, when the transmission data signal TX is at a logic high level, the output resistance Rdiff is 40Ω.

[0059] Figure 9 gives Figure 8 the waveform diagrams of the signals in the illustrated CAN transceiver, with reference to Figure 8 the CAN transceiver structure shown in Figure 9 explain the waveforms of the signals in

[0060] During the period from time t0 to time t1, the transmission data signal TX is at a logic low potential. At this time, the first high-side control signal TH1 and the first low-side control signal TL1 are at a logic high potential, the second high-side control signal TH2 and the second low-side control signal TL2 are at a logic low potential, and the third high-side control signal TH3 and the third low-side control signal TL3 are at a logic low potential. Since the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the first low-side switch SL1, the second low-side switch SL2, and the third low-side switch SL3 are all N-type field-effect transistors, during the period from time t0 to time t1, the high-side power transistor MH0, the low-side power transistor ML0, the first high-side switch SH1, and the first low-side switch SH1 are turned on, and the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are all turned off. During the period from time t0 to time t1, the load voltage Vdiff is 2.2V.

[0061] During the period from time t1 to time t2, the transmission data signal TX is at a logic high potential, the first high-side control signal TH1 and the first low-side control signal TL1 are at logic low potentials, the second high-side control signal TH2 and the second low-side control signal TL2 are at logic high potentials, and the third high-side control signal TH3 and the third low-side control signal TL3 are at logic high potentials. Therefore, during the period from time t1 to time t2, the second high-side switch SH2, the second low-side switch SL2, the third high-side switch SH3, and the third low-side switch SL3 are all turned on, and the high-side power transistor MH0, the low-side power transistor ML0, the first high-side switch SH1, and the first low-side switch SL1 are turned off. During the period from time t1 to time t2, the load voltage Vdiff is -2.2V.

[0062] During the period from time t0 to time t2, the output impedance Rdiff between the high-side bus VH and the low-side bus VL remains unchanged at 40Ω.

[0063] Figure 10 The circuit structure diagram of a CAN transceiver according to an embodiment of the present invention is given. It includes a transmission data port TXD for receiving the transmission data signal TX, a high-side bus port CANH for outputting the high-side signal VH, and a low-side bus port CANL for outputting the low-side signal VL. The high-side power transistor MH0 has a first end, a second end, and a control end, where the first end receives the supply voltage VCC and the control end receives the transmission data signal TX. The first high-side switch SH1 has a first end, a second end, and a control end, where the first end is coupled to the second end of the high-side power transistor MH0, the second end is coupled to the high-side bus port CANH, and the control end receives the first high-side control signal TH1. The second high-side switch SH2 has a first end, a second end, and a control end, where the first end is coupled to the second end of the first high-side switch SH1 and the control end receives the second high-side control signal TH2. The third high-side switch SH3 has a first end, a second end, and a control end, where the first end is coupled to the second end of the second high-side switch SH2, the second end is coupled to the first preset voltage VS1, and the control end receives the third high-side control signal TH3.

[0064] The first low-side switch SL1 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the low-side bus port CANL, and the control terminal receives the first low-side control signal TL1. The low-side power transistor ML0 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the second terminal of the first low-side switch SL1, the second terminal is coupled to the reference ground GND, and the control terminal receives the transmit data non-signal TX1, where the transmit data non-signal TX1 and the transmit data signal TX are complementary signals. The second low-side switch SL2 has a first terminal, a second terminal, and a control terminal, where the first terminal is coupled to the low-side bus port CANL, and the control terminal receives the second low-side control signal TL2. And the third low-side switch SL3 has a first terminal, a second terminal, and a control terminal, where the first terminal receives the second preset voltage VS2, the second terminal is coupled to the second terminal of the second low-side switch SL2, and the control terminal receives the third low-side control signal TL3. Wherein, when the transmit data signal TX is at a logical low potential, the difference between the high-side signal VH and the low-side signal VL is between 1.8V and 3.3V, and when the transmit data signal TX is at a logical high potential, the difference between the high-side signal VH and the low-side signal VL is between -300mV and 300mV.

[0065] In Figure 10 In the illustrated embodiment, when the transmit data signal TX is at a logical low potential, the high-side power transistor MH0, the first high-side switch SH1, the low-side power transistor ML0, and the first low-side switch SL1 are turned on, and the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are turned off. The high-side power transistor MH0, the low-side power transistor ML0, the first high-side switch SH1, and the first low-side switch SH1 are turned on, such that the line between the high-side bus port CANH and the supply voltage VCC is turned on, and the line between the low-side bus port CANL and the reference ground GND is turned on, and current flows through the load resistor RL, and the load voltage Vdiff is between 1.8V and 3.3V.

[0066] When the transmit data signal TX is at a logical high, in the first working cycle, the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are turned on, and the high-side power transistor MH0, the first high-side switch SH1, the low-side power transistor ML0, and the first low-side switch SL1 are turned off. The high-side power transistor MH0, the low-side power transistor ML0, the first high-side switch SH1, and the first low-side switch SL1 are turned off, such that the line between the high-side bus port CANH and the supply voltage VCC is turned off, and the line between the low-side bus port CANL and the reference ground GND is turned off. The second high-side switch SH2, the second low-side switch SL2, the third high-side switch SH3, and the third low-side switch SL3 are all turned on, such that the line between the high-side bus port CANH and the first preset voltage VS1 is turned on, and the line between the low-side bus port CANL and the second preset voltage VS2 is turned on. InFigure 10 In the illustrated embodiment, the first preset voltage VS1 is half of the supply voltage VCC, the second preset voltage VS2 is half of the supply voltage VCC, and the load voltage Vdiff is between -300 mV and 300 mV. In the second working cycle, the high-side power transistor MH0, the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the first low-side switch SL1, the low-side power transistor ML0, the second low-side switch SL2, and the third low-side switch SL3 are all turned off, so that the line between the high-side bus port CANH and the supply voltage VCC is turned off, and the line between the low-side bus port CANL and the reference ground GND is turned off, and the load voltage Vdiff is between -300 mV and 300 mV.

[0067] In Figure 10 the illustrated embodiment, the CAN transceiver further includes a receive data port to output a receive data signal RX, where when the difference between the high-side signal VH and the low-side signal VL is between 1.8 V and 3.3 V, the receive data signal RX is at a logic low level, and when the difference between the high-side signal VH and the low-side signal VL is between -300 mV and 300 mV, the receive data signal RX is at a logic high level.

[0068] In Figure 10 the illustrated embodiment, the high-side power transistor MH0 is a P-type field-effect transistor, and the low-side power transistor ML0 is an N-type field-effect transistor. The first high-side switch SH1, the second high-side switch SH2, and the third high-side switch SH3 are N-type field-effect transistors. The voltage value of the supply voltage VCC is between 4.5 V and 5.5 V. The first preset voltage VS1 is equal to the second preset voltage VS2, where the voltage value of the first preset voltage VS1 is half of the supply voltage VCC.

[0069] Figure 11 The Figure 10 waveform diagrams of the signals in the illustrated CAN transceiver are given. Refer to Figure 10 the structure of the illustrated CAN transceiver to Figure 11 describe the waveforms of the signals in

[0070] During the period from time t0 to time t1, the transmitted data signal TX is at a logic low potential. At this time, the first high-side control signal TH1 and the first low-side control signal TL1 are at a logic high potential, the second high-side control signal TH2 and the second low-side control signal TL2 are at a logic low potential, and the third high-side control signal TH3 and the third low-side control signal TL3 are at a logic low potential. Since the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the first low-side switch SL1, the second low-side switch SL2, and the third low-side switch SL3 are all N-type field-effect transistors, during the period from time t0 to time t1, the high-side power transistor MH0, the first high-side switch SH1, the low-side power transistor ML0, and the first low-side switch SL1 are turned on, and the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are turned off. During the period from time t0 to time t1, the load voltage Vdiff is 2.2V, and the output impedance Rdiff is 40Ω.

[0071] During the period from time t1 to time t2 (the first working cycle), the transmitted data signal TX is at a logic high potential, the first high-side control signal TH1 and the first low-side control signal TL1 are at a logic low potential, the second high-side control signal TH2 and the second low-side control signal TL2 are at a logic high potential, the third high-side control signal TH3 and the third low-side control signal TL3 are at a logic high potential, the second high-side switch SH2, the third high-side switch SH3, the second low-side switch SL2, and the third low-side switch SL3 are turned on, and the high-side power transistor MH0, the first high-side switch SH1, the low-side power transistor ML0, and the first low-side switch SL1 are turned off. During the period from time t1 to time t2, the load voltage Vdiff is 0V, and the output impedance Rdiff is 100Ω.

[0072] During the period from time t2 to time t3 (the second working cycle), the first high-side control signal TH1 and the first low-side control signal TL1 are at a logic low potential, the second high-side control signal TH2 and the second low-side control signal TL2 are at a logic low potential, the third high-side control signal TH3 and the third low-side control signal TL3 are at a logic low potential, and the high-side power transistor MH0, the first high-side switch SH1, the second high-side switch SH2, the third high-side switch SH3, the first low-side switch SL1, the low-side power transistor ML0, the second low-side switch SL2, and the third low-side switch SL3 are all turned off. During the period from time t2 to time t3, the load voltage Vdiff is 0V, and the output impedance Rdiff is 40kΩ.

[0073] Figure 11 , which shows a switching form of the multimodal output of the CAN transceiver. As Figure 11As shown, exemplarily, when the transmitted data signal TX is at a logical low potential, the CAN transceiver is in the first mode. When the transmitted data signal TX is at a logical high potential, the CAN transceiver is in the second mode or the third mode according to different duty cycles. The CAN transceiver switches between the first mode, the third mode, and the second mode according to the different transmitted data signal TX. Through the multi-mode output of the CAN transceiver, the bus ringing problem can be eliminated by adjusting the output voltage and output impedance. In this process, the output characteristics in different modes can smoothly affect the bus signal, thereby reducing the occurrence of ringing. Specifically, in the first mode, by generating a specific load voltage and differential impedance, potential signal reflections and interferences can be suppressed, keeping the bus stable. In the third mode, by outputting a load voltage of 0V and a higher differential impedance, signal fluctuations and reflections are effectively reduced, thereby improving the quality of the bus signal. After entering the second mode, a load voltage of 0V and an appropriate differential impedance are generated to further ensure the stability of data transmission on the bus and eliminate the ringing phenomenon.

[0074] Therefore, by sequentially switching these modes, the CAN transceiver can effectively adjust the characteristics of the output voltage, reduce signal interference, and optimize the quality of bus communication, thus solving the ringing problem. This method helps to maintain the stability and reliability of the bus signal, and improves the accuracy and stability of data transmission without affecting the normal communication protocol level.

[0075] In the embodiments of the present invention, one or more high-side switches and low-side switches can be configured according to actual situations, rather than being limited to three or four, which are all within the scope of patent protection of this application.

[0076] In addition, the access point of the second low-side switch SL2 and the second high-side switch SH2 can be the position shown in Figure 4-10 or can be selected to be connected to any node on the line between the high-side bus port CANH and the first high-side switch SH1, and the low-side bus port CANL and the first low-side switch SL1. That is to say, when building the circuit, the connection method of the second low-side switch SL2 and the second high-side switch SH2 can be flexibly selected.

[0077] Moreover, for all the switches shown in Figure 4-10 , this application does not limit the type of the device. In actual design and manufacturing, a suitable switch device type can be selected according to specific situations. And it is not limited to the number settings of voltages such as the first voltage V1, the second voltage V2, the third voltage V3, the fourth voltage V4, the first reference voltage VE1, and the second reference voltage VE2. According to the circuit structure design, it can include one voltage port or multiple voltage ports. For example, they can also be floating potentials, that is, there is no clearly defined voltage form limit.

[0078] While the invention has been described with reference to several exemplary embodiments, it should be understood that the terms used are illustrative and exemplary rather than restrictive. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be construed broadly within the spirit and scope defined by the appended claims, and thus all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A CAN transceiver, comprising: A transmit data port for receiving a transmit data signal; A control port for receiving a mode control signal; A high-side bus port for outputting a high-side signal; And A low-side bus port for outputting a low-side signal; Wherein, when the mode control signal is in the first state and the transmit data signal is at a logic low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V; when the mode control signal is in the first state and the transmit data signal is at a logic high potential, the difference between the high-side signal and the low-side signal is between -1.8V and -3.3V; When the mode control signal is in the second state and the transmit data signal is at a logic low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V; when the mode control signal is in the second state and the transmit data signal is at a logic high potential, the difference between the high-side signal and the low-side signal is between -300mV and 300mV; The CAN transceiver further includes a receive data port for outputting a receive data signal, wherein when the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V, the receive data signal is at a logic low potential, and when the difference between the high-side signal and the low-side signal is between -3.3V and -1.8V or between -300mV and 300mV, the receive data signal is at a logic high potential.

2. The CAN transceiver according to claim 1, wherein when the mode control signal is in the first state, the mode control signal is at a logic high potential, and when the mode control signal is in the second state, the mode control signal is at a logic low potential.

3. The CAN transceiver according to claim 1, further comprising: A high-side power transistor having a first end, a second end, and a control end, wherein the first end receives a supply voltage and the control end receives the transmit data signal; A first high-side switch having a first end, a second end, and a control end, wherein the first end is coupled to the second end of the high-side power transistor, the second end is coupled to the high-side bus port, and the control end receives a first high-side control signal; A second high-side switch having a first end, a second end, and a control end, wherein the first end is coupled to the high-side bus port and the control end receives a second high-side control signal; A third high-side switch having a first end, a second end, and a control end, wherein the first end is coupled to the second end of the second high-side switch, the second end receives a first voltage, and the control end receives a third high-side control signal; A fourth high-side switch having a first end, a second end, and a control end, wherein the first end is coupled to the second end of the second high-side switch, the second end receives a second voltage, and the control end receives a fourth high-side control signal; A first low-side switch having a first end, a second end, and a control end, wherein the first end is coupled to the low-side bus port and the control end receives a first low-side control signal; A second low-side switch having a first end, a second end, and a control end, wherein the first end is coupled to the low-side bus port and the control end receives a second low-side control signal; A third low-side switch having a first end, a second end, and a control end, wherein the first end is coupled to the second end of the second low-side switch, the second end receives a third voltage, and the control end receives a third low-side control signal; The fourth low-side switch, having a first end, a second end and a control end, wherein the first end is coupled to the second end of the second low-side switch, the second end receives a fourth voltage, and the control end receives a fourth low-side control signal; and A low-side power transistor, having a first end, a second end and a control end, wherein the first end is coupled to the second end of the first low-side switch, the second end is coupled to a reference ground, and the control end receives a transmit data not signal, where the transmit data not signal is a complementary signal of the transmit data signal.

4. The CAN transceiver according to claim 3, wherein When the mode control signal is in the first state and the transmit data signal is at a logic low level, the high-side power transistor, the first high-side switch, the low-side power transistor and the first low-side switch are turned on; the second high-side switch, the third high-side switch, the fourth high-side switch, the second low-side switch, the third low-side switch and the fourth low-side switch are turned off; When the mode control signal is in the first state and the transmit data signal is at a logic high level, the second high-side switch, the fourth high-side switch, the second low-side switch and the fourth low-side switch are turned on, and the high-side power transistor, the first high-side switch, the third high-side switch, the first low-side switch, the third low-side switch and the low-side power transistor are turned off; When the mode control signal is in the second state and the transmit data signal is at a logic low level, the high-side power transistor, the first high-side switch, the first low-side switch and the low-side power transistor are turned on, and the second high-side switch, the third high-side switch, the fourth high-side switch, the second low-side switch, the third low-side switch and the fourth low-side switch are turned off; When the mode control signal is in the second state and the transmit data signal is at a logic high level, in the first working cycle, the second high-side switch, the third high-side switch, the second low-side switch and the third low-side switch are turned on, and the high-side power transistor, the first high-side switch, the fourth high-side switch, the first low-side switch, the fourth low-side switch and the low-side power transistor are turned off. In the second working cycle, the high-side power transistor, the first high-side switch, the second high-side switch, the third high-side switch, the fourth high-side switch, the first low-side switch, the second low-side switch, the third low-side switch, the fourth low-side switch and the low-side power transistor are all turned off.

5. The CAN transceiver according to claim 3, wherein the high-side power transistor is a P-type field effect transistor.

6. The CAN transceiver according to claim 3, wherein the low-side power transistor is an N-type field effect transistor.

7. The CAN transceiver according to claim 3, wherein the first high-side switch, the second high-side switch, the third high-side switch and the fourth high-side switch are N-type field effect transistors.

8. The CAN transceiver according to claim 3, wherein the first voltage is between 3.5V and 5.5V, the second voltage is between -1V and 1V, the third voltage is between 3.5V and 5.5V, and the fourth voltage is between 4.5V and 5.5V.

9. The CAN transceiver according to claim 3, wherein the first voltage and the third voltage are equal to half of the supply voltage, the second voltage is equal to the voltage of the reference ground, and the fourth voltage is equal to the supply voltage.

10. The CAN transceiver according to claim 1, further comprising High-side power transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal receives a supply voltage and the control terminal receives a transmission data signal; First high-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor and the control terminal receives a first high-side control signal; High-side withstand voltage circuit, having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor and the second terminal is coupled to a high-side bus port; Second high-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the high-side withstand voltage circuit and the control terminal receives a second high-side control signal; Third high-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch, the second terminal is coupled to a first voltage, and the control terminal receives a third high-side control signal; Fourth high-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch, the second terminal is coupled to a second voltage, and the control terminal receives a fourth high-side control signal; Low-side withstand voltage circuit, having a first terminal and a second terminal, wherein the first terminal is coupled to a low-side bus port; First low-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the low-side withstand voltage circuit and the control terminal receives a first low-side control signal; Second low-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the low-side withstand voltage circuit and the control terminal receives a second low-side control signal; Third low-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the second low-side switch, the second terminal receives a third voltage, and the control terminal receives a third low-side control signal; and Fourth low-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the second low-side switch, the second terminal receives a fourth voltage, and the control terminal receives a fourth low-side control signal.

11. A CAN transceiver, comprising: A transmission data port for receiving a transmission data signal; A high-side bus port for outputting a high-side signal; And A low-side bus port for outputting a low-side signal; wherein, when the transmission data signal is at a logic low potential, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V, and when the transmission data signal is at a logic high potential, the difference between the high-side signal and the low-side signal is between -1.8V and -3.3V; The CAN transceiver further includes a reception data port for outputting a reception data signal, wherein when the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V, the reception data signal is at a logic low potential, and when the difference between the high-side signal and the low-side signal is between -1.8V and -3.3V, the reception data signal is at a logic high potential.

12. The CAN transceiver according to claim 11, comprising: High-side power transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal receives a supply voltage and the control terminal receives a transmission data signal; First high-side switch, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor and the control terminal receives a first high-side control signal; A second high-side switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the first high-side switch, and the control terminal receives a second high-side control signal; A third high-side switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch, the second terminal is coupled to a first reference voltage, and the control terminal receives a third high-side control signal; A first low-side switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a low-side bus port, and the control terminal receives a first low-side control signal; A low-side power transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the first low-side switch, the second terminal is coupled to a reference ground, and the control terminal receives a transmit data not signal, wherein the transmit data not signal and the transmit data signal are complementary signals; A second low-side switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first low-side switch, and the control terminal receives a second low-side control signal; and A third low-side switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second low-side switch, the second terminal receives a second reference voltage, and the control terminal receives a third low-side control signal.

13. The CAN transceiver according to claim 12, wherein when the transmit data signal is at a logic low level, the high-side power transistor, the first high-side switch, the first low-side switch, and the low-side power transistor are turned on, and the second high-side switch, the third high-side switch, the second low-side switch, and the third low-side switch are all turned off; when the transmit data signal is at a logic high level, the second high-side switch, the third high-side switch, the second low-side switch, and the third low-side switch are all turned on, and the high-side power transistor, the first high-side switch, the first low-side switch, and the low-side power transistor are turned off.

14. The CAN transceiver according to claim 12, wherein the high-side power transistor is a P-type field effect transistor.

15. The CAN transceiver according to claim 12, wherein the low-side power transistor is an N-type field effect transistor.

16. The CAN transceiver according to claim 12, wherein the first high-side switch, the second high-side switch, and the third high-side switch are N-type field effect transistors.

17. The CAN transceiver according to claim 12, wherein the voltage value of the supply voltage is between 4.5V and 5.5V.

18. The CAN transceiver according to claim 12, wherein the voltage value of the first reference voltage is between -1V and 1V, and the voltage value of the second reference voltage is between 4.5V and 5.5V.

19. A CAN transceiver, comprising: A transmit data port that receives a transmit data signal; A high-side bus port that outputs a high-side signal; A low-side bus port that outputs a low-side signal; A high-side power transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal receives a supply voltage, and the control terminal receives a transmit data signal; A first high-side switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the high-side power transistor, the second terminal is coupled to the high-side bus port, and the control terminal receives a first high-side control signal; The second high-side switch has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the first high-side switch, and the control terminal receives a second high-side control signal; The third high-side switch has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the second high-side switch, the second terminal is coupled to a first preset voltage, and the control terminal receives a third high-side control signal; The first low-side switch has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a low-side bus port, and the control terminal receives a first low-side control signal; The low-side power transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the first low-side switch, the second terminal is coupled to a reference ground, and the control terminal receives a transmit data not signal, wherein the transmit data not signal and the transmit data signal are complementary signals; The second low-side switch has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a low-side bus port, and the control terminal receives a second low-side control signal; and The third low-side switch has a first terminal, a second terminal, and a control terminal, wherein the first terminal receives a second preset voltage, the second terminal is coupled to the second terminal of the second low-side switch, and the control terminal receives a third low-side control signal; wherein, when the transmit data signal is at a logic low level, the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V, and when the transmit data signal is at a logic high level, the difference between the high-side signal and the low-side signal is between -300mV and 300mV; The CAN transceiver further includes a receive data port for outputting a receive data signal, wherein when the difference between the high-side signal and the low-side signal is between 1.8V and 3.3V, the receive data signal is at a logic low level, and when the difference between the high-side signal and the low-side signal is between -300mV and 300mV, the receive data signal is at a logic high level.

20. The CAN transceiver according to claim 19, when the transmit data signal is at a logic low level, the high-side power transistor, the first high-side switch, the first low-side switch, and the low-side power transistor are turned on, and the second high-side switch, the third high-side switch, the second low-side switch, and the third low-side switch are turned off; When the transmit data signal is at a logic high level, in the first operating cycle, the second high-side switch, the third high-side switch, the second low-side switch, and the third low-side switch are turned on, and the high-side power transistor, the first high-side switch, the first low-side switch, and the low-side power transistor are turned off; In the second operating cycle, the high-side power transistor, the first high-side switch, the second high-side switch, the third high-side switch, the first low-side switch, the second low-side switch, the third low-side switch, and the low-side power transistor are all turned off.

21. The CAN transceiver according to claim 19, wherein the high-side power transistor is a P-type field effect transistor.

22. The CAN transceiver according to claim 19, wherein the low-side power transistor is an N-type field effect transistor.

23. The CAN transceiver according to claim 19, wherein the first high-side switch, the second high-side switch, and the third high-side switch are N-type field effect transistors.

24. The CAN transceiver according to claim 19, wherein the voltage value of the supply voltage is between 4.5V - 5.5V.

25. The CAN transceiver according to claim 19, wherein the first preset voltage is equal to the second preset voltage.

26. The CAN transceiver according to claim 19, wherein the voltage value of the first preset voltage is half of the supply voltage.

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