Chip testing method and chip

Abstract

The present invention discloses a chip testing method and a chip. The chip to be tested first receives a detection instruction including a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction. Then, based on the detection mode conversion instruction and the detection time node instruction, the normal working mode is switched to an internal signal detection mode, and an internal signal corresponding to the detection signal selection instruction is obtained. Finally, after converting the obtained internal signal, a target single-bit signal obtained by conversion is output, and a detection device determines whether the chip to be tested meets a preset standard according to the target single-bit signal. Since the internal signal of the chip to be tested can be detected in the embodiment of the present application, and a target single-bit signal corresponding to the obtained internal signal is output, therefore, when judging whether the chip meets the preset standard, the position of the failure of the chip to be tested can be determined based on the target single-bit signal, thereby improving the accuracy of the chip test.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a chip testing method and a chip. Background Art

[0002] Chips are an important component of electronic products. The stability and reliability of their performance directly affect the overall quality of electronic products. Therefore, chip testing is very important in the chip manufacturing process. Measuring the quality of chips is crucial to ensuring the performance of electronic products.

[0003] At present, the chip testing method usually detects the output signal through the pins after packaging is completed, and cannot detect the internal signal of the chip. Therefore, when the chip fails, the failure position cannot be accurately located. Summary of the invention

[0004] The present invention provides a chip testing method and a chip, which are used to solve the problem in the prior art that when a chip fails, the failure position cannot be accurately located.

[0005] In a first aspect, the present application provides a chip testing method, the method comprising:

[0006] Receiving a detection instruction, wherein the detection instruction includes a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction;

[0007] Based on the detection mode conversion instruction and the detection time node instruction, switching from the normal working mode to the internal signal detection mode;

[0008] Acquire an internal signal corresponding to the detection signal selection instruction;

[0009] After converting the acquired internal signal, the target single-bit signal obtained by the conversion is output, and the detection device determines whether the chip to be tested meets the preset standard according to the target single-bit signal.

[0010] In a possible implementation, switching from the normal working mode to the internal signal detection mode based on the detection mode conversion instruction and the detection time node instruction includes:

[0011] After receiving the detection mode conversion instruction, the normal working mode is switched to the internal signal detection mode after the detection duration carried in the detection time node instruction is reached.

[0012] In a possible implementation, the internal signal includes a multi-bit signal, and after converting the acquired internal signal, outputting a target single-bit signal obtained by the conversion includes:

[0013] Based on the bit positions of the multi-bit signal, the multi-bit signal is converted into a target single-bit signal, and the target single-bit signal is output.

[0014] In a possible implementation, the internal signal includes a plurality of single-bit signals, and the detection signal selection instruction corresponds to the single-bit signal one-to-one;

[0015] After converting the acquired internal signal, outputting the converted target single-bit signal comprises:

[0016] The priorities of the instructions are selected based on the plurality of detection signals, the plurality of single-bit signals are converted into the target single-bit signal, and the target single-bit signal is output.

[0017] In a possible implementation, the selecting the priority of the instruction based on the plurality of detection signals to convert the plurality of single-bit signals into the target single-bit signal includes:

[0018] Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priorities of the plurality of detection signal selection instructions from high to low;

[0019] Using the single-bit signals output in sequence as the target single-bit signal; or

[0020] Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priority of the plurality of detection signal selection instructions from low to high;

[0021] The single-bit signals output in sequence are used as the target single-bit signals.

[0022] In a possible implementation, the internal signal includes a plurality of multi-bit signals, and the detection signal selection instruction corresponds one-to-one to the multi-bit signals;

[0023] After converting the acquired internal signal, outputting the converted target single-bit signal comprises:

[0024] Based on the priorities of the plurality of detection signal selection instructions, determining the priority of the multi-bit signal corresponding to each detection signal selection instruction;

[0025] The chip under test performs the following processing on each multi-bit signal in order of priority from high to low:

[0026] The chip under test converts the multi-bit signal into a single-bit signal based on the bit position of the multi-bit signal;

[0027] The chip under test uses the signal composed of the converted single-bit signal as the target single-bit signal, and outputs the target single-bit signal.

[0028] In a possible implementation manner, before the chip under test outputs the target single-bit signal, the method further includes:

[0029] Determine the starting signal;

[0030] After the start signal is output, the target single-bit signal is output.

[0031] In a second aspect, the present application provides a chip, including:

[0032] An input port, used to receive a detection instruction, wherein the detection instruction includes a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction;

[0033] A mode conversion module, used for switching from a normal working mode to an internal signal detection mode based on the detection mode conversion instruction and the detection time node instruction;

[0034] An internal signal detection module, used to obtain an internal signal corresponding to the detection signal selection instruction; after converting the obtained internal signal, a target single-bit signal is obtained;

[0035] The output port is used to output the target single-bit signal obtained by conversion, and the detection device determines whether the chip meets the preset standard based on the target single-bit signal.

[0036] In a possible implementation, the mode conversion module is specifically used to:

[0037] After receiving the detection mode conversion instruction, the normal working mode is switched to the internal signal detection mode after the detection duration carried in the detection time node instruction is reached.

[0038] In a possible implementation manner, the internal signal includes a multi-bit signal, and the internal signal detection module is specifically used to:

[0039] Based on the bit positions of the multi-bit signal, the multi-bit signal is converted into a target single-bit signal, and the target single-bit signal is output.

[0040] In a possible implementation, the internal signal includes a plurality of single-bit signals, and the detection signal selection instruction corresponds one-to-one to the single-bit signal;

[0041] The internal signal detection module is specifically used for:

[0042] The priorities of the instructions are selected based on the plurality of detection signals, the plurality of single-bit signals are converted into the target single-bit signal, and the target single-bit signal is output.

[0043] In a possible implementation manner, the internal signal detection module is specifically used to:

[0044] Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priorities of the plurality of detection signal selection instructions from high to low;

[0045] Using the single-bit signals output in sequence as the target single-bit signal; or

[0046] Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priority of the plurality of detection signal selection instructions from low to high;

[0047] The single-bit signals output in sequence are used as the target single-bit signals.

[0048] In a possible implementation, the internal signal includes a plurality of multi-bit signals, and the detection signal selection instruction corresponds one-to-one to the multi-bit signals;

[0049] The internal signal detection module is specifically used for:

[0050] Based on the priorities of the plurality of detection signal selection instructions, determining the priority of the multi-bit signal corresponding to each detection signal selection instruction;

[0051] The following processing is performed on each multi-bit signal in descending order of priority:

[0052] Based on the bit position of the multi-bit signal, convert the multi-bit signal into a single-bit signal;

[0053] The signal composed of the converted single-bit signals is used as the target single-bit signal, and the target single-bit signal is output.

[0054] In a possible implementation manner, before outputting the single-bit signal, the internal signal detection module is further configured to:

[0055] Determine the starting signal;

[0056] After the start signal is output, the target single-bit signal is output.

[0057] The beneficial effects of the present invention are as follows:

[0058] The embodiment of the present application provides a chip testing method and chip, in which the chip to be tested first receives a detection instruction including a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction, and then switches from a normal working mode to an internal signal detection mode based on the detection mode conversion instruction and the detection time node instruction, obtains an internal signal corresponding to the detection signal selection instruction, and finally converts the obtained internal signal, outputs the converted target single-bit signal, and the detection device determines whether the chip to be tested meets the preset standard based on the target single-bit signal. Since the internal signal of the chip to be tested can be detected in the embodiment of the present application, and the target single-bit signal corresponding to the obtained internal signal is output, therefore, when analyzing whether the chip meets the preset standard, the location of the failure of the chip to be tested can be determined based on the target single-bit signal, thereby improving the accuracy of the chip test. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0060] Figure 1 A schematic diagram of a chip testing method provided in an embodiment of the present application;

[0061] Figure 2 A schematic diagram of the structure of a detection instruction provided in an embodiment of the present application;

[0062] Figure 3 A schematic diagram of internal signal conversion provided by an embodiment of the present application;

[0063] Figure 4 A schematic diagram of another internal signal conversion provided in an embodiment of the present application;

[0064] Figure 5 A schematic diagram of another internal signal conversion provided in an embodiment of the present application;

[0065] Figure 6 A schematic diagram of another internal signal conversion provided in an embodiment of the present application;

[0066] Figure 7 A schematic diagram of another internal signal conversion provided in an embodiment of the present application;

[0067] Figure 8 A schematic diagram of another internal signal conversion provided in an embodiment of the present application;

[0068] Fig. 9A schematic diagram of another internal signal conversion provided in an embodiment of the present application;

[0069] Fig.10 A schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] Chips are the result of the development of contemporary science and technology, and they play an irreplaceable role in various fields such as military and civilian use. The current chip testing method is to detect the final output signal of the chip through the pins after packaging. This only detects external signals, and cannot accurately detect important signals and working conditions inside the chip. The internal signals and working conditions of the chip to be tested are conducive to the failure analysis of the chip.

[0072] A chip testing method and a chip provided in an embodiment of the present application are described in detail below with reference to the accompanying drawings.

[0073] like Figure 1 FIG. 1 is a flow chart of a chip testing method provided in an embodiment of the present application, which specifically includes the following steps:

[0074] S101, receiving a detection instruction, wherein the detection instruction includes a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction;

[0075] S102, switching from the normal working mode to the internal signal detection mode based on the detection mode conversion instruction and the detection time node instruction;

[0076] S103, acquiring an internal signal corresponding to the detection signal selection instruction;

[0077] S104, after converting the acquired internal signal, outputting the converted target single-bit signal, the detection device determines whether the chip to be tested meets the preset standard according to the target single-bit signal.

[0078] A chip testing method provided in an embodiment of the present application, the chip to be tested first receives a detection instruction including a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction, and then switches from a normal working mode to an internal signal detection mode based on the detection mode conversion instruction and the detection time node instruction, obtains an internal signal corresponding to the detection signal selection instruction, and finally converts the obtained internal signal, outputs the converted target single-bit signal, and the detection device determines whether the chip to be tested meets a preset standard based on the target single-bit signal. Since the internal signal of the chip to be tested can be detected in the embodiment of the present application, and the target single-bit signal corresponding to the obtained internal signal is output, therefore, when analyzing whether the chip meets the preset standard, the location of the failure of the chip to be tested can be determined based on the target single-bit signal, thereby improving the accuracy of the chip test.

[0079] In implementation, the detection instruction may be sent by the host computer, and the detection device may be the host computer or an oscilloscope. If the detection device is an oscilloscope, after the target single-bit signal is output to the oscilloscope, the staff determines whether the chip to be tested meets the preset standard according to the waveform displayed on the oscilloscope. If the chip to be tested does not meet the preset standard, the failure position of the chip can be determined according to the internal signal that does not meet the preset standard.

[0080] If the detection device is a host computer, the host computer determines whether the signal to be tested meets the preset standard based on the received target single-bit signal. For example, the target single-bit signal is 0101. The host computer determines that the target detection signal corresponding to the target single-bit signal is 0101 based on the detection signal selection instruction output to the chip to be tested. The host computer compares the target single-bit signal with the target detection signal. If the comparison result is the same, it is determined that the internal signal corresponding to the detection signal selection instruction in the chip to be tested is valid, that is, the internal signal corresponding to the detection signal selection instruction in the chip to be tested meets the preset standard. If only this one internal signal is detected, it can also be said that the chip to be tested meets the preset standard.

[0081] It should be noted that when judging whether the chip under test meets the preset standard, multiple internal signals will be tested. When the comparison results of the target single-bit signals corresponding to all the tested internal signals are the same, it is determined that the chip under test meets the preset standard, or it can be said that the signal under test is valid. That is to say, in the embodiment of the present application, judging whether the chip under test meets the preset standard, that is, judging whether the chip under test is valid, is also a validity analysis of the chip under test.

[0082] The internal signal in the embodiment of the present application can represent the working status of the chip, can be a transmission signal between various modules inside the chip, can also represent the actual value of the functional parameter in the functional module within the chip, can also represent the actual value after the signal is processed by the signal receiving module, and can also represent whether the various modules in the chip are operating normally.

[0083] In a specific implementation, after the chip under test receives the detection instruction, it switches from the normal working mode to the internal signal detection mode based on the detection mode conversion instruction and the detection time node instruction. Specifically, after the chip under test receives the detection mode conversion instruction, it switches from the normal working mode to the internal signal detection mode after the detection duration carried in the detection time node instruction is reached.

[0084] In an embodiment of the present application, after receiving the detection mode conversion instruction, the chip under test first performs timing, and the timing duration is the detection duration carried in the detection time node instruction. After the timing duration is reached, the chip under test switches the normal working mode to the internal signal detection mode. The chip under test processes the signal normally in the normal working mode, that is, during the timing process, the chip under test processes the signal normally. When the working mode of the chip under test is switched from the normal working mode to the internal signal detection mode, the chip under test obtains the internal signal corresponding to the detection signal selection instruction.

[0085] like Figure 2 As shown, it is a schematic diagram of the structure of a detection instruction provided in an embodiment of the present application, from Figure 2 It can be seen that the first part of the detection instruction is the detection mode conversion instruction, the second part is the detection time node instruction, and the third part is the detection signal selection instruction;

[0086] The chip under test first receives the first part of the detection instruction, that is, the detection mode conversion instruction, then receives the second part of the detection instruction, that is, the detection time node instruction, and finally receives the third part of the detection instruction, that is, the detection signal selection instruction.

[0087] Figure 2 In the detection time node instruction, the detection duration carried in the detection time node instruction is 10ms.

[0088] In a specific implementation, after the chip under test switches the normal working mode to the internal signal detection mode, an internal signal corresponding to the detection signal selection instruction is obtained. The detection signal selection instruction may include one or more. If the detection signal selection instruction includes multiple, each detection signal selection instruction corresponds to a multi-bit signal or a single-bit signal. The following four cases are described in detail below:

[0089] Case 1, the internal signal includes a single-bit signal:

[0090] When the internal signal includes a single-bit signal, the detection instruction includes a detection signal selection instruction. After the chip to be tested receives the detection instruction, it outputs a start signal after the detection time is reached, and then outputs a logic "0" signal or a logic "1" signal corresponding to the input single-bit signal.

[0091] like Figure 3 As shown, after the conversion module in the chip under test obtains a single-bit signal of logic "0", it first outputs a start signal and then outputs a single-bit signal of logic "0";

[0092] like Figure 4 As shown, after the conversion module in the chip under test obtains a single-bit signal of logic "1", it first outputs a start signal and then outputs a single-bit signal of logic "1".

[0093] In a specific implementation, the start signal can be composed of a 10μs high-level signal and a 20μs low-level signal, the logic "1" signal is a 50μs high-level signal, and the logic "0" signal is a 50μs low-level signal. The level width of the start signal, logic "1" signal and logic "0" signal are all adjustable.

[0094] The total time of the internal signal output is the sum of the level width of the start signal and the level width of all the logic bits of the internal signal. During the exceeding time, a low level signal is output.

[0095] In the above embodiment, the total time for outputting the internal signal = 10μs + 20μs + (50μs × the number of bits of the internal signal). For example, if the internal signal is a 3-bit signal, the total time for outputting the internal signal = 10μs + 20μs + (50μs × 3) = 180μs. For another example, if the internal signal is a 4-bit signal, the total time for outputting the internal signal = 10μs + 20μs + (50μs × 4) = 230μs.

[0096] Case 2: the internal signal includes a multi-bit signal;

[0097] When the internal signal includes a multi-bit signal and the detection instruction includes a detection signal selection instruction, after the chip to be tested receives the detection instruction, it outputs a start signal after the detection time is reached, and then converts the multi-bit signal into a target single-bit signal based on the bit position of the multi-bit signal, and outputs the target single-bit signal.

[0098] like Figure 5As shown, after the conversion module in the chip under test obtains the multi-bit signal singal[2:0]=3'b101, it first outputs a start signal, and then starts from the low or high bit of the multi-bit signal, collects the multi-bit signal in sequence, and converts the collected signal into a single-bit signal. The single-bit signal output in sequence is the target single-bit signal, for example, Figure 5 As shown, starting from the low bit of the multi-bit signal, the multi-bit signal singal[2:0]=3'b101 is collected in sequence to obtain the target single-bit signal, such as Figure 6 As shown, starting from the high bit of the multi-bit signal, the multi-bit signal singal[2:0]=3'b101 is collected in sequence to obtain the target single-bit signal.

[0099] Case 3: the internal signal includes multiple single-bit signals, and the detection signal selection instruction corresponds to the single-bit signal one by one;

[0100] In an embodiment of the present application, the detection signal selection instruction corresponds one-to-one to the single-bit signal, that is, the number of single-bit signals included in the internal signal is the same as the number of detection signal selection instructions included in the detection instruction. For example, the internal signal includes 3 single-bit signals, and the detection instruction includes 3 detection signal selection instructions.

[0101] In a specific implementation, the chip under test selects the priority of instructions based on multiple detection signals, converts multiple single-bit signals into target single-bit signals, and outputs the target single-bit signals.

[0102] In one embodiment, based on the priorities of multiple detection signal selection instructions, multiple single-bit signals are converted into target single-bit signals. The single-bit signals corresponding to each detection signal selection instruction can be output in sequence from high to low according to the priorities of the multiple detection signal selection instructions, and the single-bit signals output in sequence are used as target single-bit signals.

[0103] For example, Figure 7 As shown, the conversion module in the chip to be tested obtains multiple single-bit signals, each single-bit signal corresponds to a detection signal selection instruction, specifically, single-bit signal 1 corresponds to detection signal selection instruction 1, and single-bit signal 2 corresponds to detection signal selection instruction 2, wherein the priority of detection signal selection instruction 1 is higher than the priority of detection signal selection instruction 2. Therefore, after obtaining single-bit signal 1 and single-bit signal 2, the conversion module first outputs a start signal, then outputs a logic "0" signal corresponding to single-bit signal 1, and then outputs a logic "1" signal corresponding to single-bit signal 2.

[0104] In another embodiment, according to the priority of multiple detection signal selection instructions from low to high, the single-bit signal corresponding to each detection signal selection instruction is output in sequence, and the single-bit signal output in sequence is used as the target single-bit signal.

[0105] For example, the conversion module in the chip to be tested obtains multiple single-bit signals, each single-bit signal corresponds to a detection signal selection instruction, single-bit signal 1 corresponds to detection signal selection instruction 1, and single-bit signal 2 corresponds to detection signal selection instruction 2, wherein the priority of detection signal selection instruction 1 is higher than the priority of detection signal selection instruction 2. Therefore, after obtaining single-bit signal 1 and single-bit signal 2, the conversion module first outputs a start signal, then outputs a logic "1" signal corresponding to single-bit signal 2, and then outputs a logic "0" signal corresponding to single-bit signal 1.

[0106] Case 4: the internal signal includes a plurality of multi-bit signals, and the detection signal selection instruction corresponds one-to-one to the multi-bit signals;

[0107] In an embodiment of the present application, the detection signal selection instruction corresponds one-to-one to the multi-bit signal, that is, the number of multi-bit signals included in the internal signal is the same as the number of detection signal selection instructions included in the detection instruction. For example, the internal signal includes 3 multi-bit signals, and the detection instruction includes 3 detection signal selection instructions.

[0108] In a specific implementation, the chip under test determines the priority of the multi-bit signal corresponding to each detection signal selection instruction based on the priority of multiple detection signal selection instructions. The chip under test performs the following processing on each multi-bit signal in turn based on the priority of the multi-bit signal: based on the high and low bits of the multi-bit signal, the multi-bit signal is converted into a single-bit signal, the signal composed of the converted single-bit signals is used as the target single-bit signal, and the target single-bit signal is output.

[0109] For example, Figure 8 As shown, the conversion module in the chip to be tested obtains multiple multi-bit signals, each multi-bit signal corresponds to a detection signal selection instruction. Specifically, the multi-bit signal Signal#1 corresponds to the detection signal selection instruction 1, and the multi-bit signal Signal#2 corresponds to the detection signal selection instruction 2. The priority of the detection signal selection instruction 1 is higher than that of the detection signal selection instruction 2. After the conversion module obtains the multi-bit signal Signal#1 and the multi-bit signal Signal#2, it first outputs the start signal, then converts the multi-bit signal Signal#1 with a high priority, and outputs the converted logic signals in sequence, and then converts the multi-bit signal Signal#2 with a low priority, and outputs the converted logic signals in sequence.

[0110] It should be noted that the conversion of the multi-bit signal may be performed starting from the high bit of the multi-bit signal or starting from the low bit of the multi-bit signal, and the embodiments of the present application do not impose any limitation on this.

[0111] Case 5: the internal signal includes at least one single-bit signal and at least one multi-bit signal, and the detection signal selection instruction corresponds one-to-one to each signal included in the internal signal;

[0112] In an embodiment of the present application, the detection signal selection instruction corresponds one-to-one to each signal included in the internal signal, that is, the number of signals included in the internal signal is the same as the number of detection signal selection instructions included in the detection instruction. For example, the internal signal includes 1 single-bit signal and 3 multi-bit signals, and the detection instruction includes 4 detection signal selection instructions.

[0113] In a specific implementation, the chip under test selects the priority of instructions based on multiple detection signals, and performs the following conversions on the signals included in the internal signals in turn. If the signal is a single-bit signal, the single-bit signal is converted into a target single-bit signal. If the signal is a multi-bit signal, the signal of each bit is converted based on the high and low bits of the multi-bit signal to obtain a target single-bit signal, and each target single-bit signal obtained by conversion is output in turn.

[0114] For example, Fig. 9 As shown, the internal signals obtained by the conversion module in the chip to be tested include a single-bit signal Signal#3 and a multi-bit signal Signal#4. The single-bit signal Signal#3 corresponds to the detection signal selection instruction 3, and the multi-bit signal Signal#4 corresponds to the detection signal selection instruction 4. The priority of the detection signal selection instruction 3 is higher than the priority of the detection signal selection instruction 4. The conversion module first converts the single-bit signal Signal#3 to obtain the target single-bit signal, and then converts the multi-bit signal Signal#4 to obtain the target single-bit signal, and outputs the target single-bit signals in sequence.

[0115] It should be noted that in a specific implementation, the start signal may or may not exist. When the start signal exists, the detection device can determine, based on the start signal, that the signal after the start signal is the target single-bit signal corresponding to the acquired internal signal, thereby making the detection result more accurate.

[0116] A chip detection method provided in an embodiment of the present application, wherein the default working mode of the chip to be tested is the normal working mode, and a detection instruction is sent by an external device to the chip to be tested, wherein the detection instruction includes a detection mode conversion instruction, a detection time node instruction and at least one detection signal selection instruction, and the detection mode conversion instruction, the detection time node instruction and the detection signal selection instruction are all composed of specific numerical combinations, for example, the detection mode conversion instruction is composed of the numerical value of "0001", the detection time node instruction is composed of the numerical value of "9527", and the detection signal selection instruction is composed of the numerical value of "0002". After receiving the numerical combination of "0001", the chip to be tested suspends normal operation at "9527" time units, and after entering the internal signal detection mode, the chip to be tested scans, processes and outputs the signal corresponding to "0002".

[0117] Specifically, after the chip under test receives the detection mode switching instruction, the internal signal module starts timing; if no detection mode switching instruction is received, the chip under test remains in the normal working mode.

[0118] When the timer of the internal signal module of the chip under test reaches the set detection time, the processing of normal data of the chip under test is suspended. When the detection time is reached, all internal signals remain in the current state.

[0119] The internal signal detection module of the chip to be tested scans the internal signal, which is the internal signal corresponding to the detection signal selection instruction.

[0120] The chip under test processes the scanned internal signal. For example, a single-bit signal is converted into a logic signal with a preset level width and output through the signal output port. For another example, a multi-bit signal is processed by a parallel signal to serial signal module, and the multi-bit signal is converted into a single-bit signal, which is transmitted to the signal output port and output by the signal output port.

[0121] The signal output port of the chip under test outputs the processed single-bit signal. The signal output port may be an independent internal signal output port or a chip output port in a normal mode.

[0122] In the above manner, the chip under test can output the signal inside the chip at any time through the signal port.

[0123] Based on the same inventive concept, an embodiment of the present application also provides a chip, the principle of which is similar to the principle of the above-mentioned chip testing method for solving technical problems. The implementation of the chip can refer to the implementation of the chip testing method, and the repeated parts will not be repeated.

[0124] like Fig.10FIG. 1 is a schematic diagram of a chip structure provided in an embodiment of the present application, wherein the chip includes:

[0125] An input port 101 is used to receive a detection instruction, wherein the detection instruction includes a detection mode switching instruction, a detection time node instruction, and a detection signal selection instruction;

[0126] A mode conversion module 102, configured to switch from a normal working mode to an internal signal detection mode based on the detection mode conversion instruction and the detection time node instruction;

[0127] The internal signal detection module 103 is used to obtain the internal signal corresponding to the detection signal selection instruction; after converting the obtained internal signal, a target single-bit signal is obtained;

[0128] The output port 104 is used to output the target single-bit signal obtained by conversion. The detection device determines whether the chip meets the preset standard according to the target single-bit signal.

[0129] In one embodiment, the mode conversion module is specifically used to:

[0130] After receiving the detection mode conversion instruction, the normal working mode is switched to the internal signal detection mode after the detection duration carried in the detection time node instruction is reached.

[0131] In one embodiment, the internal signal detection module is specifically used to:

[0132] Based on the bit positions of the multi-bit signal, the multi-bit signal is converted into a target single-bit signal, and the target single-bit signal is output.

[0133] In one embodiment, the internal signal includes a plurality of single-bit signals, and the detection signal selection instruction corresponds one-to-one to the single-bit signals;

[0134] The internal signal detection module is specifically used for:

[0135] The priorities of the instructions are selected based on the plurality of detection signals, the plurality of single-bit signals are converted into the target single-bit signal, and the target single-bit signal is output.

[0136] In one embodiment, the internal signal detection module is specifically used to:

[0137] Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priorities of the plurality of detection signal selection instructions from high to low;

[0138] Using the single-bit signals output in sequence as the target single-bit signal; or

[0139] Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priority of the plurality of detection signal selection instructions from low to high;

[0140] The single-bit signals output in sequence are used as the target single-bit signals.

[0141] In one embodiment, the internal signal includes a plurality of multi-bit signals, and the detection signal selection instruction corresponds one-to-one to the multi-bit signals;

[0142] The internal signal detection module is specifically used for:

[0143] Based on the priorities of the plurality of detection signal selection instructions, determining the priority of the multi-bit signal corresponding to each detection signal selection instruction;

[0144] The following processing is performed on each multi-bit signal in descending order of priority:

[0145] Based on the bit position of the multi-bit signal, convert the multi-bit signal into a single-bit signal;

[0146] The signal composed of the converted single-bit signals is used as the target single-bit signal, and the target single-bit signal is output.

[0147] In one embodiment, before outputting the single-bit signal, the internal signal detection module is further used to:

[0148] Determine the starting signal;

[0149] After the start signal is output, the target single-bit signal is output.

[0150] It should be noted that Fig.10 The main logic module in the process processes the signal normally in the normal working mode to obtain the internal signal. The mode conversion module 102 can send a normal working instruction to the main logic module. After receiving the normal working instruction, the main logic module enters the normal working mode and processes the signal normally. The mode conversion module 102 can also receive the detection mode conversion instruction. After the detection duration carried in the detection time node instruction is reached, the mode conversion module 102 sends a switching instruction to the internal signal detection module 103. After receiving the switching instruction, the internal signal detection module 103 sends an instruction to stop normal operation to the main logic module. The main logic module stops working normally, that is, after switching from the normal working mode to the internal signal detection mode, the internal signal detection module 103 obtains the internal signal corresponding to the detection signal selection instruction from the main logic module, and obtains the target single-bit signal after converting the obtained internal signal. The output port 104 outputs the target single-bit signal.

[0151] In the embodiment of the present application, the selection of the internal signal output mode is selected by the detection signal selection instruction. The single-send detection signal selection instruction is to detect only one internal signal. The multiple-send detection signal selection instruction is to detect multiple internal signals. The internal signal detection module identifies the type of signal and processes the internal signal accordingly.

[0152] The present application is described above with reference to the block diagrams and / or flow charts showing the methods, devices (systems) and / or computer program products according to the embodiments of the present application. It should be understood that a block of the block diagram and / or flow chart diagram and a combination of blocks of the block diagram and / or flow chart diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer and / or other programmable data processing device to produce a machine, so that the instructions executed by the computer processor and / or other programmable data processing device create a method for implementing the functions / actions specified in the block diagram and / or flow chart block.

[0153] Accordingly, the present application may also be implemented in hardware and / or software (including firmware, resident software, microcode, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium, which has a computer-usable or computer-readable program code implemented in the medium for use by an instruction execution system or in conjunction with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium may be any medium that may contain, store, communicate, transmit, or convey a program for use by an instruction execution system, device, or apparatus, or in conjunction with an instruction execution system, device, or apparatus.

[0154] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A chip testing method, characterized in that: Applied to a chip, the chip includes an input port, a mode conversion module, an internal signal detection module, an output port and a main logic module, the method includes: In the normal working mode, the signal is processed normally by the main logic module to obtain the internal signal; Receiving a detection instruction through the input port, wherein the detection instruction includes a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction; After receiving the detection mode switching instruction through the mode switching module, after the detection duration carried in the detection time node instruction is reached, sending a switching instruction to the internal signal detection module; After receiving the switching instruction through the internal signal detection module, sending an instruction to stop normal operation to the main logic module; After receiving the instruction to stop normal operation through the main logic module, the normal operation is stopped and the normal operation mode is switched to the internal signal detection mode; Acquire an internal signal corresponding to the detection signal selection instruction from the main logic module through the internal signal detection module; convert the acquired internal signal to obtain a target single-bit signal; The target single-bit signal obtained by the conversion is outputted through the output port, and the detection device determines whether the chip to be tested meets the preset standard according to the target single-bit signal.

2. The method according to claim 1, characterized in that The internal signal includes a multi-bit signal, and after converting the acquired internal signal, outputting a target single-bit signal obtained by the conversion includes: Based on the bit positions of the multi-bit signal, the multi-bit signal is converted into a target single-bit signal, and the target single-bit signal is output.

3. The method according to claim 1, characterized in that The internal signal includes a plurality of single-bit signals, and the detection signal selection instruction corresponds to the single-bit signal one by one; After converting the acquired internal signal, outputting the converted target single-bit signal comprises: The priorities of the instructions are selected based on the plurality of detection signals, the plurality of single-bit signals are converted into the target single-bit signal, and the target single-bit signal is output.

4. The method according to claim 3, characterized in that The step of selecting the priority of the instruction based on the plurality of detection signals and converting the plurality of single-bit signals into the target single-bit signal comprises: Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priorities of the plurality of detection signal selection instructions from high to low; Using the single-bit signals output in sequence as the target single-bit signal; or Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priority of the plurality of detection signal selection instructions from low to high; The single-bit signals outputted sequentially are used as the target single-bit signals.

5. The method according to claim 1, characterized in that The internal signal includes a plurality of multi-bit signals, and the detection signal selection instruction corresponds to the multi-bit signal one by one; After converting the acquired internal signal, outputting the converted target single-bit signal comprises: Determining the priority of the multi-bit signal corresponding to each detection signal selection instruction based on the priorities of the plurality of detection signal selection instructions; The following processing is performed on each multi-bit signal in descending order of priority: Based on the bit position of the multi-bit signal, convert the multi-bit signal into a single-bit signal; The signal composed of the converted single-bit signals is used as the target single-bit signal, and the target single-bit signal is output.

6. The method according to any one of claims 3 to 5, characterized in that: Before outputting the target single-bit signal, the method further comprises: Determine the starting signal; After the start signal is output, the target single-bit signal is output.

7. A chip, characterized in that: The chip includes: an input port, a mode conversion module, an internal signal detection module, a main logic module and an output port; The main logic module is used to process the signal normally in the normal working mode to obtain the internal signal; and after receiving the instruction to stop the normal working mode, stop the normal working mode and switch from the normal working mode to the internal signal detection mode; The input port is used to receive a detection instruction, wherein the detection instruction includes a detection mode conversion instruction, a detection time node instruction, and a detection signal selection instruction; The mode conversion module is configured to, after receiving the detection mode conversion instruction, send a switching instruction to the internal signal detection module after the detection duration carried in the detection time node instruction has arrived; The internal signal detection module is used to send the instruction to stop normal operation to the main logic module after receiving the switching instruction; and obtain the internal signal corresponding to the detection signal selection instruction from the main logic module; convert the obtained internal signal to obtain a target single-bit signal; The output port is used to output the target single-bit signal obtained by conversion, and the detection device determines whether the chip meets the preset standard based on the target single-bit signal.

8. The chip according to claim 7, characterized in that: The internal signal includes a multi-bit signal, and the internal signal detection module is specifically used for: Based on the bit positions of the multi-bit signal, the multi-bit signal is converted into a target single-bit signal, and the target single-bit signal is output.

9. The chip according to claim 7, characterized in that: The internal signal includes a plurality of single-bit signals, and the detection signal selection instruction corresponds to the single-bit signal one by one; The internal signal detection module is specifically used for: The priorities of the instructions are selected based on the plurality of detection signals, the plurality of single-bit signals are converted into the target single-bit signal, and the target single-bit signal is output.

10. The chip according to claim 9, characterized in that: The internal signal detection module is specifically used for: Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priorities of the plurality of detection signal selection instructions from high to low; Using the single-bit signals outputted sequentially as the target single-bit signals; or Outputting a single-bit signal corresponding to each detection signal selection instruction in sequence according to the priority of the plurality of detection signal selection instructions from low to high; The single-bit signals outputted sequentially are used as the target single-bit signals.

11. The chip according to claim 7, characterized in that: The internal signal includes a plurality of multi-bit signals, and the detection signal selection instruction corresponds to the multi-bit signal one by one; The internal signal detection module is specifically used for: Determining the priority of the multi-bit signal corresponding to each detection signal selection instruction based on the priorities of the plurality of detection signal selection instructions; The following processing is performed on each multi-bit signal in descending order of priority: Based on the bit position of the multi-bit signal, convert the multi-bit signal into a single-bit signal; The signal composed of the converted single-bit signals is used as the target single-bit signal, and the target single-bit signal is output.

12. The chip according to any one of claims 8 to 11, characterized in that: Before outputting the single-bit signal, the internal signal detection module is further used for: Determine the starting signal; After the start signal is output, the target single-bit signal is output.

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