A switch quantity acquisition circuit and detection method compatible with active and passive inputs

Abstract

The invention belongs to the technical field of switch quantity acquisition circuits, and discloses a switch quantity acquisition circuit and a detection method compatible with active and passive inputs. The acquisition circuit comprises an acquisition port and a single-chip microcomputer input port, and a protection conditioning module, a level conversion module and an output pulsating voltage smoothing processing module are arranged between the acquisition port and the single-chip microcomputer input port; the protection conditioning module is used to absorb surge voltage and protect the subsequent circuit from being affected by static electricity and surge voltage; the level conversion module is used to convert the working state of the switch to be detected into high and low levels and input them into the single-chip microcomputer; the output pulsating voltage smoothing processing module is used to reduce the ripple of the previous stage DC voltage and stabilize the high and low levels of the output; the circuit is used to perform data acquisition on active and passive switches, so as to realize the self-adaptation of input voltage level and voltage polarity, get rid of the dependence on power supply when acquiring passive switch quantity signals, reduce the cost of the circuit, and facilitate operation.

Description

Technical Field

[0001] The present invention belongs to the technical field of switch quantity acquisition circuits, and in particular, relates to a switch quantity acquisition circuit and a detection method which are compatible with active and passive inputs. Background Art

[0002] Switch quantity is a non-continuous field signal commonly used in industrial control systems and automation fields. It is expressed as a pair of contacts with only two states: open and closed. Input switch quantity can be used to monitor the operating status of various devices or systems, and at the same time feed back the collected related signals as digital signals that can be received by the CPU unit. The input types of switch quantity are divided into active input and passive input. Active input refers to the signal with power supply in the "open" and "closed" states, with polarity, also known as wet contact. Passive input refers to the signal without power supply in the "open" and "closed" states, with no polarity, also known as dry contact.

[0003] For the acquisition of active switch input signals, the circuits commonly used are as follows: Fig.15 , the dotted box is the active switch quantity, DI+ and DI- are the input ports of the acquisition circuit, RV is the varistor RV, R1, R2, R3, R4 are resistors, D1 is the switch diode, and U1 is the photocoupler. According to the different levels of DC power supply signals, select the appropriate R1, R2, R3 resistance values ​​so that the output side of the photocoupler can isolate the output changing digital quantity signal and send it to the microcontroller. The resistance value of this circuit needs to be selected according to the level of the power supply signal. It is only suitable for occasions with fixed voltage and cannot be used flexibly; at the same time, DI+ and DI- need to distinguish the positive and negative polarity of the power supply, and reverse wiring is prohibited. If reversed, the photocoupler will be damaged.

[0004] For the acquisition of passive switch input signals, it is usually necessary to provide an additional drive power supply in series with the switch. The drive power supply can be connected in series externally or the internal power supply of the device can be used. Commonly used circuits are as follows Fig.16 , use an external power supply and switch quantity in series and then connect to DI+ and DI- for sampling. The sampling principle is the same as Fig.15 The circuit is the same as shown. Fig.15 It has all the disadvantages of active switch quantity acquisition circuit, and in addition, it requires additional power supply, which is inconvenient to operate.

[0005] like Figure 17-18As shown, the device power supply VCC is converted into voltage VDD through an isolated DC-DC power module. VDD is connected in series with resistor R2 and connected to the anode of the photocoupler. The switch quantity is connected to DI1 and DI2. DI1 is connected to the ground of the DC-DC secondary output voltage. When the switch is closed, a loop is formed to drive the photocoupler to work. DI1 and DI2 have no polarity. Because this circuit uses a DC-DC with an isolated power module, it will take up too much space when designing the circuit board, increasing the system power consumption. At the same time, the price of the isolated power module is relatively high, which is easy to cause cost waste. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a switch quantity acquisition circuit and a detection method which are compatible with active and passive inputs, which can be compatible with input acquisition of both active and passive switch quantities, has simple operation, small space occupation and low cost.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] A switch quantity acquisition circuit compatible with active and passive inputs comprises an acquisition port and a single-chip microcomputer input port, wherein a protection conditioning module, a level conversion module and an output pulsating voltage smoothing processing module are arranged between the acquisition port and the single-chip microcomputer input port; the protection conditioning module is used to absorb surge voltage and protect the subsequent circuit from being affected by static electricity and surge voltage; the level conversion module is used to convert the working state of the switch to be detected into high and low levels and input them into the single-chip microcomputer; the output pulsating voltage smoothing processing module is used to reduce the ripple of the previous stage DC voltage and stabilize the high and low levels of the output.

[0009] The following is a further optimization of the above technical solution by the present invention:

[0010] The level conversion module comprises a first conversion module and a second conversion module connected in parallel, wherein an NPN transistor Q1 and a first PMOS transistor Q2 are connected in series in the first conversion module, and a PNP transistor Q3 and a second PMOS transistor Q4 are connected in series in the second conversion module.

[0011] Further optimization: in the first conversion module, a first Schottky diode D1, a first resistor R1, an NPN transistor Q1, and a first PMOS tube Q2 are connected in series in sequence, a second resistor R2 is connected in parallel between the base and the emitter of the NPN transistor Q1, the emitter of the NPN transistor Q1 is grounded, the collector of the NPN transistor Q1 is connected to the gate of the first PMOS tube Q2, a third resistor R3 is connected in parallel between the gate and the source of the first PMOS tube Q2, the source of the first PMOS tube Q2 is connected to the first power supply, and the drain of the first PMOS tube Q2 is connected to the input port of the microcontroller.

[0012] Further optimization: the second conversion module is connected in series with a second Schottky diode D2, a sixth resistor R6, a PNP transistor Q3, and a second PMOS tube Q4 in sequence, the base of the PNP transistor Q3 is also connected to the second power supply, a seventh resistor R7 is connected in series between the second power supply and the base of the PNP transistor Q3, the collector of the PNP transistor Q3 is grounded, the emitter of the PNP transistor Q3 is connected to the eighth resistor R8, the eighth resistor R8 is grounded, the emitter of the PNP transistor Q3 is connected to the gate of the second PMOS tube Q4, the source of the second PMOS tube Q4 is connected to the third power supply, a ninth resistor R9 is connected in parallel between the gate and the source of the second PMOS tube Q4, and the drain of the second PMOS tube Q4 is connected to the input port of the single-chip computer.

[0013] Further optimization: a fifth resistor R5 is connected in series between the drain of the first PMOS tube Q2 and the ground, and a fifth capacitor C5 is connected in parallel to the fifth resistor R5; a tenth resistor R10 is connected in series between the drain of the second PMOS tube Q4 and the ground, and a fourth capacitor C4 is connected in parallel to the tenth resistor R10.

[0014] Further optimization: the acquisition port includes a first port DI1 and a second port DI2, the first port DI1 is connected to the first Schottky diode D1 and the second Schottky diode D2, and the second port DI2 is grounded.

[0015] Further optimization: the protection and conditioning module includes a varistor RV, a bidirectional transient suppression diode TVS1 and a first capacitor C1 connected in parallel between the first port DI1 and the second port DI2.

[0016] The present invention also discloses a detection method for a switch quantity acquisition circuit compatible with active and passive inputs, wherein the first port DI1 and the second port DI2 are respectively connected to two ends of an active switch or a passive switch, and the state change of the switch is recorded according to the high and low levels output by the input port of a single-chip computer. When the positive pole of the active switch is connected to the first port DI1 and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the positive pole of the active switch is connected to the first port DI1 and the switch is closed, the input port of the single-chip computer outputs a high level; when the positive pole of the active switch is connected to the second port DI2 and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the positive pole of the active switch is connected to the second port DI2 and the switch is closed, the input port of the single-chip computer outputs a high level; when the passive switch is connected to the acquisition port and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the passive switch is connected to the acquisition port and the switch is closed, the input port of the single-chip computer outputs a high level.

[0017] The beneficial effects of the present invention are as follows: the acquisition ports of the passive and active switch quantity input acquisition circuits are compatible and unified, and the self-adaptation of the input voltage level and the voltage polarity is realized. When acquiring passive switch quantity signals, the dependence on the power supply is eliminated, the circuit as a whole is simpler, and the cost of the circuit is reduced. The voltage polarity of the active switch is self-adaptive, and the circuit will not be damaged due to wrong port connection, thereby realizing a common acquisition port for passive and active switch quantity acquisition, which is convenient to operate.

[0018] The present invention is further described below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of a specific embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of the operation of positive sequence connection when collecting active switching quantity in a specific embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the operation of negative sequence connection when collecting active switching quantity in a specific embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the operation of collecting passive switch quantities in a specific embodiment of the present invention;

[0023] Figure 5 It is a simulation diagram of the switch being disconnected when the positive sequence connection is made when collecting active switch quantity in a specific embodiment of the present invention;

[0024] Figure 6 It is a simulation diagram of the switch closing when the positive sequence connection is connected when collecting active switch quantity in a specific embodiment of the present invention;

[0025] Figure 7 This is a simulation diagram of a specific embodiment of the present invention when the active switch quantity is collected and the switch is closed during positive sequence wiring and the switch power supply is 2V;

[0026] Figure 8 This is a simulation diagram of a specific embodiment of the present invention when collecting active switch quantities and the switch is closed during positive sequence wiring and the switch power supply is 3V;

[0027] Fig. 9 This is a simulation diagram of a specific embodiment of the present invention when the active switch quantity is collected and the switch is closed during positive sequence wiring and the switch power supply is 30V;

[0028] Fig.10 It is a simulation diagram of the case where the switch is closed and the switch power supply is 0V when the negative sequence connection is connected when the active switch quantity is collected for a specific embodiment of the present invention;

[0029] Fig.11 This is a simulation diagram of a specific embodiment of the present invention when the switch is closed and the switch power supply is -1V during negative sequence wiring when collecting active switch quantity;

[0030] Fig.12 The simulation diagram of the specific embodiment of the present invention is collected when the switch is closed and the switch power supply is -2V during the negative sequence wiring of the active switch quantity;

[0031] Fig.13 The simulation diagram of the specific embodiment of the present invention is collected when the switch is closed and the switch power supply is -30V during the negative sequence connection of the active switch quantity;

[0032] Fig.14 It is a simulation diagram of a switch closing when collecting passive switch quantity for a specific embodiment of the present invention;

[0033] Fig.15 It is a commonly used circuit for collecting active switch quantities in the prior art;

[0034] Fig.16 It is a commonly used circuit for collecting passive switch quantities in the prior art;

[0035] Fig.17 A circuit of a DC-DC power supply module with isolation in the prior art;

[0036] Fig.18 The invention discloses a connection method between a commonly used circuit for collecting passive switch quantities and an isolated DC-DC power supply module in the prior art. DETAILED DESCRIPTION

[0037] like Figure 1-18 As shown, a switch quantity acquisition circuit compatible with active and passive inputs includes an acquisition port and a single-chip microcomputer input port, and a protection conditioning module, a level conversion module and an output pulsating voltage smoothing processing module are arranged between the acquisition port and the single-chip microcomputer input port; the protection conditioning module is used to absorb surge voltage and protect the subsequent circuit from static electricity and surge voltage; the level conversion module is used to convert the working state of the switch to be detected into high and low levels and input them into the single-chip microcomputer; the output pulsating voltage smoothing processing module is used to reduce the ripple of the previous stage DC voltage and stabilize the high and low levels of the output.

[0038] The level conversion module comprises a first conversion module and a second conversion module connected in parallel, wherein an NPN transistor Q1 and a first PMOS transistor Q2 are connected in series in the first conversion module, and a PNP transistor Q3 and a second PMOS transistor Q4 are connected in series in the second conversion module.

[0039] The first conversion module is connected in series with a first Schottky diode D1, a first resistor R1, an NPN transistor Q1, and a first PMOS transistor Q2 in sequence, a second resistor R2 is connected in parallel between the base and the emitter of the NPN transistor Q1, the emitter of the NPN transistor Q1 is grounded, the collector of the NPN transistor Q1 is connected to the gate of the first PMOS transistor Q2, a third resistor R3 is connected in parallel between the gate and the source of the first PMOS transistor Q2, the source of the first PMOS transistor Q2 is connected to the first power supply, and the drain of the first PMOS transistor Q2 is connected to the input port of the single-chip computer.

[0040] The second conversion module is connected in series with a second Schottky diode D2, a sixth resistor R6, a PNP transistor Q3, and a second PMOS tube Q4 in sequence. The base of the PNP transistor Q3 is also connected to the second power supply. A seventh resistor R7 is connected in series between the second power supply and the base of the PNP transistor Q3. The collector of the PNP transistor Q3 is grounded. The emitter of the PNP transistor Q3 is connected to the eighth resistor R8. The eighth resistor R8 is grounded. The emitter of the PNP transistor Q3 is connected to the gate of the second PMOS tube Q4. The source of the second PMOS tube Q4 is connected to the third power supply. A ninth resistor R9 is connected in parallel between the gate and the source of the second PMOS tube Q4. The drain of the second PMOS tube Q4 is connected to the input port of the single-chip computer.

[0041] A fifth resistor R5 is connected in series between the drain of the first PMOS tube Q2 and the ground, and a fifth capacitor C5 is connected in parallel to the fifth resistor R5; a tenth resistor R10 is connected in series between the drain of the second PMOS tube Q4 and the ground, and a fourth capacitor C4 is connected in parallel to the tenth resistor R10.

[0042] The acquisition port includes a first port DI1 and a second port DI2 , the first port DI1 is connected to a first Schottky diode D1 and a second Schottky diode D2 , and the second port DI2 is grounded.

[0043] The protection and conditioning module includes a varistor RV, a bidirectional transient suppression diode TVS1 and a first capacitor C1 connected in parallel between a first port DI1 and a second port DI2.

[0044] Among them, the protection and conditioning module includes a varistor RV, a bidirectional transient suppression diode TVS1 and a first capacitor C1. The varistor RV is connected in parallel to the acquisition port, with a rated working voltage of about DC30V, and is used to absorb surge voltage; the bidirectional transient suppression diode TVS1 is connected in parallel to the acquisition port, with a reverse cut-off voltage of about DC30V, which protects the subsequent circuit from static electricity and surge voltage; the first capacitor C1 filters the input voltage, and a 100nF chip capacitor is selected with a rated voltage of DC50V.

[0045] The first Schottky diode D1 and the second Schottky diode D2 play a role in preventing reverse connection and ensure normal signal collection of the circuit when the active switch is connected in negative sequence.

[0046] The NPN transistor Q1 and the PNP transistor Q3 are silicon transistors. The drains of the first PMOS transistor Q2 and the second PMOS transistor Q4 are connected to each other and connected to the input port of the single-chip computer. The fifth resistor R5 and the tenth resistor R10 are resistors with the same resistance value. The first PMOS transistor Q2 and the second PMOS transistor Q4 are connected to two resistors with the same resistance value and then grounded.

[0047] The fourth capacitor C4 and the fifth capacitor C5 play a filtering role. They use 100nF chip capacitors with a rated voltage of DC10V. They are mainly used to reduce the ripple of the previous DC voltage so that the input port of the microcontroller can obtain a relatively stable high and low level.

[0048] During the detection process of the active switch, there are two situations: positive sequence wiring and negative sequence wiring. The positive sequence wiring is that the positive end of the active switch is connected to the first port DI1, and the negative end of the active switch is connected to the second port DI2. The negative sequence wiring is opposite to the positive sequence wiring. The positive end of the active switch is connected to the second port DI2, and the negative end of the active switch is connected to the first port DI1.

[0049] In the positive sequence wiring state, when the switch to be detected is in the disconnected state, there is no voltage input to the acquisition port, the output signal of the microcontroller input port is set to a low level, and the parameters are set to make the NPN transistor Q1 and the PNP transistor Q3 in the cut-off state, and the first PMOS tube Q2 and the second PMOS tube Q4 in the non-conducting state. At this time, the microcontroller input port is grounded through the fifth resistor R5 and the tenth resistor R10.

[0050] The voltage of the second power supply is 3.3V. The second power supply is grounded through the seventh resistor R7, the sixth resistor R6, the second Schottky diode D2, the first Schottky diode D1, the first resistor R1 and the second resistor R2 to form a loop. The forward conduction voltage drop of the second Schottky diode D2 and the first Schottky diode D1 is selected to be 0.4V.

[0051] Assume VbQ1 is the base voltage of NPN transistor Q1, then:

[0052] VbQ1=(3.3V-0.4V-0.4V) / (R1+R2+R6+R7)*R2.

[0053] Assume VbQ3 is the base voltage of PNP transistor Q3, then:

[0054] VbQ3=(3.3V-0.4V-0.4V) / (R1+R2+R6+R7)*(R1+R2+R6)+0.4V+0.4V.

[0055] Assume VeQ3 is the emitter voltage of the PNP transistor Q3, which is also the gate voltage of the second PMOS transistor Q4, then:

[0056] VeQ3=3.3V / (R8+R9)*R8.

[0057] Assume that VgsQ4 is the voltage difference between the gate and the source of the second PMOS transistor Q4, and the conduction threshold of the second PMOS transistor Q4 is Vgs(th), then:

[0058] VgsQ4=VeQ3-3.3V.

[0059] In order to make the NPN transistor Q1 and the first PMOS transistor Q2 in the cut-off state, and the PNP transistor Q3 and the second PMOS transistor Q4 in the non-conducting state, the following conditions need to be met at the same time: VbQ1<0.7V, VeQ3≤VbQ3, VgsQ4>Vgs(th).

[0060] Select a PMOS tube with a conduction threshold Vgs(th)=-1.8V as the second PMOS tube Q4; then VgsQ4>-1.8V satisfies the second PMOS tube Q4 not conducting. Select R1=4.7KΩ, R2=5.1KΩ, R6=1.5KΩ, R7=22KΩ, R8=1KΩ, R9=1KΩ, substitute into the above formula for calculation, and get VbQ1=0.382V<0.7V, NPN transistor Q1 is cut off, and the first PMOS tube Q2 is not conducting; VbQ3=1.648V, VeQ3=1.65V, VgsQ4=-1.65V, PNP transistor Q3 is cut off, and the second PMOS tube Q4 is not conducting.

[0061] In the positive sequence connection state, when the switch to be detected is in the closed state, the input DC signal of the acquisition port is set to VDC. Due to the existence of the second Schottky diode D2, the VDC voltage can only pass through the first Schottky diode D1, the first resistor R1, and the second resistor R2 to the ground to form a loop. After the NPN transistor Q1 is turned on, the value of VbQ1 is a fixed value of 0.7V. Let the current flowing through the first resistor R1 be IR1, the current flowing through the second resistor R2 be IR2, the base current of the NPN transistor Q1 be IbQ1, the collector current of the NPN transistor Q1 be IcQ1, the collector voltage of the NPN transistor Q1 be VcQ1, the voltage difference between the gate and the source of the first PMOS tube Q2 be VgsQ2, and the amplification factor of the NPN transistor Q1 be A, then:

[0062] IR2=VbQ1 / R2,

[0063] IR1=(VDC-VbQ1-0.4V) / R1,

[0064] IbQ1=IR1-IR2=(VDC-VbQ1-0.4V) / R1-VbQ1 / R2,

[0065] IcQ1=A*IbQ1,

[0066] VcQ1=3.3V-R3*IcQ1,

[0067] VgsQ2=VcQ1-3.3V.

[0068] A transistor with an amplification factor A of 50 is selected as the NPN transistor Q1, and a PMOS transistor with a conduction threshold Vgs(th)=-1.8V is selected as the first PMOS transistor Q2. When the input VDC is equal to 1V, because the forward conduction voltage drop of the first Schottky diode D1 is 0.4V, the base voltage VbQ1 of the NPN transistor Q1 is <0.7V, and the NPN transistor Q1 is in the cut-off state; when the input VDC is equal to 2V, it is assumed that the NPN transistor Q1 is in the amplification state, and the calculation is:

[0069] IR2=0.137mA,

[0070] IR1=0.191mA,

[0071] IbQ1=0.191mA-0.137mA=0.054mA,

[0072] IcQ1=50*0.054mA=2.7mA,

[0073] VcQ1=3.3V-1KΩ*2.7mA=0.6V,

[0074] VgsQ2=0.6V-3.3V=-2.7V.

[0075] Because VgsQ2=-2.7V<-1.8V, the first PMOS tube Q2 is turned on, and the drain outputs a high level to the microcontroller input port. When the input VDC is equal to 3V, assuming that the NPN transistor Q1 is in the amplification state, calculate:

[0076] IR2=0.137mA,

[0077] IR1=0.404mA,

[0078] IbQ1=0.404mA-0.137mA=0.267mA,

[0079] IcQ1=50*0.267mA=13.35mA,

[0080] VcQ1=3.3V-1KΩ*13.35mA=-10.05V,

[0081] VgsQ2=-10.05V-3.3V=-13.35V.

[0082] In the above calculation, the absolute values ​​of VcQ1 and VgsQ2 have far exceeded the voltage value of the second power supply. At this time, the collector current IcQ1 and the base current IbQ1 of the transistor are no longer proportional. The above assumption is wrong. The transistor should be in saturation, and the collector and emitter are connected. VcQ1=0V; the gate voltage of the first PMOS tube Q2 is close to 0V, VgsQ2=0V-3.3V=-3.3V<-1.8V, the first PMOS tube Q2 is turned on, and the drain outputs a high level to the microcontroller input port. In summary, when the power supply voltage of the active switch is greater than 3V, the NPN transistor Q1 is saturated and turned on, and the first PMOS tube Q2 is turned on.

[0083] In the negative sequence wiring state, when the switch to be detected is in the disconnected state, the analysis steps are the same as the analysis process when the switch in the positive sequence wiring is disconnected, and the output is a low level.

[0084] In the negative sequence connection state, when the switch to be detected is in the closed state, due to the unidirectional conductivity of the first Schottky diode D1, the current of the second power supply forms a loop through the sixth resistor R6, the second Schottky diode D2, the active switch to the ground, and the calculation is:

[0085] VbQ3=(3.3V+VDC-0.4V) / (R6+R7)*R6+VDC+0.4V,

[0086] Assume VDC=0V, then VbQ3=0.585V. Assuming that the PNP transistor Q3 is in the cut-off state, VeQ3=3.3V / (R8+R9)*R8=1.65V, and the collector voltage VcQ3 of the PNP transistor Q3=0V. Since the voltage relationship of VeQ3>VbQ3>VcQ3 is satisfied, the above assumption that the PNP transistor Q3 is in the cut-off state is wrong. The PNP transistor Q3 should be in the amplification state, and VeQ3=VbQ3+0.7V=1.285V, and VgsQ4=VeQ3-3.3V=-2.015V, VgsQ4=-2.015V<-1.8V, so the second PMOS tube Q4 is turned on, and the drain outputs a high level to the microcontroller input port.

[0087] Assume VDC=-1V, substitute it into the above formula, and get VbQ3=-0.478V, VeQ3 is a positive voltage, VcQ3=0V, and the voltage relationship of VeQ3>VcQ3>VbQ3 is satisfied. At this time, the PNP transistor Q3 is in a saturated conduction state. After conduction, VeQ3 is close to 0V, VgsQ4=0V-3.3V=-3.3V<-1.8V, the second PMOS tube Q4 is turned on, and the drain outputs a high level to the microcontroller input port. In summary, when the input VDC is less than -1V, the PNP transistor Q3 has entered a saturated conduction state, and the second PMOS tube Q4 is turned on.

[0088] The collection and analysis of passive switch quantities is the same as the analysis when VDC=0V in the above-mentioned negative-sequence connection of active switches.

[0089] The present invention also discloses a detection method for a switch quantity acquisition circuit compatible with active and passive inputs, wherein the first port DI1 and the second port DI2 are respectively connected to two ends of an active switch or a passive switch, and the state change of the switch is recorded according to the high and low levels output by the input port of a single-chip computer. When the positive pole of the active switch is connected to the first port DI1 and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the positive pole of the active switch is connected to the first port DI1 and the switch is closed, the input port of the single-chip computer outputs a high level; when the positive pole of the active switch is connected to the second port DI2 and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the positive pole of the active switch is connected to the second port DI2 and the switch is closed, the input port of the single-chip computer outputs a high level; when the passive switch is connected to the acquisition port and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the passive switch is connected to the acquisition port and the switch is closed, the input port of the single-chip computer outputs a high level.

[0090] Through the simulation diagram, it can be determined that during the acquisition of the switch quantity, the output signal of the circuit matches the state of the switch, and the change data of the switch can be correctly collected.

[0091] For those skilled in the art, according to the teachings of the present invention, without departing from the principles and spirit of the present invention, changes, modifications, substitutions and variations made to the implementation methods are still within the protection scope of the present invention.

Claims

1. A switch quantity acquisition circuit compatible with active and passive inputs, comprising an acquisition port and a single-chip microcomputer input port, characterized in that: A protection conditioning module, a level conversion module and an output pulsating voltage smoothing processing module are arranged between the acquisition port and the single chip computer input port; The protection and conditioning module is used to absorb surge voltage and protect the subsequent circuit from being affected by static electricity and surge voltage; The level conversion module is used to convert the working state of the switch to be detected into high and low levels and input them into the single chip microcomputer; The output pulsating voltage smoothing processing module is used to reduce the ripple of the previous DC voltage and stabilize the high and low levels of the output; The level conversion module comprises a first conversion module and a second conversion module connected in parallel, wherein an NPN transistor Q1 and a first PMOS transistor Q2 are connected in series in the first conversion module, and a PNP transistor Q3 and a second PMOS transistor Q4 are connected in series in the second conversion module; The first conversion module is sequentially connected in series with a first Schottky diode D1, a first resistor R1, an NPN transistor Q1, and a first PMOS transistor Q2, a second resistor R2 is connected in parallel between the base and the emitter of the NPN transistor Q1, the emitter of the NPN transistor Q1 is grounded, the collector of the NPN transistor Q1 is connected to the gate of the first PMOS transistor Q2, a third resistor R3 is connected in parallel between the gate and the source of the first PMOS transistor Q2, the source of the first PMOS transistor Q2 is connected to the first power supply, and the drain of the first PMOS transistor Q2 is connected to the input port of the single-chip computer; The second conversion module is connected in series in sequence with a second Schottky diode D2, a sixth resistor R6, a PNP transistor Q3, and a second PMOS transistor Q4. The base of the PNP transistor Q3 is also connected to the second power supply. A seventh resistor R7 is connected in series between the second power supply and the base of the PNP transistor Q3. The collector of the PNP transistor Q3 is grounded. The emitter of the PNP transistor Q3 is connected to the eighth resistor R8. The eighth resistor R8 is grounded. The emitter of the PNP transistor Q3 is connected to the gate of the second PMOS transistor Q4. The source of the second PMOS transistor Q4 is connected to the third power supply. A ninth resistor R9 is connected in parallel between the gate and the source of the second PMOS transistor Q4. The drain of the second PMOS transistor Q4 is connected to the input port of the single-chip computer. A fifth resistor R5 is connected in series between the drain of the first PMOS tube Q2 and the ground, and a fifth capacitor C5 is connected in parallel to the fifth resistor R5; a tenth resistor R10 is connected in series between the drain of the second PMOS tube Q4 and the ground, and a fourth capacitor C4 is connected in parallel to the tenth resistor R10.

2. The active and passive input compatible switch quantity acquisition circuit according to claim 1, characterized in that: The acquisition port includes a first port DI1 and a second port DI2 , the first port DI1 is connected to a first Schottky diode D1 and a second Schottky diode D2 , and the second port DI2 is grounded.

3. The active and passive input compatible switch quantity acquisition circuit according to claim 2, characterized in that: The protection and conditioning module includes a varistor RV, a bidirectional transient suppression diode TVS1 and a first capacitor C1 connected in parallel between a first port DI1 and a second port DI2.

4. A detection method for a switch quantity acquisition circuit compatible with active and passive inputs, based on the circuit of claim 3, characterized in that: The first port DI1 and the second port DI2 are respectively connected to the two ends of an active switch or a passive switch, and the state change of the switch is recorded according to the high and low levels output by the input port of the single-chip computer. When the positive pole of the active switch is connected to the first port DI1 and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the positive pole of the active switch is connected to the first port DI1 and the switch is closed, the input port of the single-chip computer outputs a high level; when the positive pole of the active switch is connected to the second port DI2 and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the positive pole of the active switch is connected to the second port DI2 and the switch is closed, the input port of the single-chip computer outputs a high level; when the passive switch is connected to the acquisition port and the switch is disconnected, the input port of the single-chip computer outputs a low level; when the passive switch is connected to the acquisition port and the switch is closed, the input port of the single-chip computer outputs a high level.

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