A method for checking whether photoresist can block ion implantation

Abstract

A method for checking whether a photoresist can block ion implantation comprises: providing a substrate to be tested; performing an experimental treatment on the substrate to be tested, wherein the experimental treatment comprises: covering the surface of the substrate to be tested with a photoresist layer to be tested; adopting a target ion implantation process to implant ions into the surface of the photoresist layer to be tested; after implanting ions into the surface of the photoresist layer to be tested, removing the photoresist layer to be tested; after the experimental treatment, adopting a MOS device process to form a MOS device group to be tested on the substrate to be tested, wherein the MOS device group to be tested includes at least one MOS device to be tested; performing threshold voltage detection on each MOS device to be tested, and obtaining a threshold voltage detection value of at least one MOS device to be tested; and judging whether the photoresist layer to be tested can block ion implantation in the target ion implantation process based on the threshold voltage detection value of the at least one MOS device to be tested, thereby improving the accuracy of the judgment.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for checking whether photoresist can block ion implantation. Background Art

[0002] Photoresist (abbreviated as PR), also known as photoresist, is a photosensitive material. The photosensitive components in it will undergo chemical changes under the irradiation of light, thereby causing changes in the dissolution rate. Its main function is to transfer the pattern on the mask to a substrate such as a wafer.

[0003] In the existing ion implantation process, when ions are implanted into a target area (such as a well area), a photoresist is required to shield the non-target area to prevent the ions from being implanted into the non-target area and affecting the performance of the non-target area.

[0004] However, existing detection methods cannot confirm whether the photoresist has provided sufficient shielding effect. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for checking whether photoresist can block ion implantation, so as to improve the accuracy of the judgment.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for checking whether a photoresist can block ion implantation, comprising: providing a substrate to be tested; performing an experimental treatment on the substrate to be tested, wherein the experimental treatment comprises: covering the surface of the substrate to be tested with a photoresist layer to be tested; adopting a target ion implantation process to implant ions into the surface of the photoresist layer to be tested; after implanting ions into the surface of the photoresist layer to be tested, removing the photoresist layer to be tested; after the experimental treatment, adopting a MOS device process to form a MOS device group to be tested on the substrate to be tested, wherein the MOS device group to be tested includes at least one MOS device to be tested; performing threshold voltage detection on each of the MOS devices to be tested, and obtaining a threshold voltage detection value of at least one MOS device to be tested; and judging whether the photoresist layer to be tested can block ion implantation in the target ion implantation process based on the threshold voltage detection value of at least one MOS device to be tested.

[0007] Optionally, the method for determining whether the photoresist layer to be tested can block the ion injection in the target ion injection process based on the threshold voltage detection value of at least one of the MOS devices to be tested includes: obtaining a threshold voltage determination value of the MOS device group to be tested based on the threshold voltage detection value of at least one of the MOS devices to be tested; obtaining a reference threshold voltage value range; and according to the threshold voltage determination value and the reference threshold voltage value range, when the threshold voltage determination value is within the reference threshold voltage value range, determining that the photoresist layer to be tested fails to block the ion injection in the target ion injection process.

[0008] Optionally, the reference threshold voltage value range is obtained based on the first threshold voltage of the first control MOS device group; the method for forming the first control MOS device group includes: providing a first substrate, the first substrate having the same performance as the substrate to be tested; using the same MOS device process as that for forming the MOS device to be tested to form a first control MOS device group on the first substrate, the first control MOS device group including at least one first control MOS device; the method for obtaining the first threshold voltage includes: performing threshold voltage detection on each of the first control MOS devices respectively, and obtaining a threshold voltage detection value of at least one of the first control MOS devices; and obtaining the first threshold voltage of the first control MOS device group based on the threshold voltage detection value of at least one of the first control MOS devices.

[0009] Optionally, the first control MOS device includes: a first gate and a first source and drain region, the first gate is located on a portion of the surface of the first substrate, and the first source and drain region is located in the first substrate on both sides of the first gate; the MOS device process for forming the first control MOS device includes: forming the first gate on a portion of the surface of the first substrate; forming the first source and drain region in the first substrate on both sides of the first gate.

[0010] Optionally, the reference threshold voltage value range is also obtained based on the second threshold voltage of the second control MOS device group; the method for forming the second control MOS device group includes: providing a second substrate, the second substrate having the same performance as the substrate to be tested; using the same process as the target ion implantation process to implant ions into the second substrate; after implanting ions into the second substrate, using the same MOS device process as that for forming the MOS device to be tested to form a second control MOS device group on the second substrate, the second control MOS device group including at least one second control MOS device; the method for obtaining the second threshold voltage includes: performing threshold voltage detection on each of the second control MOS devices respectively, and obtaining a threshold voltage detection value of at least one second control MOS device; and obtaining the second threshold voltage of the second control MOS device group based on the threshold voltage detection value of at least one second control MOS device.

[0011] Optionally, the second control MOS device includes: a second gate and a second source and drain region, the second gate is located on a portion of the surface of the second substrate, and the second source and drain region is located in the second substrate on both sides of the second gate; the MOS device process for forming the second control MOS device includes: forming the second gate on a portion of the surface of the second substrate; forming the second source and drain region in the second substrate on both sides of the second gate.

[0012] Optionally, the method for forming the MOS device group to be tested, the first control MOS device group and the second control MOS device group further includes: after removing the photoresist layer to be tested and after injecting ions into the second substrate, allowing the first substrate, the second substrate and the substrate to be tested to enter the MOS device process flow at the same time.

[0013] Optionally, the method for forming the second control MOS device further includes: after injecting ions into the second substrate and before entering the MOS device process flow, processing the second substrate using the same process as that for removing the photoresist layer to be tested.

[0014] Optionally, the first control MOS device includes a Native MOS device.

[0015] Optionally, the doping concentration range of the substrate to be tested is 1E10atom / cm 3 to 1E11 atoms / cm 3 .

[0016] Optionally, the process parameters of the target ion implantation process include: the conductivity type of the ions includes N-type or P-type, and the ion implantation dose range is 1E11 atom / cm2 to 1E15 atoms / cm 2 .

[0017] Optionally, the process of removing the photoresist layer to be tested includes a dry etching process and a wet etching process after the dry etching process.

[0018] Optionally, the MOS device to be tested includes: an experimental gate and an experimental source and drain region, the experimental gate is located on a portion of the surface of the substrate to be tested, and the experimental source and drain region is located in the substrate to be tested on both sides of the experimental gate; the method for forming the MOS device group to be tested includes: forming the experimental gate on a portion of the surface of the substrate to be tested; and forming the experimental source and drain region in the substrate to be tested on both sides of the experimental gate.

[0019] Optionally, the method further includes: determining a thickness value or thickness range of a target photoresist layer according to a result of determining whether the photoresist layer to be tested can block ion implantation in the target ion implantation process.

[0020] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] In a method for checking whether a photoresist can block ion implantation provided by the technical solution of the present invention, an experimental treatment is performed on the substrate to be tested. After the experimental treatment, a MOS device group to be tested is formed on the substrate to be tested using a MOS device process. The MOS device group to be tested includes at least one MOS device to be tested. Due to different blocking effects of the photoresist layer to be tested on ion implantation, the threshold voltage detection values ​​of the MOS devices to be tested are different. Based on the threshold voltage detection values ​​of the MOS devices to be tested, it is determined whether the photoresist layer to be tested can block ion implantation in the target ion implantation process. The lower the doping concentration in the substrate to be tested, the more significant the effect of ion implantation on the threshold voltage of the MOS device to be tested. For example, the sensitivity of the threshold voltage of a native MOS device to ion implantation can be utilized to improve the accuracy of the determination.

[0022] Furthermore, based on the result of determining whether the photoresist layer to be tested can block ion implantation, a thickness value or thickness range of the photoresist layer that can block ion implantation is determined. Determining the thickness value or thickness range of the target photoresist layer facilitates selecting a photoresist of appropriate thickness in the target ion implantation process, thereby reducing the probability of ion breakdown of the photoresist and, after exposure and development of the photoresist, controlling the critical dimension (CD) of the photolithographic pattern formed by the residual photoresist. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1 to 4is a flowchart of the steps of a method for checking whether a photoresist can block ion implantation according to an embodiment of the present invention;

[0024] Figures 5 to 12 It is a structural schematic diagram of each step in the method for checking whether photoresist can block ion implantation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0026] As described in the background art, existing detection methods cannot confirm whether the photoresist has played an adequate shielding role. Specifically, existing detection methods use thermal wave (TW) or sheet resistance measurement methods to monitor ion implantation.

[0027] However, if the dose of ions penetrating the photoresist is small, due to the limitation of measurement accuracy, the existing detection method cannot accurately define whether the photoresist has played a sufficient shielding role.

[0028] To address the above-mentioned problem, the present invention provides a method for checking whether a photoresist can block ion implantation, wherein an experimental treatment is performed on the substrate to be tested. After the experimental treatment, a MOS device process is used to form a MOS device group to be tested on the substrate to be tested, wherein the MOS device group to be tested includes at least one MOS device to be tested. Due to different blocking effects of the photoresist layer to be tested on ion implantation, the threshold voltage detection values ​​of the MOS devices to be tested are different. Based on the threshold voltage detection values ​​of the MOS devices to be tested, it is determined whether the photoresist layer to be tested can block ion implantation in the target ion implantation process. The lower the doping concentration in the substrate to be tested, the more obvious the effect of ion implantation on the threshold voltage of the MOS device to be tested. For example, the sensitivity of the threshold voltage of the Native MOS device to ion implantation can be utilized to improve the accuracy of the determination.

[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 1 to 4 It is a flowchart of the steps of a method for checking whether a photoresist can block ion implantation according to an embodiment of the present invention.

[0031] In this embodiment, the method for checking whether the photoresist can block ion implantation includes the following steps:

[0032] Step S11, providing a substrate to be tested;

[0033] Step S12: performing an experimental treatment on the substrate to be tested, wherein the experimental treatment includes:

[0034] Covering the surface of the substrate to be tested with a photoresist layer to be tested;

[0035] Using a target ion implantation process, ions are implanted into the surface of the photoresist layer to be tested;

[0036] After injecting ions into the surface of the photoresist layer to be tested, removing the photoresist layer to be tested;

[0037] Step S13, after the experimental treatment, forming a MOS device group to be tested on the substrate to be tested by using a MOS device process, wherein the MOS device group to be tested includes at least one MOS device to be tested;

[0038] Step S14, performing threshold voltage detection on each of the MOS devices to be tested, and obtaining a threshold voltage detection value of at least one of the MOS devices to be tested;

[0039] Step S15 , determining whether the photoresist layer to be tested can block ion implantation in the target ion implantation process based on a threshold voltage detection value of at least one of the MOS devices to be tested.

[0040] The following is a detailed description with reference to the accompanying drawings.

[0041] Figures 5 to 12 It is a structural schematic diagram of each step in the method for checking whether photoresist can block ion implantation according to an embodiment of the present invention.

[0042] Please refer to Figure 5 , perform step S11 and provide a substrate 200 to be tested.

[0043] In this embodiment, the material of the substrate to be tested 200 is silicon.

[0044] The substrate to be tested 200 has a first conductivity type, which includes N-type or P-type. In this embodiment, the first conductivity type is P-type, which is used to form an NMOS device.

[0045] In other embodiments, the material of the substrate to be tested includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] In this embodiment, the doping concentration range of the substrate to be tested 200 is 1E10atom / cm 3 to 1E11atom / cm3 The lower the doping concentration in the substrate 200 to be tested, the greater the blocking degree of the subsequent photoresist layer to be tested against ion implantation, the greater the impact on the doping ion concentration in the substrate 200 to be tested, and thus the greater the impact on the threshold voltage of the formed MOS device to be tested.

[0047] In other embodiments, the substrate to be tested may have a well region, and the source / drain doped regions and the channel of the MOS device to be tested are located in the well region. However, the higher the doping concentration of the well region, the more difficult it is to obtain an accurate determination result.

[0048] Execute step S12 to perform experimental treatment on the substrate 200 to be tested. For the experimental treatment, please refer to Figures 6 and 7 .

[0049] Please continue to refer to Figure 6 The surface of the substrate 200 to be tested is covered with a photoresist layer 201 to be tested.

[0050] A photoresist under certain conditions (such as set thickness, set viscosity, etc.) can be set as the photoresist layer 201 to be tested, and then it is determined whether the photoresist layer 201 to be tested under the conditions can block ion implantation in a target ion implantation process.

[0051] Please continue to refer to Figure 6 , ions are implanted into the surface of the photoresist layer 201 to be tested using a target ion implantation process.

[0052] If the photoresist layer 201 to be tested cannot block the ion implantation in the target ion implantation process, ions will enter the substrate 200 to be tested. Conversely, if the photoresist layer 201 to be tested can block the ion implantation in the target ion implantation process, no ions will enter the substrate 200 to be tested.

[0053] The ions in the target ion implantation process have a second conductivity type, which is N-type or P-type. If ions enter the substrate 200 to be tested, the threshold voltage of the subsequently formed MOS device to be tested will be affected.

[0054] In this embodiment, the second conductivity type is the same as the first conductivity type, that is, the ions in the target ion implantation process are P-type. In other embodiments, the second conductivity type may be different from the first conductivity type.

[0055] It should be noted that when the photoresist layer 201 to be tested cannot block the ion injection in the target ion injection process, that is, ions enter the substrate to be tested 200, if the second conductivity type is the same as the first conductivity type, then compared with the case where no ions enter the substrate to be tested 200, the threshold voltage of the MOS device to be tested will be larger; conversely, if the second conductivity type is different from the first conductivity type, then compared with the case where no ions enter the substrate to be tested 200, the threshold voltage of the MOS device to be tested will be smaller.

[0056] In this embodiment, the process parameters of the target ion implantation process include: the conductivity type of the ions includes N-type or P-type, the ion implantation dose range is 1E11 atom / cm 2 to 1E15 atoms / cm 2 .

[0057] Please refer to Figure 7 , before applying the photoresist layer 201 to be tested (such as Figure 6 After ions are implanted into the surface of the photoresist layer 201 to be tested, the photoresist layer 201 to be tested is removed.

[0058] In this embodiment, the process of removing the photoresist layer 201 to be tested includes a dry etching process and a wet etching process after the dry etching process.

[0059] The dry etching process includes an ashing process.

[0060] Execute step S103, please refer to Figure 8 After the experimental treatment, a MOS device group to be tested is formed on the substrate to be tested 200 using a MOS device process, and the MOS device group to be tested includes at least one MOS device to be tested 30 .

[0061] It should be noted that, the greater the number of MOS devices 30 under test in the MOS device group under test, the more favorable it is for improving the accuracy of determination, but at the same time it increases the complexity of detection.

[0062] The MOS device 30 to be tested can be NMOS or PMOS. In this embodiment, the MOS device 30 to be tested is NMOS.

[0063] In this embodiment, the MOS device 30 under test includes: an experimental gate 300 and an experimental source and drain region 301 . The experimental gate 300 is located on a portion of the surface of the substrate 200 under test, and the experimental source and drain region 301 is located in the substrate 200 under test on both sides of the experimental gate 300 .

[0064] In this embodiment, the method for forming the MOS device group to be tested includes: forming the experimental gate 300 on a portion of the surface of the substrate to be tested 200 ; and forming the experimental source and drain regions 301 in the substrate to be tested 200 on both sides of the experimental gate 300 .

[0065] In this embodiment, the MOS device to be tested 30 further includes: an experimental sidewall 302 and an experimental shallowly doped region 303. The experimental sidewall 302 is located on the sidewall of the experimental gate 300. The experimental shallowly doped region 303 is located between the experimental source and drain regions 301 and is located in the substrate to be tested 200 at the bottom of the experimental sidewall 302.

[0066] In this embodiment, before forming the experimental source and drain regions 301, the process further includes: using the experimental gate 300 as a mask to form an initial shallow doping region (not shown in the figure) in the substrate to be tested 200; after forming the initial shallow doping region, forming a sidewall 302 on the sidewall of the experimental gate 300, with the initial shallow doping region at the bottom of the sidewall 302 as a shallow doping region 303; using the sidewall 302 and the experimental gate 300 as masks, injecting doping ions into the substrate to be tested 200 to form the experimental source and drain regions 301.

[0067] Continue to refer Figure 8 , executing step S14, performing threshold voltage detection on each of the MOS devices 30 under test, and obtaining a threshold voltage detection value of at least one of the MOS devices 30 under test.

[0068] Continue to refer Figure 8 , execute step S15, according to the threshold voltage detection value of at least one of the MOS devices 30 to be tested, the photoresist layer 201 to be tested (such as Figure 3 As shown in the figure, it is determined whether the ion implantation in the target ion implantation process can be blocked.

[0069] At this point, based on the threshold voltage detection value of the MOS device to be tested, it is determined whether the photoresist layer to be tested can block the ion implantation in the target ion implantation process. The lower the doping concentration in the substrate to be tested, the more obvious the impact of ion implantation on the threshold voltage of the MOS device to be tested. For example, the sensitivity of the threshold voltage of the Native MOS device to ion implantation can be utilized to improve the accuracy of the determination.

[0070] In this embodiment, the method for determining whether the photoresist layer 201 to be tested can block the ion implantation in the target ion implantation process according to the threshold voltage detection value of at least one of the MOS devices 30 to be tested is described in detail. Figure 8 , and refer to Figure 2 , including the following steps:

[0071] Step S151, obtaining a threshold voltage determination value Vtc of the MOS device group under test according to a threshold voltage detection value of at least one MOS device under test 30;

[0072] Step S152, obtaining a value range of a reference threshold voltage Vt0;

[0073] Step S153 , based on the threshold voltage determination value Vtc and the reference threshold voltage Vt0 value range, when the threshold voltage determination value Vtc is within the reference threshold voltage Vt0 value range, it is determined that the photoresist layer 201 to be tested fails to block the ion implantation in the target ion implantation process.

[0074] Specifically, the average value of the threshold voltage detection values ​​of all the MOS devices 30 under test in the MOS device group under test may be obtained as the threshold voltage determination value Vtc of the MOS device group under test.

[0075] The reference threshold voltage value range may be obtained based on the first threshold voltage of the first comparison MOS device group and / or the second threshold voltage of the second comparison MOS device group.

[0076] Here, the first control MOS device group is equivalent to the MOS device group to be tested formed when the photoresist layer 201 to be tested plays a blocking role and no ions are implanted into the substrate to be tested 200; the second control MOS device group is equivalent to the MOS device group to be tested formed when the photoresist layer 201 to be tested does not play any blocking role and all ions are implanted into the substrate to be tested 200.

[0077] In this embodiment, the reference threshold voltage value range is obtained according to the first threshold voltage Vt1 of the first reference MOS device group.

[0078] Specifically, the upper limit (or lower limit) of the reference threshold voltage value range can be obtained according to the first threshold voltage Vt1:

[0079] When the first conductivity type and the second conductivity type are the same, the lower limit of the reference threshold voltage value range can be obtained according to Vt1. Based on this situation, if the threshold voltage determination value Vtc of the MOS device group to be tested is within the reference threshold voltage value range, it can be determined that the photoresist layer to be tested fails to block ion implantation in the target ion implantation process; if the threshold voltage determination value Vtc of the MOS device group to be tested is lower than the lower limit of the reference threshold voltage value range, it can be determined that the photoresist layer to be tested can block ion implantation in the target ion implantation process;

[0080] On the contrary, when the first conductivity type and the second conductivity type are different, the upper limit of the reference threshold voltage value range can be obtained according to Vt1. Based on this situation, if the threshold voltage determination value Vtc of the MOS device group to be tested is within the reference threshold voltage value range, it can be determined that the photoresist layer to be tested fails to block the ion implantation in the target ion implantation process; if the threshold voltage determination value Vtc of the MOS device group to be tested is greater than the upper limit of the reference threshold voltage value range, it can be determined that the photoresist layer to be tested can block the ion implantation in the target ion implantation process.

[0081] Furthermore, the upper limit (lower limit) of the reference threshold voltage value range may be obtained based on actual experience or the second threshold voltage Vt2 of the second reference MOS device group.

[0082] In this embodiment, the reference threshold voltage value range is also obtained based on the second threshold voltage Vt2 of the second reference MOS device group. That is, the upper limit (lower limit) of the reference threshold voltage value range is obtained based on the second threshold voltage Vt2 of the second reference MOS device group.

[0083] In this embodiment, the method for forming the first control MOS device group is described in detail. Figure 3 , including the following steps:

[0084] Step S1521, providing a first substrate, wherein the first substrate has the same performance as the substrate to be tested;

[0085] Step S1522 : forming a first control MOS device group on the first substrate using the same MOS device process as that used to form the MOS device to be tested, wherein the first control MOS device group includes at least one first control MOS device.

[0086] Please refer to Figure 9 , providing a first substrate 400 , wherein the performance of the first substrate 400 is the same as that of the substrate to be tested 200 .

[0087] Please refer to Figure 10 A first control MOS device group is formed on the first substrate 400 using the same MOS device process as that used to form the MOS device under test. The first control MOS device group includes at least one first control MOS device 40 .

[0088] In this embodiment, the method for obtaining the first threshold voltage Vt1 includes: performing threshold voltage detection on each of the first control MOS devices 40 to obtain a threshold voltage detection value of at least one of the first control MOS devices 40; and obtaining the first threshold voltage Vt1 of the first control MOS device group based on the threshold voltage detection value of at least one of the first control MOS devices 40.

[0089] Specifically, the average value of the threshold voltage detection values of all the first reference MOS devices 40 in the first reference MOS device group can be obtained as the first threshold voltage Vt1.

[0090] In this embodiment, the first reference MOS device includes a Native MOS device. The doping concentration in the channel of the Native MOS device is very low, and the change of ions in the channel has a great influence on its threshold voltage.

[0091] In other embodiments, the first reference MOS device may also be a common MOS device.

[0092] In this embodiment, the first reference MOS device 40 includes: a first gate 401 and a first source-drain region 402. The first gate 401 is located on the surface of a part of the first substrate 200, and the first source-drain region 402 is located in the first substrate 400 on both sides of the first gate 401.

[0093] In this embodiment, the MOS device process for forming the first reference MOS device includes: forming the first gate 401 on the surface of a part of the first substrate 400; forming the first source-drain region 402 in the first substrate 400 on both sides of the first gate 401.

[0094] In this embodiment, the first reference MOS device 40 further includes: a first sidewall 403 and a first lightly doped region 404. The first sidewall 403 is located on the sidewall of the first gate 401, and the first lightly doped region 404 is located between the first source-drain regions 402 and in the first substrate 400 at the bottom of the first sidewall 403.

[0095] [[ID=2,0]]In this embodiment, the value range of the reference threshold voltage Vt0 is also obtained according to the second threshold voltage Vt2 of the second reference MOS device group.

[0096] Specifically, the value range of the reference threshold voltage is between the first threshold voltage Vt1 and the second threshold voltage Vt2.

[0097] It should be noted here that when the first conduction type and the second conduction type are the same, Vt1 < Vt2, that is, the upper limit value of the value range of the reference threshold voltage is obtained according to the second threshold voltage Vt2; and when the first conduction type and the second conduction type are different, Vt2 < Vt1, that is, the lower limit value of the value range of the reference threshold voltage is obtained according to the second threshold voltage Vt2.

[0098] In this embodiment, for the method of forming the second reference MOS device group, please refer to Figure 4, including the following steps:

[0099] Step S152i, providing a second substrate, wherein the second substrate has the same performance as the substrate to be tested;

[0100] Step S152ii, using the same process as the target ion implantation process, implanting ions into the second substrate;

[0101] Step S152iii: After ions are implanted into the second substrate, a second control MOS device group is formed on the second substrate using the same MOS device process as that used to form the MOS device to be tested, wherein the second control MOS device group includes at least one second control MOS device.

[0102] Please refer to Figure 11 , providing a second substrate 500, wherein the performance of the second substrate 500 is the same as that of the substrate to be tested 200; and using the same process as the target ion implantation process to implant ions into the second substrate 500.

[0103] Please refer to Figure 12 After ions are implanted into the second substrate 500, a second control MOS device group is formed on the second substrate 500 using the same MOS device process as that used to form the MOS device under test. The second control MOS device group includes at least one second control MOS device 50

[0104] In this embodiment, the method for obtaining the second threshold voltage Vt2 includes: performing threshold voltage detection on each second reference MOS device 50 to obtain a threshold voltage detection value of at least one second reference MOS device; and obtaining the second threshold voltage Vt2 of the second reference MOS device group based on the threshold voltage detection value of at least one second reference MOS device 50.

[0105] Specifically, an average value of the threshold voltage detection values ​​of all the second reference MOS devices 50 in the second reference MOS device group may be obtained as the second threshold voltage Vt2.

[0106] In this embodiment, the second control MOS device 50 includes: a second gate 501 and a second source and drain region 502 . The second gate 501 is located on a portion of the surface of the second substrate 500 , and the second source and drain region 502 is located in the second substrate 500 on both sides of the second gate 501 .

[0107] In this embodiment, the second control MOS device 50 further includes: a second sidewall 503 and a second shallowly doped region 502 , wherein the second sidewall 503 is located on the sidewall of the second gate 501 , and the second shallowly doped region 502 is located between the second source and drain regions 502 and within the second substrate 500 at the bottom of the second sidewall 503 .

[0108] In this embodiment, the method for forming the second control MOS device 50 includes: forming the second gate 501 on the second substrate 500 ; and forming the second source and drain regions 502 in the second substrate 500 on both sides of the second gate 501 .

[0109] In this embodiment, the method for forming the MOS device group to be tested, the first control MOS device group and the second control MOS device group further includes: after removing the photoresist layer 201 to be tested and after injecting ions into the second substrate 500, allowing the first substrate 400, the second substrate 500 and the substrate to be tested 200 to enter the MOS device process flow at the same time.

[0110] In this embodiment, the method for forming the second control MOS device 50 further includes: after injecting ions into the second substrate 500 and before entering the MOS device process flow, the second substrate 500 is processed using the same process as the process for removing the photoresist layer 201 to be tested.

[0111] Here, after ions are implanted into the second substrate 500 and onto the surface of the photoresist layer 201 to be tested, the second substrate 500 and the substrate 200 to be tested may simultaneously enter the process of removing the photoresist layer 201 to be tested.

[0112] In this embodiment, the thickness value or thickness range of the target photoresist layer is determined according to the result of determining whether the photoresist layer 201 to be tested can block ion implantation in the target ion implantation process.

[0113] Here, the target photoresist layer thickness value or thickness range is determined to select a photoresist of appropriate thickness in the target ion implantation process, thereby reducing the probability of ion breakdown of the photoresist and controlling the critical dimension (CD) of the photolithographic pattern formed by the residual photoresist after exposure and development of the photoresist.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for checking whether a photoresist can block ion implantation, characterized in that: include: providing a substrate to be tested; Performing an experimental treatment on the substrate to be tested, wherein the experimental treatment includes: Covering the surface of the substrate to be tested with a photoresist layer to be tested; Using a target ion implantation process, ions are implanted into the surface of the photoresist layer to be tested; After injecting ions into the surface of the photoresist layer to be tested, removing the photoresist layer to be tested; After the experimental treatment, a MOS device group to be tested is formed on the substrate to be tested by using a MOS device process, wherein the MOS device group to be tested includes at least one MOS device to be tested; Performing threshold voltage detection on each of the MOS devices to be tested, respectively, to obtain a threshold voltage detection value of at least one of the MOS devices to be tested; According to the threshold voltage detection value of at least one of the MOS devices to be tested, it is determined whether the photoresist layer to be tested can block the ion implantation in the target ion implantation process.

2. The method for checking whether a photoresist can block ion implantation according to claim 1, wherein: The method for determining whether the photoresist layer to be tested can block ion injection in the target ion injection process based on the threshold voltage detection value of at least one of the MOS devices to be tested includes: obtaining a threshold voltage determination value of the MOS device group to be tested based on the threshold voltage detection value of at least one of the MOS devices to be tested; obtaining a reference threshold voltage value range; and determining, based on the threshold voltage determination value and the reference threshold voltage value range, that the photoresist layer to be tested fails to block ion injection in the target ion injection process when the threshold voltage determination value is within the reference threshold voltage value range.

3. The method for checking whether a photoresist can block ion implantation according to claim 2, wherein: The reference threshold voltage value range is obtained according to the first threshold voltage of the first reference MOS device group; The method for forming the first control MOS device group includes: providing a first substrate, the first substrate having the same performance as the substrate to be tested; using the same MOS device process as that for forming the MOS device to be tested to form a first control MOS device group on the first substrate, the first control MOS device group including at least one first control MOS device; the method for obtaining the first threshold voltage includes: performing threshold voltage detection on each of the first control MOS devices respectively to obtain a threshold voltage detection value of at least one of the first control MOS devices; and obtaining a first threshold voltage of the first control MOS device group based on the threshold voltage detection value of at least one of the first control MOS devices.

4. The method for checking whether a photoresist can block ion implantation according to claim 3, wherein: The first control MOS device includes: a first gate and a first source and drain region, the first gate is located on a portion of the surface of the first substrate, and the first source and drain region is located in the first substrate on both sides of the first gate; the MOS device process for forming the first control MOS device includes: forming the first gate on a portion of the surface of the first substrate; forming the first source and drain region in the first substrate on both sides of the first gate.

5. The method for checking whether a photoresist can block ion implantation according to claim 3, wherein: The reference threshold voltage value range is also obtained based on the second threshold voltage of the second reference MOS device group; The method for forming the second control MOS device group includes: providing a second substrate, the second substrate having the same performance as the substrate to be tested; using a process identical to the target ion implantation process to implant ions into the second substrate; after implanting ions into the second substrate, using a MOS device process identical to that used to form the MOS device to be tested to form a second control MOS device group on the second substrate, the second control MOS device group including at least one second control MOS device; the method for obtaining the second threshold voltage includes: performing threshold voltage detection on each of the second control MOS devices, respectively, to obtain a threshold voltage detection value of at least one second control MOS device; and obtaining a second threshold voltage of the second control MOS device group based on the threshold voltage detection value of at least one second control MOS device.

6. The method for checking whether a photoresist can block ion implantation according to claim 5, wherein: The second control MOS device includes: a second gate and a second source and drain region, the second gate is located on a portion of the surface of the second substrate, and the second source and drain region is located in the second substrate on both sides of the second gate; the MOS device process for forming the second control MOS device includes: forming the second gate on a portion of the surface of the second substrate; forming the second source and drain region in the second substrate on both sides of the second gate.

7. The method for checking whether a photoresist can block ion implantation according to claim 5, wherein: The method for forming the MOS device group to be tested, the first control MOS device group and the second control MOS device group further includes: after removing the photoresist layer to be tested and after injecting ions into the second substrate, allowing the first substrate, the second substrate and the substrate to be tested to enter the MOS device process flow at the same time.

8. The method for checking whether a photoresist can block ion implantation according to claim 5, wherein: The method for forming the second control MOS device further includes: after implanting ions into the second substrate and before entering the MOS device process flow, processing the second substrate using the same process as that for removing the photoresist layer to be tested.

9. The method for checking whether a photoresist can block ion implantation according to claim 3, wherein: The first control MOS device includes a Native MOS device.

10. The method for inspecting whether a photoresist can block ion implantation according to claim 1, wherein: The doping concentration range of the substrate to be tested is 1E10atom / cm 3 to 1E11 atoms / cm 3 .

11. The method for inspecting whether a photoresist can block ion implantation according to claim 1, wherein: The process parameters of the target ion implantation process include: the conductivity type of the ions includes N-type or P-type, the ion implantation dose range is 1E11 atom / cm 2 to 1E15 atoms / cm 2 .

12. The method for inspecting whether a photoresist can block ion implantation according to claim 1, wherein: The process of removing the photoresist layer to be tested includes a dry etching process and a wet etching process after the dry etching process.

13. The method for inspecting whether a photoresist can block ion implantation according to claim 1, wherein: The MOS device to be tested includes: an experimental gate and an experimental source and drain region, the experimental gate is located on a portion of the surface of the substrate to be tested, and the experimental source and drain region are located in the substrate to be tested on both sides of the experimental gate; the method for forming the MOS device group to be tested includes: forming the experimental gate on a portion of the surface of the substrate to be tested; and forming the experimental source and drain regions in the substrate to be tested on both sides of the experimental gate.

14. The method for inspecting whether a photoresist can block ion implantation according to claim 1, wherein: Also includes: The thickness value or thickness range of the target photoresist layer is determined according to a result of determining whether the photoresist layer to be tested can block ion implantation in the target ion implantation process.

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