A control signal multiplexing circuit

Abstract

The present application discloses a control signal multiplexing circuit, which relates to the field of circuit design. The multiplexing circuit includes a first output module, a second output module, a judgment signal conversion module and a judgment signal output module. The first output module receives the first signal S1 or the second signal S2, and outputs a working signal S1-T and a first conversion signal S1 / S2-B; the second output module outputs a rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B; the judgment signal conversion module outputs a second conversion signal SD based on the rising edge trigger signal S2-T; the judgment signal output module outputs a judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD. In this solution, a low-level judgment signal S3 is output when the first signal S1 is input; a high-level judgment signal S3 is output when the second signal S2 is input, which realizes the effective input and output of multiple signals on the basis of reducing the number of signal input terminals.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, and in particular to a control signal multiplexing circuit. Background Art

[0002] With the rapid development of electronic technology, integration and miniaturization have become important trends in the development of integrated circuit control chips. On the one hand, in order to meet the needs of integration, more circuit modules need to be integrated inside the control chip, which requires the control chip to be able to process more signal inputs, thereby increasing the number of signal input terminals. On the other hand, in order to achieve miniaturization, the volume size of the control chip needs to be further reduced, which requires that the number of signal input terminals be reduced as much as possible while ensuring the chip function to save space resources. However, in the prior art, it is difficult to balance between increasing the number of signal input terminals to meet the needs of integration and reducing the number of signal input terminals to achieve miniaturization.

[0003] Therefore, in order to make the integrated circuit control chip meet the development needs of integration and miniaturization at the same time, the field is in urgent need of a control signal multiplexing circuit that can realize the effective input and output of multiple signals while reducing the number of signal input terminals. Summary of the invention

[0004] The purpose of the present invention is to provide a control signal multiplexing circuit that can realize the effective input and output of multiple signals on the basis of reducing the number of signal input terminals, thereby solving the problem in the prior art that integrated circuit control chips are difficult to simultaneously take into account integration and miniaturization.

[0005] To achieve the above object, the present invention discloses the following technical solution:

[0006] A first aspect of the present invention provides a control signal multiplexing circuit, the circuit comprising a first output module, a second output module, a judgment signal conversion module and a judgment signal output module;

[0007] The first output module is used to receive the input first signal S1 or second signal S2, generate and output the working signal S1-T and the first conversion signal S1 / S2-B, and input the first conversion signal S1 / S2-B to the second output module and the judgment signal output module respectively;

[0008] The second output module generates and outputs a rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B, and inputs the rising edge trigger signal S2-T to the judgment signal conversion module;

[0009] The judgment signal conversion module generates a second conversion signal SD based on the rising edge trigger signal S2-T, and inputs the second conversion signal SD to the judgment signal output module;

[0010] The judgment signal output module generates and outputs a judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD;

[0011] When the first signal S1 is input to the first output module, the judgment signal output module outputs a low-level judgment signal S3; when the second signal S2 is input to the first output module, the judgment signal output module outputs a high-level judgment signal S3.

[0012] In a possible implementation, in the first output module, the input ends of the first signal S1 and the second signal S2 are grounded through the first resistor R1, the first switch tube M1 and the second resistor R2 in sequence, and the control end of the first switch tube M1 is connected to the power supply voltage VCC, and the second resistor R2 is connected in parallel to the first capacitor C1;

[0013] The power supply voltage VCC is grounded through the third resistor R3 and the second switch tube M2 in sequence, and the control end of the second switch tube M2 is connected to the current output end of the first switch tube M1, and the current input end of the second switch tube M2 is connected to the output end of the first conversion signal S1 / S2-B;

[0014] The power supply voltage VCC is also grounded through the fourth switch tube M4, the fourth resistor R4 and the third switch tube M3 in sequence, and the control end of the fourth switch tube M4 is connected to the control end of the third switch tube M3 and connected to the output end of the first conversion signal S1 / S2-B, the current output end of the fourth switch tube M4 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, and the current output end of the fourth switch tube M4 outputs the working signal S1-T.

[0015] In a possible implementation, in the second output module, the input end of the first conversion signal S1 / S2 -B is connected to an input end of the first NAND gate U1 through a fifth inverter F5;

[0016] The power supply voltage VCC is connected to the ground through the sixth switch tube M6, the fifth resistor R5 and the fifth switch tube M5 in sequence, and the control end of the sixth switch tube M6 is connected to the control end of the fifth switch tube M5 and connected to the output end of the fifth inverter F5, the current output end of the sixth switch tube M6 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is grounded, and the current output end of the sixth switch tube M6 is connected to the other input end of the first NAND gate U1;

[0017] The output end of the first NAND gate U1 outputs the rising edge trigger signal S2-T through the eighth inverter F8.

[0018] In a possible implementation, in the judgment signal conversion module, the rising edge trigger signal S2-T is connected to the input end of the ninth inverter F9;

[0019] The power supply voltage VCC is grounded through the eighth switch tube M8, the sixth resistor R6 and the seventh switch tube M7 in sequence, and the control end of the eighth switch tube M8 is connected to the control end of the seventh switch tube M7 and connected to the output end of the ninth inverter F9, the current output end of the eighth switch tube M8 is connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and the current output end of the eighth switch tube M8 outputs the second conversion signal SD.

[0020] In a possible implementation, in the judgment signal output module, the first conversion signal S1 / S2-B and the second conversion signal SD are respectively connected to the two input terminals of the second NAND gate U2, the output terminal of the second NAND gate U2 is connected to the set terminal S of the RS trigger Q1, the second conversion signal SD is also connected to the reset terminal R of the RS trigger Q1, and the output terminal of the RS trigger outputs the judgment signal S3.

[0021] In a possible implementation, the resistance of the fourth resistor R4 and the capacitance of the second capacitor C2 are respectively set to a first preset resistance and a first preset capacitance, so that before the second signal S2 is switched from a low level to a high level, the voltage in the second capacitor C2 is greater than the flip voltage of the third inverter F3;

[0022] The resistance of the fifth resistor R5 and the capacitance of the third capacitor C3 are set to the second preset resistance and the second preset capacitance respectively, so that before the second signal S2 switches from a high level to a low level, the voltage in the third capacitor C3 remains greater than the flip voltage of the sixth inverter F6 for a period of time;

[0023] The resistance of the sixth resistor R6 and the capacitance of the fourth capacitor C4 are set to the third preset resistance and the third preset capacitance respectively, so that before the rising edge trigger signal S2-T switches from a low level to a high level, the voltage in the fourth capacitor C4 is greater than the flip voltage of the tenth inverter F10.

[0024] In a possible implementation, the current input end of the second switch tube M2 is connected to the output end of the first conversion signal S1 / S2 -B through the first inverter F1 and the second inverter F2 in sequence;

[0025] The current output end of the fourth switch tube M4 sequentially outputs the working signal S1-T through the third inverter F3 and the fourth inverter F4;

[0026] The current output end of the sixth switch tube M6 is connected to the other input end of the first NAND gate U1 through the sixth inverter F6 and the seventh inverter F7 in sequence;

[0027] The current output end of the eighth switch tube M8 sequentially outputs the second conversion signal SD through the tenth inverter F10 and the eleventh inverter F11;

[0028] The output end of the RS trigger sequentially outputs the determination signal S3 through the twelfth inverter F12 and the thirteenth inverter F13.

[0029] In a possible implementation, the number of inverters in the branch where the first inverter F1 and the second inverter F2 are located is 2n1;

[0030] The number of inverters in the branch where the third inverter F3 and the fourth inverter F4 are located is 2n2;

[0031] The number of inverters in the branch where the sixth inverter F6 and the seventh inverter F7 are located is 2n3;

[0032] The number of inverters in the branch where the tenth inverter F10 and the eleventh inverter F11 are located is 2n4;

[0033] The number of inverters in the branch where the twelfth inverter F12 and the thirteenth inverter F13 are located is 2n5;

[0034] Among them, n1, n2, n3, n4 and n5 are all integers.

[0035] In a possible implementation, the first switch tube M1, the second switch tube M2, the third switch tube M3, the fifth switch tube M5 and the seventh switch tube M7 are all NMOS tubes;

[0036] The fourth switch tube M4 , the sixth switch tube M6 , and the eighth switch tube M8 are all PMOS tubes.

[0037] In a possible implementation, when the first signal S1 is input to the first output module, the first output module outputs a first conversion signal S1 / S2-B and a high-level working signal S1-T; the second output module outputs a low-level rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B; the judgment signal conversion module outputs a second conversion signal SD based on the low-level rising edge trigger signal S2-T; the judgment signal output module outputs a low-level judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD;

[0038] When the second signal S2 is input to the first output module, the first output module outputs a first conversion signal S1 / S2-B and a high-level working signal S1-T; the second output module outputs a rising edge trigger signal S2-T with the same frequency as the second signal S2 based on the first conversion signal S1 / S2-B; the judgment signal conversion module outputs a second conversion signal SD based on the rising edge trigger signal S2-T with the same frequency as the second signal S2; the judgment signal output module outputs a high-level judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD.

[0039] A second aspect of the present invention provides an integrated circuit control chip, wherein the integrated circuit control chip comprises the control signal multiplexing circuit as described in the first aspect.

[0040] The effects provided in the content of the invention are only the effects of the embodiments, not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:

[0041] The present application provides a control signal multiplexing circuit, including a first output module, a second output module, a judgment signal conversion module and a judgment signal output module. The first output module receives an input first signal S1 or a second signal S2, generates and outputs a working signal S1-T and a first conversion signal S1 / S2-B; the second output module generates and outputs a rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B; the judgment signal conversion module generates and outputs a second conversion signal SD based on the rising edge trigger signal S2-T; the judgment signal output module generates and outputs a judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD. In this circuit, the input of two signals, the first signal S1 and the second signal S2, is realized through a single signal input terminal, and two different output signals, the first output signal (a low-level judgment signal S3 and a low-level rising edge trigger signal S2-T) and the second output signal (a high-level judgment signal S3 and a rising edge trigger signal S2-T with the same frequency as the second signal S2) are obtained respectively. Therefore, on the basis of reducing the number of signal input terminals, effective input and output of multiple signals can be realized, meeting the needs of dual development of integration and miniaturization of integrated circuit control chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0043] Figure 1 A schematic diagram of a control signal multiplexing circuit structure of an embodiment of the present application;

[0044] Figure 2 for Figure 1 The circuit schematic diagram of the first output module;

[0045] Figure 3 for Figure 1 The circuit schematic diagram of the second output module;

[0046] Figure 4 for Figure 1 The circuit schematic diagram of the judgment signal conversion module;

[0047] Figure 5 for Figure 1 The circuit schematic diagram of the judgment signal output module;

[0048] Figure 6 for Figure 1 A specific structural principle diagram of a control signal multiplexing circuit of an embodiment;

[0049] Figure 7 is a schematic diagram of waveforms of various signals when the input signal is the first signal S1;

[0050] Figure 8 Schematic diagram of various signal waveforms when the input signal is the second signal S2. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] It should be noted that references to "one embodiment", "embodiment", "example embodiment", etc. in this specification refer to the embodiment being described which may include specific features, structures or characteristics, but not every embodiment must include these specific features, structures or characteristics. In addition, such expressions do not refer to the same embodiment. Furthermore, when describing specific features, structures or characteristics in conjunction with an embodiment, whether or not there is an explicit description, it is indicated that incorporating such features, structures or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0053] As described in the background technology, it is difficult for existing integrated circuit control chips to simultaneously meet the development requirements of integration and miniaturization, and it is impossible to effectively control the size of the chip while increasing the signal processing capability. Based on this, the embodiment of the present application provides a control signal multiplexing circuit, which aims to achieve efficient multiplexing of multiple signals while reducing the number of signal input terminals, so as to meet the integration and miniaturization requirements of the integrated circuit control chip, improve chip performance and optimize its space utilization.

[0054] refer to Figure 1 , Figure 1 FIG. 2 shows a schematic diagram of a control signal multiplexing circuit according to an embodiment of the present application. Figure 1 As shown, the circuit includes a first output module, a second output module, a judgment signal conversion module and a judgment signal output module. Among them, the first output module is used to receive the input first signal S1 or the second signal S2, generate and output the working signal S1-T and the first conversion signal S1 / S2-B, and input the first conversion signal S1 / S2-B to the second output module and the judgment signal output module respectively. The second output module generates and outputs the rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B, and inputs the rising edge trigger signal S2-T to the judgment signal conversion module. The judgment signal conversion module generates the second conversion signal SD based on the rising edge trigger signal S2-T, and inputs the second conversion signal SD to the judgment signal output module. The judgment signal output module generates and outputs the judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD.

[0055] In the circuit of this embodiment, when the first signal S1 is input to the first output module, the judgment signal output module outputs a low-level judgment signal S3. When the second signal S2 is input to the first output module, the judgment signal output module outputs a high-level judgment signal S3. That is, this circuit structure realizes the input of two signals through a single signal input terminal, and obtains two different output signals, achieving the purpose of multiplexing multiple signals while reducing the number of signal input terminals, and taking into account the integration and miniaturization requirements of the integrated circuit control chip.

[0056] Figure 2 for Figure 1 The circuit diagram of the first output module in FIG. Figure 2As shown, in the first output module of this embodiment, the input ends of the first signal S1 and the second signal S2 are grounded through the first resistor R1, the first switch tube M1 and the second resistor R2 in sequence, and the control end of the first switch tube M1 is connected to the power supply voltage VCC, and the second resistor R2 is connected in parallel to the first capacitor C1. The power supply voltage VCC is grounded through the third resistor R3 and the second switch tube M2 in sequence, and the control end of the second switch tube M2 is connected to the current output end of the first switch tube M1; the current input end of the second switch tube M2 outputs the first conversion signal S1 / S2-B through the first inverter F1 and the second inverter F2 in sequence. The power supply voltage VCC is also grounded through the fourth switch tube M4, the fourth resistor R4 and the third switch tube M3 in sequence, and the control end of the fourth switch tube M4 is connected to the control end of the third switch tube M3 and connected to the output end of the first conversion signal S1 / S2-B; the current output end of the fourth switch tube M4 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded; the current output end of the fourth switch tube M4 also outputs the working signal S1-T through the third inverter F3 and the fourth inverter F4 in sequence. Among them, in this circuit, the first inverter F1 and the second inverter F2, as well as the third inverter F3 and the fourth inverter F4 are set in order to improve the current capacity of the branch where the inverter is located. Therefore, according to the actual circuit demand for current capacity, no inverter or an even number of inverters can be set in the corresponding branch. For example, the branch where the first inverter F1 and the second inverter F2 are located can be provided with no inverter, or 2 or 4 even number of inverters can be set, and the present application is not limited to this.

[0057] In some embodiments, the resistance of the fourth resistor R4 and the capacitance of the second capacitor C2 can be set to the first preset resistance and the first preset capacitance respectively, so that before the second signal S2 switches from a low level to a high level, the voltage in the second capacitor C2 is greater than the flip voltage of the third inverter F3.

[0058] Figure 3 for Figure 1 The circuit diagram of the second output module in FIG. Figure 3As shown, in the second output module of this embodiment, the input end of the first conversion signal S1 / S2-B is connected to an input end of the first NAND gate U1 through the fifth inverter F5. The power supply voltage VCC is grounded through the sixth switch tube M6, the fifth resistor R5 and the fifth switch tube M5 in sequence, and the control end of the sixth switch tube M6 is connected to the control end of the fifth switch tube M5 and connected to the output end of the fifth inverter F5; the current output end of the sixth switch tube M6 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded; the current output end of the sixth switch tube M6 is also connected to the other input end of the first NAND gate U1 through the sixth inverter F6 and the seventh inverter F7 in sequence. The output end of the first NAND gate U1 outputs the rising edge trigger signal S2-T through the eighth inverter F8. Similarly, in this circuit, the number of the sixth inverter F6 and the seventh inverter F7 is set according to the current capacity requirements of the actual circuit.

[0059] In some embodiments, the resistance of the fifth resistor R5 and the capacitance of the third capacitor C3 can be set to a second preset resistance and a second preset capacitance, respectively, so that before the second signal S2 switches from a high level to a low level, the voltage in the third capacitor C3 remains greater than the flipping voltage of the sixth inverter F6 for a period of time.

[0060] Figure 4 for Figure 1 The circuit schematic diagram of the judgment signal conversion module. Figure 4 As shown, in the judgment signal conversion module of this embodiment, the rising edge trigger signal S2-T is connected to the input end of the ninth inverter F9. The power supply voltage VCC is grounded through the eighth switch tube M8, the sixth resistor R6 and the seventh switch tube M7 in sequence, and the control end of the eighth switch tube M8 is connected to the control end of the seventh switch tube M7 and connected to the output end of the ninth inverter F9; the current output end of the eighth switch tube M8 is connected to one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is grounded; the current output end of the eighth switch tube M8 also outputs the second conversion signal SD through the tenth inverter F10 and the eleventh inverter F11 in sequence. Similarly, in this circuit, the number of the tenth inverter F10 and the eleventh inverter F11 is set according to the current capacity requirements of the actual circuit.

[0061] In some embodiments, the resistance of the sixth resistor R6 and the capacitance of the fourth capacitor C4 can be set to a third preset resistance and a third preset capacitance, respectively, so that before the rising edge trigger signal S2-T switches from a low level to a high level, the voltage in the fourth capacitor C4 is greater than the flipping voltage of the tenth inverter F10.

[0062] Figure 5 for Figure 1 The circuit schematic diagram of the judgment signal output module. Figure 5As shown, in the judgment signal output module of this embodiment, the first conversion signal S1 / S2-B and the second conversion signal SD are respectively connected to the two input terminals of the second NAND gate U2, and the output terminal of the second NAND gate U2 is connected to the set terminal S of the RS trigger Q1; the second conversion signal SD is also connected to the reset terminal R of the RS trigger Q1; the output terminal of the RS trigger sequentially passes through the twelfth inverter F12 and the thirteenth inverter F13 to output the judgment signal S3. Similarly, in this circuit, the number of the twelfth inverter F12 and the thirteenth inverter F13 is set according to the current capacity requirements of the actual circuit.

[0063] In some embodiments, the first switch transistor M1, the second switch transistor M2, the third switch transistor M3, the fifth switch transistor M5 and the seventh switch transistor M7 are all NMOS transistors, and the fourth switch transistor M4, the sixth switch transistor M6 and the eighth switch transistor M8 are all PMOS transistors.

[0064] Specific reference Figure 6 , Figure 6 for Figure 1 A specific structural principle diagram of a control signal multiplexing circuit of an embodiment. As can be seen from the figure, the circuit includes Figure 2 The first output module shown, Figure 3 The second output module shown, Figure 4 The judgment signal conversion module shown and Figure 5 The judgment signal output module shown. In the circuit of this embodiment, when the first signal S1 is input to the first output module, the first output module outputs the first conversion signal S1 / S2-B and the high-level working signal S1-T; the second output module outputs the low-level rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B; the judgment signal conversion module outputs the second conversion signal SD based on the low-level rising edge trigger signal S2-T; the judgment signal output module outputs the low-level judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD. When the second signal S2 is input to the first output module, the first output module outputs the first conversion signal S1 / S2-B and the high-level working signal S1-T; the second output module outputs the rising edge trigger signal S2-T with the same frequency as the second signal S2 based on the first conversion signal S1 / S2-B; the judgment signal conversion module outputs the second conversion signal SD based on the rising edge trigger signal S2-T with the same frequency as the second signal S2; the judgment signal output module outputs a high-level judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD.

[0065] In some embodiments, when the first signal S1 is input, the control signal multiplexing circuit outputs a high-level working signal S1-T and a low-level judgment signal S3. After the low-level judgment signal S3 is input into the control circuit (not shown in the present application), the control circuit only uses the high-level working signal S1-T to participate in the subsequent control work. When the second signal S2 is input, the control signal multiplexing circuit outputs a high-level working signal S1-T, a rising edge trigger signal S2-T with the same frequency as the second signal S2, and a high-level judgment signal S3. After the high-level judgment signal S3 is input into the control circuit (not shown in the present application), the control circuit uses the high-level working signal S1-T and the rising edge trigger signal S2-T with the same frequency as the second signal S2 to participate in the subsequent control work.

[0066] Next, based on Figure 6 The specific structural principle diagram of the control signal multiplexing circuit of the embodiment is divided into two cases where the first signal S1 or the second signal S2 is input at the input end, and its working principle and working process are described in detail. Since each signal is a periodic signal, in order to facilitate the description of the working principle, the input signal is high level when the circuit is powered on.

[0067] refer to Figure 7 , Figure 7 Schematic diagram of various signal waveforms when the input signal is the first signal S1 is shown. Figure 7 The waveform diagram in the figure introduces the working principle of the circuit when the input signal is the first signal S1:

[0068] Depend on Figure 7 It can be seen that when the input signal S1 / S2 is the first signal S1, at time T, after the circuit is powered on, the first signal S1 is in a high level state, and after the power supply voltage VCC is input to the control end of the first switch tube M1, the first switch tube M1 is turned on. At this time, the voltage at the control end of the second switch tube M2 is pulled up by the first switch tube M1, and the second switch tube M2 is also turned on, so the input end of the first inverter F1 is pulled down by the second switch tube M2. Afterwards, the low-level voltage passes through the first inverter F1 and the second inverter F2, and outputs a low-level first conversion signal S1 / S2-B. And at this time, after the low-level first conversion signal S1 / S2-B is input to the control end of the third switch tube M3 and the control end of the fourth switch tube M4, the fourth switch tube M4 is turned on, and the third switch tube M3 is turned off. At this time, the voltage at the input end of the third inverter F3 is pulled up by the fourth switch tube M4, so it can be obtained that the working signal S1-T output by the fourth inverter F4 is a high level.

[0069] At this time, after the low-level first conversion signal S1 / S2-B is input into the fifth inverter F5, the fifth inverter F5 outputs a high-level signal, so the fifth switch tube M5 is turned on and the sixth switch tube M6 is turned off. Since the circuit has just been powered on, there is no charge in the third capacitor C3. Therefore, the fifth switch tube M5 after being turned on instantly pulls down the input voltage of the sixth inverter F6. Therefore, at this time, the output of the seventh inverter F7 is a low level. Afterwards, after the low-level signal is input into the first NAND gate U1, the first NAND gate U1 must output a high-level signal. After the high-level signal passes through the eighth inverter F8, it outputs a low-level rising edge trigger signal S2-T.

[0070] At this time, after the low-level rising edge trigger signal S2-T is input into the ninth inverter F9, the ninth inverter F9 outputs a high level, so the eighth switch tube M8 is turned off and the seventh switch tube M7 is turned on. Since the circuit has just been powered on, there is no charge in the fourth capacitor C4. Therefore, the seventh switch tube M7, after being turned on, instantly pulls down the input terminal voltage of the tenth inverter F10, so it can be obtained that the second conversion signal SD output by the eleventh inverter F11 is a low level. After the low-level second conversion signal SD is input into the R terminal of the RS trigger Q1, the RS trigger Q1 outputs a low-level signal. Therefore, at this time, after the low-level signal passes through the twelfth inverter F12 and the thirteenth inverter F13, a low-level judgment signal S3 is obtained.

[0071] refer to Figure 8 , Figure 8 The following is a schematic diagram of the waveforms of various signals when the input signal is the second signal S2. Figure 8 The waveform diagram in the figure introduces the working principle of the circuit when the input signal is the second signal S2:

[0072] Depend on Figure 8 It can be seen that when the input signal S1 / S2 is the second signal S2, at time T, the power supply voltage VCC is input to the control end of the first switch tube M1. In the first cycle after the circuit is powered on, first, since the second signal S2 is in a high level state, the first switch tube M1 is turned on. At this time, the first capacitor C1 is charged, and the voltage at the control end of the second switch tube M2 is pulled up by the first switch tube M1, and the second switch tube M2 is turned on. Therefore, the input end of the first inverter F1 is pulled down by the second switch tube M2. Afterwards, the low-level voltage passes through the first inverter F1 and the second inverter F2 to obtain a low-level first conversion signal S1 / S2-B. At this time, after the low-level first conversion signal S1 / S2-B is input to the control end of the third switch tube M3 and the control end of the fourth switch tube M4, the fourth switch tube M4 is turned on and the third switch tube M3 is turned off. At this time, the second capacitor C2 is charged, and the voltage at the input end of the third inverter F3 is pulled up by the fourth switch tube M4, so it can be obtained that the working signal S1-T output by the fourth inverter F4 is a high level.

[0073] At this time, after the low-level first conversion signal S1 / S2-B is input into the fifth inverter F5, the fifth inverter F5 outputs a high-level signal, so the fifth switch tube M5 is turned on and the sixth switch tube M6 is turned off. Since the circuit has just been powered on, there is no charge in the third capacitor C3. Therefore, the fifth switch tube M5 after being turned on instantly pulls down the input voltage of the sixth inverter F6. Therefore, at this time, the output of the seventh inverter F7 is a low level. Afterwards, after the low-level signal is input into the first NAND gate U1, the first NAND gate U1 must output a high-level signal. After the high-level signal passes through the eighth inverter F8, it outputs a low-level rising edge trigger signal S2-T.

[0074] At this time, after the low-level rising edge trigger signal S2-T is input into the ninth inverter F9, the ninth inverter F9 outputs a high level, so the eighth switch tube M8 is turned off and the seventh switch tube M7 is turned on. Since the circuit has just been powered on, there is no charge in the fourth capacitor C4. Therefore, the seventh switch tube M7, after being turned on, instantly pulls down the input terminal voltage of the tenth inverter F10, so it can be obtained that the second conversion signal SD output by the eleventh inverter F11 is a low level. After the low-level second conversion signal SD is input into the R terminal of the RS trigger Q1, the RS trigger Q1 outputs a low-level signal. Therefore, at this time, after the low-level signal passes through the twelfth inverter F12 and the thirteenth inverter F13, a low-level judgment signal S3 is obtained.

[0075] Afterwards, if Figure 8 As shown, the second signal S2 switches to a low level state, and the first switch tube M1 is turned off. At this time, since the capacity of the first capacitor C1 is small, the first capacitor C1 discharges quickly, and the control terminal voltage of the second switch tube M2 is quickly pulled down by the second resistor R2, and the second switch tube M2 is also turned off. Therefore, the input end of the first inverter F1 inputs the power supply voltage VCC. After that, the power supply voltage VCC passes through the first inverter F1 and the second inverter F2 to obtain a high-level first conversion signal S1 / S2-B. At this time, after the high-level first conversion signal S1 / S2-B is input to the control end of the third switch tube M3 and the control end of the fourth switch tube M4, the fourth switch tube M4 is turned off, and the third switch tube M3 is turned on. At this time, the second capacitor C2 starts to discharge through the fourth resistor R4 and the third switch tube M3. The resistance of the fourth resistor R4 and the capacitance of the second capacitor C2 can be designed to be the first preset resistance and the first preset capacitance respectively, so that before the second signal S2 switches from a low level to a high level, the voltage in the second capacitor C2 is greater than the flip voltage of the third inverter F3. That is, at this time, the input voltage of the third inverter F3 is always at a high level, so it can be obtained that the working signal S1-T output by the fourth inverter F4 is also always at a high level.

[0076] At this time, after the high-level first conversion signal S1 / S2-B is input into the fifth inverter F5, the fifth inverter F5 outputs a low-level signal. Afterwards, after the low-level signal is input into the first NAND gate U1, the first NAND gate U1 will inevitably output a high-level signal, and after the high-level signal passes through the eighth inverter F8, it outputs a low-level rising edge trigger signal S2-T. At the same time, after the low-level signal output by the fifth inverter F5 is input into the control end of the fifth switch tube M5 and the control end of the sixth switch tube M6, the fifth switch tube M5 is turned off and the sixth switch tube M6 is turned on. At this time, the third capacitor C3 is charged through the sixth switch tube M6.

[0077] After that, after the rising edge trigger signal S2-T of the low level is input into the ninth inverter F9, the ninth inverter F9 outputs a high level, so the eighth switch tube M8 is turned off and the seventh switch tube M7 is turned on. At this time, since there is no charge in the fourth capacitor C4, the seventh switch tube M7 after being turned on instantly pulls down the input terminal voltage of the tenth inverter F10, so it can be obtained that the second conversion signal SD output by the eleventh inverter F11 is a low level. After the low-level second conversion signal SD is input into the R terminal of the RS trigger Q1, the RS trigger Q1 outputs a low-level signal. Therefore, at this time, after the low-level signal passes through the twelfth inverter F12 and the thirteenth inverter F13, a low-level judgment signal S3 is obtained.

[0078] Continue to refer Figure 8 In the second cycle after the circuit is powered on, first, the second signal S2 is switched from a low level to a high level, and the first switch tube M1 is turned on again. At this time, the first capacitor C1 is charged, and the voltage at the control end of the second switch tube M2 is pulled up by the first switch tube M1, and the second switch tube M2 is turned on. Therefore, the input end of the first inverter F1 is pulled down by the second switch tube M2. After that, the low-level voltage passes through the first inverter F1 and the second inverter F2 to obtain a low-level first conversion signal S1 / S2-B, and after the low-level first conversion signal S1 / S2-B is input to the control end of the third switch tube M3 and the control end of the fourth switch tube M4, the fourth switch tube M4 is turned on, and the third switch tube M3 is turned off. At this time, the second capacitor C2 is charged again through the fourth switch tube M4, and the voltage at the input end of the third inverter F3 is always in a high-level state, so it can be obtained that the working signal S1-T output by the fourth inverter F4 is also always at a high level.

[0079] At this time, after the low-level first conversion signal S1 / S2-B is input into the fifth inverter F5, the fifth inverter F5 outputs a high-level signal, so the fifth switch tube M5 is turned on and the sixth switch tube M6 is turned off. At this time, the third capacitor C3 starts to discharge through the fifth resistor R5 and the fifth switch tube M5, and the resistance value of the fifth resistor R5 and the capacitance value of the third capacitor C3 can be designed as the second preset resistance value and the second preset capacitance value, respectively, so that before the second signal S2 is switched from a high level to a low level, the voltage in the third capacitor C3 remains greater than the flip voltage of the sixth inverter F6 for a period of time. That is, at this time, the input voltage of the sixth inverter F6 remains at a high level for a period of time before switching to a low level state, so the output of the seventh inverter F7 remains at a high level for a period of time before switching to a low level state. Therefore, when the seventh inverter F7 outputs a high level, since the fifth inverter F5 also outputs a high level signal, the first NAND gate U1 outputs a low level signal, and the low level signal outputs a high level rising edge trigger signal S2-T after passing through the eighth inverter F8. When the seventh inverter F7 outputs a low level, the first NAND gate U1 must output a high level signal, and the high level signal outputs a low level rising edge trigger signal S2-T after passing through the eighth inverter F8. That is, the rising edge trigger signal S2-T maintains a high level for a period of time and then switches to a low level state.

[0080] At this time, when the rising edge trigger signal S2-T is at a high level, the ninth inverter F9 outputs a low level, so the eighth switch tube M8 is turned on and the seventh switch tube M7 is turned off. The fourth capacitor C4 is charged through the eighth switch tube M8, and the input voltage of the tenth inverter F10 is pulled up, so it can be obtained that the second conversion signal SD output by the eleventh inverter F11 is a high level. At the same time, since the first conversion signal S1 / S2-B is at a low level, the second NAND gate U2 must output a high level signal. At this time, the S end of the RS trigger Q1 inputs a high level signal, and the R end also inputs a high level signal, so the output signal of the RS trigger Q1 maintains the previous state, and the RS trigger Q1 still outputs a low level signal. Therefore, at this time, after the low level signal passes through the twelfth inverter F12 and the thirteenth inverter F13, a low level judgment signal S3 is obtained.

[0081] Afterwards, when the rising edge trigger signal S2-T switches to a low level, the ninth inverter F9 outputs a high level, so the eighth switch tube M8 is turned off and the seventh switch tube M7 is turned on. The fourth capacitor C4 starts to discharge through the sixth resistor R6 and the seventh switch tube M7. The resistance of the sixth resistor R6 and the capacitance of the fourth capacitor C4 can be designed to be the third preset resistance and the third preset capacitance, respectively, so that before the rising edge trigger signal S2-T switches from a low level to a high level, the voltage in the fourth capacitor C4 is greater than the flip voltage of the tenth inverter F10, that is, at this time, the eleventh inverter F11 always outputs a high level, that is, the second conversion signal SD is always a high level. At this time, the S end of the RS trigger Q1 still inputs a high level signal, and the R end also still inputs a high level signal, so the output signal of the RS trigger Q1 maintains the previous state, and the RS trigger Q1 still outputs a low level signal. Therefore, at this time, the low level signal passes through the twelfth inverter F12 and the thirteenth inverter F13 to obtain a low level judgment signal S3, that is, at this time, the judgment signal S3 always maintains a low level state.

[0082] Afterwards, at time T1, the second signal S2 switches to a low level state, and the first switch tube M1 is turned off. At this time, since the capacity of the first capacitor C1 is small, the first capacitor C1 is discharged quickly, the control terminal voltage of the second switch tube M2 is quickly pulled down by the second resistor R2, the second switch tube M2 is also turned off, and the input terminal of the first inverter F1 inputs the power supply voltage VCC. Afterwards, the power supply voltage VCC passes through the first inverter F1 and the second inverter F2 to obtain a high-level first conversion signal S1 / S2-B. And at this time, after the high-level first conversion signal S1 / S2-B is input to the control terminal of the third switch tube M3 and the control terminal of the fourth switch tube M4, the fourth switch tube M4 is turned off, and the third switch tube M3 is turned on. At this time, the second capacitor C2 starts to discharge through the fourth resistor R4 and the third switch tube M3. From the above analysis, it can be seen that the input terminal voltage of the third inverter F3 is always at a high level, so it can be obtained that the working signal S1-T output by the fourth inverter F4 is also always at a high level.

[0083] At this time, after the high-level first conversion signal S1 / S2-B is input into the fifth inverter F5, the fifth inverter F5 outputs a low-level signal. Afterwards, after the low-level signal is input into the first NAND gate U1, the first NAND gate U1 must output a high-level signal, and after the high-level signal passes through the eighth inverter F8, the rising edge trigger signal S2-T remains in a low-level state. At the same time, after the low-level signal output by the fifth inverter F5 is input into the control end of the fifth switch tube M5 and the control end of the sixth switch tube M6, the fifth switch tube M5 is turned off and the sixth switch tube M6 is turned on. At this time, the third capacitor C3 is charged through the sixth switch tube M6.

[0084] After that, after the rising edge trigger signal S2-T of the low level is input into the ninth inverter F9, the ninth inverter F9 outputs a high level, therefore, the eighth switch tube M8 is still in the off state, and the seventh switch tube M7 is still in the on state. From the above analysis, it can be seen that the voltage in the fourth capacitor C4 is always greater than the flip voltage of the tenth inverter F10, that is, at this time, the eleventh inverter F11 always outputs a high level, that is, the second conversion signal SD is always a high level. At this time, since the first conversion signal S1 / S2-B is in a high level state, and the second conversion signal SD is also in a high level state, the second NAND gate U2 outputs a low level. That is, at this time, the S end of the RS trigger Q1 inputs a low level signal, and the R end still inputs a high level signal, so the RS trigger Q1 outputs a high level signal. Therefore, at this time, after the high level signal passes through the twelfth inverter F12 and the thirteenth inverter F13, a high level judgment signal S3 is obtained.

[0085] Continue to refer Figure 8 , in the third cycle after the circuit is powered on, the second signal S2 switches from a low level to a high level, and the first switch tube M1 is turned on again. At this time, the first capacitor C1 is charged, the voltage at the control end of the second switch tube M2 is pulled up by the first switch tube M1, and the second switch tube M2 is turned on, so the input end of the first inverter F1 is pulled down by the second switch tube M2. Afterwards, the low-level voltage passes through the first inverter F1 and the second inverter F2 to obtain a low-level first conversion signal S1 / S2-B. And at this time, after the low-level first conversion signal S1 / S2-B is input to the control end of the third switch tube M3 and the control end of the fourth switch tube M4, the fourth switch tube M4 is turned on, and the third switch tube M3 is turned off. At this time, the second capacitor C2 is charged again through the fourth switch tube M4, and the voltage at the input end of the third inverter F3 is always in a high-level state, so it can be obtained that the working signal S1-T output by the fourth inverter F4 is also always at a high level.

[0086] At this time, after the low-level first conversion signal S1 / S2-B is input into the fifth inverter F5, the fifth inverter F5 outputs a high-level signal, so the fifth switch tube M5 is turned on and the sixth switch tube M6 is turned off. At this time, it can be seen from the above analysis that before the second signal S2 is switched from a high level to a low level, the voltage in the third capacitor C3 remains greater than the flip voltage of the sixth inverter F6 for a period of time, that is, the input voltage of the sixth inverter F6 remains at a high level for a period of time before switching to a low level state, therefore, the output of the seventh inverter F7 remains at a high level for a period of time before switching to a low level state. When the seventh inverter F7 outputs a high level, since the fifth inverter F5 also outputs a high level, the first NAND gate U1 outputs a low level signal, and after the low level signal passes through the eighth inverter F8, the eighth inverter F8 outputs a high level rising edge trigger signal S2-T. When the seventh inverter F7 outputs a low level, the first NAND gate U1 must output a high level signal, and after the high level signal passes through the eighth inverter F8, the eighth inverter F8 outputs a low level rising edge trigger signal S2-T. That is, at this time, the rising edge trigger signal S2-T maintains a high level for a period of time and then switches to a low level state.

[0087] At this time, when the rising edge trigger signal S2-T is at a high level, the ninth inverter F9 outputs a low level, so the eighth switch tube M8 is turned on and the seventh switch tube M7 is turned off. The fourth capacitor C4 is charged again through the eighth switch tube M8, and the input terminal voltage of the tenth inverter F10 always maintains a high level state, so it can be obtained that the second conversion signal SD output by the eleventh inverter F11 is always at a high level. At the same time, since the first conversion signal S1 / S2-B is at a low level, the second NAND gate U2 must output a high level signal. At this time, the S end of the RS trigger Q1 inputs a high level signal, and the R end also inputs a high level signal, so the output signal of the RS trigger Q1 maintains the previous state, that is, the output of the RS trigger Q1 maintains a high level state. Therefore, at this time, after the high level signal passes through the twelfth inverter F12 and the thirteenth inverter F13, a high level judgment signal S3 is obtained.

[0088] Afterwards, when the rising edge trigger signal S2-T switches to a low level, the ninth inverter F9 outputs a high level, so the eighth switch tube M8 is turned off and the seventh switch tube M7 is turned on. From the above analysis, it can be seen that the voltage in the fourth capacitor C4 is always greater than the flip voltage of the tenth inverter F10, that is, at this time, the eleventh inverter F11 always outputs a high level, that is, the second conversion signal SD is always a high level. At this time, the S end of the RS trigger Q1 still inputs a high level signal, and the R end also still inputs a high level signal. Therefore. The output signal of the RS trigger Q1 maintains the previous state, and the RS trigger Q1 still outputs a high level signal. Therefore, at this time, after the high level signal passes through the twelfth inverter F12 and the thirteenth inverter F13, a high level judgment signal S3 is obtained, that is, at this time, the judgment signal S3 always maintains a high level state.

[0089] In the third cycle after the circuit is powered on, after the second signal S2 switches from high level to low level, the circuit returns to the circuit state after the second signal S2 switches from high level to low level in the second cycle, that is, at this time, the circuit enters a normal cycle.

[0090] In summary, combined with Figure 6 , Figure 7 and Figure 8 It can be seen that when the input signal is the first signal S1, starting from the moment T, the control signal multiplexing circuit outputs a high-level working signal S1-T, a low-level rising edge trigger signal S2-T and a low-level judgment signal S3. After the low-level judgment signal S3 is input into the control circuit (not shown in the present application), the control circuit can only use the high-level working signal S1-T to participate in the subsequent control work. When the input signal is the second signal S2, starting from the moment T1, the control signal multiplexing circuit outputs a high-level working signal S1-T, a rising edge trigger signal S2-T with the same frequency as the second signal S2, and a high-level judgment signal S3. After the high-level judgment signal S3 is input into the control circuit (not shown in the present application), the control circuit can use the high-level working signal S1-T and the rising edge trigger signal S2-T with the same frequency as the second signal S2 to jointly participate in the subsequent control work.

[0091] From the above analysis, we can see that Figure 6The control signal multiplexing circuit of the embodiment realizes the input of two signals, the first signal S1 and the second signal S2, through a single signal input terminal, and obtains two different output signals, the first output signal (low-level judgment signal S3 and low-level rising edge trigger signal S2-T) and the second output signal (high-level judgment signal S3 and rising edge trigger signal S2-T with the same frequency as the second signal S2), respectively, solving the problem of the difficulty in simultaneously taking into account the increase in the number of input signals and the reduction in chip size in the prior art. The circuit design can realize the input and output of multiple signals on the basis of reducing the number of signal input terminals, so that the integrated circuit control chip can simultaneously meet the development needs of integration and miniaturization.

[0092] It should be noted that Figure 6 The control signal multiplexing circuit shown in the embodiment is only a preferred circuit structure to achieve the purpose of the present invention. In other embodiments, each circuit module or device may also use other circuit structures that can achieve the same function, and the present application is not limited thereto.

[0093] In addition, the embodiment of the present application also provides an integrated circuit control chip, which includes a control signal multiplexing circuit as in the above embodiment, and is used to realize the effective input and output of multiple signals on the basis of reducing the number of signal input terminals. Regarding the circuit structure and working process of the integrated circuit control chip not described in detail in this embodiment, reference can be made to the relevant parts in the above control signal multiplexing circuit embodiment, and no further description is given here.

[0094] The above description is only a preferred embodiment of the present invention and does not limit the present invention in other forms. Any technician familiar with the profession may use the technical content disclosed above to change or modify it into an equivalent embodiment with equivalent changes and apply it to other fields. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A control signal multiplexing circuit, characterized in that: It includes a first output module, a second output module, a judgment signal conversion module and a judgment signal output module; The first output module is used to receive the input first signal S1 or second signal S2, generate and output the working signal S1-T and the first conversion signal S1 / S2-B, and input the first conversion signal S1 / S2-B to the second output module and the judgment signal output module respectively; The second output module generates and outputs a rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B, and inputs the rising edge trigger signal S2-T to the judgment signal conversion module; The judgment signal conversion module generates a second conversion signal SD based on the rising edge trigger signal S2-T, and inputs the second conversion signal SD to the judgment signal output module; The judgment signal output module generates and outputs a judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD; in the judgment signal output module, the first conversion signal S1 / S2-B and the second conversion signal SD are respectively connected to two input terminals of a second NAND gate U2, the output terminal of the second NAND gate U2 is connected to the set terminal S of the RS trigger Q1, the second conversion signal SD is also connected to the reset terminal R of the RS trigger Q1, and the output terminal of the RS trigger outputs the judgment signal S3; When the first signal S1 is input to the first output module, the judgment signal output module outputs a low-level judgment signal S3; when the second signal S2 is input to the first output module, the judgment signal output module outputs a high-level judgment signal S3.

2. The control signal multiplexing circuit according to claim 1, characterized in that: In the first output module, the input ends of the first signal S1 and the second signal S2 are grounded through the first resistor R1, the first switch tube M1 and the second resistor R2 in sequence, and the control end of the first switch tube M1 is connected to the power supply voltage VCC, and the second resistor R2 is connected in parallel to the first capacitor C1; The power supply voltage VCC is grounded through the third resistor R3 and the second switch tube M2 in sequence, and the control end of the second switch tube M2 is connected to the current output end of the first switch tube M1, and the current input end of the second switch tube M2 is connected to the output end of the first conversion signal S1 / S2-B; The power supply voltage VCC is also grounded through the fourth switch tube M4, the fourth resistor R4 and the third switch tube M3 in sequence, and the control end of the fourth switch tube M4 is connected to the control end of the third switch tube M3 and connected to the output end of the first conversion signal S1 / S2-B, the current output end of the fourth switch tube M4 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, and the current output end of the fourth switch tube M4 outputs the working signal S1-T.

3. The control signal multiplexing circuit according to claim 2, characterized in that: In the second output module, the input end of the first conversion signal S1 / S2-B is connected to one input end of the first NAND gate U1 through the fifth inverter F5; The power supply voltage VCC is connected to the ground through the sixth switch tube M6, the fifth resistor R5 and the fifth switch tube M5 in sequence, and the control end of the sixth switch tube M6 is connected to the control end of the fifth switch tube M5 and connected to the output end of the fifth inverter F5, the current output end of the sixth switch tube M6 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is grounded, and the current output end of the sixth switch tube M6 is connected to the other input end of the first NAND gate U1; The output end of the first NAND gate U1 outputs the rising edge trigger signal S2-T through the eighth inverter F8.

4. The control signal multiplexing circuit according to claim 3, characterized in that: In the judgment signal conversion module, the rising edge trigger signal S2-T is connected to the input end of the ninth inverter F9; The power supply voltage VCC is grounded through the eighth switch tube M8, the sixth resistor R6 and the seventh switch tube M7 in sequence, and the control end of the eighth switch tube M8 is connected to the control end of the seventh switch tube M7 and connected to the output end of the ninth inverter F9, the current output end of the eighth switch tube M8 is connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and the current output end of the eighth switch tube M8 outputs the second conversion signal SD.

5. The control signal multiplexing circuit according to claim 4, characterized in that: The resistance of the fourth resistor R4 and the capacitance of the second capacitor C2 are respectively set to a first preset resistance and a first preset capacitance, so that before the second signal S2 switches from a low level to a high level, the voltage in the second capacitor C2 is greater than the flip voltage of the third inverter F3; The resistance of the fifth resistor R5 and the capacitance of the third capacitor C3 are set to the second preset resistance and the second preset capacitance respectively, so that before the second signal S2 switches from a high level to a low level, the voltage in the third capacitor C3 remains greater than the flip voltage of the sixth inverter F6 for a period of time; The resistance of the sixth resistor R6 and the capacitance of the fourth capacitor C4 are set to the third preset resistance and the third preset capacitance respectively, so that before the rising edge trigger signal S2-T switches from a low level to a high level, the voltage in the fourth capacitor C4 is greater than the flip voltage of the tenth inverter F10.

6. The control signal multiplexing circuit according to claim 4, characterized in that: The current input end of the second switch tube M2 is connected to the output end of the first conversion signal S1 / S2-B through the first inverter F1 and the second inverter F2 in sequence; The current output end of the fourth switch tube M4 sequentially outputs the working signal S1-T through the third inverter F3 and the fourth inverter F4; The current output end of the sixth switch tube M6 is connected to the other input end of the first NAND gate U1 through the sixth inverter F6 and the seventh inverter F7 in sequence; The current output end of the eighth switch tube M8 sequentially outputs the second conversion signal SD through the tenth inverter F10 and the eleventh inverter F11; The output end of the RS trigger sequentially outputs the determination signal S3 through the twelfth inverter F12 and the thirteenth inverter F13.

7. The control signal multiplexing circuit according to claim 6, characterized in that: The number of inverters in the branch where the first inverter F1 and the second inverter F2 are located is 2n1; The number of inverters in the branch where the third inverter F3 and the fourth inverter F4 are located is 2n2; The number of inverters in the branch where the sixth inverter F6 and the seventh inverter F7 are located is 2n3; The number of inverters in the branch where the tenth inverter F10 and the eleventh inverter F11 are located is 2n4; The number of inverters in the branch where the twelfth inverter F12 and the thirteenth inverter F13 are located is 2n5; Among them, n1, n2, n3, n4 and n5 are all integers.

8. The control signal multiplexing circuit according to claim 4, characterized in that: The first switch tube M1, the second switch tube M2, the third switch tube M3, the fifth switch tube M5 and the seventh switch tube M7 are all NMOS tubes; The fourth switch tube M4 , the sixth switch tube M6 , and the eighth switch tube M8 are all PMOS tubes.

9. The control signal multiplexing circuit according to any one of claims 1 to 8, characterized in that: When the first signal S1 is input to the first output module, the first output module outputs a first conversion signal S1 / S2-B and a high-level working signal S1-T; the second output module outputs a low-level rising edge trigger signal S2-T based on the first conversion signal S1 / S2-B; the judgment signal conversion module outputs a second conversion signal SD based on the low-level rising edge trigger signal S2-T; the judgment signal output module outputs a low-level judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD; When the second signal S2 is input to the first output module, the first output module outputs a first conversion signal S1 / S2-B and a high-level working signal S1-T; the second output module outputs a rising edge trigger signal S2-T with the same frequency as the second signal S2 based on the first conversion signal S1 / S2-B; the judgment signal conversion module outputs a second conversion signal SD based on the rising edge trigger signal S2-T with the same frequency as the second signal S2; the judgment signal output module outputs a high-level judgment signal S3 according to the first conversion signal S1 / S2-B and the second conversion signal SD.

10. An integrated circuit control chip, characterized in that: The method comprises the control signal multiplexing circuit as claimed in any one of claims 1 to 9.

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