Data buffer, data buffer method and data synchronization system

Abstract

The present application belongs to the field of data cache technology, and specifically relates to a data cache, a data cache method and a data synchronization system, wherein the data cache includes a storage module, a write clock domain module and a read clock domain module; the write clock domain module is used to generate a data write address when a write enable signal is input externally and the storage module is in a non-full state; the storage module is used to write a received data signal into a storage space corresponding to the data write address under the write clock domain, and is also used to read a data signal from a storage space corresponding to the data read address under the read clock domain; when the read clock domain module in the present application detects that the storage module is in a nearly empty state, it waits for the storage module to be in a non-nearly empty state or waits for a fixed time before sending a data read address to the storage module, so that a certain amount of data is stored in the storage module before a read operation is performed, thereby ensuring the continuity and synchronization of the read data.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of data caching, and in particular relates to a data cache, a data caching method and a data synchronization system. Background Art

[0002] Data synchronization is mainly used to adjust the data error between two interconnected chips and the alignment relationship between the clock and data to ensure normal communication between the two interconnected chips. When the working clock of the data synchronization is different from the working clock of the two interconnected chips, an asynchronous data buffer is required for cross-clock domain processing.

[0003] However, when the write clock frequency on both sides of the asynchronous data buffer is faster than the read clock frequency, there is a discontinuous non-empty state, which causes the problem of discontinuous read data and affects the synchronization requirements of the data. Summary of the invention

[0004] The present application provides a data buffer, a data buffer method and a data synchronization system, which solve the problem of discontinuous read data when the write clock frequency of the data buffer is greater than the read clock frequency.

[0005] In a first aspect, the present application provides a data buffer, which includes: a storage module, including a plurality of storage spaces for caching data, and each storage space corresponds to an address with a unique identifier; wherein the storage module includes a non-full state and an almost empty state, and the almost empty state indicates that there are less than or equal to a preset threshold number of storage spaces in the storage module that store data; a write clock domain module, wherein the enable end of the write clock domain module is connected to an external write enable output end, and the write address output end of the write clock domain module is connected to the write address input end of the storage module, and is used to receive a write enable signal input from the outside and the storage A module generates a data write address when it is in a non-full state; a read clock domain module, wherein the read address output terminal of the read clock domain module is connected to the read address input terminal of the storage module, and is used to generate a data read address after waiting for a preset time when the storage module is in an empty state; the data input terminal of the storage module is connected to an external data output terminal, and the data output terminal of the storage module is connected to an external data receiving terminal, and is used to write a received first data signal into a storage space corresponding to the data write address in the write clock domain, and is also used to read a second data signal from the storage space corresponding to the data read address in the read clock domain.

[0006] Optionally, the storage module also includes a non-empty state and a non-to-be-empty state, and the read clock domain module includes an empty control mode and a normal control mode; in the normal control mode, the read clock domain module is used to generate a data read address when the storage module is in a non-empty state; in the empty control mode, the read clock domain module is used to generate the data read address when the storage module is converted from the empty state to the non-to-be-empty state, or when the storage module is in the empty state and waits for a preset period of time.

[0007] Optionally, the read clock domain module includes: a write address synchronization unit, the input end of the write address synchronization unit is connected to the synchronization end of the write clock domain module, and is used to obtain the current data write address; a read address generation unit, the first output end of the read address generation unit is connected to the read address input end of the storage module, and is used to generate the current data read address under the action of the read enable signal, and send the current data read address to the storage module, and is also used to generate the next data read address according to the current data read address; an empty judgment unit, the first input end of the empty judgment unit is connected to the output end of the write address synchronization unit, and the second input end of the empty judgment unit is connected to the second output end of the read address generation unit, and is used to generate the current data read address according to the current data read address. According to the difference between the current data write address and the next data read address, determine whether the storage module is in a will-be-empty state; a read enable generating unit, wherein the first input end of the read enable generating unit is connected to the output end of the will-be-empty judgment unit, and the output end of the read enable generating unit is connected to the input end of the read address generating unit, and is used to output a read enable signal to the read address generating unit when the will-be-empty control mode is in the will-be-empty control mode and the will-be-empty judgment unit outputs a non-will-be-empty state, or output a read enable signal to the read address generating unit after waiting for a preset time when the will-be-empty control mode and the will-be-empty judgment unit outputs a will-be-empty state, so that the read address generating unit outputs the next data read address to the storage module according to the read enable signal.

[0008] Optionally, the read clock domain module also includes: a read empty judgment unit, the input end of the read empty judgment unit is connected to the output end of the write address synchronization unit, and the output end of the read empty judgment unit is connected to the second input end of the read enable generation unit, and is used to judge whether the storage module is in a non-empty state according to the difference between the current data write address and the next data read address, so that the read enable generation unit outputs a read enable signal according to the non-empty state in the normal control mode.

[0009] Optionally, the read enable generating unit includes: an empty enable switch, used to control the working mode of the read clock domain module; wherein, when the empty enable switch is in an open state, it indicates the empty control mode, and when the empty enable switch is in a closed state, it indicates the normal control mode; a counter decrementer, the counter decrementer is used to count down under the action of a count enable signal; a selection signal generator, the first input end of the selection signal generator is connected to the output end of the empty enable switch, the second input end of the selection signal generator is connected to the output end of the count decrementer, and is used to output a first selection signal when the empty enable switch is in an open state and the count value output by the count decrementer is equal to zero or the count value output by the count decrementer is a default value, and is also used to output a first selection signal when the empty enable switch is in an open state Outputs a second selection signal when in a closed state; a selector, wherein the first input end of the selector is connected to the output end of the will-be-empty judgment unit, the second input end of the selector is connected to the output end of the read-empty judgment unit, the third input end of the selector is connected to the output end of the selection signal generator, the first output end of the selector is connected to the input end of the read address generating unit, and the second output end of the selector is connected to the input end of the counter decrementer, and is used to generate a read enable signal according to the non-will-be-empty state output by the will-be-empty judgment unit under the action of the first selection signal, and output a count enable signal to the count decrementer when the will-be-empty judgment unit outputs the will-be-empty state, and is also used to generate a read enable signal according to the non-empty state output by the read-empty judgment unit under the action of the second selection signal.

[0010] Optionally, the write clock domain module includes: a read address synchronization unit, the input end of the read address synchronization unit is connected to the synchronization end of the read clock domain module, and is used to obtain the current data read address; a write address generation unit, the first output end of the write address generation unit is connected to the write address input end of the storage module, and is used to generate the current data write address under the action of the write enable signal, and send the current data write address to the storage module, and is also used to generate the next data write address according to the current data write address; a write full judgment unit, the first input end of the write full judgment unit is connected to the output end of the read address synchronization unit, and the second input end of the write full judgment unit is connected to the second input end of the read address generation unit. The output end is connected, and is used to judge whether the storage module is in a non-full state according to the difference between the current data read address and the next data write address; a write enable generating unit, the first input end of the write enable generating unit is connected to the external write enable output end, the second input end of the write enable generating unit is connected to the output end of the write full judgment unit, and the output end of the write enable generating unit is connected to the input end of the write address generating unit, and is used to output the write enable signal to the write address generating unit when the write enable signal of the external input is received and the write full judgment unit outputs a non-full state, so that the write address generating unit outputs the next data write address to the storage module according to the write enable signal.

[0011] Optionally, the write clock domain module also includes: a first encoding unit, the input end of the first encoding unit is connected to the first output end of the write address generating unit, the output end of the first encoding unit is connected to the write address synchronization unit, and is used to convert the current data write address into Gray code and output it to the write address synchronization unit; the read clock domain module also includes: a second encoding unit, the input end of the second encoding unit is connected to the first output end of the read address generating unit, the output end of the second encoding unit is connected to the read address synchronization unit, and is used to convert the current data read address into Gray code and output it to the read address synchronization unit.

[0012] In a second aspect, the present application provides a data caching method, which includes: when a write enable signal is input externally and the storage module is in a non-full state, a write clock domain module generates a data write address; the storage module writes the received first data signal into the storage space corresponding to the data write address under the write clock domain; when the storage module is in a nearly empty state, a read clock domain module generates a data read address after waiting for a preset period of time; the storage module reads a second data signal from the storage space corresponding to the data read address under the read clock domain.

[0013] Optionally, when the storage module is in the empty state, the read clock domain module generates a data read address after waiting for a preset time, including: when the empty enable switch is in the open state and the empty judgment unit outputs the empty state, the selector generates multiple count enable signals; the count decrementer sequentially decreases from the default value to zero according to the received multiple count enable signals; wherein the time duration for the count decrementer to sequentially decrease from the default value to zero is the preset time duration; the selection signal generator outputs a target selection signal according to the count value equal to zero, so that the selector generates a read enable signal according to the non-empty state output by the empty judgment unit; and the read address generation unit generates a data read address according to the read enable signal.

[0014] In a third aspect, the present application provides a data synchronization system, which includes: a first buffer, wherein the enable end of the first buffer is connected to an external write enable output end, and the data input end of the first buffer is connected to an external data output end; a data synchronization module, wherein the data receiving end of the data synchronization module is connected to the data output end of the first buffer; a second buffer, wherein the enable end of the second buffer is connected to the write enable output end of the data synchronization module, the data input end of the second buffer is connected to the data output end of the data synchronization module, and the data output end of the second buffer is connected to the external data receiving end; wherein any one of the first buffer and the second buffer includes the data buffer.

[0015] The technical solution provided by this application has at least the following beneficial effects:

[0016] When the reading clock domain module in the present application detects that the storage module is in the empty state, it waits for the storage module to be in the non-empty state or waits for a fixed time before sending the data read address to the storage module, so that a certain amount of data is stored in the storage module before performing the read operation, thereby ensuring the continuity and synchronization of the read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0018] Figure 1 Shown is a structural schematic diagram of a data synchronization system provided in an embodiment of the present application.

[0019] Figure 2 Shown is a schematic diagram of the structure of a data buffer provided in an embodiment of the present application.

[0020] Figure 3 The figure is a flow chart of a data caching method provided in an embodiment of the present application.

[0021] Description of reference numerals:

[0022] 100, data buffer; 110, storage module; 120, write clock domain module; 130, read clock domain module; 121, read address synchronization unit; 122, write address generation unit; 123, write full judgment unit; 124, write enable generation unit; 125, first encoding unit; 131, write address synchronization unit; 132, read address generation unit; 133, empty judgment unit; 134, read enable generation unit; 135, read empty judgment unit; 136, second encoding unit; 1341, empty enable switch; 1342, count decrementer; 1343, selection signal generator; 1344, selector;

[0023] Wen, write enable signal; Ren, read enable signal; Wadd, current data write address; Wadd_n, next data write address; Radd, current data read address; Radd_n, next data read address; Se, selection signal; Cou, count enable signal; Val, count value; Sta, status signal; R1, empty status signal; R2, read empty status signal; R3, write full status signal. DETAILED DESCRIPTION

[0024] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0025] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0026] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0027] like Figure 1 The data synchronization system shown is mainly used for data synchronization schemes across different chips, and is used to adjust the error and offset of data between two interconnected chips, as well as the alignment relationship between clock and data, to ensure that data is communicated correctly between the two chips. In actual system-level chips, due to some functional considerations, such as the chip can be used as both a root node and a branch node, when both modes are supported, there will be certain constraints on the clock planning of the chip, resulting in a certain difference between the clock of the data synchronization system and the chips on both sides, so it is necessary to use an asynchronous buffer to realize data cross-clock transmission. It should be noted that the first chip can be a PHY (Physical, a chip with an external signal interface) or an FPGA (Field Programmable Gate Array), and the second chip can also be a PHY or an FPGA.

[0028] like Figure 1 As shown, when the working clock of the data synchronization system is 600Mhz and the working clock of the PHY chips on both sides is 500Mhz, the corresponding asynchronous data buffer needs to be added to the entire data synchronization system for data transmission. For the first transmission data buffer, the write enable is a write enable signal sent by the external first chip, and the read enable is generated based on the non-empty state inside the data buffer. As long as there is data in the first transmission data buffer, that is, when the first transmission data buffer is in a non-empty state, the read operation will be triggered to ensure timely transmission of data.

[0029] For the second transmission data buffer, the write enable is sent by the data synchronization module; however, the inventors have analyzed and found that when the clock frequency (600Mhz) of writing to the second transmission data buffer is significantly higher than the read clock frequency (500Mhz) and there is no obvious regularity in the write operation, using the non-empty state of the traditional asynchronous data buffer to generate the read enable will cause the data read from the second transmission data buffer to be discontinuous; the reason is that the logic for generating the non-empty state is that when the write pointer address is equal to the next read pointer address, the data buffer will generate a non-empty state, and at this time the data buffer can be To read data, but because the write clock is fast and the read clock is slow, when the write pointer is transmitted to the read clock after passing through the Gray code, due to synchronization limitations, some write pointers will change too fast, and the write pointer synchronized to the read clock domain will be discontinuous, so the non-empty state of the read clock domain is not continuous; therefore, when the write clock frequency on both sides of the asynchronous data buffer is faster than the read clock frequency, the generation of the non-empty state is a discontinuous state, which will cause the data read out of the data buffer to have a problem of too long data latch time, and ultimately the data transmission between the chips on both sides will be inconsistent, seriously affecting the data synchronization requirements.

[0030] In order to solve the above problems, Figure 2 As shown, the present application provides a data buffer 100 , which specifically includes a storage module 110 , a write clock domain module 120 and a read clock domain module 130 .

[0031] In this embodiment, the storage module 110 includes a write control unit, a read control unit and a storage unit (not shown in the figure), and the storage unit includes a plurality of storage spaces for caching data, and each storage space corresponds to an address with a unique identifier; assuming that the depth of the storage unit is n, that is, it includes n storage spaces, and a binary address is set for each storage control; for example: when n=32, the address of the first storage space is "00000" represented by a binary number with a bit width of 5, the address of the second storage space is "00001", and so on, and the address of the nth storage space is "11111".

[0032] In this embodiment, the storage module 110 includes a full state, a non-full state, an empty state, a non-empty state, a nearly empty state and a non-nearly empty state; wherein the full state indicates that each storage space in the storage unit stores data, and the full state is negated to be a non-full state; the empty state indicates that no data is stored in each storage space in the storage unit, and the empty state is negated to be a non-empty state; the nearly empty state indicates that there are less than or equal to a preset threshold storage space in the storage module 110 that stores data, for example, the preset threshold is 3, the nearly empty state indicates that there are ≤3 storage spaces in the storage module 110 that store data, and the empty state is negated to be a non-nearly empty state, that is, a storage unit that stores >3 data is in a non-nearly empty state; wherein the preset threshold can be flexibly set according to the read and write clock frequency.

[0033] In this embodiment, the enable end of the write clock domain module 120 is connected to the external write enable output end, and the write address output end of the write clock domain module 120 is connected to the write address input end of the storage module 110, and is used to generate a data write address when the external write enable signal Wen is input and the storage module 110 is in a non-full state; that is to say: when the write clock domain module 120 detects that the storage module 110 is in a non-full state, and at the same time receives the external input write enable signal Wen, the write clock domain module 120 generates a data write address to the storage module 110; optionally, when the write clock domain module 120 detects that the storage module 110 is in a full state, even if the external input write enable signal Wen is received, the data write address will not be generated; optionally, when the write clock detects that the storage module 110 is in a non-full state, but does not receive the external input write enable signal Wen, the write clock domain module 120 still will not generate a data write address. It should also be noted that the external write enable output end can be Figure 1 The write enable output of the first chip in the Figure 1The write enable output of the data synchronization module in.

[0034] In this embodiment, the read address output terminal of the read clock domain module 130 is connected to the read address input terminal of the storage module 110, and is used to generate a data read address after waiting for a preset time when the storage module 110 is in the empty state; that is to say: when the read clock domain module 130 detects that the storage module 110 is in the empty state, the read clock domain module 130 does not immediately send the data read address to the storage module 110, and needs to wait for the storage module 110 to be in a non-empty state or wait for a fixed time before sending the data read address to the storage module 110, so that a certain amount of data is accumulated in the storage module 110 before performing a read operation, thereby ensuring the continuity of the read data; wherein, the preset time can be the time for the storage module 110 to switch from the empty state to the non-empty state, or it can be a fixed time set according to the read and write frequency.

[0035] In this embodiment, the data input terminal of the storage module 110 is connected to the external data output terminal, and the data output terminal of the storage module 110 is connected to the external data receiving terminal, and is used to write the received first data signal into the storage space corresponding to the data write address in the write clock domain, and is also used to read the second data signal from the storage space corresponding to the data read address in the read clock domain. It should be noted that when the storage module 110 receives the first data signal output by the external data output terminal and receives the data write address output by the write clock domain module 120, the write control unit in the storage module 110 stores the first data signal in the storage space corresponding to the data write address; optionally, when the storage module 110 receives the data read address output by the read clock domain module 130, the read control unit in the storage module 110 reads the second data signal from the storage space corresponding to the data read address and sends the second data signal to the external data receiving terminal.

[0036] It should be noted that the data buffer 100 in this embodiment corresponds to Figure 1 For the second sending data buffer 100 in the application scenario, the external data output end may be the data output end of the data synchronization module, and the external data receiving end may be the second chip.

[0037] It can be seen from this that when the read clock domain module 130 in the present application detects that the storage module 110 is in a nearly empty state, it waits for the storage module 110 to be in a non-nearly empty state or waits for a fixed period of time before sending the data read address to the storage module 110, so that a certain amount of data is stored in the storage module 110 before performing a read operation, thereby ensuring the continuity and synchronization of the read data.

[0038] In one embodiment, the read clock domain module 130 includes an empty control mode and a normal control mode; in the normal control mode, the read clock domain module 130 is used to generate a data read address when the storage module 110 is in a non-empty state; in the empty control mode, the read clock domain module 130 is used to generate a data read address when the storage module 110 is converted from an empty state to a non-empty state, or when the storage module 110 is in the empty state and waits for a preset period of time.

[0039] In order to improve the compatibility of the data buffer 100, this embodiment sets the empty control mode and the normal control mode according to the requirements of different application scenarios of the data buffer 100. The empty control mode can be applied to the application scenario where the write clock frequency is greater than the read clock frequency (i.e. Figure 1 The normal control mode can be applied in application scenarios where the write clock frequency is less than or equal to the read clock frequency.

[0040] In the normal control mode, the read clock domain module 130 determines whether to generate a data read address based on whether the storage module 110 is in a non-empty state, that is, when the storage module 110 is in a non-empty state, the read clock domain module 130 generates a data read address, and when the storage module 110 is in an empty state, the data read address is not generated; optionally, in the near-empty control mode, the read clock domain module 130 determines whether to generate a data read address based on whether the storage module 110 is in a near-empty state, that is, when the storage module 110 is in a non-near-empty state, the read clock domain module 130 immediately generates a data read address; when the storage module 110 is in a near-empty state, it is necessary to wait for the near-empty state to be converted into a non-near-empty state or wait for a fixed time before generating a data read address, so the generation of the data read address is delayed so that a certain amount of data is stored in the storage module 110 before performing a read operation, thereby ensuring the continuity of the read data.

[0041] In one embodiment, if Figure 2As shown, the read clock domain module 130 includes: a write address synchronization unit 131, a read address generation unit 132, an empty judgment unit 133 and a read enable generation unit 134; the input end of the write address synchronization unit 131 is connected to the synchronization end of the write clock domain module 120, and is used to obtain the current data write address Wadd; the first output end of the read address generation unit 132 is connected to the read address input end of the storage module 110, and is used to generate the current data read address Radd under the action of the read enable signal Ren, and send the current data read address Radd to the storage module 110, and is also used to generate the next data read address Radd_n according to the current data read address Radd; the first input end of the empty judgment unit 133 is connected to the output end of the write address synchronization unit 131, and the second input end of the empty judgment unit 133 is connected to the read address generation unit 134. The first input end of the read enable generating unit 134 is connected to the output end of the will-be-empty judgment unit 133, and the output end of the read enable generating unit 134 is connected to the input end of the read address generating unit 132, and is used to output a read enable signal Ren to the read address generating unit 132 in the will-be-empty control mode and when the will-be-empty judgment unit 133 outputs a non-will-be-empty state, or to output a read enable signal Ren to the read address generating unit 132 after waiting for a preset time in the will-be-empty control mode and when the will-be-empty judgment unit 133 outputs a will-be-empty state, so that the read address generating unit 132 outputs the next data read address Radd_n to the storage module 110 according to the read enable signal Ren.

[0042] The working principle of the read clock domain module 130 in this embodiment is as follows: (1) the read address generation unit 132 generates the current data read address Radd and the next data read address Radd_n upon receiving the read enable signal Ren. The read address generation unit 132 only sends the current data read address Radd to the storage module 110, so that the storage module 110 reads the data signal according to the current data read address Radd; (2) the current data write address Wadd is obtained from the write clock domain module 120 through the write address synchronization unit 131; (3) the empty judgment unit 133 obtains the next data read address Radd_n from the read address generation unit 132 and the current data write address Wadd from the write address synchronization unit 131, and obtains the next data read address Radd_n from the write address synchronization unit 131, and obtains the next data read address Radd_n from the read address generation unit 132 and the current data write address Wadd according to the current data write address Wadd and the next data read address Radd. The difference between the two data read addresses Radd_n determines whether the storage module 110 is in the empty state, thereby outputting the corresponding empty state signal R1. When the difference is less than or equal to the preset threshold, it is determined to be in the empty state, and the empty state signal R1 is the first judgment signal; when the difference is greater than the preset threshold, it is determined to be in the non-empty state, and the empty state signal R1 is the second judgment signal; (4) When the read clock domain module 130 is in the empty control mode, the read enable generation unit 134 immediately sends the read enable signal Ren after receiving the second judgment signal, or when the read enable generation unit 134 receives the first judgment signal, it waits for a preset time before sending the read enable signal Ren, so that the read address generation unit 132 outputs the next data read address Radd_n to the storage module 110 according to the read enable signal Ren.

[0043] In one embodiment, if Figure 2 As shown, the read clock domain module 130 also includes: a read empty judgment unit 135, the input end of the read empty judgment unit 135 is connected to the output end of the write address synchronization unit 131, and the output end of the read empty judgment unit 135 is connected to the second input end of the read enable generation unit 134, which is used to judge whether the storage module 110 is in a non-empty state according to the difference between the current data write address Wadd and the next data read address Radd_n, so that the read enable generation unit 134 outputs a read enable signal Ren according to the non-empty state in the normal control mode.

[0044] It should be noted that the read empty judgment unit 135 in this embodiment judges whether the storage module 110 is in a non-empty state based on the difference between the current data write address Wadd and the next data read address Radd_n, and outputs the corresponding read empty state signal R2, that is, when the difference is greater than or equal to 1, it indicates a non-empty state, and the read empty state signal R2 is a first state signal; when the difference is equal to 0, it indicates an empty state, and the read empty state signal R2 is a second state signal; when the read clock domain module 130 is in the normal control mode, the read enable generation unit 134 outputs the read enable signal Ren according to the first state signal.

[0045] In summary, in the normal control mode, the read enable generation unit 134 selects the output signal of the read empty judgment unit 135 to determine whether to generate the read enable signal Ren; in the read empty control mode, the read enable generation unit 134 selects the output signal of the empty judgment unit 133 to determine whether to generate the read enable signal Ren.

[0046] In one embodiment, if Figure 2As shown, the read enable generating unit 134 includes an empty enable switch 1341, a count decrementer 1342, a selection signal generator 1343 and a selector 1344; the empty enable switch 1341 is used to control the working mode of the read clock domain module 130; wherein, when the empty enable switch 1341 is in an open state, it indicates an empty control mode, and when the empty enable switch 1341 is in a closed state, it indicates a normal control mode; the count decrementer 1342 is used to perform a decrement count under the action of the count enable signal Cou; the first input end of the selection signal generator 1343 is connected to the output end of the empty enable switch 1341, and the second input end of the selection signal generator 1343 is connected to the output end of the count decrementer 1342, and is used to output when the empty enable switch 1341 is in an open state, and the count value Val output by the count decrementer 1342 is equal to zero and or the count value Val output by the count decrementer 1342 is a default value. The selector 1344 outputs a first selection signal and is also used to output a second selection signal when the empty enable switch 1341 is in a closed state; the first input end of the selector 1344 is connected to the output end of the empty judgment unit 133, the second input end of the selector 1344 is connected to the output end of the read empty judgment unit 135, the third input end of the selector 1344 is connected to the output end of the selection signal generator 1343, the first output end of the selector 1344 is connected to the input end of the read address generating unit 132, and the second output end of the selector 1344 is connected to the input end of the counter decrementer 1342, and is used to generate a read enable signal Ren according to the non-empty state output by the empty judgment unit 133 under the action of the first selection signal, and output a count enable signal to the count decrementer when the empty judgment unit outputs the empty state; and is also used to generate a read enable signal Ren according to the non-empty state output by the read empty judgment unit 135 under the action of the second selection signal.

[0047] It should be noted that the working principle of the read enable generating unit 134 in this embodiment is as follows: (1) the switch between the empty control mode and the normal control mode is achieved by controlling the opening and closing of the empty enable switch 1341; the state signal Sta output by the empty enable switch 1341 includes a first state signal and a second state signal, for example: when the empty enable switch 1341 is in the open state, the first state signal is output, and when the empty enable switch 1341 is in the closed state, the second state signal is output; (2) the counter decrementer 1342 has a default value. The count value Val is decremented in sequence when receiving the count enable signal Cou output by the selector 1344, and the corresponding count value Val is output; wherein the default value can be flexibly set according to the read-write clock frequency, so that the countdown time from the default value to 0 is the preset waiting time of the read clock domain, that is, after the count decrementer 1342 counts from the default value to 0, the storage module 110 must be in a non-empty state; in addition, when the count decrementer 1342 outputs 0, it will automatically return to the default value and wait for the next round of count enable signal Cou to perform decrement control. (3) The selection signal generator 1343 receives the state signal Sta output by the empty enable switch 1341 and the count value Val output by the count decrementer 1342. When the state signal Sta is the first state signal and the count value Val is the default value or the count value Val is zero, the output selection signal Se is the first selection signal; when the state signal Sta is the second state signal, the selection signal Se output by the selection signal generator 1343 is the second selection signal; that is to say: when the empty enable switch 1341 is in the closed state, the selection signal generator 1343 only outputs the second selection signal; when the empty enable switch 1341 is in the open state and the count decrementer 1342 outputs 0, the selection signal generator 1343 outputs the second selection signal again. Before the count decrementer 1342 outputs 0, the selection signal generator 1343 does not output any selection signal Se.(4) When the selector 1344 receives the second selection signal (that is, the normal control mode), the selector 1344 generates a corresponding read enable signal Ren according to the read empty state signal R2 output by the read empty judgment unit 135, that is, when the read empty state signal R2 output by the read empty judgment unit 135 is empty, the selector 1344 does not generate the read enable signal Ren, and when the read empty state signal R2 output by the read empty judgment unit 135 is not empty, the selector 1344 generates the read enable signal Ren; when the selector 1344 receives the second selection signal, the selector 1344 generates a corresponding enable signal according to the empty state signal R1 output by the empty judgment unit 133, that is, the empty judgment unit 133 When the output empty state signal R1 is not empty, the read enable signal Ren is generated. When the empty state output by the empty judgment unit 133 is empty, the read enable signal Ren is not generated, and multiple count enable signals Cou are generated at the same time and sent to the count decrementer 1342 in sequence, so that the count decrementer 1342 is decremented in sequence according to the received count enable signal Cou, until the count value Val output by the count decrementer 1342 is equal to 0, and then the selection signal generator 1343 outputs the second selection signal again. At this time, the empty state signal R1 output by the empty judgment unit 133 is not empty, so that the selector 1344 outputs the read enable signal Ren and suspends the output of the count enable signal Cou.

[0048] In one embodiment, if Figure 2As shown, the write clock domain module 120 includes a read address synchronization unit 121, a write address generation unit 122, a write full judgment unit 123 and a write enable generation unit 124; the input end of the read address synchronization unit 121 is connected to the synchronization end of the read clock domain module 130, and is used to obtain the current data read address Radd; the first output end of the write address generation unit 122 is connected to the write address input end of the storage module 110, and is used to generate the current data write address Wadd under the action of the write enable signal Wen, and send the current data write address Wadd to the storage module 110, and is also used to generate the next data write address Wadd_n according to the current data write address Wadd; the first input end of the write full judgment unit 123 is connected to the output end of the read address synchronization unit 121, and the second input end of the write full judgment unit 123 is connected to the second output end of the read address generation unit 132, and is used to generate the next data write address Wadd_n according to the current data read address Wadd. The write enable generating unit 124 outputs a corresponding full state signal R3 according to the difference between the address Radd and the next data write address Wadd_n, and the full state signal R3 includes a full state and a non-full state; when the difference is equal to the depth of the storage module 110, the full state signal R3 output is a full state, otherwise the full state signal R3 output is a non-full state; the first input end of the write enable generating unit 124 is connected to the external write enable output end, the second input end of the write enable generating unit 124 is connected to the output end of the write full judgment unit 123, and the output end of the write enable generating unit 124 is connected to the input end of the write address generating unit 122, and is used for outputting the write enable signal Wen to the write address generating unit 122 when the write enable signal Wen is input externally and the write full judgment unit 123 outputs a non-full state, so that the write address generating unit 122 outputs the next data write address Wadd_n to the storage module 110 according to the write enable signal Wen.

[0049] In one embodiment, the write clock domain module 120 also includes: a first encoding unit 125, the input end of the first encoding unit 125 is connected to the first output end of the write address generating unit 122, and the output end of the first encoding unit 125 is connected to the write address synchronization unit 131, which is used to convert the current data write address Wadd into Gray code and output it to the write address synchronization unit 131.

[0050] In one embodiment, the read clock domain module 130 also includes: a second encoding unit 136, the input end of the second encoding unit 136 is connected to the first output end of the read address generating unit 132, and the output end of the second encoding unit 136 is connected to the read address synchronization unit 121, which is used to convert the current data read address Radd into Gray code and output it to the read address synchronization unit 121.

[0051] Figure 3 FIG. 1 is a flow chart of a data caching method provided in an embodiment of the present application; Figure 3As shown, the data caching method specifically includes the following steps:

[0052] Step S100: When a write enable signal is input externally and the storage module is in a non-full state, the write clock domain module generates a data write address;

[0053] Step S200: The storage module writes the received first data signal into a storage space corresponding to the data write address in the write clock domain;

[0054] Step S300: When the storage module is in an empty state, the clock domain reading module generates a data read address after waiting for a preset time.

[0055] Step S400: The storage module reads out a second data signal from a storage space corresponding to a data read address in a read clock domain.

[0056] In one embodiment, when the storage module is in a will-be-empty state, the read clock domain module generates a data read address after waiting for a preset time, including: when the will-be-empty enable switch is in an on state and the will-be-empty judgment unit outputs the will-be-empty state, the selector generates multiple count enable signals; the count decrementer sequentially decreases from a default value to zero according to the multiple count enable signals received; wherein the time duration for the count decrementer to sequentially decrease from the default value to zero is a preset time duration; the selection signal generator outputs a target selection signal according to a count value equal to zero, so that the selector generates a read enable signal according to the non-will-be-empty state output by the will-be-empty judgment unit; and the read address generation unit generates a data read address according to the read enable signal.

[0057] It should be noted that the data caching method of this embodiment has the same working principle as the data cache of the above embodiment, which will not be described in detail here.

[0058] In one embodiment, the present application provides a data synchronization system, which includes: a first buffer, an enable end of the first buffer is connected to an external write enable output end, and a data input end of the first buffer is connected to an external data output end; a data synchronization module, a data receiving end of the data synchronization module is connected to a data output end of the first buffer; a second buffer, an enable end of the second buffer is connected to a write enable output end of the data synchronization module, a data input end of the second buffer is connected to a data output end of the data synchronization module, and a data output end of the second buffer is connected to an external data receiving end.

[0059] In this embodiment, the first buffer corresponds to Figure 1 The first transmit data buffer in the second buffer corresponds to Figure 1 The second sending data buffer in; wherein any one of the first buffer and the second buffer is the data buffer of the above embodiment.

[0060] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0061] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0062] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A data buffer, characterized in that: Applied to data synchronization across different chips, the data buffer includes: A storage module, comprising a plurality of storage spaces for caching data, and each storage space corresponds to an address with a unique identifier; wherein the storage module comprises a non-full state, a nearly empty state, a non-empty state, and a non-nearly empty state, wherein the nearly empty state indicates that data is stored in less than or equal to a preset threshold number of storage spaces in the storage module; A write clock domain module, wherein the enable end of the write clock domain module is connected to the external write enable output end, and the write address output end of the write clock domain module is connected to the write address input end of the storage module, and is used to generate a data write address when an external write enable signal is input and the storage module is in a non-full state; A read clock domain module, wherein the read address output terminal of the read clock domain module is connected to the read address input terminal of the storage module, and is used to generate a data read address after waiting for a preset time when the storage module is in a near-empty state; wherein the read clock domain module includes a near-empty control mode and a normal control mode; in the normal control mode, the read clock domain module is used to generate a data read address when the storage module is in a non-near state; in the near-empty control mode, the read clock domain module is used to generate the data read address when the storage module is converted from the near-empty state to the non-near-empty state, or when the storage module is in the near-empty state and waits for a preset time, The data input terminal of the storage module is connected to the external data output terminal, and the data output terminal of the storage module is connected to the external data receiving terminal, and is used to write the received first data signal into the storage space corresponding to the data write address in the write clock domain, and is also used to read the second data signal from the storage space corresponding to the data read address in the read clock domain; The read clock domain module includes a write address synchronization unit, a read address generation unit, a will-be-empty judgment unit, a read enable generation unit and a read-empty judgment unit; the first input end of the will-be-empty judgment unit is connected to the output end of the write address synchronization unit, and the second input end of the will-be-empty judgment unit is connected to the second output end of the read address generation unit, and is used to judge whether the storage module is in a will-be-empty state according to the difference between the current data write address and the next data read address; wherein the read enable generation unit includes: The empty enable switch is used to control the working mode of the read clock domain module; wherein, when the empty enable switch is in an open state, it indicates an empty control mode, and when the empty enable switch is in an closed state, it indicates a normal control mode; A counter decrementer, the counter decrementer is used to count down under the action of a count enable signal; A selection signal generator, wherein a first input terminal of the selection signal generator is connected to an output terminal of the empty enable switch, and a second input terminal of the selection signal generator is connected to an output terminal of the counter decrementer, and is used to output a first selection signal when the empty enable switch is in an open state and a count value output by the counter decrementer is equal to zero or a count value output by the counter decrementer is a default value, and is also used to output a second selection signal when the empty enable switch is in a closed state; A selector, wherein the first input end of the selector is connected to the output end of the will-be-empty judgment unit, the second input end of the selector is connected to the output end of the read-empty judgment unit, the third input end of the selector is connected to the output end of the selection signal generator, the first output end of the selector is connected to the input end of the read address generating unit, and the second output end of the selector is connected to the input end of the counter decrementer, and is used to generate a read enable signal according to the non-will-be-empty state output by the will-be-empty judgment unit under the action of the first selection signal, and output a count enable signal to the count decrementer when the will-be-empty judgment unit outputs the will-be-empty state, and is also used to generate a read enable signal according to the non-empty state output by the read-empty judgment unit under the action of the second selection signal.

2. The data buffer according to claim 1, characterized in that: The input end of the write address synchronization unit is connected to the synchronization end of the write clock domain module, and is used to obtain the current data write address; The first output terminal of the read address generating unit is connected to the read address input terminal of the storage module, and is used to generate a current data read address under the action of a read enable signal, and send the current data read address to the storage module, and is also used to generate a next data read address according to the current data read address; The first input end of the read enable generating unit is connected to the output end of the will-be-empty judgment unit, and the output end of the read enable generating unit is connected to the input end of the read address generating unit, and is used to output a read enable signal to the read address generating unit when the will-be-empty control mode is in progress and the will-be-empty judgment unit outputs a non-will-be-empty state, or to output a read enable signal to the read address generating unit after waiting for a preset time when the will-be-empty control mode and the will-be-empty judgment unit outputs a will-be-empty state, so that the read address generating unit outputs the next data read address to the storage module according to the read enable signal.

3. The data buffer according to claim 2, characterized in that: The input end of the read empty judgment unit is connected to the output end of the write address synchronization unit, and the output end of the read empty judgment unit is connected to the second input end of the read enable generation unit, and is used to judge whether the storage module is in a non-empty state according to the difference between the current data write address and the next data read address, so that the read enable generation unit outputs a read enable signal according to the non-empty state in the normal control mode.

4. The data buffer according to claim 2, characterized in that: The write clock domain module comprises: A read address synchronization unit, the input end of which is connected to the synchronization end of the read clock domain module, and is used to obtain the current data read address; a write address generating unit, wherein a first output terminal of the write address generating unit is connected to a write address input terminal of the storage module, and is used to generate a current data write address under the action of a write enable signal, and send the current data write address to the storage module, and is also used to generate a next data write address according to the current data write address; a full judgment unit, wherein a first input end of the full judgment unit is connected to an output end of the read address synchronization unit, and a second input end of the full judgment unit is connected to a second output end of the read address generation unit, and is used to judge whether the storage module is in a non-full state according to a difference between the current data read address and the next data write address; A write enable generating unit, wherein a first input terminal of the write enable generating unit is connected to the external write enable output terminal, a second input terminal of the write enable generating unit is connected to the output terminal of the write full judgment unit, and the output terminal of the write enable generating unit is connected to the input terminal of the write address generating unit, and is used for outputting the write enable signal to the write address generating unit when the external input write enable signal is received and the write full judgment unit outputs a non-full state, so that the write address generating unit outputs the next data write address to the storage module according to the write enable signal.

5. The data buffer according to claim 4, characterized in that: The write clock domain module further includes: a first encoding unit, wherein an input end of the first encoding unit is connected to a first output end of the write address generating unit, and an output end of the first encoding unit is connected to the write address synchronization unit, and is used for converting the current data write address into a Gray code and outputting the converted code to the write address synchronization unit; The read clock domain module also includes: a second encoding unit, the input end of the second encoding unit is connected to the first output end of the read address generating unit, and the output end of the second encoding unit is connected to the read address synchronization unit, which is used to convert the current data read address into Gray code and output it to the read address synchronization unit.

6. A data caching method, characterized in that: Applied to the data buffer according to any one of claims 1 to 5, the data caching method comprises: When the write enable signal is input externally and the storage module is in a non-full state, the write clock domain module generates a data write address; The storage module writes the received first data signal into the storage space corresponding to the data write address in the write clock domain; When the storage module is in a nearly empty state, the clock domain reading module generates a data read address after waiting for a preset time length; The storage module reads out a second data signal from the storage space corresponding to the data read address in the read clock domain; When the storage module is in a nearly empty state, the clock domain reading module generates a data read address after waiting for a preset time, including: When the empty enable switch is in an on state and the empty judgment unit outputs an empty state, the selector generates a plurality of counting enable signals; The counter decrementer sequentially decrements from a default value to zero according to the received multiple count enable signals; wherein the duration for the counter decrementer to sequentially decrement from the default value to zero is the preset duration; The selection signal generator outputs a target selection signal according to the count value equal to zero, so that the selector generates a read enable signal according to the non-will-be-empty state output by the will-be-empty judgment unit; The read address generating unit generates a data read address according to the read enable signal.

7. A data synchronization system, characterized in that: The data synchronization system comprises: A first buffer, wherein an enable terminal of the first buffer is connected to an external write enable output terminal, and a data input terminal of the first buffer is connected to an external data output terminal; A data synchronization module, wherein a data receiving end of the data synchronization module is connected to a data output end of the first buffer; a second buffer, wherein an enable terminal of the second buffer is connected to a write enable output terminal of the data synchronization module, a data input terminal of the second buffer is connected to a data output terminal of the data synchronization module, and a data output terminal of the second buffer is connected to an external data receiving terminal; Wherein, any one of the first buffer and the second buffer comprises the data buffer according to any one of claims 1-5.

Images