A method and system for calculating logic execution wear of state logic gates

Abstract

The present invention discloses a method and system for calculating the logic execution wear of a state logic gate. The method for calculating the logic execution wear of a state logic gate includes the following steps: S1, determining the number of all logic input combinations of the state logic gate and the corresponding original logic output value; S2, counting the number of all logic input combinations that change the logic output value of the state logic gate; S3, dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations to obtain the flip rate of the state logic gate as the logic execution wear of the state logic gate. The present invention aims to realize the evaluation of the logic execution wear of the state logic gate, so as to provide the underlying information basis for the subsequent optimization of the total flip number of complex state logic calculation processes.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a method and system for calculating logic execution wear of a state logic gate. Background Art

[0002] The state logic gate is a logic gate design based on memristors. It uses the unique resistance change characteristics of memristors to realize logical operations. By integrating the functions of Boolean logic and non-volatile storage, the state logic gate can eliminate data movement in the calculation process, realize calculation in memory, and break the "storage wall" and "energy consumption wall" of the traditional "von Neumann" computing system. However, memristors have a certain physical service life due to the durability of their own resistance state flipping. The process of state logic gates completing logical calculations is to use the "conditional transition" process to complete logical calculations. The completion of a logical operation may be accompanied by the flipping of the resistance state on the output device, making the memristors on the memristor array easy to wear and fail. For the execution process of a state logic gate, only when the logic output changes, it represents a flip of the device state (i.e. wear), which only exists under individual logic input combinations. In the process of complex calculation execution, too many flips may cause device failure, thereby reducing the service life of the memristor array (device). In particular, under the current preparation process, the durability of memristor arrays is generally lower than that of mature transistors, which has caused researchers to worry about the life of the in-memory state logic computing system. In particular, for many application scenarios where equipment repair and maintenance are difficult, the state logic computing process that uses state logic gates for multiple frequent erases and writes faces huge challenges. How to evaluate the logical execution wear of state logic gates has become a key technical issue that needs to be solved urgently. Summary of the invention

[0003] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a method and system for calculating the logic execution wear of state logic gates are provided. The present invention aims to realize the evaluation of the logic execution wear of state logic gates, so as to provide the underlying information basis for the subsequent optimization of the total number of flips in complex state logic calculation processes.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A method for calculating the logic execution wear of a state logic gate comprises the following steps:

[0006] S1, determine the number of all logic input combinations of the state logic gate and the corresponding original logic output values;

[0007] S2, counting the number of all logic input combinations that change the logic output value of the state logic gate;

[0008] S3, dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations to obtain a flip rate of the state logic gate as the logic execution wear of the state logic gate;

[0009] Before step S1, it also includes judging the type of the state logic gate. If the state logic gate is a basic logic gate, jump to step S1; if the state logic gate is a composite logic gate extended from the basic logic gate, if the flip rate of the corresponding basic logic gate is known, the flip rate of the corresponding basic logic gate is multiplied by 1 / 2 to obtain the flip rate of the composite logic gate as the logic execution wear, end and exit of the state logic gate. If the flip rate of the corresponding basic logic gate is unknown, jump to step S1.

[0010] Optionally, the number of all logic input combinations of the state logic gate determined in step S1 is ,in The number of logical input variables for the state logic gate.

[0011] Optionally, the corresponding logic output value in step S1 is obtained by calculating the logic input combination of the state logic gate through the logic expression of the state logic gate, or by querying the logic input combination of the state logic gate through the truth table of the state logic gate.

[0012] Optionally, step S2 includes:

[0013] S2.1, initialize and set the value of variable M to 0;

[0014] S2.2, traverse all logic input combinations of the state logic gate to obtain a logic input combination as the current logic input combination. If the traversal has not been completed, jump to step S2.3; otherwise, jump to step S2.5;

[0015] S2.3, combining the current logic inputs through the state logic gate to obtain the corresponding logic output value;

[0016] S2.4, determine whether the logic output value of the current logic input combination is the same as the original logic output value corresponding to the current logic input combination, if they are different, add 1 to the variable M, otherwise keep the variable M unchanged and jump to step S2.2;

[0017] S2.5, set the variable M as the number of logic input combinations that causes the logic output value of the state logic gate to change.

[0018] Optionally, in step S2.3, when the current logic input combination is passed through the state logic gate to obtain the corresponding logic output value, it includes judging the type of the state logic gate. If the state logic gate is a basic logic gate, the logic input and logic output of the basic logic gate are clearly represented by the resistance states of different devices, and the original value on the logic output device is a constant 0 or a constant 1. After the logic operation is completed, the value on the logic output device is the logic output of the basic logic gate; if the state logic gate is a composite logic gate expanded from the basic logic gate, the original value on the logic output device of the composite logic gate is also used as one of the logic inputs. After the logic operation is completed, the value on the logic output device is the logic output of the composite logic gate.

[0019] Optionally, in step S3, the function expression of the flip rate of the state logic gate obtained by dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations is: ,in The number of logic input combinations that change the logic output value of the state logic gate, is the number of all logical input combinations, The number of logical input variables for the state logic gate.

[0020] In addition, the present invention also provides a logic execution wear calculation system for state logic gates, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the logic execution wear calculation method for state logic gates.

[0021] In addition, the present invention also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the logic execution wear calculation method for state logic gates through a processor.

[0022] In addition, the present invention also provides a computer program product, including a computer program or an instruction, which is programmed or configured to execute the logic execution wear calculation method for the state logic gate through a processor.

[0023] Compared with the prior art, the present invention mainly has the following advantages: the method for calculating the logic execution wear of the state logic gate of the present invention includes determining the number of all logic input combinations of the state logic gate and the corresponding original logic output values, counting the number of all logic input combinations that change the logic output value of the state logic gate, and dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations to obtain the flip rate of the state logic gate as the logic execution wear of the state logic gate. The present invention solves the statistical problem of the number of all logic input combinations by means of permutation and combination calculation, solves the statistical problem of the number of all logic input combinations that change the logic output value by means of logic calculation and traversal comparison, and uses the flip rate of the state logic gate to characterize the logic execution wear of the state logic gate, so as to accurately realize the evaluation of the logic execution wear of the state logic gate. On this basis, methods for reducing the total flip times of devices in complex state logic calculation processes can be explored to meet the needs of low-wear application scenarios, so as to provide the underlying information basis for the subsequent optimization of the total flip times of complex state logic calculation processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention. DETAILED DESCRIPTION

[0025] like Figure 1 As shown, the method for calculating the logic execution wear of the state logic gate in this embodiment includes the following steps:

[0026] S1, determine the number of all logic input combinations of the state logic gate and the corresponding original logic output values;

[0027] S2, counting the number of all logic input combinations that change the logic output value of the state logic gate;

[0028] S3, dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations to obtain the flip rate of the state logic gate as the logic execution wear of the state logic gate.

[0029] In this embodiment, the number of all logic input combinations of the state logic gate determined in step S1 is ,in The number of logical input variables for the state logic gate.

[0030] In this embodiment, the corresponding logic output value in step S1 is obtained by calculating the logic input combination of the state logic gate through the logic expression of the state logic gate, or by querying the logic input combination of the state logic gate through the truth table of the state logic gate. Taking the two-input NOR state logic gate as an example, its truth table is shown in Table 1.

[0031] Table 1. Truth table of NOR state logic gate

[0032]

[0033] As shown in Table 1, for the NOR state logic gate, the initial value of its logic output device is always 0. Only when the logic input is 00, the value of the logic output device changes from 0 to 1, and the value of the logic output device remains unchanged at 0 in other cases. The number of logic inputs of this state logic gate is 2, so the number of all logic input combinations of this state logic gate can be calculated as , which is consistent with the result of the truth table.

[0034] Taking the ONOR compound logic gate expanded from the OR state logic gate as an example, its truth table is shown in Table 2.

[0035] Table 2, truth table of ONOR compound logic gate

[0036]

[0037] As can be seen from Table 2, the initial value of the output device of the compound gate is not fixed, it represents the third logic input value. The number of logic inputs of the ONOR compound logic gate is 3, and the number of all logic input combinations of the state logic gate can be calculated as , which is consistent with the result of the truth table. The logical function implemented by the ONOR compound logic gate is , calculated through the logical expression, when the first two logic inputs A and B are both 0 or the third logic input C is 1, the logic output is 1, and for the remaining logic input combinations, the logic output is 0.

[0038] In this embodiment, step S2 includes:

[0039] S2.1, initialize and set the value of variable M to 0;

[0040] S2.2, traverse all logic input combinations of the state logic gate to obtain a logic input combination as the current logic input combination. If the traversal has not been completed, jump to step S2.3; otherwise, jump to step S2.5;

[0041] S2.3, combining the current logic inputs through the state logic gate to obtain the corresponding logic output value;

[0042] S2.4, determine whether the logic output value of the current logic input combination is the same as the original logic output value corresponding to the current logic input combination, if they are different, add 1 to the variable M, otherwise keep the variable M unchanged and jump to step S2.2;

[0043] S2.5, set the variable M as the number of logic input combinations that causes the logic output value of the state logic gate to change.

[0044] Taking the NOR state logic gate as an example, the function of this state logic gate is to complete the NOR operation of two inputs. It is calculated through the logical expression that only when both logic inputs are 0, the logic output is 1, and in the case of other logic input combinations, the logic output is 0 (maintaining the original value unchanged). According to the steps recorded in steps S2.1 to S2.5, it can be obtained that the number M of all logic input combinations that change the logic output value is 1. Therefore, the flip rate of this NOR state logic gate is 1 / 4.

[0045] Taking the ONOR compound logic gate as an example, according to the steps recorded in steps S2.1 to S2.5, it can be obtained that the number M of all logic input combinations that change the logic output value is 1, which is consistent with the result of the truth table.

[0046] In this embodiment, when the current logic input combination is used to obtain the corresponding logic output value through the state logic gate in step S2.3, it includes judging the type of the state logic gate. If the state logic gate is a basic logic gate, the logic input and logic output of the basic logic gate are clearly represented by the resistance states of different devices, and the original value on the logic output device is a constant 0 or a constant 1. After the logic operation is completed, the value on the logic output device is the logic output of the basic logic gate; if the state logic gate is a composite logic gate expanded from the basic logic gate, the original value on the logic output device of the composite logic gate is also used as one of the logic inputs. After the logic operation is completed, the value on the logic output device is the logic output of the composite logic gate.

[0047] In this embodiment, the function expression of the flip rate of the state logic gate obtained by dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations in step S3 is: ,in The number of logic input combinations that change the logic output value of the state logic gate, is the number of all logical input combinations, The number of logical input variables of the state logic gate. Taking the NOR state logic gate as an example, the number of all its logical input combinations is , the number of logic input combinations that change the logic output value of the state logic gate , then the flip rate of the state logic gate obtained by dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations is 1 / 4. Taking the ONOR compound logic gate as an example, the number of all logic input combinations is , the number of logic input combinations that change the logic output value of the state logic gate , then the flip rate of the state logic gate obtained by dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations is 1 / 8, which is 1 / 2 of the flip rate of the NOR state logic gate.

[0048] Similarly, the flip rate of the two-input basic state logic gate based on three devices can be statistically shown in Table 3, and the flip rate of the single-input basic state logic gate based on two devices is shown in Table 4.

[0049] Table 3. Flip rates of two-input basic state logic gates based on three devices

[0050]

[0051] In Table 3, AND is AND logic, OR is OR logic, NAND is NAND logic, NOR is NOR logic; IMP is implication logic, and its logical expression is ; RIMP is the anti-implication logic, and its logical expression is NIMP is implied negation logic, and its logical expression is ; RNIMP is the negative implied negation logic, and its logical expression is In the above representation, A and B represent the logic inputs, C represents the original value of the logic output (and also represents another logic input of the compound gate expanded from the simple gate). Represents the logic output after the logic operation is completed. The flip rate of the composite logic gate expanded from these basic logic gates is the original flip rate value multiplied by 1 / 2.

[0052] Table 4. Flip rates of single-input basic state logic gates based on two devices

[0053]

[0054] In Table 4, COPY is a copy gate. As the name implies, the logic output is a copy of the logic input, that is, the logic output is equal to the logic input ( ); NOT is a NOT gate, that is, the logic output is the inversion of the logic input, and the logical expression is In the above representation, A represents the logic input, B represents the original value of the logic output (also represents another logic input of the compound gate expanded from the simple gate), Represents the logic output value after the logic operation is completed. Similarly, the flip rate of the composite gate expanded from these gates is the original flip rate value multiplied by 1 / 2.

[0055] Based on the rules of Table 3 and Table 4, as an optional implementation method, before step S1 of this embodiment, the type of state logic gate is also included in judging. If the state logic gate is a basic logic gate, then jump to step S1; if the state logic gate is a compound logic gate extended from a basic logic gate, then if the flip rate of the corresponding basic logic gate is known, then the flip rate of the corresponding basic logic gate is multiplied by 1 / 2 to obtain the flip rate of the compound logic gate as the logic execution wear of the state logic gate, end and exit; if the flip rate of the corresponding basic logic gate is unknown, then jump to step S1. Through the above method, the flip rate of the compound logic gate extended from the basic logic gate can be quickly calculated when the flip rate of the corresponding basic logic gate is known, thereby improving the efficiency of calculating the logic execution wear of the compound logic gate extended from the basic logic gate.

[0056] In summary, the method of this embodiment includes determining the number of all logic input combinations of the state logic gate and the corresponding original logic output values, counting the number of all logic input combinations that change the logic output value of the state logic gate, and dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations to obtain the flip rate of the state logic gate as the logic execution wear of the state logic gate. The method of this embodiment solves the statistical problem of the number of all logic input combinations by means of permutation and combination calculation, and solves the statistical problem of the number of all logic input combinations that change the logic output value by means of logic calculation and traversal comparison. The flip rate of the state logic gate is used to characterize the logic execution wear of the state logic gate, so as to accurately realize the evaluation of the logic execution wear of the state logic gate. On this basis, methods for reducing the total flip times of devices in complex state logic calculation processes can be explored to meet the needs of low-wear application scenarios, so as to provide the underlying information basis for the subsequent optimization of the total flip times of complex state logic calculation processes.

[0057] In addition, the present embodiment also provides a logic execution wear calculation system for a state logic gate, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the logic execution wear calculation method for a state logic gate.

[0058] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program or instruction is stored. The computer program or instruction is programmed or configured to execute the logic execution wear calculation method for the state logic gate through a processor.

[0059] In addition, the present embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the logic execution wear calculation method for state logic gates through a processor.

[0060] Those skilled in the art should understand that the technical solutions provided by the embodiments of the present application may be in the form of methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0061] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for calculating the logic execution wear of a state logic gate, characterized in that: The steps include: S1, determine the number of all logic input combinations of the state logic gate and the corresponding original logic output values; S2, counting the number of all logic input combinations that change the logic output value of the state logic gate; S3, dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations to obtain a flip rate of the state logic gate as the logic execution wear of the state logic gate; Before step S1, it also includes judging the type of the state logic gate. If the state logic gate is a basic logic gate, jump to step S1; if the state logic gate is a composite logic gate extended from the basic logic gate, if the flip rate of the corresponding basic logic gate is known, the flip rate of the corresponding basic logic gate is multiplied by 1 / 2 to obtain the flip rate of the composite logic gate as the logic execution wear, end and exit of the state logic gate. If the flip rate of the corresponding basic logic gate is unknown, jump to step S1.

2. The method for calculating the logic execution wear of a state logic gate according to claim 1, characterized in that: The number of all logic input combinations of the state logic gate determined in step S1 is ,in The number of logical input variables for the state logic gate.

3. The method for calculating the logic execution wear of a state logic gate according to claim 1, characterized in that: The corresponding logic output value in step S1 is obtained by calculating the logic input combination of the state logic gate through the logic expression of the state logic gate, or by querying the logic input combination of the state logic gate through the truth table of the state logic gate.

4. The method for calculating the logic execution wear of a state logic gate according to claim 1, characterized in that: Step S2 includes: S2.1, initially setting the value of a variable M to 0, where the variable M is the number of logic input combinations that causes the logic output value of the state logic gate to change; S2.2, traverse all logic input combinations of the state logic gate to obtain a logic input combination as the current logic input combination. If the traversal has not been completed, jump to step S2.3; otherwise, jump to step S2.5; S2.3, combining the current logic inputs through the state logic gate to obtain the corresponding logic output value; S2.4, determine whether the logic output value of the current logic input combination is the same as the original logic output value corresponding to the current logic input combination, if they are different, add 1 to the variable M, otherwise keep the variable M unchanged and jump to step S2.2; S2.5, set the variable M as the number of logic input combinations that causes the logic output value of the state logic gate to change.

5. The method for calculating the logic execution wear of a state logic gate according to claim 4, characterized in that: In step S2.3, when the current logic input combination is used to obtain the corresponding logic output value through the state logic gate, it includes judging the type of the state logic gate. If the state logic gate is a basic logic gate, the logic input and logic output of the basic logic gate are clearly represented by the resistance states of different devices, and the original value on the logic output device is a constant 0 or a constant 1. After the logic operation is completed, the value on the logic output device is the logic output of the basic logic gate; if the state logic gate is a composite logic gate expanded from the basic logic gate, the original value on the logic output device of the composite logic gate is also used as one of the logic inputs. After the logic operation is completed, the value on the logic output device is the logic output of the composite logic gate.

6. The method for calculating the logic execution wear of a state logic gate according to claim 1, characterized in that: In step S3, the function expression of the flip rate of the state logic gate obtained by dividing the number of all logic input combinations that change the logic output value of the state logic gate by the number of all logic input combinations is: ,in The number of logic input combinations that change the logic output value of the state logic gate, is the number of all logical input combinations, The number of logical input variables for the state logic gate.

7. A logic execution wear calculation system for state logic gates, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the logic execution wear calculation method for state logic gates as claimed in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the logic execution wear calculation method for state logic gates according to any one of claims 1 to 6 through a processor.

9. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the logic execution wear calculation method for state logic gates according to any one of claims 1 to 6 through a processor.

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