An enhancement-mode gallium nitride high electron mobility transistor with JFET structure

Abstract

This invention belongs to the field of microelectronics, specifically a GaN high electron mobility transistor (HEMT) incorporating a JFET structure. By introducing a JFET structure connecting the gate and source in an enhancement-mode GaN HEMT, this invention clamps the gate-under-gate barrier layer when a bias is applied to the gate, ensuring the gate voltage is fully applied to the JFET. When the JFET reaches its turn-off voltage, the gate bias is applied to the barrier layer, conducting the two-dimensional electron gas channel. The threshold voltage is controlled by the JFET structure's turn-off voltage, achieving decoupling between the threshold voltage and reverse conduction voltage, resulting in a significant increase in the threshold voltage. This invention significantly improves the threshold voltage while reducing the reverse conduction voltage and minimizing reverse conduction losses. During fast switching operations, the charge induced in the p-type doped GaN layer can be rapidly released through the JFET connecting the gate and source, improving the stability of the device's threshold voltage. Furthermore, the process used is compatible with conventional processes.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics, specifically an enhanced gallium nitride high electron mobility transistor with a JFET structure, which is a semiconductor transistor that can effectively improve the threshold voltage and threshold voltage stability of the device. Background Technology

[0002] Gallium nitride-based high electron mobility transistors (HEMTs) possess excellent characteristics such as high critical breakdown electric field, high electron saturation velocity, good thermal conductivity, radiation resistance, and good chemical stability. They are particularly suitable for high-current, low-power, high-frequency, and high-voltage applications, and are gradually becoming the primary choice for high-voltage power switching modules. To ensure the safe operation of power electronic systems, normally-off characteristics are essential, i.e., the realization of enhancement-mode (E-mode) GaNHEMTs.

[0003] In recent years, several methods for realizing enhancement-mode gallium nitride (GaN) field-effect transistors (FETs) have been proposed, such as using Cascode structures, recessed gate structures, fluorine ion implantation, and p-type doped GaN layers. Among these, GaN FETs with p-type doped GaN layers (p-GaN) have been widely commercialized due to their simple fabrication process, high reliability, and excellent performance.

[0004] The structure of traditional enhanced p-GaN HEMTs is as follows: Figure 1 As shown, it mainly includes a substrate, a gallium nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, a p-type doped gallium nitride layer, and a source, drain, and gate formed on the aluminum gallium nitride barrier layer; wherein the source and drain form ohmic contacts with the aluminum gallium nitride barrier layer, and the gate forms ohmic contacts with the p-type doped gallium nitride layer.

[0005] In 2013, Hao Wang et al. replaced nickel with tungsten, which has a high work function, as the gate metal. Tungsten forms a higher Schottky barrier with p-GaN. This structure allows for a greater gate bias within the p-GaN, increasing the threshold voltage from 1.23V to 3.03V. In the same year, the team proposed a source-connected p-GaN HEMT structure, which increased the width of the Schottky barrier depletion region, raising the threshold voltage from 0.93V to 2.44V. In 2022, Shun-Wei Tang et al. proposed a method of regrowing a p-GaN layer after recessing an AlGaN barrier in the gate region; the threshold voltage of p-GaN HEMTs fabricated using this method increased from 1.5V to 2.7V. In 2023, Yue Hao's team combined oxygen plasma treatment with oxygen atmosphere annealing to form a thin oxide interlayer on top of the p-GaN layer, raising the threshold voltage from 1.8V to 3.9V; however, these methods still have two main problems.

[0006] On the one hand, in power conversion with inductive loads, the power switch needs to provide a freewheeling path so that the current in the inductive load can flow uninterruptedly from the source to the drain for energy transfer; due to the lack of a body diode, the reverse conduction capability of a GaN HEMT is controlled by the gate; therefore, the reverse conduction voltage V of a GaN HEMT is... RT Essentially, and the threshold voltage V th and gate voltage V GS Relatedly, the above method inevitably increases the reverse conduction voltage while increasing the threshold voltage, thus introducing severe reverse conduction losses.

[0007] On the other hand, for Schottky contact p-GaN HEMTs, the p-GaN region below the Schottky barrier is not electrically connected to any electrode. This results in the p-GaN region being floating and unable to exchange free carriers with the outside environment. Therefore, during fast switching operations, the threshold voltage of the p-GaN gate GaN HEMT drifts because the charge induced in the floating p-GaN region cannot be quickly eliminated, leading to poor threshold voltage stability of the device. Summary of the Invention

[0008] To address the aforementioned problems and shortcomings, this invention provides an enhancement-mode gallium nitride high electron mobility transistor (HEMT) with a JFET structure. By introducing a JFET structure connecting the gate and source in an enhancement-mode GaN HEMT, when a bias is applied to the gate, the JFET clamps the barrier layer beneath the gate, and the gate voltage is fully applied to the JFET. When the JFET reaches the turn-off voltage, the gate bias is applied to the barrier layer, and the two-dimensional electron gas channel is turned on. This invention significantly increases the threshold voltage while reducing the reverse conduction voltage and minimizing reverse conduction losses. During fast switching operations, the charge induced in the p-type doped gallium nitride layer can be rapidly released through the JFET connecting the gate and source, improving the stability of the device's threshold voltage.

[0009] An enhancement-mode gallium nitride high electron mobility transistor with a JFET structure, the structure of which, from bottom to top, includes a substrate 101, a buffer layer 102, a channel layer 103, and a barrier layer 104.

[0010] Above the barrier layer 104 are a source 108, an insulating dielectric layer 105, a p-type doped gallium nitride layer 106, and a drain 111; wherein the source 108 forms an ohmic contact with the barrier layer 104 and the p-type doped gallium nitride layer 106, and the drain 111 forms an ohmic contact with the barrier layer 104.

[0011] The p-type doped gallium nitride layer 106 is divided into two parts: one part is located above the insulating dielectric layer 105, and the other part is located to the right of the insulating dielectric layer 105 and above the barrier layer 104; the p-type doped gallium nitride layer 106 located above the insulating dielectric layer 105 also has an n-type doped gallium nitride region 107.

[0012] A second gate 110 is provided above the n-type gallium nitride doped region 107, and the second gate 110 forms an ohmic contact with the n-type gallium nitride doped region 107.

[0013] At a distance d to the right of the insulating dielectric layer 105, a first gate 109 is provided above the p-type doped gallium nitride layer 106, where d>0. The first gate 109 and the p-type doped gallium nitride layer 106 form a Schottky contact; and the first gate 109 and the second gate 110 are interconnected to form a gate G.

[0014] The n-type gallium nitride doped region 107, the p-type gallium nitride doped layer 106, and the second gate 110 form a junction field-effect transistor (JFET) structure that connects the source 108 and the first gate 109.

[0015] A passivation layer 112 is covered between the source 108 and the second gate 110, between the second gate 110 and the first gate 109, and between the first gate 109 and the drain 111 on the surface of the entire device.

[0016] Furthermore, the n-type doped gallium nitride region 107, the p-type doped gallium nitride layer 106, and the second gate 110 form a junction field-effect transistor (JFET) structure connecting the source 108 and the first gate 109, as shown below. Figure 3 As shown, this structure clamps the voltage of the p-type gallium nitride doped layer 106 below the first gate 109 and provides a path for the discharge of induced charges in the p-type gallium nitride doped region 106.

[0017] Furthermore, the n-type doped gallium nitride region 107 is doped by ion implantation to form a multi-n-well region or by uniform doping.

[0018] Furthermore, the substrate 101 is made of one or a combination of sapphire, Si, SiC, AlN, GaN, and diamond.

[0019] Furthermore, the materials used for the buffer layer 102 and the channel layer 103 are one or a combination of GaN, AlN, AlGaN, InGaN, and InAlN.

[0020] Furthermore, the barrier layer 104 is made of Al material. x Ga 1-x N, where 0 ≤ x ≤ 1.

[0021] Furthermore, the insulating dielectric layer 105 is made of one or a combination of Al2O3, HfO2, ZnO and SiO2.

[0022] Furthermore, the passivation layer 112 is made of either SiO2 or Si3N4.

[0023] The beneficial effects of this invention are: 1) Based on the traditional p-GaN HEMT, this invention introduces a JFET structure connecting the gate and source. When a bias is applied to the gate, the JFET clamps the voltage of the p-type gallium nitride doped layer 106 below the first gate 109, and the gate voltage is fully applied to the JFET. When the JFET reaches the turn-off voltage, the gate bias is applied to the barrier layer, and the two-dimensional electron gas channel is turned on. The threshold voltage is controlled by the turn-off voltage of the JFET structure, realizing the decoupling of the threshold voltage and the reverse conduction voltage, resulting in a significant increase in the threshold voltage. 2) The introduction of the JFET structure provides a path for the discharge of induced charges in the p-GaN region, improving the stability of the device threshold voltage. 3) The fabrication process of this invention is simple and easy to implement, and compatible with traditional processes, allowing for industrial production. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a traditional p-GaN HEMT structure.

[0025] Figure 2 This is a schematic diagram of the GaN HEMT structure containing a JFET structure in Example 1.

[0026] Figure 3 This is a schematic diagram of the JFET structure of the present invention.

[0027] Figure 4 This is a schematic diagram of the GaN HEMT structure containing a JFET structure in Example 2.

[0028] Figure 5 This is a comparison graph of the transfer characteristic curves of Example 1 and a conventional p-GaN HEMT. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0030] Example 1

[0031] An enhancement-mode gallium nitride high electron mobility transistor with a JFET structure, the device structure of which is as follows: Figure 2 As shown, from bottom to top, it includes: a substrate (101), a buffer layer (102), a channel layer (103), and a barrier layer (104); above the barrier layer (104) are a source (108), an insulating dielectric layer (105), a p-type doped gallium nitride layer (106), and a drain (111); wherein the source (108) forms an ohmic contact with the barrier layer (104) and the p-type doped gallium nitride layer (106), and the drain (111) forms an ohmic contact with the barrier layer (104).

[0032] The p-type doped gallium nitride layer (106) is divided into two parts: one part is located above the insulating dielectric layer (105), and the other part is located to the right of the insulating dielectric layer (105) and above the barrier layer (104). The p-type doped gallium nitride layer (106) located above the insulating dielectric layer (105) also contains an n-type doped gallium nitride region (107). A second gate (110) is located above the n-type doped gallium nitride region (107), forming an ohmic contact. At a distance d to the right of the insulating dielectric layer (105), a first gate (109) is located above the p-type doped gallium nitride layer (106), where d > 0. The first gate (109) forms a Schottky contact with the p-type doped gallium nitride layer (106), and the first gate (109) and the second gate (110) are interconnected to form a gate G. The n-type doped gallium nitride region (107), together with the p-type doped gallium nitride layer (106) and the second gate (110), form a junction field-effect transistor (JFET) structure that connects the source (108) and the first gate (109).

[0033] A passivation layer (112) is covered between the source (108) and the second gate (110), between the second gate (110) and the first gate (109), and between the first gate (109) and the drain (111) on the surface of the overall device.

[0034] In this embodiment, the substrate (101) is made of silicon substrate with crystal orientation 111; the buffer layer (102) is made of gallium nitride; the channel layer (103) is made of gallium nitride; the barrier layer (104) is made of aluminum gallium nitride; the insulating dielectric layer (105) is made of silicon dioxide; and the passivation layer (112) is made of silicon nitride.

[0035] Table 1: Device parameters of Example 1 and conventional p-GaN HEMT

[0036]

[0037] As can be seen from Table 1, the threshold voltage of a conventional p-GaN HEMT device is 0.94V, while the threshold voltage of Embodiment 1 of the present invention is increased to 4.20V, which is about 4 times that of a conventional p-GaN HEMT device. Figure 5 This is a comparison of the transfer characteristic curves of the JFET GaN HEMT device proposed in this embodiment of the invention and the traditional enhancement-mode p-GaN HEMT device structure. The results fully demonstrate the advantages of this invention in improving the threshold voltage. The JFET between the gate and source provides a path for the discharge of induced charges in the p-GaN region, improving the stability of the device's threshold voltage.

[0038] Example 2

[0039] Compared to Example 1, the device in this example uses ion implantation to form a multi-n-well process below the second gate (110) to form an n-type doped gallium nitride region. Other structures are the same as in Example 1, such as... Figure 4 As shown.

[0040] As can be seen from the above embodiments, this invention introduces a novel GaN HEMT device structure by introducing a JFET structure connecting the gate and source in an enhancement-mode GaN HEMT. When a bias is applied to the gate, the JFET clamps the barrier layer below the gate, and the gate voltage is fully applied to the JFET. When the JFET reaches the turn-off voltage, the gate bias is applied to the barrier layer, and the two-dimensional electron gas channel is turned on. The threshold voltage is controlled by the turn-off voltage of the JFET structure, achieving decoupling between the threshold voltage and the reverse conduction voltage, resulting in a significant increase in the threshold voltage. The structure of this invention can significantly improve the threshold voltage while reducing the reverse conduction voltage of the device, thus reducing reverse conduction losses. During fast switching operations, the charge induced in the p-type doped gallium nitride layer can be quickly released through the JFET connecting the gate and source, improving the stability of the device threshold voltage. The process is simple and easy to implement, and compatible with traditional processes, making it suitable for industrial production.

Claims

1. An enhancement-mode gallium nitride high electron mobility transistor with a JFET structure, characterized in that: From bottom to top, it includes a substrate (101), a buffer layer (102), a channel layer (103), and a barrier layer (104); Above the barrier layer (104) are a source (108), an insulating dielectric layer (105), a p-type doped gallium nitride layer (106), and a drain (111); wherein the source (108) forms an ohmic contact with the barrier layer (104) and the p-type doped gallium nitride layer (106), and the drain (111) forms an ohmic contact with the barrier layer (104); The p-type doped gallium nitride layer (106) is divided into two parts, one part is located above the insulating dielectric layer (105), and the other part is located to the right of the insulating dielectric layer (105) and above the barrier layer (104); the p-type doped gallium nitride layer (106) located above the insulating dielectric layer (105) also has an n-type doped gallium nitride region (107); A second gate (110) is provided above the n-type doped gallium nitride region (107), and the second gate (110) forms an ohmic contact with the n-type doped gallium nitride region (107); At a distance d to the right of the insulating dielectric layer (105), a first gate (109) is provided above the p-type doped gallium nitride layer (106), where d>0. The first gate (109) and the p-type doped gallium nitride layer (106) form a Schottky contact; and the first gate (109) and the second gate (110) are interconnected to form a gate G. The n-type doped gallium nitride region (107), the p-type doped gallium nitride layer (106), and the second gate (110) form a junction field-effect transistor (JFET) structure that connects the source (108) and the first gate (109); A passivation layer (112) is covered between the source (108) and the second gate (110), between the second gate (110) and the first gate (109), and between the first gate (109) and the drain (111) on the surface of the overall device.

2. The enhancement-mode gallium nitride high electron mobility transistor with JFET structure as described in claim 1, characterized in that: The junction field-effect transistor (JFET) structure clamps the voltage of the p-type gallium nitride doped layer 106 below the first gate 109 and provides a path for the discharge of induced charges in the p-type doped gallium nitride layer (106).

3. The enhancement-mode gallium nitride high electron mobility transistor with a JFET structure as described in claim 1, characterized in that: The doping method of the n-type doped gallium nitride region (107) is either ion implantation to form a multi-n well region or uniform doping.

4. The enhancement-mode gallium nitride high electron mobility transistor with JFET structure as described in claim 1, characterized in that: The substrate (101) is made of one or a combination of sapphire, Si, SiC, AlN, GaN, and diamond.

5. The enhancement-mode gallium nitride high electron mobility transistor with a JFET structure as described in claim 1, characterized in that: The buffer layer (102) and the channel layer (103) are made of one or a combination of GaN, AlN, AlGaN, InGaN, and InAlN.

6. The enhancement-mode gallium nitride high electron mobility transistor with a JFET structure as described in claim 1, characterized in that: The barrier layer (104) is made of Al material. x Ga 1-x N, where 0 ≤ x ≤ 1.

7. The enhancement-mode gallium nitride high electron mobility transistor with a JFET structure as described in claim 1, characterized in that: The insulating dielectric layer (105) is made of one or a combination of Al2O3, HfO2, ZnO and SiO2.

8. The enhancement-mode gallium nitride high electron mobility transistor with a JFET structure as described in claim 1, characterized in that: The passivation layer (112) is made of SiO2 or Si3N4.

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