Semiconductor test structures and their fabrication methods, semiconductor parameter testing methods

Abstract

This disclosure relates to a semiconductor test structure and its fabrication method, as well as a semiconductor parameter testing method. The test structure includes a first test structure and a second test structure. The first test structure includes a first conductive portion, a first contact layer, a second contact layer, a first connecting line, and a second connecting line. The first and second contact layers are spaced apart on the first conductive portion. The first connecting line is connected to the first contact layer, and the second connecting line is connected to the second contact layer. The second test structure includes a second conductive portion, a third contact layer, a third connecting line, and a fourth connecting line. The third contact layer covers the second conductive portion. The third connecting line is connected to a first end of the third contact layer, and the fourth connecting line is connected to a second end of the third contact layer. The resistances of the first and third connecting lines are equal, and the resistances of the second and fourth connecting lines are equal. The sum of the resistances of the first and second contact layers is equal to the resistance of the third contact layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor test structure and its fabrication method, and a semiconductor parameter testing method. Background Technology

[0002] Semiconductor test structures are often used to test various parameters of semiconductor devices, thereby providing data support for the optimization of semiconductor manufacturing processes. However, existing semiconductor test structures can only perform parameter testing on the final device and cannot determine the main source of the parameter, thus preventing targeted optimization of the device manufacturing process.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor test structure and its fabrication method, as well as a semiconductor parameter testing method, which can calculate the contact resistance between the first conductive part and the first contact layer and the second contact layer, providing data support for product process optimization.

[0005] According to one aspect of this disclosure, a semiconductor test structure is provided, comprising:

[0006] The first test structure includes a first conductive part, a first contact layer, a second contact layer, a first connecting line, and a second connecting line. The first contact layer and the second contact layer are spaced apart on the surface of the first conductive part. The first connecting line is connected to the first contact layer, and the second connecting line is connected to the second contact layer.

[0007] The second test structure includes a second conductive portion, a third contact layer, a third connecting line, and a fourth connecting line. The third contact layer covers the surface of the second conductive portion, and the resistance of the third contact layer is less than the resistance of the second conductive portion. The third contact layer includes a first end and a second end. The third connecting line is connected to the first end, and the fourth connecting line is connected to the second end. The resistance of the first connecting line is equal to the resistance of the third connecting line, and the resistance of the second connecting line is equal to the resistance of the fourth connecting line. The sum of the resistances of the first contact layer and the second contact layer is equal to the resistance of the third contact layer.

[0008] In one exemplary embodiment of this disclosure, the semiconductor test structure further includes:

[0009] The third test structure includes a third conductive part, a fourth contact layer, a fifth connecting line, and a sixth connecting line. The fourth contact layer is located on the surface of one end of the third conductive part. The sixth connecting line is connected to the fourth contact layer. The fifth connecting line is connected to the end of the third conductive part away from the fourth contact layer. The resistance of the third conductive part is equal to the resistance of the first conductive part. The resistance of the fifth connecting line is equal to the resistance of the first connecting line. The resistance of the sixth connecting line is equal to the resistance of the second connecting line. The resistance of the fourth contact layer is equal to the resistance of the second contact layer.

[0010] In one exemplary embodiment of this disclosure, the semiconductor test structure further includes:

[0011] The fourth test structure includes a fourth conductive part, a seventh connecting line, and an eighth connecting line. The seventh connecting line and the eighth connecting line are respectively connected to two ends of the fourth conductive part. The resistance of the fourth conductive part is equal to the resistance of the first conductive part, the resistance of the seventh connecting line is equal to the resistance of the first connecting line, and the resistance of the eighth connecting line is equal to the resistance of the second connecting line.

[0012] In an exemplary embodiment of this disclosure, the first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion are all ion-doped regions, and the materials of the first contact layer, the second contact layer, the third contact layer, and the fourth contact layer are all metal silicides.

[0013] In one exemplary embodiment of this disclosure, the semiconductor test structure further includes:

[0014] A first gate structure is disposed on the first conductive portion and located between the first contact layer and the second contact layer;

[0015] A second gate structure is disposed on the third conductive portion and located between the fourth contact layer and the sixth connection line;

[0016] A third gate structure is disposed on the fourth conductive portion and located between the seventh connecting line and the eighth connecting line.

[0017] According to one aspect of this disclosure, a method for testing semiconductor parameters is provided, wherein the contact resistance between the first conductive portion and the first contact layer and the second contact layer is determined using the semiconductor test structure described in any one of the above claims.

[0018] In one exemplary embodiment of this disclosure, the testing method includes:

[0019] Test the resistance of the first conductive part;

[0020] A first voltage is applied to the first connecting line and the third connecting line respectively, and a second voltage is applied to the second connecting line and the fourth connecting line respectively;

[0021] The first current value flowing within the first test structure and the second current value flowing within the second test structure are detected.

[0022] The total resistance of the first test structure is determined based on the first voltage, the second voltage, and the first current value.

[0023] The total resistance of the second test structure is determined based on the first voltage, the second voltage, and the second current value.

[0024] The contact resistance between the first conductive part and the first contact layer and the second contact layer is determined based on the total resistance of the first test structure, the total resistance of the second test structure, and the resistance of the first conductive part.

[0025] In one exemplary embodiment of this disclosure, when the semiconductor test structure includes a third test structure, the test method further includes:

[0026] A first voltage is applied to the first connecting line and the fifth connecting line respectively, and a second voltage is applied to the second connecting line and the sixth connecting line respectively;

[0027] The first current value flowing within the first test structure and the third current value flowing within the third test structure are detected.

[0028] The total resistance of the first test structure is determined based on the first voltage, the second voltage, and the first current value.

[0029] The total resistance of the third test structure is determined based on the first voltage, the second voltage, and the third current value.

[0030] Compare the total resistance of the first test structure with the total resistance of the third test structure.

[0031] In one exemplary embodiment of this disclosure, when the semiconductor test structure includes a fourth test structure, the test method further includes:

[0032] A first voltage is applied to the seventh connection line, and a second voltage is applied to the eighth connection line;

[0033] The value of the fourth current flowing within the fourth test structure is detected;

[0034] The total resistance of the fourth test structure is determined based on the first voltage, the second voltage, and the fourth current value.

[0035] Compare the total resistance of the fourth test structure with the total resistance of the first test structure;

[0036] Compare the total resistance of the fourth test structure with the total resistance of the third test structure.

[0037] According to one aspect of this disclosure, a method for fabricating a semiconductor test structure is provided, comprising:

[0038] A first test structure is formed, the first test structure includes a first conductive part, a first contact layer, a second contact layer, a first connecting line and a second connecting line, the first contact layer and the second contact layer are distributed at intervals on the surface of the first conductive part, the first connecting line is connected to the first contact layer, and the second connecting line is connected to the second contact layer;

[0039] A second test structure is formed, comprising a second conductive portion, a third contact layer, a third connecting line, and a fourth connecting line. The third contact layer covers the surface of the second conductive portion, and the resistance of the third contact layer is less than the resistance of the second conductive portion. The third contact layer includes a first end and a second end. The third connecting line is connected to the first end, and the fourth connecting line is connected to the second end. The resistance of the first connecting line is equal to the resistance of the third connecting line, and the resistance of the second connecting line is equal to the resistance of the fourth connecting line. The sum of the resistances of the first contact layer and the second contact layer is equal to the resistance of the third contact layer.

[0040] In one exemplary embodiment of this disclosure, the manufacturing method further includes:

[0041] A third test structure is formed, comprising a third conductive portion, a fourth contact layer, a fifth connecting line, and a sixth connecting line. The fourth contact layer is located on the surface of one end of the third conductive portion. The sixth connecting line is connected to the fourth contact layer, and the fifth connecting line is connected to the end of the third conductive portion away from the fourth contact layer. The resistance of the third conductive portion is equal to the resistance of the first conductive portion, the resistance of the fifth connecting line is equal to the resistance of the first connecting line, and the resistance of the sixth connecting line is equal to the resistance of the second connecting line.

[0042] In one exemplary embodiment of this disclosure, the manufacturing method further includes:

[0043] A fourth test structure is formed, comprising a fourth conductive part, a seventh connecting line, and an eighth connecting line. The seventh connecting line and the eighth connecting line are respectively connected to two ends of the fourth conductive part. The resistance of the fourth conductive part is equal to the resistance of the first conductive part, the resistance of the seventh connecting line is equal to the resistance of the first connecting line, and the resistance of the eighth connecting line is equal to the resistance of the second connecting line.

[0044] In one exemplary embodiment of this disclosure, forming the first test structure, the second test structure, the third test structure, and the fourth test structure includes:

[0045] Multiple doped portions are formed on the substrate in an array;

[0046] The portion to be doped is ion-doped to form a conductive portion; the conductive portion located in the first row is designated as the first conductive portion, the conductive portion located in the second row is designated as the second conductive portion, the conductive portion located in the third row is designated as the third conductive portion, and the conductive portion located in the fourth row is designated as the fourth conductive portion.

[0047] The first contact layer and the second contact layer are formed on the surface of the first conductive portion, the third contact layer is formed on the surface of the second conductive portion, and the fourth contact layer is formed on the surface of the third conductive portion;

[0048] An insulating layer is formed on the side of the first contact layer, the second contact layer, the third contact layer, the fourth contact layer, and the fourth conductive portion away from the substrate;

[0049] The insulating layer is etched to form a first through-hole, a second through-hole, a third through-hole, a fourth through-hole, a fifth through-hole, a sixth through-hole, a seventh through-hole, and an eighth through-hole. The first and second through-holes expose the first and second contact layers, respectively. The third through-hole exposes a first end of the third contact layer, and the fourth through-hole exposes a second end of the third contact layer. The sixth through-hole exposes the fourth contact layer, and the fifth through-hole exposes the end of the third conductive portion away from the fourth contact layer. The seventh and eighth through-holes expose two ends of the fourth conductive portion, respectively.

[0050] A first connecting line that at least fills the first through hole, a second connecting line that at least fills the second through hole, a third connecting line that at least fills the third through hole, a fourth connecting line that at least fills the fourth through hole, a fifth connecting line that at least fills the fifth through hole, a sixth connecting line that at least fills the sixth through hole, a seventh connecting line that at least fills the seventh through hole, and an eighth connecting line that at least fills the eighth through hole are formed.

[0051] In one exemplary embodiment of this disclosure, before forming the first contact layer, the second contact layer, the third contact layer, and the fourth contact layer, the fabrication method further includes:

[0052] A first gate structure is formed on the first conductive portion, and the first gate structure is located between the first contact layer and the second contact layer;

[0053] A second gate structure is formed on the third conductive portion, and the second gate structure is located between the fourth contact layer and the sixth connection line;

[0054] A third gate structure is formed on the fourth conductive portion, and the third gate structure is located between the seventh connecting line and the eighth connecting line.

[0055] In one exemplary embodiment of this disclosure, the manufacturing method further includes:

[0056] After forming the first connecting line, the second connecting line, the third connecting line, the fourth connecting line, the fifth connecting line, the sixth connecting line, the seventh connecting line, and the eighth connecting line, the insulating layer is removed.

[0057] The semiconductor test structure, fabrication method, and semiconductor parameter testing method disclosed herein ensure that the resistance of the first connecting line equals the resistance of the third connecting line, and the resistance of the second connecting line equals the resistance of the fourth connecting line. This means that the contribution of each connecting line's resistance to the total resistance is equal in both the first and second test structures, thus eliminating the influence of each connecting line on the resistance when comparing the total resistance of the first and second test structures. Furthermore, since the sum of the resistances of the first and second contact layers equals the resistance of the third contact layer, the influence of the first, second, and third contact layers on the resistance can be further eliminated when comparing the total resistance of the first and second test structures. When comparing the total resistance of the first and second test structures, the resistance contributions of the connecting lines and contact layers can be eliminated, thereby obtaining the sum of the resistance of the first conductive part and the contact resistances between the first conductive part and the first and second contact layers. In addition, the resistance of the first conductive part can be measured during the manufacturing process; therefore, through simple mathematical calculations, the contact resistance between the first conductive part and the first and second contact layers can be determined, clearly identifying the location of resistance generation in the device. Staff can use the calculated contact resistance to determine whether the contact resistance meets the product requirements, thereby providing data support for product process optimization, which helps to accelerate the process optimization process and improve product performance.

[0058] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0059] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0060] Figure 1 This is a schematic diagram of the semiconductor test structure in an embodiment of this disclosure.

[0061] Figure 2 This is a flowchart illustrating the method for fabricating a semiconductor test structure according to an embodiment of this disclosure.

[0062] Figure 3 This is a schematic diagram of the substrate, the first mask layer, and the photoresist layer in an embodiment of this disclosure.

[0063] Figure 4 This is a schematic diagram of the part to be doped in an embodiment of this disclosure.

[0064] Figure 5 This is a schematic diagram of the first mask layer after thinning in an embodiment of this disclosure.

[0065] Figure 6 This is a schematic diagram of the insulating material layer in an embodiment of this disclosure.

[0066] Figure 7 This is a schematic diagram of the trench isolation structure in an embodiment of this disclosure.

[0067] Figure 8 This is a schematic diagram of the first photoresist layer in an embodiment of this disclosure.

[0068] Figure 9 This is a schematic diagram of the first gate structure, the second gate structure, and the third gate structure in the embodiments of this disclosure.

[0069] Figure 10 This is a schematic diagram of the gate oxide layer in an embodiment of this disclosure.

[0070] Figure 11 This is a schematic diagram of the gate material layer and photoresist portion in an embodiment of this disclosure.

[0071] Figure 12 This is a schematic diagram of the photoresist section and the first gate structure, the second gate structure and the third gate structure in the embodiments of this disclosure.

[0072] Figure 13 This is a schematic diagram of the insulating covering layer in an embodiment of this disclosure.

[0073] Figure 14 This is a schematic diagram of the second photoresist layer in an embodiment of this disclosure.

[0074] Figure 15 This is a schematic diagram of the first opening, the second opening, the third opening, and the fourth opening in an embodiment of this disclosure.

[0075] Figure 16 This is a schematic diagram of the first contact layer, the second contact layer, the third contact layer, and the fourth contact layer in an embodiment of this disclosure.

[0076] Figure 17 This is a schematic diagram of the insulating layer and the third photoresist layer in an embodiment of this disclosure.

[0077] Figure 18 For the embodiments of this disclosure along Figure 17 A cross-sectional view taken in the direction indicated by the middle arrow.

[0078] Figure 19 This is a schematic diagram of the conductive layer in an embodiment of this disclosure.

[0079] Figure 20 For the embodiments of this disclosure along Figure 19 A cross-sectional view taken along the AA direction.

[0080] Figure 21 For the embodiments of this disclosure along Figure 19 A cross-sectional view taken along the BB direction.

[0081] Figure 22 For the embodiments of this disclosure along Figure 19 A cross-sectional view taken along the CC direction.

[0082] Figure 23 For the embodiments of this disclosure along Figure 19 A cross-sectional view taken along the DD direction.

[0083] Figure 24 This is a schematic diagram of the fourth photoresist layer in an embodiment of this disclosure.

[0084] Figure 25 This is a schematic diagram of each pad in an embodiment of this disclosure.

[0085] Explanation of reference numerals in the attached figures:

[0086] 1. First test structure; 11. First conductive part; 12. First contact layer; 13. Second contact layer; 14. First connecting line; 15. Second connecting line; 16. First gate structure; 17. First pad; 18. Second pad; 2. Second test structure; 21. Second conductive part; 22. Third contact layer; 23. Third connecting line; 24. Fourth connecting line; 25. Third pad; 26. Fourth pad; 3. Third test structure; 31. Third conductive part; 32. Fourth contact layer; 33. Fifth connecting line; 34. Sixth connecting line; 35. Second gate structure; 36. Fifth pad; 37. Sixth pad; 4. Fourth test structure; 41. Fourth conductive part; 42. Seventh connecting line; 43. Eighth connecting line; 44. Triple gate structure; 45, Seventh pad; 46, Eighth pad; 5, Insulating layer; 51, Fifth via; 52, Sixth via; 6, Insulating isolation layer; 61, First opening; 62, Second opening; 63, Third opening; 64, Fourth opening; 7, Second photoresist layer; 71, First developing area; 72, Second developing area; 73, Third developing area; 74, Fourth developing area; 8, Third photoresist layer; 81, Mask opening; 9, Conductive layer; 10, Substrate; 20, Doped portion; 30, First mask layer; 301, Photoresist layer; 40, Insulating material layer; 401, Trench isolation structure; 50, First photoresist layer; 501, Developing area; 60, Gate oxide layer; 70, Gate material layer; 80, Photoresist portion; 90, Fourth photoresist layer. Detailed Implementation

[0087] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0088] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0089] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” … “eighth,” etc. are used only as markers and are not a limitation on the number of objects.

[0090] In semiconductor device manufacturing processes, it is often necessary to test the contact resistance between various structures within the device. However, existing test structures can only measure the parameters of the final device and cannot determine whether ohmic contacts have formed between specific structures, thus hindering targeted process optimization. For example, when testing the resistance of a transistor, only the resistance of the entire circuit from the source to the drain of the final device can be tested. This makes it impossible to determine whether the contact resistance between the active region and other structures meets the device requirements when the transistor's resistance does not meet the requirements. Therefore, a test structure capable of detecting the contact resistance within a transistor is needed.

[0091] Based on this, embodiments of this disclosure provide a semiconductor testing structure. Figure 1 A schematic diagram of the semiconductor test structure of this disclosure is shown; as follows: Figure 1 As shown, the semiconductor test structure may include a first test structure 1 and a second test structure 2, wherein:

[0092] The first test structure 1 includes a first conductive part 11, a first contact layer 12, a second contact layer 13, a first connecting line 14, and a second connecting line 15. The first contact layer 12 and the second contact layer 13 are distributed at intervals on the surface of the first conductive part 11. The first connecting line 14 is connected to the first contact layer 12, and the second connecting line 15 is connected to the second contact layer 13.

[0093] The second test structure 2 includes a second conductive part 21, a third contact layer 22, a third connecting line 23, and a fourth connecting line 24. The third contact layer 22 covers the surface of the second conductive part 21, and the resistance of the third contact layer 22 is less than the resistance of the second conductive part 21. The third contact layer 22 includes a first end and a second end. The third connecting line 23 is connected to the first end, and the fourth connecting line 24 is connected to the second end. The resistance of the first connecting line 14 is equal to the resistance of the third connecting line 23, and the resistance of the second connecting line 15 is equal to the resistance of the fourth connecting line 24. The sum of the resistance of the first contact layer 12 and the resistance of the second contact layer 13 is equal to the resistance of the third contact layer 22.

[0094] In the semiconductor test structure disclosed herein, since the resistance of the first connecting line 14 is equal to the resistance of the third connecting line 23, and the resistance of the second connecting line 15 is equal to the resistance of the fourth connecting line 24, the contribution of the resistance of each connecting line to the total resistance is the same in both the first test structure 1 and the second test structure 2. Therefore, when comparing the total resistance of the first test structure 1 and the second test structure 2, the influence of each connecting line on the resistance can be eliminated. Simultaneously, since the sum of the resistances of the first contact layer 12 and the second contact layer 13 is equal to the resistance of the third contact layer 22, the influence of the first contact layer 12, the second contact layer 13, and the third contact layer 22 on the resistance can be further eliminated when comparing the total resistance of the first test structure 1 and the second test structure 2. When comparing the total resistance of the first test structure 1 with the total resistance of the second test structure 2, the resistance contributions of the connecting lines and contact layers can be eliminated, thereby obtaining the sum of the resistance of the first conductive part 11 and the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13. In addition, the resistance of the first conductive part 11 can be measured during the manufacturing process. Therefore, through simple mathematical calculations, the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13 can be determined, thus identifying the location of resistance generation in the device. Based on the calculated contact resistance, operators can determine whether the contact resistance meets product requirements, thereby providing data support for process optimization, accelerating the process optimization process, and improving product performance.

[0095] The following provides a detailed description of each part of the semiconductor test structure disclosed herein, along with its specific details:

[0096] Please continue reading Figure 1 As shown, the first test structure 1 may include a first conductive part 11, a first contact layer 12, a second contact layer 13, a first connecting line 14, and a second connecting line 15, wherein:

[0097] The first conductive portion 11 may be in the form of a block, and its material may be a semiconductor material, such as silicon or silicon-germanium. The first conductive portion 11 may be an ion-doped region; that is, the first conductive portion 11 may be a conductive structure formed after ion doping. For example, an ion implantation process can be used to dope a semiconductor material to form the first conductive portion 11 with conductive function. For instance, the first conductive portion 11 may be an active region in a transistor. It should be noted that in this disclosure, the resistance of the first conductive portion 11 can be detected after its formation for subsequent calculations.

[0098] The first contact layer 12 may be disposed on the surface of the first conductive portion 11. For example, the first contact layer 12 may cover the top surface of one end of the first conductive portion 11. The material of the first contact layer 12 may be a contact material with good conductivity. For example, the material of the first contact layer 12 may be a metal silicide, such as cobalt silicide.

[0099] The second contact layer 13 may also be disposed on the surface of the first conductive portion 11. The second contact layer 13 may be spaced apart from the first contact layer 12. For example, the second contact layer 13 may cover the top surface of the end of the first conductive portion 11 away from the first contact layer 12. The material of the second contact layer 13 may be the same as that of the first contact layer 12, and the area of ​​the second contact layer 13 may be equal to that of the first contact layer 12. For example, both the second contact layer 13 and the first contact layer 12 may be made of cobalt silicide. In this disclosure, the resistances of the first contact layer 12 and the second contact layer 13 are equal.

[0100] The first connecting line 14 may be disposed on the side of the first contact layer 12 away from the first conductive portion 11, and one end of the first connecting line 14 may be connected to the first contact layer 12, while the other end may extend away from the first conductive portion 11. The first connecting line 14 may serve as a lead, through which the first contact layer 12 can be electrically led out. The material of the first connecting line 14 may be a conductive material, such as titanium nitride, tungsten, or gold.

[0101] The second connecting wire 15 can be disposed on the side of the second contact layer 13 away from the first conductive part 11, and one end of the second connecting wire 15 can be connected to the second contact layer 13, while the other end can extend away from the first conductive part 11. The second connecting wire 15 can serve as a lead wire, through which the second contact layer 13 can be electrically led out. The material of the second connecting wire 15 is the same as that of the first connecting wire 14. The first test structure 1 can be a unidirectional conducting structure, that is, when different voltages are applied to the two ends of the first test structure 1, the first test structure 1 conducts unidirectionally.

[0102] Please continue reading Figure 1 As shown, the second test structure 2 may include a second conductive part 21, a third contact layer 22, a third connecting line 23, and a fourth connecting line 24, wherein:

[0103] The structure, dimensions, material, and resistance of the second conductive portion 21 are the same as those of the first conductive portion 11. Specific details can be found in the first conductive portion 11 and will not be repeated here. The third contact layer 22 can cover the surface of the second conductive portion 21. For example, the third contact layer 22 can cover the entire top surface of the second conductive portion 21. The third contact layer 22 may include a first end and a second end, which are continuous without interruption. The first end and the second end are located in the edge region of the third contact layer 22, and are spaced apart along the extension direction of the third contact layer 22. The resistance of the third contact layer 22 can be less than the resistance of the second conductive portion 21. After a voltage is applied to the second test structure 2, the current generated inside it flows through the third contact layer 22 and not through the second conductive portion 21. The material of the third contact layer 22 is the same as that of the first contact layer 12 and the second contact layer 13. For example, the materials of the third contact layer 22, the first contact layer 12, and the second contact layer 13 can all be metal silicides. In this disclosure, the resistance of the first contact layer 12 is equal to the resistance of the second contact layer 13, and the sum of the resistances of the first contact layer 12 and the second contact layer 13 is equal to the resistance of the third contact layer 22.

[0104] The third connecting line 23 may be disposed on the side of the third contact layer 22 away from the second conductive portion 21, and one end of the third connecting line 23 may be connected to the first end of the third contact layer 22, while the other end may extend away from the second conductive portion 21. The third connecting line 23 may serve as a lead, through which the first end of the third contact layer 22 may be electrically led out. The material of the third connecting line 23 may be a conductive material, such as titanium nitride, tungsten, or gold. The resistance of the third connecting line 23 is equal to the resistance of the first connecting line 14.

[0105] The fourth connecting wire 24 can be disposed on the side of the third contact layer 22 away from the second conductive portion 21, and one end of the fourth connecting wire 24 can be connected to the second end of the third contact layer 22, while the other end can extend away from the second conductive portion 21. The fourth connecting wire 24 can serve as a lead, through which the second end of the third contact layer 22 can be electrically led out. The material of the fourth connecting wire 24 is the same as that of the second connecting wire 15, and the resistance of the fourth connecting wire 24 is equal to the resistance of the second connecting wire 15.

[0106] When determining the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13 using the first test structure 1 and the second test structure 2, a first voltage can be applied to the first connecting line 14 and the third connecting line 23 respectively; simultaneously, a second voltage is applied to the second connecting line 15 and the fourth connecting line 24 respectively. The first current value flowing in the first test structure 1 and the second current value flowing in the second test structure 2 are detected, and then the total resistance of the first test structure 1 and the total resistance of the second test structure 2 are calculated respectively. Subsequently, the total resistance of the first test structure 1 and the total resistance of the second test structure 2 can be subtracted to obtain the sum of the resistance of the first conductive part 11 and the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13. Since the resistance of the first conductive part 11 has been measured in advance, the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13 can be determined through simple mathematical calculations. Workers can use the determined contact resistance to determine whether the contact resistance meets the product requirements, thereby providing data support for product process optimization, helping to accelerate the process optimization process and improve product performance.

[0107] Please refer to some embodiments of this disclosure. Figure 1 As shown, there can be multiple first conductive parts 11, which can be distributed sequentially at intervals. Each first conductive part 11 is provided with a first contact layer 12, a second contact layer 13, a first connecting line 14, and a second connecting line 15. In two adjacent first conductive parts 11, the second connecting line 15 corresponding to the previous first conductive part 11 is connected to the first connecting line 14 corresponding to the next first conductive part 11, thereby forming a first test structure 1 composed of multiple first conductive parts 11 connected in series. At the same time, there can be multiple second conductive parts 21, which can be distributed sequentially at intervals. Each second conductive part 21 is provided with a third contact layer 22, a third connecting line 23, and a fourth connecting line 24. In two adjacent second conductive parts 21, the fourth connecting line 24 corresponding to the previous second conductive part 21 is connected to the third connecting line 23 corresponding to the next second conductive part 21, thereby forming a second test structure 2 composed of multiple second conductive parts 21 connected in series. It should be noted that the number of second conductive parts 21 is equal to the number of first conductive parts 11. The first test structure 1, which includes multiple first conductive parts 11, and the second test structure 2, which includes multiple second conductive parts 21, can be compared to calculate the contact resistance between the first conductive parts 11 and the first contact layer 12 and the second contact layer 13. Since the first test structure 1 includes multiple first conductive parts 11 and the second test structure 2 includes multiple second conductive parts 21, the final calculated contact resistance is based on the average value of multiple conductive parts, resulting in higher accuracy.

[0108] In one exemplary embodiment of this disclosure, the resistance of the third connecting line 23 and the fourth connecting line 24 can be calculated based on the resistivity of the materials of the third connecting line 23 and the fourth connecting line 24 and the dimensions of the third connecting line 23 and the fourth connecting line 24. The resistance value of the third contact layer 22 can be obtained by simple calculation based on the total resistance of the second test structure 2 and the resistance of the third connecting line 23 and the fourth connecting line 24.

[0109] In one exemplary embodiment of this disclosure, please continue to refer to Figure 1 As shown, the semiconductor test structure disclosed herein may further include a third test structure 3. The third test structure 3 may include a third conductive portion 31, a fourth contact layer 32, a fifth connecting line 33, and a sixth connecting line 34, wherein:

[0110] The structure, dimensions, material, and resistance of the third conductive part 31 are the same as those of the first conductive part 11. Specific details can be found in the first conductive part 11 and will not be repeated here. The fourth contact layer 32 may be located on the surface of one end of the third conductive part 31. The material of the fourth contact layer 32 is the same as that of the second contact layer 13, and the area of ​​the fourth contact layer 32 is equal to that of the second contact layer 13; that is, the resistance of the fourth contact layer 32 is equal to that of the second contact layer 13. One end of the sixth connecting line 34 may be connected to the fourth contact layer 32, and the other end may extend away from the third conductive part 31. The material of the sixth connecting line 34 is the same as that of the second connecting line 15, and the resistance of the sixth connecting line 34 is equal to that of the second connecting line 15. For example, the materials of both the second connecting line 15 and the sixth connecting line 34 may be titanium nitride, tungsten, or gold. One end of the fifth connecting line 33 can be connected to the end of the third conductive part 31 that is away from the fourth contact layer 32, and the other end can extend to the side away from the third conductive part 31; the material of the fifth connecting line 33 is the same as the material of the first connecting line 14, and the resistance of the fifth connecting line 33 is equal to the resistance of the first connecting line 14.

[0111] In one exemplary embodiment of this disclosure, the third test structure 3 is a unidirectional conduction structure, capable of applying a first voltage to the first connecting line 14 and the fifth connecting line 33 respectively; simultaneously, applying a second voltage to the second connecting line 15 and the sixth connecting line 34 respectively, detecting the first current value flowing in the first test structure 1 and the third current value flowing in the third test structure 3, and then calculating the total resistance of the first test structure 1 and the total resistance of the third test structure 3 respectively. By comparing the total resistance of the third test structure 3 and the total resistance of the first test structure 1, the resistance of the first contact layer 12 can be obtained. Furthermore, by comparing the total resistance of the first test structure 1 and the third test structure 3, it can be determined which structural design of a single-sided contact layer on the conductive part (e.g., the active region) is more effective in reducing the contact resistance in the device compared to a double-sided contact layer design. For example, if the total resistance of the first test structure 1 is less than the total resistance of the third test structure 3 after power is applied, it indicates that the structure of setting contact layers on both sides of the first conductive part 11 in the first test structure 1 has a more significant effect on reducing contact resistance. When designing the device (e.g., transistor) structure, the first test structure 1 can be referenced, and contact layers can be designed on both sides of the top of the conductive part (e.g., active region) to reduce the contact resistance between the conductive part (e.g., active region) and the lead used for electrical lead-out conductive part.

[0112] In one exemplary embodiment of this disclosure, please continue to refer to Figure 1 As shown, the semiconductor test structure disclosed herein may further include a fourth test structure 4. The fourth test structure 4 may include a fourth conductive portion 41, a seventh connecting line 42, and an eighth connecting line 43. The fourth conductive portion 41 has the same structure, size, material, and resistance as the first conductive portion 11. Specific details can be found in the first conductive portion 11, and will not be repeated here. The seventh connecting line 42 and the eighth connecting line 43 may be connected to the two ends of the fourth conductive portion 41, respectively. The resistance of the seventh connecting line 42 is equal to the resistance of the first connecting line 14, and the resistance of the eighth connecting line 43 is equal to the resistance of the second connecting line 15.

[0113] A first voltage can be applied to the first connecting line 14 and the seventh connecting line 42 respectively; simultaneously, a second voltage can be applied to the second connecting line 15 and the eighth connecting line 43 respectively. The first current value flowing in the first test structure 1 and the fourth current value flowing in the fourth test structure 4 are detected, and the total resistance of the first test structure 1 and the total resistance of the fourth test structure 4 are calculated respectively. By comparing the total resistance of the fourth test structure 4 and the total resistance of the first test structure 1, it can be determined whether adding a contact layer can reduce the contact resistance. Simultaneously, the total resistance of the first test structure 1 can be compared with the total resistance of the third test structure 3 to further verify whether adding a contact layer can reduce the contact resistance. Verification results show that the addition of a contact layer (e.g., metal silicide) can reduce the contact resistance of the device, and the contact resistance of the device is minimized when contact layers are provided on both sides of the top of the conductive portion.

[0114] In one exemplary embodiment of this disclosure, please continue to refer to Figure 1 As shown, the semiconductor test structure disclosed herein may further include a first gate structure 16, a second gate structure 35, and a third gate structure 44. The first gate structure 16 may be disposed on a first conductive portion 11 and located between a first contact layer 12 and a second contact layer 13. When there are multiple first conductive portions 11, there may also be multiple first gate structures 16, with one first gate structure 16 disposed on each first conductive portion 11. The second gate structure 35 may be disposed on a third conductive portion 31 and located between a fourth contact layer 32 and a sixth connecting line 34. When there are multiple third conductive portions 31, there may also be multiple second gate structures 35, with one second gate structure 35 disposed on each third conductive portion 31. The third gate structure 44 may be disposed on a fourth conductive portion 41 and located between a seventh connecting line 42 and an eighth connecting line 43. When there are multiple fourth conductive portions 41, there may also be multiple fourth gate structures, with one third gate structure 44 disposed on each fourth conductive portion 41.

[0115] Since the first conductive part 11 is provided with a first gate structure 16, the third conductive part 31 is provided with a second gate structure 35, and the fourth conductive part 41 is provided with a third gate structure 44, the actual structural environment of the first conductive part 11, the third conductive part 31, and the fourth conductive part 41 can be realistically simulated. This helps to improve the accuracy of the contact resistance calculation results, provide reliable data support for process optimization, accelerate the process optimization process, and improve product performance.

[0116] This disclosure also provides a method for testing semiconductor parameters, which uses the semiconductor test structure in any of the above embodiments to determine the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13.

[0117] In one exemplary embodiment of this disclosure, the method for testing semiconductor parameters may include steps S110-S160, wherein:

[0118] Step S110: Test the resistance of the first conductive part 11.

[0119] The resistance value of the first conductive part 11 can be tested before the first contact layer 12 and the second contact layer 13 are formed. For example, the resistance value of the first conductive part 11 can be detected by a multimeter or resistance meter using a probe.

[0120] Step S120: Apply a first voltage to the first connecting line 14 and the third connecting line 23 respectively, and apply a second voltage to the second connecting line 15 and the fourth connecting line 24 respectively.

[0121] The first voltage can be a low-level voltage, and the second voltage can be a high-level voltage. After applying the first voltage to the first connecting line 14 and the second voltage to the second connecting line 15, a voltage difference is generated between the first connecting line 14 and the second connecting line 15, thereby forming a current path, that is, a current path is formed in the first test structure 1. Simultaneously, after applying the first voltage to the third connecting line 23 and the second voltage to the fourth connecting line 24, a voltage difference is generated between the third connecting line 23 and the fourth connecting line 24, thereby forming a current path, that is, a current path is formed in the second test structure 2.

[0122] Step S130: Detect the first current value flowing in the first test structure 1 and the second current value flowing in the second test structure 2.

[0123] The first current value flowing in the first test structure 1 and the second current value flowing in the second test structure 2 can be detected by a multimeter or ammeter. Of course, the first current value and the second current value can also be detected by other means. No special limitation is made here on the detection method of the first current value and the second current value.

[0124] Step S140: Determine the total resistance of the first test structure 1 based on the first voltage, the second voltage, and the first current value.

[0125] The total resistance of the first test structure 1 can be determined based on the ratio of the voltage difference between the first voltage and the second voltage to the first current value. This total resistance may include the resistance of the first connecting line 14, the resistance of the first conductive part 11, the resistance of the first contact layer 12, the resistance of the second contact layer 13, the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13, and the resistance of the second connecting line 15.

[0126] Step S150: Determine the total resistance of the second test structure 2 based on the first voltage, the second voltage, and the second current value.

[0127] The total resistance of the second test structure 2 can be determined based on the ratio of the voltage difference between the first voltage and the second voltage to the second current value. This total resistance may include the resistance of the third connecting line 23, the resistance of the third contact layer 22, and the resistance of the fourth connecting line 24.

[0128] Step S160: Determine the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13 based on the total resistance of the first test structure 1, the total resistance of the second test structure 2, and the resistance of the first conductive part 11.

[0129] Since the resistance of the first connecting line 14 is equal to the resistance of the third connecting line 23, and the resistance of the second connecting line 15 is equal to the resistance of the fourth connecting line 24, the contribution of the resistance of each connecting line to the total resistance is the same in both the first test structure 1 and the second test structure 2. Therefore, when comparing the total resistance of the first test structure 1 and the second test structure 2, the influence of each connecting line on the resistance can be eliminated. Simultaneously, since the sum of the resistances of the first contact layer 12 and the second contact layer 13 is equal to the resistance of the third contact layer 22, the influence of the first contact layer 12, the second contact layer 13, and the third contact layer 22 on the resistance can be further eliminated when comparing the total resistance of the first test structure 1 and the second test structure 2. When comparing the total resistance of the first test structure 1 with the total resistance of the second test structure 2, the resistance contributions of the connecting lines and contact layers can be eliminated, thereby obtaining the sum of the resistance of the first conductive part 11 and the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13. Furthermore, since the resistance of the first conductive part 11 has been measured, the contact resistance between the first conductive part 11 and the first contact layer 12 and the second contact layer 13 can be determined by simple mathematical calculations.

[0130] In an exemplary embodiment of this disclosure, the materials and dimensions of the first conductive portion 11, the second conductive portion 21, the third conductive portion 31, and the fourth conductive portion 41 are all equal, such that the resistances of the first conductive portion 11, the second conductive portion 21, the third conductive portion 31, and the fourth conductive portion 41 are all equal. When the semiconductor test structure includes the third test structure 3, the resistances of the first test structure 1 and the third test structure 3 can be compared. For example, the semiconductor parameter testing method of this disclosure may further include steps S210-S250, wherein:

[0131] Step S210: Apply a first voltage to the first connecting line 14 and the fifth connecting line 33 respectively, and apply a second voltage to the second connecting line 15 and the sixth connecting line 34 respectively.

[0132] After applying a first voltage to the first connecting line 14 and a second voltage to the second connecting line 15, a current path is formed in the first test structure 1. Simultaneously, after applying a first voltage to the fifth connecting line 33 and a second voltage to the sixth connecting line 34, a voltage difference is generated between the fifth connecting line 33 and the sixth connecting line 34, thereby forming a current path, i.e., a current path is formed in the third test structure 3.

[0133] Step S220: Detect the first current value flowing in the first test structure 1 and the third current value flowing in the third test structure 3.

[0134] The first current value flowing in the first test structure 1 and the third current value flowing in the third test structure 3 can be detected by a multimeter or ammeter. Of course, the first current value and the third current value can also be detected by other means. No special limitation is made on the detection method of the first current value and the third current value here.

[0135] Step S230: Determine the total resistance of the first test structure 1 based on the first voltage, the second voltage, and the first current value. The specific process of step S230 is similar to that of step S140, therefore, it will not be described again here.

[0136] Step S240: Determine the total resistance of the third test structure 3 based on the first voltage, the second voltage, and the third current value.

[0137] The total resistance of the third test structure 3 can be determined based on the ratio of the voltage difference between the first voltage and the second voltage to the third current value. This total resistance may include the resistance of the fifth connecting line 33, the resistance of the third conductive part 31, the resistance of the fourth contact layer 32, the contact resistance between the fourth contact layer 32 and the third conductive part 31, and the resistance of the fourth connecting line 24.

[0138] Step S250: Compare the total resistance of the first test structure 1 and the total resistance of the third test structure 3.

[0139] Since the resistance of the fifth connecting line 33 is equal to the resistance of the first connecting line 14, and the resistance of the sixth connecting line 34 is equal to the resistance of the second connecting line 15, the contribution of each connecting line's resistance to the total resistance is the same in both the first test structure 1 and the third test structure 3. Therefore, when comparing the total resistance of the first test structure 1 and the third test structure 3, the influence of each connecting line on the resistance can be eliminated. Since the resistance of the fourth contact layer 32 is equal to the resistance of the second contact layer 13, the influence of the fourth contact layer 32 and the second contact layer 13 on the resistance can be further eliminated when comparing the total resistance of the first test structure 1 and the third test structure 3. Furthermore, since the resistance of the third conductive part 31 is equal to the resistance of the first conductive part 11, the influence of the conductive part on the resistance can be ignored. Therefore, when comparing the first test structure 1 and the third test structure 3, it is possible to determine which design, with a single-sided contact layer on the conductive part (e.g., the active region), is more effective in reducing contact resistance in the device compared to a design with a double-sided contact layer, thus providing data support for subsequent process optimization.

[0140] In an exemplary embodiment of this disclosure, the materials and dimensions of the first conductive portion 11, the third conductive portion 31, and the fourth conductive portion 41 are all equal, such that the resistances of the first conductive portion 11, the third conductive portion 31, and the fourth conductive portion 41 are all equal. When the semiconductor test structure includes the fourth test structure 4, the resistances of the fourth test structure 4 and the first test structure 1 can be compared respectively. For example, the semiconductor parameter testing method of this disclosure may further include steps S310-S350, wherein:

[0141] Step S310: Apply a first voltage to the seventh connection line 42 and apply a second voltage to the eighth connection line 43.

[0142] After applying a first voltage to the seventh connection line 42 and a second voltage to the eighth connection line 43, a voltage difference can be generated between the seventh connection line 42 and the eighth connection line 43, thereby forming a current path, that is, a current path is formed in the fourth test structure 4.

[0143] Step S320: Detect the fourth current value flowing within the fourth test structure 4.

[0144] The fourth current value flowing through the fourth test structure 4 can be detected by a multimeter or ammeter. Of course, the fourth current value can also be detected by other means. No special limitation is made here on the detection method of the fourth current value.

[0145] Step S330: Determine the total resistance of the fourth test structure 4 based on the first voltage, the second voltage, and the fourth current value. The specific process of step S330 is similar to that of step S140, therefore, it will not be described again here.

[0146] Step S340: Compare the total resistance of the fourth test structure 4 with the total resistance of the first test structure 1.

[0147] Since the resistance of the seventh connecting line 42 is equal to the resistance of the first connecting line 14, the resistance of the eighth connecting line 43 is equal to the resistance of the second connecting line 15, and the resistance of the first conductive part 11 is equal to the resistance of the fourth conductive part 41, the contribution of the resistance of each connecting line to the total resistance is the same in both the first test structure 1 and the fourth test structure 4. Therefore, when comparing the resistances of the first test structure 1 and the fourth test structure 4, the influence of each connecting line on the resistance can be eliminated. Simultaneously, since the resistance of the first conductive part 11 is equal to the resistance of the fourth conductive part 41, the influence of the conductive part on the resistance can be ignored when comparing the first test structure 1 and the fourth test structure 4. Therefore, when comparing the first test structure 1 and the fourth test structure 4, it can be determined whether the addition of a contact layer (e.g., the first contact layer 12 and the second contact layer 13) can reduce the contact resistance of the device. The comparison shows that the total resistance of the first test structure 1 is less than the total resistance of the fourth test structure 4, thus it can be determined that the addition of a contact layer can reduce the contact resistance of the device.

[0148] Step S350: Compare the total resistance of the fourth test structure 4 with the total resistance of the third test structure 3.

[0149] In some embodiments of this disclosure, the fourth test structure 4 and the third test structure 3 can also be compared. The comparison method is similar to that of the first test structure 1 and the fourth test structure 4. The comparison shows that the total resistance of the third test structure 3 is less than the total resistance of the fourth test structure 4, which further verifies that the addition of the contact layer can reduce the contact resistance of the device.

[0150] This disclosure also provides a method for fabricating a semiconductor test structure. Figure 2 A flowchart illustrating the method for fabricating the semiconductor test structure of this disclosure is shown, such as... Figure 2 As shown, the manufacturing method includes steps S410 and S420, wherein:

[0151] Step S410: Form a first test structure 1. The first test structure 1 includes a first conductive part 11, a first contact layer 12, a second contact layer 13, a first connecting line 14, and a second connecting line 15. The first contact layer 12 and the second contact layer 13 are distributed at intervals on the surface of the first conductive part 11. The first connecting line 14 is connected to the first contact layer 12, and the second connecting line 15 is connected to the second contact layer 13.

[0152] Step S420: A second test structure 2 is formed. The second test structure 2 includes a second conductive part 21, a third contact layer 22, a third connecting line 23, and a fourth connecting line 24. The third contact layer 22 covers the surface of the second conductive part 21, and the resistance of the third contact layer 22 is less than the resistance of the second conductive part 21. The third contact layer 22 includes a first end and a second end. The third connecting line 23 is connected to the first end, and the fourth connecting line 24 is connected to the second end. The resistance of the first connecting line 14 is equal to the resistance of the third connecting line 23, and the resistance of the second connecting line 15 is equal to the resistance of the fourth connecting line 24. The sum of the resistance of the first contact layer 12 and the resistance of the second contact layer 13 is equal to the resistance of the third contact layer 22.

[0153] The method for fabricating the semiconductor test structure disclosed herein ensures that the resistance of each connecting line contributes equally to the total resistance in the first test structure 1 and the second test structure 2. The contributions of the first contact layer 12 and the second contact layer 13 to the resistance of the first test structure 1 are equal to the contribution of the third contact layer 22 to the resistance of the second test structure 2. Therefore, when comparing the total resistance of the first test structure 1 and the second test structure 2, the influence of each connecting line, the first contact layer 12, the second contact layer 13, and the third contact layer 22 on the resistance can be eliminated. Furthermore, since the resistance of the first conductive portion 11 can be directly measured during the manufacturing process, the contact resistance between the first conductive portion 11 and the first contact layer 12 and the second contact layer 13 can be determined through simple mathematical calculations, thus clearly identifying the location of resistance generation in the device. Operators can use the calculated contact resistance to determine whether the contact resistance meets product requirements, thereby providing data support for product process optimization, accelerating the process optimization process, and improving product performance.

[0154] In some embodiments of this disclosure, the method for fabricating the semiconductor test structure may further include:

[0155] Step S430: A third test structure 3 is formed. The third test structure 3 includes a third conductive part 31, a fourth contact layer 32, a fifth connecting line 33, and a sixth connecting line 34. The fourth contact layer 32 is located on one end surface of the third conductive part 31. The sixth connecting line 34 is connected to the fourth contact layer 32. The fifth connecting line 33 is connected to the end of the third conductive part 31 away from the fourth contact layer 32. The resistance of the third conductive part 31 is equal to the resistance of the first conductive part 11. The resistance of the fifth connecting line 33 is equal to the resistance of the first connecting line 14. The resistance of the sixth connecting line 34 is equal to the resistance of the second connecting line 15.

[0156] In this disclosure, by comparing the total resistance of the first test structure 1 and the third test structure 3, it can be determined which structural design of a single-sided contact layer (i.e., the fourth contact layer 32) on the active region is more effective in reducing the contact resistance of the device compared to a structural design of a double-sided contact layer (i.e., the first contact layer 12 and the second contact layer 13), which can provide data support for subsequent process optimization.

[0157] In some embodiments of this disclosure, the method for fabricating the semiconductor test structure may further include:

[0158] In step S440, a fourth test structure 4 is formed. The fourth test structure 4 includes a fourth conductive part 41, a seventh connecting line 42, and an eighth connecting line 43. The seventh connecting line 42 and the eighth connecting line 43 are respectively connected to the two ends of the fourth conductive part 41. The resistance of the fourth conductive part 41 is equal to the resistance of the first conductive part 11, the resistance of the seventh connecting line 42 is equal to the resistance of the first connecting line 14, and the resistance of the eighth connecting line 43 is equal to the resistance of the second connecting line 15.

[0159] In this disclosure, the total resistance of the first test structure 1 can be compared with the total resistance of the fourth test structure 4 to further verify whether adding a contact layer can reduce the contact resistance. The verification results show that the addition of a contact layer (e.g., metal silicide) can reduce the contact resistance of the device, and by comparing the first test structure 1 and the third test structure 3, it can be seen that the contact resistance of the device is minimized when contact layers are provided on both sides of the top of the conductive portion.

[0160] In one exemplary embodiment of this disclosure, a first test structure 1, a second test structure 2, a third test structure 3, and a fourth test structure 4 may be formed simultaneously. Forming each test structure may include steps S510-S560, wherein:

[0161] In step S510, a plurality of doped portions 20 are formed on the substrate 10 in an array.

[0162] like Figure 3 As shown, the substrate 10 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal, or irregular in shape. Its material can be a semiconductor material, for example, silicon, but is not limited to silicon. No special limitations are made on the shape and material of the substrate 10. A first mask layer 30 and a photoresist layer 301 can be formed on the substrate 10. The photoresist layer 301 is exposed and developed. The developed photoresist layer 301 can be used as a mask to etch the first mask layer 30 and the substrate 10, thereby forming multiple arrayed doped portions 20 (e.g., ...). Figure 4As shown, the dimensions of each doped portion 20 are equal. It should be noted that the first mask layer 30 can be a single-layer film structure or a composite film structure composed of multiple layers, and no special limitation is made here.

[0163] like Figure 5 As shown, after forming the doped portion 20, the thickness of the first mask layer 30 can be reduced, or a portion of the film in the first mask layer 30 can be removed. Subsequently, an insulating material layer 40 can be formed on the substrate 10 having the doped portion 20, such as... Figure 6 As shown, the insulating material layer 40 can cover the top of each doped portion 20 and fill the gaps between them. The insulating material layer 40 can be made of silicon oxide. The insulating material layer 40 can be chemically mechanically polished to expose the surface of the first mask layer 30. The first mask layer 30 can be removed by etching or other processes, followed by continued chemical mechanical polishing of the insulating material layer 40 until the surface of each doped portion 20 is fully exposed. Figure 7 As shown, the surface of the remaining insulating material layer 40 is substantially flush with the surface of each doped portion 20. The remaining insulating material layer 40 can be used as a trench isolation structure 401, which can provide insulation isolation for different doped portions 20.

[0164] In step S520, the part to be doped 20 is ion doped to form a conductive part; the conductive part located in the first row is designated as the first conductive part 11, the conductive part located in the second row is designated as the second conductive part 21, the conductive part located in the third row is designated as the third conductive part 31, and the conductive part located in the fourth row is designated as the fourth conductive part 41.

[0165] like Figure 8 As shown, a first photoresist layer 50 can be formed on the surface of the structure jointly formed by each doped portion 20 and the trench isolation structure 401. The first photoresist layer 50 can be exposed and developed to form multiple corresponding developing areas 501 exposing each doped portion 20. Ion implantation can be performed on each doped portion 20 in the developing areas 501 to transform each doped portion 20 into a conductive portion with conductive function. It should be noted that the first photoresist layer 50 can be removed after the conductive portion is formed. Please continue to see... Figure 7 As shown, for ease of distinction and explanation, each conductive part in the first row can be defined as the first conductive part 11, each conductive part in the second row can be defined as the second conductive part 21, each conductive part in the third row can be defined as the third conductive part 31, and each conductive part in the fourth row can be defined as the fourth conductive part 41.

[0166] In one exemplary embodiment of this disclosure, before performing step S530, the method for fabricating the semiconductor test structure of this disclosure may further include:

[0167] A first gate structure 16 is formed on the first conductive portion 11, such as Figure 9 As shown, the first gate structure 16 is located between the first contact layer 12 and the second contact layer 13; a second gate structure 35 is formed on the third conductive portion 31, and the second gate structure 35 is located between the fourth contact layer 32 and the sixth connecting line 34; a third gate structure 44 is formed on the fourth conductive portion 41, and the third gate structure 44 is located between the seventh connecting line 42 and the eighth connecting line 43. It should be noted that the first gate structure 16, the second gate structure 35, and the third gate structure 44 can be formed simultaneously in the same process, which simplifies the process and reduces manufacturing costs.

[0168] In some embodiments of this disclosure, the specific process of forming the first gate structure 16, the second gate structure 35, and the third gate structure 44 is as follows:

[0169] like Figure 10 As shown, a gate oxide layer 60 can be formed on each conductive part through an in-situ water vapor oxidation process, such as... Figure 11 As shown, a gate material layer 70 and a second photoresist layer are sequentially formed on the surface of the structure jointly formed by the gate oxide layer 60 and the trench isolation structure 401. The second photoresist layer is exposed and developed to form a plurality of photoresist portions 80. A photoresist portion 80 is formed above each first conductive portion 11, a photoresist portion 80 is formed above each third conductive portion 31, and a photoresist portion 80 is formed above each fourth conductive portion 41, as shown. Figure 12 As shown, the gate material layer 70 and the gate oxide layer 60 can be etched using each photoresist portion 80 as a mask to form a first gate structure 16 on the first conductive portion 11, a second gate structure 35 on the third conductive portion 31, and a third gate structure 44 on the fourth conductive portion 41, exposing the areas on each conductive portion outside the gate structures. It should be noted that the photoresist portions 80 can be removed after forming the gate structures. The structure after removing the photoresist portions 80 is as follows... Figure 9 As shown.

[0170] In some embodiments of this disclosure, such as Figure 13 As shown, a conformal covering substrate 10, trench isolation structure 401, and insulating isolation layer 6 for each gate structure can be formed. The insulating isolation layer 6 can provide insulation protection for the sidewalls of each gate structure and the surface of the substrate 10. The insulating isolation layer 6 can be a composite film structure composed of a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer conformally covers the surface of the substrate 10, trench isolation structure 401, and each gate structure, and the silicon nitride layer is located on the surface of the silicon oxide layer.

[0171] like Figure 14As shown, a second photoresist layer 7 can be formed on the surface of the insulating isolation layer 6, and the second photoresist layer 7 can be exposed and developed to form a first developing region 71, a second developing region 72, a third developing region 73, and a fourth developing region 74. The orthographic projections of the first developing region 71 and the second developing region 72 on the substrate 10 are both located on the first conductive portion 11, and the orthographic projections of the first developing region 71 and the second developing region 72 on the substrate 10 are respectively located on both sides of the first gate structure 16; the orthographic projection of the third developing region 73 on the substrate 10 is located on the second conductive portion 21; and the orthographic projection of the fourth developing region 74 on the substrate 10 is located on the third conductive portion 31 and is located on one side of the second gate structure 35.

[0172] like Figure 15 As shown, the second photoresist layer 7, which has a first developing region 71, a second developing region 72, a third developing region 73, and a fourth developing region 74, can be used as a mask to etch the insulating isolation layer 6. This forms a first opening 61 and a second opening 62 on both sides of the first gate structure 16, exposing the first conductive portion 11, a third opening 63 exposing the second conductive portion 21, and a fourth opening 64 on one side of the second gate structure 35, exposing the third conductive portion 31. It should be noted that the second photoresist layer 7 can be removed after forming the first opening 61, the second opening 62, the third opening 63, and the fourth opening 64.

[0173] In step S530, the first contact layer 12 and the second contact layer 13 are formed on the surface of the first conductive part 11, the third contact layer 22 is formed on the surface of the second conductive part 21, and the fourth contact layer 32 is formed on the surface of the third conductive part 31.

[0174] For example, contact materials can be deposited simultaneously in the first opening 61, the second opening 62, the third opening 63, and the fourth opening 64 in the same process, thereby forming a first contact layer 12 in the first opening 61, a second contact layer 13 in the second opening 62, a third contact layer 22 in the third opening 63, and a fourth contact layer 32 in the fourth opening 64. The contact material can be a metal silicide, for example, cobalt silicide. In the embodiments of this disclosure, the structure after step S530 is as follows: Figure 16 As shown.

[0175] In step S540, an insulating layer 5 is formed on the side of the first contact layer 12, the second contact layer 13, the third contact layer 22, the fourth contact layer 32, and the fourth conductive portion 41 away from the substrate 10.

[0176] like Figure 17As shown, the insulating layer 5 can be a single-layer film structure or a composite film structure composed of multiple film layers, without any special limitation. The material of the insulating layer 5 may include one or more of silicon nitride, silicon oxide, carbon, and silicon oxynitride. Taking the insulating layer 5 as a composite film structure as an example, it may include a silicon nitride layer, a silicon oxide layer, and a carbon film layer, etc.

[0177] An insulating layer 5 can be formed on the side of the first contact layer 12, the second contact layer 13, the third contact layer 22, the fourth contact layer 32, and the fourth conductive portion 41 away from the substrate 10 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the insulating layer 5 can also be formed by other means, and no special limitation is made here. It should be noted that the insulating layer 5 can not only cover the insulating isolation layer 6, the first contact layer 12, the second contact layer 13, the third contact layer 22, and the fourth contact layer 32, but also fill the gap between each gate structure and other surrounding structures.

[0178] In step S550, the insulating layer 5 is etched to form a first through hole, a second through hole, a third through hole, a fourth through hole, a fifth through hole 51, a sixth through hole 52, a seventh through hole, and an eighth through hole. The first through hole and the second through hole expose the first contact layer 12 and the second contact layer 13, respectively. The third through hole exposes the first end of the third contact layer 22, and the fourth through hole exposes the second end of the third contact layer 22. The sixth through hole 52 exposes the fourth contact layer 32, and the fifth through hole 51 exposes the end of the third conductive portion 31 that is away from the fourth contact layer 32. The seventh through hole and the eighth through hole expose the two ends of the fourth conductive portion 41, respectively.

[0179] Please continue reading Figure 17 As shown, a third photoresist layer 8 can be formed on the surface of the insulating layer 5. The third photoresist layer 8 can be exposed and developed to form a plurality of mask openings 81. The orthographic projection of each mask opening 81 on the substrate 10 is located on the conductive part, and each conductive part has two orthographic projections of mask openings 81.

[0180] The third photoresist layer 8, having a mask opening 81, can be etched onto the insulating layer 5 to form a first through-hole exposing the first contact layer 12, a second through-hole exposing the second contact layer 13, a third through-hole and a fourth through-hole exposing the two end surfaces of the third contact layer 22 respectively, and a sixth through-hole 52 exposing the fourth contact layer 32. For example... Figure 18As shown, when the end of the third conductive portion 31 away from the fourth contact layer 32 and the surface of the fourth conductive portion 41 are still covered with the insulating isolation layer 6, the insulating isolation layer 6 can also be etched simultaneously to form a fifth through hole 51 exposing the surface of the end of the third conductive portion 31 away from the fourth contact layer 32, and a seventh through hole and an eighth through hole exposing the surfaces of the two ends of the fourth conductive portion 41 respectively. After forming the first through hole, the second through hole, the third through hole, the fourth through hole, the fifth through hole 51, the sixth through hole 52, the seventh through hole, and the eighth through hole, the third photoresist layer 8 can be removed to expose the surface of the insulating layer 5.

[0181] Step S560: A first connecting line 14 that at least fills the first through hole, a second connecting line 15 that at least fills the second through hole, a third connecting line 23 that at least fills the third through hole, a fourth connecting line 24 that at least fills the fourth through hole, a fifth connecting line 33 that at least fills the fifth through hole 51, a sixth connecting line 34 that at least fills the sixth through hole 52, a seventh connecting line 42 that at least fills the seventh through hole, and an eighth connecting line 43 that at least fills the eighth through hole.

[0182] like Figures 19-23 As shown, a conductive layer 9 can be formed on the surface of the insulating layer 5 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The conductive layer 9 can cover the entire surface of the insulating layer 5 and fill the first through-hole, the second through-hole, the third through-hole, the fourth through-hole, the fifth through-hole 51, the sixth through-hole 52, the seventh through-hole, and the eighth through-hole. Figure 24 As shown, a fourth photoresist layer 90 can be formed on the conductive layer 9, and the fourth photoresist layer 90 can be exposed and developed to form a developing area, such as... Figure 25 As shown, the fourth photoresist layer 90, after development, can be used as a mask to etch the conductive layer 9, thereby forming the first connecting line 14, the second connecting line 15, the third connecting line 23, the fourth connecting line 24, the fifth connecting line 33, the sixth connecting line 34, the seventh connecting line 42, and the eighth connecting line 43. The material of the conductive layer 9 can be a material with good conductivity, such as titanium nitride, tungsten, or gold.

[0183] In one exemplary embodiment of this disclosure, please continue to refer to Figure 25As shown, during the formation of each connecting line, the following pads can also be formed simultaneously: a first pad 17 connected to the end of the first connecting line 14 away from the first conductive part 11; a second pad 18 connected to the end of the second connecting line 15 away from the first conductive part 11; a third pad 25 connected to the end of the third connecting line 23 away from the second conductive part 21; a fourth pad 26 connected to the end of the fourth connecting line 24 away from the second conductive part 21; a fifth pad 36 connected to the end of the fifth connecting line 33 away from the third conductive part 31; a sixth pad 37 connected to the end of the sixth connecting line 34 away from the third conductive part 31; a seventh pad 45 connected to the end of the seventh connecting line 42 away from the fourth conductive part 41; and an eighth pad 46 connected to the end of the eighth connecting line 43 away from the fourth conductive part 41. The width of each pad is greater than the width of each connecting line. During testing, voltage can be applied to each pad to reduce the difficulty of aligning the probe with the test structure during testing. It should be noted that after forming each connection line and each pad, the fourth photoresist layer 90 can be removed to expose the top of each connection line.

[0184] In one exemplary embodiment of this disclosure, the method for fabricating the semiconductor test structure of this disclosure may further include:

[0185] In step S570, after forming the first connecting line 14, the second connecting line 15, the third connecting line 23, the fourth connecting line 24, the fifth connecting line 33, the sixth connecting line 34, the seventh connecting line 42, and the eighth connecting line 43, the insulating layer 5 is removed.

[0186] The insulating layer 5 can be removed by an etching process, for example, by a wet etching process. The etching solution for wet etching can be set according to the specific material of the insulating layer 5, as long as it can remove the insulating layer 5 without damaging (or only slightly damaging) other surrounding structures. No specific limitations are placed on the etching solution here. In this disclosure, the structure after removing the insulating layer 5 is as follows: Figure 1 As shown.

[0187] When there are multiple first conductive parts 11, second conductive parts 21, third conductive parts 31, and fourth conductive parts 41 in this disclosure, in two adjacent first conductive parts 11, the second connecting line 15 corresponding to the preceding first conductive part 11 is connected to the first connecting line 14 corresponding to the following first conductive part 11, thereby forming a first test structure 1 composed of multiple first conductive parts 11 connected in series; in two adjacent second conductive parts 21, the fourth connecting line 24 corresponding to the preceding second conductive part 21 is connected to the third connecting line 23 corresponding to the following second conductive part 21, thereby forming a first test structure 1 composed of multiple first conductive parts 11 connected in series. A second test structure 2 is formed by connecting multiple second conductive parts 21 in series; in two adjacent third conductive parts 31, the sixth connecting line 34 corresponding to the first third conductive part 31 is connected to the fifth connecting line 33 corresponding to the second third conductive part 31, thereby forming a third test structure 3 composed of multiple third conductive parts 31 connected in series; in two adjacent fourth conductive parts 41, the eighth connecting line 43 corresponding to the first fourth conductive part 41 is connected to the seventh connecting line 42 corresponding to the second fourth conductive part 41, thereby forming a fourth test structure 4 composed of multiple fourth conductive parts 41 connected in series. It should be noted that when there are multiple conductive parts, each pad can be connected to the connecting lines of the two outermost conductive parts in the multiple series-connected conductive parts that are not connected to other connecting lines respectively.

[0188] The fabrication process of the semiconductor test structure disclosed herein is basically the same as that of conventional semiconductor devices. The semiconductor test structure disclosed herein can be fabricated simultaneously during the fabrication of semiconductor devices, thereby obtaining the semiconductor test structure disclosed herein without increasing the process cost.

[0189] It should be noted that although the steps of the semiconductor test structure fabrication method and semiconductor parameter testing method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0190] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor testing structure, characterized in that, include: The first test structure includes a first conductive part, a first contact layer, a second contact layer, a first connecting line, and a second connecting line. The first contact layer and the second contact layer are spaced apart on the surface of the first conductive part. The first connecting line is connected to the first contact layer, and the second connecting line is connected to the second contact layer. The second test structure includes a second conductive portion, a third contact layer, a third connecting line, and a fourth connecting line. The third contact layer covers the surface of the second conductive portion, and the resistance of the third contact layer is less than the resistance of the second conductive portion. The third contact layer includes a first end and a second end. The third connecting line is connected to the first end, and the fourth connecting line is connected to the second end. The resistance of the first connecting line is equal to the resistance of the third connecting line, and the resistance of the second connecting line is equal to the resistance of the fourth connecting line. The sum of the resistances of the first contact layer and the second contact layer is equal to the resistance of the third contact layer.

2. The semiconductor test structure according to claim 1, characterized in that, The semiconductor testing structure also includes: The third test structure includes a third conductive part, a fourth contact layer, a fifth connecting line, and a sixth connecting line. The fourth contact layer is located on the surface of one end of the third conductive part. The sixth connecting line is connected to the fourth contact layer. The fifth connecting line is connected to the end of the third conductive part away from the fourth contact layer. The resistance of the third conductive part is equal to the resistance of the first conductive part. The resistance of the fifth connecting line is equal to the resistance of the first connecting line. The resistance of the sixth connecting line is equal to the resistance of the second connecting line. The resistance of the fourth contact layer is equal to the resistance of the second contact layer.

3. The semiconductor test structure according to claim 2, characterized in that, The semiconductor testing structure also includes: The fourth test structure includes a fourth conductive part, a seventh connecting line, and an eighth connecting line. The seventh connecting line and the eighth connecting line are respectively connected to two ends of the fourth conductive part. The resistance of the fourth conductive part is equal to the resistance of the first conductive part, the resistance of the seventh connecting line is equal to the resistance of the first connecting line, and the resistance of the eighth connecting line is equal to the resistance of the second connecting line.

4. The semiconductor test structure according to claim 3, characterized in that, The first conductive portion, the second conductive portion, the third conductive portion, and the fourth conductive portion are all ion-doped regions, and the materials of the first contact layer, the second contact layer, the third contact layer, and the fourth contact layer are all metal silicides.

5. The semiconductor test structure according to claim 4, characterized in that, The semiconductor testing structure also includes: A first gate structure is disposed on the first conductive portion and located between the first contact layer and the second contact layer; The second gate structure is disposed on the third conductive portion and located between the fourth contact layer and the sixth connection line; A third gate structure is disposed on the fourth conductive portion and located between the seventh connecting line and the eighth connecting line.

6. A method for testing semiconductor parameters, characterized in that, The contact resistance between the first conductive portion and the first contact layer and the second contact layer is determined using the semiconductor test structure according to any one of claims 1-5.

7. The method for testing semiconductor parameters according to claim 6, characterized in that, The testing method includes: Test the resistance of the first conductive part; A first voltage is applied to the first connecting line and the third connecting line respectively, and a second voltage is applied to the second connecting line and the fourth connecting line respectively; The first current value flowing within the first test structure and the second current value flowing within the second test structure are detected. The total resistance of the first test structure is determined based on the first voltage, the second voltage, and the first current value. The total resistance of the second test structure is determined based on the first voltage, the second voltage, and the second current value. The contact resistance between the first conductive part and the first contact layer and the second contact layer is determined based on the total resistance of the first test structure, the total resistance of the second test structure, and the resistance of the first conductive part.

8. The method for testing semiconductor parameters according to claim 6, characterized in that, When the semiconductor test structure includes a third test structure, the test method further includes: A first voltage is applied to the first connecting line and the fifth connecting line respectively, and a second voltage is applied to the second connecting line and the sixth connecting line respectively; The first current value flowing within the first test structure and the third current value flowing within the third test structure are detected. The total resistance of the first test structure is determined based on the first voltage, the second voltage, and the first current value. The total resistance of the third test structure is determined based on the first voltage, the second voltage, and the third current value. Compare the total resistance of the first test structure with the total resistance of the third test structure.

9. The method for testing semiconductor parameters according to claim 8, characterized in that, When the semiconductor test structure includes a fourth test structure, the test method further includes: A first voltage is applied to the seventh connection line, and a second voltage is applied to the eighth connection line; The value of the fourth current flowing within the fourth test structure is detected; The total resistance of the fourth test structure is determined based on the first voltage, the second voltage, and the fourth current value. Compare the total resistance of the fourth test structure with the total resistance of the first test structure; Compare the total resistance of the fourth test structure with the total resistance of the third test structure.

10. A method for fabricating a semiconductor test structure, characterized in that, include: A first test structure is formed, the first test structure includes a first conductive part, a first contact layer, a second contact layer, a first connecting line and a second connecting line, the first contact layer and the second contact layer are distributed at intervals on the surface of the first conductive part, the first connecting line is connected to the first contact layer, and the second connecting line is connected to the second contact layer; A second test structure is formed, comprising a second conductive portion, a third contact layer, a third connecting line, and a fourth connecting line. The third contact layer covers the surface of the second conductive portion, and the resistance of the third contact layer is less than the resistance of the second conductive portion. The third contact layer includes a first end and a second end. The third connecting line is connected to the first end, and the fourth connecting line is connected to the second end. The resistance of the first connecting line is equal to the resistance of the third connecting line, and the resistance of the second connecting line is equal to the resistance of the fourth connecting line. The sum of the resistances of the first contact layer and the second contact layer is equal to the resistance of the third contact layer.

11. The method for fabricating a semiconductor test structure according to claim 10, characterized in that, The manufacturing method further includes: A third test structure is formed, comprising a third conductive portion, a fourth contact layer, a fifth connecting line, and a sixth connecting line. The fourth contact layer is located on the surface of one end of the third conductive portion. The sixth connecting line is connected to the fourth contact layer, and the fifth connecting line is connected to the end of the third conductive portion away from the fourth contact layer. The resistance of the third conductive portion is equal to the resistance of the first conductive portion, the resistance of the fifth connecting line is equal to the resistance of the first connecting line, and the resistance of the sixth connecting line is equal to the resistance of the second connecting line.

12. The method for fabricating a semiconductor test structure according to claim 11, characterized in that, The manufacturing method further includes: A fourth test structure is formed, comprising a fourth conductive part, a seventh connecting line, and an eighth connecting line. The seventh connecting line and the eighth connecting line are respectively connected to two ends of the fourth conductive part. The resistance of the fourth conductive part is equal to the resistance of the first conductive part, the resistance of the seventh connecting line is equal to the resistance of the first connecting line, and the resistance of the eighth connecting line is equal to the resistance of the second connecting line.

13. The method for fabricating a semiconductor test structure according to claim 12, characterized in that, The formation of the first test structure, the second test structure, the third test structure, and the fourth test structure includes: Multiple doped portions are formed on the substrate in an array; The portion to be doped is ion-doped to form a conductive portion; the conductive portion located in the first row is designated as the first conductive portion, the conductive portion located in the second row is designated as the second conductive portion, the conductive portion located in the third row is designated as the third conductive portion, and the conductive portion located in the fourth row is designated as the fourth conductive portion. The first contact layer and the second contact layer are formed on the surface of the first conductive portion, the third contact layer is formed on the surface of the second conductive portion, and the fourth contact layer is formed on the surface of the third conductive portion; An insulating layer is formed on the side of the first contact layer, the second contact layer, the third contact layer, the fourth contact layer, and the fourth conductive portion away from the substrate; The insulating layer is etched to form a first through-hole, a second through-hole, a third through-hole, a fourth through-hole, a fifth through-hole, a sixth through-hole, a seventh through-hole, and an eighth through-hole. The first and second through-holes expose the first and second contact layers, respectively. The third through-hole exposes a first end of the third contact layer, and the fourth through-hole exposes a second end of the third contact layer. The sixth through-hole exposes the fourth contact layer, and the fifth through-hole exposes the end of the third conductive portion away from the fourth contact layer. The seventh and eighth through-holes expose two ends of the fourth conductive portion, respectively. A first connecting line that at least fills the first through hole, a second connecting line that at least fills the second through hole, a third connecting line that at least fills the third through hole, a fourth connecting line that at least fills the fourth through hole, a fifth connecting line that at least fills the fifth through hole, a sixth connecting line that at least fills the sixth through hole, a seventh connecting line that at least fills the seventh through hole, and an eighth connecting line that at least fills the eighth through hole are formed.

14. The method for fabricating a semiconductor test structure according to claim 13, characterized in that, Before forming the first contact layer, the second contact layer, the third contact layer, and the fourth contact layer, the manufacturing method further includes: A first gate structure is formed on the first conductive portion, and the first gate structure is located between the first contact layer and the second contact layer; A second gate structure is formed on the third conductive portion, and the second gate structure is located between the fourth contact layer and the sixth connection line; A third gate structure is formed on the fourth conductive portion, and the third gate structure is located between the seventh connecting line and the eighth connecting line.

15. The method for fabricating a semiconductor test structure according to claim 13, characterized in that, The manufacturing method further includes: After forming the first connecting line, the second connecting line, the third connecting line, the fourth connecting line, the fifth connecting line, the sixth connecting line, the seventh connecting line, and the eighth connecting line, the insulating layer is removed.

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