Method for manufacturing semiconductor device and semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device and a semiconductor device, belonging to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, forming a plurality of shallow trench isolation structures in the substrate; forming a plurality of first gate structures on the substrate, forming two second gate structures spaced apart on the shallow trench isolation structures; forming a protective layer on the first gate structure, the second gate structure, the substrate and the shallow trench isolation structure; etching the first gate structure and part of the protective layer on the substrate; then removing the protective layer on the first gate structure and the substrate, and simultaneously removing part of the protective layer on the second gate structure and the shallow trench isolation structure; forming sigma trenches and strain structures in the substrate on both sides of the first gate structure; removing the protective layer, and sequentially forming a contact hole etching stop layer and an interlayer dielectric layer on the substrate. The manufacturing method and semiconductor device provided by the present invention can improve the yield and performance of semiconductor devices.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] As semiconductor devices continue to shrink, the performance requirements for them become increasingly stringent. In 28nm technology, the source and drain of a PMOS transistor are formed by a combination of dry and wet etching to form a sigma trench. Strained material is then deposited within the sigma trench. Because the lattice constant of the strained material is greater than that of silicon, it creates compressive stress in the lateral channel of the PMOS transistor, thereby improving device performance.

[0003] Static random-access memory (SRAM) boasts advantages such as high speed, low power consumption, and high durability. However, in SRAM, when the source and drain regions of the PMOS transistors are exposed and developed, the connecting gates on the shallow trench isolation structures between the PMOS transistors are also simultaneously opened. This increases the aspect ratio between the connecting gates above the shallow trench isolation structures. This excessive aspect ratio can lead to voids when filling the interlayer dielectric layer. These voids can cause short circuits between adjacent connecting gates during subsequent metal filling, hindering contact hole etching, resulting in device defects and reducing yield. Summary of the Invention

[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device. Through the method for manufacturing a semiconductor device and the semiconductor device provided by the present invention, it is possible to avoid the formation of voids in the interlayer dielectric layer, avoid short circuits between adjacent gates, and improve the yield and performance of the semiconductor device.

[0005] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] Providing a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate;

[0007] A plurality of first gate structures are formed on the substrate, and two second gate structures are formed on the shallow trench isolation structure between adjacent first gate structures.

[0008] forming a protective layer on the first gate structure, the second gate structure, the substrate and the shallow trench isolation structure;

[0009] Etching the first gate structure and a portion of the protective layer on the substrate;

[0010] Etching and removing the first gate structure and the protective layer on the substrate, and simultaneously removing a portion of the protective layer on the second gate structure and the shallow trench isolation structure;

[0011] forming sigma trenches in the substrate on both sides of the first gate structure;

[0012] forming a strained structure in the sigma trench; and

[0013] The protective layer is removed, and a contact hole etching stop layer and an interlayer dielectric layer are sequentially formed on the substrate.

[0014] In one embodiment of the present invention, the manufacturing method further includes:

[0015] forming a photoresist on the protective layer, and forming a patterned photoresist layer through exposure and development processes, wherein an edge of the patterned photoresist layer is aligned with an edge of the shallow trench isolation structure where the second gate structure is located;

[0016] Using the patterned photoresist layer as a mask, etching the first gate structure and the portion of the protective layer on the substrate;

[0017] removing the patterned photoresist layer; and

[0018] The first gate structure and the protection layer on the substrate are removed by etching.

[0019] In one embodiment of the present invention, when etching the first gate structure and the portion of the protective layer on the substrate, the removed thickness of the protective layer is one third to one half of the total thickness of the protective layer.

[0020] In one embodiment of the present invention, the polarity of the photoresist is opposite to that of the photoresist used when forming the shallow trench isolation structure, and the photoresist on the protective layer is exposed and developed using the optical mask used when forming the shallow trench isolation structure.

[0021] In one embodiment of the present invention, the protective layer is removed by dry etching.

[0022] In one embodiment of the present invention, the protective layer is a silicon nitride layer, and the thickness of the protective layer is 15 nm to 20 nm.

[0023] In one embodiment of the present invention, the remaining thickness of the protection layer on the second gate structure and the shallow trench isolation structure is one third to one half of the total thickness of the protection layer.

[0024] In one embodiment of the present invention, the sigma trench is formed by combining dry etching and wet etching.

[0025] In one embodiment of the present invention, before forming the strained structure, the substrate is cleaned, and the cleaning includes cleaning with hydrofluoric acid.

[0026] The present invention further provides a semiconductor device obtained by the above-mentioned manufacturing method, comprising:

[0027] a substrate, wherein the substrate includes a plurality of shallow trench isolation structures;

[0028] a plurality of first gate structures disposed in the substrate;

[0029] Two second gate structures are spaced apart on the shallow trench isolation structure between adjacent first gate structures;

[0030] a strained structure disposed in the sigma trench in the substrate on both sides of the first gate structure; and

[0031] a contact hole etching stop layer, disposed on the substrate; and

[0032] The interlayer dielectric layer is arranged on the contact hole etching stop layer.

[0033] In summary, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device. By improving the method for manufacturing a semiconductor device, the present invention can leave a protective layer on the shallow trench isolation structure, avoid the shallow trench isolation structure from being damaged when forming a sigma trench, prevent the filling depth-to-width ratio between the two second gate structures from becoming higher due to the etching of the shallow trench isolation structure, avoid the subsequent interlayer dielectric layer from forming a cavity due to the excessive depth-to-width ratio at this location, avoid short circuits between adjacent gates, and improve the yield of the semiconductor device. By forming a protective layer, the shallow trench isolation structure is protected during the etching and cleaning process, and no new photoresist is introduced when etching the protective layer on the shallow trench isolation structure. The performance of the PMOS transistor can be improved while reducing the size of the PMOS transistor, thereby improving the performance of the static random access memory. When etching the protective layer, by using a negative photoresist, the development of an optical mask can be avoided, one optical mask can be reduced, production costs can be reduced, and the self-alignment of the patterned photoresist layer can be improved.

[0034] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 FIG. 1 is a schematic diagram of a static random access memory array according to an embodiment of the present invention.

[0037] Figure 2 For the Figure 1 A cross-sectional view after the gate structure is formed in the AA direction.

[0038] Figure 3 For the Figure 1 A cross-sectional view of the protective layer and the patterned photoresist layer formed along the AA direction.

[0039] Figure 4 For the Figure 1 A cross-sectional view of the substrate and a portion of the protective layer on the first gate structure after removal of the protective layer in the AA direction.

[0040] Figure 5 For the Figure 1 Cross-sectional view after removing the patterned photoresist layer in the AA direction.

[0041] Figure 6 For the Figure 1 A cross-sectional view of the substrate and the first gate structure after removing the protective layer in the AA direction.

[0042] Figure 7 For the Figure 1 Cross-sectional view of the sigma groove formed in the AA direction.

[0043] Figure 8 For the Figure 1 The AA direction forms a cross-sectional view of the strained structure.

[0044] Figure 9 For the Figure 1 A cross-sectional view after removing the shallow trench isolation structure, the sidewall structure and the protective layer on the second gate structure in the AA direction.

[0045] Figure 10 For the Figure 1 A cross-sectional view after forming the contact hole etching stop layer and the interlayer dielectric layer in the AA direction.

[0046] Description of labels:

[0047] 10. Substrate; 11. Shallow trench isolation structure; 12. Gate dielectric layer; 13. Gate material layer; 14. First hard mask layer; 15. Second hard mask layer; 16. Sidewall structure; 17. Protective layer; 18. Patterned photoresist layer; 19. Sigma trench; 20. Strain structure; 21. Contact hole etch stop layer; 22. Interlayer dielectric layer; 101. First gate structure; 102. Second gate structure; 100. Source line; 200. Active area. DETAILED DESCRIPTION

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] In the description of this specification, it should be understood that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "front," "back," "left," and "right" are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this solution and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific direction, be constructed, or operate in a specific direction. Therefore, they should not be construed as limitations on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] See also Figure 1 As shown, in one embodiment of the present invention, a static random access memory array is primarily composed of a plurality of static random access memory cells. Each memory cell includes six transistors, including two driver transistors PD, two load transistors PU, and two pass transistors PG. The two load transistors PU are PMOS transistors, and the two driver transistors PD are NMOS transistors, thereby forming a flip-flop circuit of two cross-latched CMOS inverters, allowing the memory cell to have two stable states, representing "0" and "1." The two pass transistors PG are NMOS transistors, used to control access to the memory cell during read and write operations. The load transistors are transistors that are pulled to the power line Vcc or the ground line Vss. The memory operates by pulling the two load transistors to the power line Vcc.

[0052] See also Figure 1As shown, in one embodiment of the present invention, a plurality of shallow trench isolation structures 11 are provided in the substrate 10. The plurality of shallow trench isolation structures 11 divide the substrate 10 into a plurality of active areas 200. Transistors are provided on the active areas 200, and different transistors share a source line 100. In this embodiment, the driving transistor PD and the load transistor PU share the same source line 100, and a connecting gate is provided on the shallow trench isolation structure 11 between the load transistors PU between adjacent units for forming a shared contact hole (Shared Contact, SCT) later. In this application, Figure 1 Taking the cross-sectional view along the AA direction in FIG as an example, the manufacturing method of the semiconductor device is described.

[0053] See also Figures 1 to 2 As shown, in one embodiment of the present invention, a substrate 10 is first provided. Substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, a silicon wafer, or other semiconductor materials formed from III / V compounds, including stacked structures composed of these semiconductor materials, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SiOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, substrate 10 is, for example, a silicon wafer semiconductor substrate, and substrate 10 is, for example, a P-type substrate. Different types of ions are implanted into substrate 10 to cause different active regions 200 to exhibit different electrical properties. For example, the active region 200 where the driver transistor PD and the pass transistor PG are located is P-type doped, while the active region 200 where the load transistor PU is located is N-type doped. A plurality of shallow trench isolation structures 11 are formed in the substrate 10. The shallow trench isolation structures 11 are obtained by etching the substrate 10 to form shallow trenches and depositing insulating material in the shallow trenches. The insulating material in the shallow trench isolation structures 11 is, for example, silicon oxide.

[0054] See also Figures 1 to 2As shown, in one embodiment of the present invention, a first gate structure 101 is formed on a substrate 10 for forming a load transistor PU. A second gate structure 102 is formed on a shallow trench isolation structure 11 between the load transistors PU of adjacent memory cells to serve as a connecting gate. The gate structure includes a gate dielectric layer 12, a gate material layer 13, a first hard mask layer 14, a second hard mask layer 15, and a sidewall structure 16. The gate dielectric layer 12 is disposed on the substrate 10 and the shallow trench isolation structure 11. The gate dielectric layer 12 is, for example, a silicon oxide layer or a high-k dielectric constant layer. The gate dielectric layer 12 is formed, for example, by in-situ water vapor growth or chemical vapor deposition. The thickness of the gate dielectric layer 12 is, for example, 8Å to 50Å, or, for example, 8Å to 15Å. The gate material layer 13 is disposed on the gate dielectric layer 12. The gate material layer 13 is, for example, polysilicon or a metal layer. The thickness of the gate material layer 13 is, for example, 50nm to 200nm, and is selected based on the requirements of the semiconductor device. A first hard mask layer 14 is disposed on the gate material layer 13. The first hard mask layer 14 is, for example, a silicon nitride layer, and has a thickness of, for example, 10 nm to 20 nm. A second hard mask layer 15 is disposed on the first hard mask layer 14. The second hard mask layer 15 is, for example, a silicon oxide layer, and has a thickness of, for example, 10 nm to 20 nm. During the fabrication process, the first and second hard mask layers 14 and 15 protect the integrity of the gate material layer 13, thereby improving the performance of the semiconductor device. Spacer structures 16 are disposed on both sides of the gate material layer 13. The spacer structures 16 are, for example, silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride. The top of the spacer structures 16 is flush with the surface of the second hard mask layer 15. The spacer structures 16 are, for example, arc-shaped. In other embodiments, the spacer structures 16 may also have other shapes and structures.

[0055] See also Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the gate structure, a protective layer 17 is formed on the substrate 10, the shallow trench isolation structure 11, and the gate structure. The protective layer 17 is, for example, a silicon nitride layer, and has a thickness of, for example, 15 nm to 20 nm. It can be formed, for example, by low-pressure chemical vapor deposition (LPCVD). Specifically, for example, the substrate 10 with the gate structure is placed in a furnace tube filled with dichlorosilane and ammonia, and the reaction is carried out at a pressure of, for example, 2T to 10T and a temperature of, for example, 700°C to 900°C to deposit the protective layer 17. The thickness of the protective layer 17 can be adjusted by controlling the heating time. In other embodiments, the protective layer 17 can be formed by other methods.

[0056] See also Figure 3As shown, in one embodiment of the present invention, after forming the protective layer 17, a photoresist layer is formed on the protective layer 17, and a patterned photoresist layer 18 is formed through processes such as exposure and development. The photoresist layer has an opposite polarity to the photoresist used when forming the shallow trench isolation structure. In this embodiment, the photoresist layer is, for example, a negative photoresist. During the exposure process, the optical mask used when forming the active area is used for exposure and development, and the photoresist layer of the shallow trench isolation structure 11 is retained to form a patterned photoresist layer 18. The patterned photoresist layer 18 covers the second gate structure 102 and the shallow trench isolation structure 11 where the second gate structure 102 is located. The edge of the patterned photoresist layer 18 is aligned with the edge of the shallow trench isolation structure 11 where the second gate structure 102 is located. By using a negative photoresist, the development of an optical mask can be avoided, one optical mask can be reduced, production costs can be reduced, and the self-alignment of the patterned photoresist layer 18 can be improved.

[0057] See also Figures 3 to 5 As shown, in one embodiment of the present invention, after forming a patterned photoresist layer 18, dry etching is performed using the patterned photoresist layer 18 as a mask to remove a portion of the protective layer 17 on the first gate structure 101 and the substrate 10. During the etching process, the etching gas, for example, includes one or a mixture of trifluoromethane (CHF3), difluoromethane (CH2F2), carbon tetrafluoride (CF4), or sulfur hexafluoride (SF6), or a mixture of at least one of these and oxygen. Through dry etching, the amount of protective layer 17 removed is accurately controlled. In this embodiment, the thickness of the protective layer 17 removed from the first gate structure 101 and the substrate 10 is, for example, one-third to one-half of the total thickness of the protective layer 17. After etching the portion of the protective layer, the patterned photoresist layer 18 is removed by wet etching or ashing.

[0058] See also Figures 5 and 6As shown, in one embodiment of the present invention, after removing the patterned photoresist layer 18, the protective layer 17 on the substrate 10 and the first gate structure 101 is removed, for example, by dry etching. After removing the protective layer 17 on the substrate 10, the remaining thickness of the protective layer 17 on the second gate structure 102 and the shallow trench isolation structure 11 is, for example, one-third to one-half of the total thickness of the protective layer 17. During the etching process, the etching gas includes, for example, one or a mixture of trifluoromethane, difluoromethane, carbon tetrafluoride, or sulfur hexafluoride, or a mixture of at least one of these and oxygen. During the etching process, the protective layer on the first gate structure 101 and the substrate 10 can be removed, and a portion of the protective layer 17 on the outer side of the sidewall structure 16 of the first gate structure 101 can be retained. When forming the sigma trench, the sidewall structure, the top and both sides of the second gate structure 102, and the remaining portion of the protective layer 17 on the shallow trench isolation structure 11 can be protected. In subsequent processes, the shallow trench isolation structure 11 can be prevented from being damaged, and the interlayer dielectric layer formed subsequently can be prevented from forming voids due to the excessive aspect ratio at this location, thereby preventing short circuits between adjacent gates and improving the yield of semiconductor devices. By first etching the protective layer on the first gate structure 101 and the substrate 10, the protective layer 17 on the shallow trench isolation structure 11 area is made higher than the protective layer 17 on the substrate 10, thereby preventing the filling aspect ratio between the two second gate structures 102 from being increased due to the etching of the shallow trench isolation structure 11. By forming a protective layer, and removing the protective layer on the substrate 10 through two etchings, the protective layer 17 on the substrate 10 and the first gate structure 101 is partially removed through the first etching. During the second etching, it can be ensured that the protective layer on the substrate 10 is completely removed. At the same time, the protective layer of the remaining part of the shallow trench isolation structure 11 protects the shallow trench isolation structure 11 during the subsequent etching and cleaning processes. At the same time, when etching the protective layer on the shallow trench isolation structure 11, no new photoresist is introduced.

[0059] See also Figures 6 and 7 As shown, in one embodiment of the present invention, after removing the protective layer 17 on the substrate 10, the substrate 10 on both sides of the first gate structure 101 is etched to form a sigma trench 19. Specifically, by dry etching, U-shaped preliminary trenches (not shown in the figure) are formed in the substrate 10 on both sides of the first gate structure 101, and then the preliminary trenches are wet etched to widen the preliminary trenches to form the sigma trenches 19. The etching gas for dry etching is, for example, carbon tetrafluoride, sulfur hexafluoride, or chlorine, or a mixture of at least one of carbon tetrafluoride, sulfur hexafluoride, or chlorine and oxygen, and the wet etching liquid is, for example, tetramethylammonium hydroxide (C4H 13NO), etc. By combining dry etching and wet etching and controlling the etching amount of dry etching and wet etching, the depth, shape, and tilt angle of the formed sigma trench 19 are controlled. In this embodiment, the sigma trench 19 is, for example, a regular pentagon with one side open. After etching, the substrate 10 is cleaned to remove etching byproducts and the natural oxide layer within the sigma trench 19. Specifically, the substrate 10 is first treated with ozone for 20s to 40s, then treated with dilute hydrofluoric acid for 10s to 30s, where the volume fraction of dilute hydrofluoric acid is, for example, 5% to 15%, then treated with an ammonium peroxide mixture (APM) solution for 20s to 40s, then treated with a nano-ammonium peroxide mixture (NANO APM) solution for 20s to 40s, then treated with a mixture of hydrochloric acid and hydrogen peroxide (HPM) for 10s to 30s, and finally cleaned with SiCoNi. During the etching and cleaning process, since there is a protective layer 17 on the shallow trench isolation structure 11 between the second gate structures 102, the shallow trench isolation structure 11 can be avoided from being etched during the etching process, thereby avoiding subsequent depressions caused by a large depth-to-width ratio.

[0060] See also Figures 7 and 8 As shown, in one embodiment of the present invention, after forming a sigma trench 19, a silicon-germanium material is epitaxially grown in the sigma trench 19 to form a strained structure 20. In this embodiment, the silicon source used for the epitaxial growth of the silicon-germanium material includes, for example, at least one of silicon chloride (SiCl4), trichlorosilane (SiHCl3), dichlorosilane (SiH2Cl2), and monosilane (SiH4). The germanium source used for the epitaxial growth of the silicon-germanium material is, for example, germanium hydride (GeH4). The silicon-germanium material fills the sigma trench 19 and overflows the sigma trench 19, forming on both sides of the first gate structure 101. The compressive stress exerted by the strained structure 20 on the PMOS transistor can generate current gain. After forming the strained structure 20, ions are implanted into the strained structure 20 to form a doped region (not shown). In this embodiment, the ions implanted into the strained structure 20 are, for example, P-type ions such as boron (B) or gallium (Ga), to serve as the source or drain region of the PMOS transistor. The performance of the PMOS transistor can be improved while the size of the PMOS transistor is reduced, thereby improving the performance of the static random access memory.

[0061] See also Figures 8 and 9As shown, in one embodiment of the present invention, after forming the doped region in the strained structure 20, the protective layer 17 on the shallow trench isolation structure 11, the sidewall structure 16, and the second gate structure 102 is removed. The protective layer 17 is removed, for example, by wet etching, using an etchant such as phosphoric acid, with a volume fraction of 86% to 88% and an etching temperature of 155°C to 165°C. This ensures that the protective layer 17 is completely removed without damaging other structures.

[0062] See also Figures 9 and 10 As shown, in one embodiment of the present invention, after removing the protective layer, a contact hole etch stop layer 21 is formed on the substrate 10, the shallow trench isolation structure 11, and the top and sidewalls of the gate structure. An interlayer dielectric layer 22 is formed on the contact hole etch stop layer 21 and planarized. The contact hole etch stop layer 21 is, for example, a silicon nitride layer and is deposited, for example, by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the contact hole etch stop layer 21 on the substrate 10 is, for example, 20 nm to 50 nm. The interlayer dielectric layer 22 is, for example, made of silicon dioxide or a low-k dielectric material to improve the reliability of the semiconductor device. The interlayer dielectric layer 22 is formed, for example, by low-pressure chemical vapor deposition (LPCVD) or a high-aspect ratio process (HARP) to improve the filling capacity of the interlayer dielectric layer 22. When depositing the interlayer dielectric layer 22, it covers the substrate 10 and the gate structure. After the interlayer dielectric layer 22 is formed, a portion of the interlayer dielectric layer 22 is removed, for example, through a chemical mechanical polishing (CMP) process, to ensure that the surface of the interlayer dielectric layer 22 is planar, thereby improving the ease of fabrication of subsequent structures. When depositing the contact hole etch stop layer 21 and the interlayer dielectric layer 22, since the shallow trench isolation structure 11 does not have a recess, the aspect ratio between adjacent second gate structures 102 will not be increased. Therefore, the filling difficulty will not be increased, and no recess will be formed in the interlayer dielectric layer 22, thereby preventing leakage and improving the yield of the semiconductor device.

[0063] In summary, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device. By improving the method for manufacturing the semiconductor device, the unexpected technical effect of the present application is that a protective layer can be left on the shallow trench isolation structure, and when forming the sigma trench, the shallow trench isolation structure is prevented from being damaged, and the filling depth-to-width ratio between the two second gate structures can be prevented from being increased due to the etching of the shallow trench isolation structure, and the interlayer dielectric layer formed subsequently is prevented from forming a cavity due to the excessive depth-to-width ratio at this location, and short circuits between adjacent gates are avoided, thereby improving the yield of the semiconductor device. By forming a protective layer, the shallow trench isolation structure is protected during the etching and cleaning process, and no new photoresist is introduced when etching the protective layer on the shallow trench isolation structure. The performance of the PMOS transistor can be improved while reducing the size of the PMOS transistor, thereby improving the performance of the static random access memory. When etching the protective layer, by using a negative photoresist, the development of an optical mask can be avoided, one optical mask can be reduced, production costs can be reduced, and the self-alignment of the patterned photoresist layer can be improved.

[0064] The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as those skilled in the art will recognize and appreciate, various equivalent modifications are possible within the spirit and scope of the present invention. As noted, modifications may be made to the present invention in light of the above description of the illustrated embodiments of the present invention, and such modifications will be within the spirit and scope of the present invention.

[0065] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application. In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be repeated here.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate; A plurality of first gate structures are formed on the substrate, and two second gate structures are formed on the shallow trench isolation structure between adjacent first gate structures. forming a protective layer on the first gate structure, the second gate structure, the substrate and the shallow trench isolation structure; Etching the first gate structure and a portion of the protection layer on the substrate; Etching and removing the first gate structure and the protective layer on the substrate, and simultaneously removing a portion of the protective layer on the second gate structure and the shallow trench isolation structure; forming sigma trenches in the substrate on both sides of the first gate structure; forming a strained structure in the sigma trench; as well as removing the protective layer, and sequentially forming a contact hole etching stop layer and an interlayer dielectric layer on the substrate; Wherein, the step of etching the protective layer comprises: Forming a photoresist on the protective layer, and forming a patterned photoresist layer through exposure and development processes, wherein the edge of the patterned photoresist layer is aligned with the edge of the shallow trench isolation structure where the second gate structure is located; Using the patterned photoresist layer as a mask, etching the first gate structure and the portion of the protective layer on the substrate, wherein the removed thickness of the protective layer is one third to one half of the total thickness of the protective layer; removing the patterned photoresist layer; The first gate structure and the protection layer on the substrate are removed by etching.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The photoresist has a polarity opposite to that of the photoresist used when forming the shallow trench isolation structure, and the photoresist on the protective layer is exposed and developed using the optical mask used when forming the shallow trench isolation structure.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The protection layer is removed by dry etching.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The protective layer is a silicon nitride layer, and the thickness of the protective layer is 15nm-20nm.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The remaining thickness of the protection layer on the second gate structure and the shallow trench isolation structure is one third to one half of the total thickness of the protection layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The sigma trench is formed by a combination of dry etching and wet etching.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the strained structure, the substrate is cleaned, and the cleaning includes cleaning with hydrofluoric acid.

8. A semiconductor device, obtained by the manufacturing method according to any one of claims 1 to 7, characterized in that: include: A substrate, wherein the substrate includes a plurality of shallow trench isolation structures; A plurality of first gate structures are disposed in the substrate; Two second gate structures are spaced apart on the shallow trench isolation structure between adjacent first gate structures; a strained structure disposed in a sigma trench in the substrate on both sides of the first gate structure; as well as A contact hole etching stop layer, disposed on the substrate; as well as The interlayer dielectric layer is arranged on the contact hole etching stop layer.

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