A voltage regulation circuit, chip, and electronic device

Abstract

This application relates to the field of power regulation circuit technology, and discloses a voltage regulation circuit, chip, and electronic device. The voltage regulation circuit includes an input unit, a first transistor unit, a second transistor unit, and a voltage regulation unit. By setting the first transistor unit and the second transistor unit to be connected to the voltage regulation unit respectively, the voltage regulation unit adjusts the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit, so that the sum of the adjusted first threshold voltage and the adjusted second threshold voltage is greater than the voltage of the external power supply. The first transistor unit and the second transistor unit are each determined to be in the on / off state according to the adjusted threshold voltage, so as to avoid short-circuit power consumption caused by short circuit between the first transistor unit and the second transistor unit, thereby achieving the purpose of reducing chip power consumption.

Description

Technical Field

[0001] This application relates to the field of power regulation circuit technology, and in particular to a voltage regulation circuit, chip, and electronic device. Background Technology

[0002] As Moore's Law continues to evolve, chip miniaturization leads to increasingly higher power density. Higher power consumption reduces the battery life of electronic devices containing these chips and causes localized heat buildup, slowing down chip performance. It also increases the difficulty and cost of heat dissipation and packaging.

[0003] Chip power consumption can generally be categorized into two types: static power consumption and dynamic power consumption. Dynamic power consumption refers to the power consumed by the device during its charging and discharging operation. Generally, dynamic power consumption accounts for a larger proportion. Therefore, reducing the dynamic power consumption of chips is a worthwhile research topic. Summary of the Invention

[0004] This application provides a voltage regulation circuit, chip, and electronic device, which reduces chip power consumption by reducing the short-circuit power consumption of the first transistor unit and the second transistor unit.

[0005] In a first aspect, one embodiment of this application provides a voltage regulation circuit, including: an input unit, a first transistor unit, a second transistor unit, and a voltage regulation unit; the first transistor unit is connected to the input unit, the second transistor unit, the voltage regulation unit, and an external power supply, respectively, and the second transistor unit is also connected to the input unit and the voltage regulation unit, respectively.

[0006] The voltage regulation unit is used to adjust the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit, so that the sum of the adjusted first threshold voltage and the adjusted second threshold voltage is greater than the voltage of the external power supply.

[0007] The first transistor unit is used to determine whether it is in an on state or an off state based on the input voltage of the input unit, the power supply voltage of the external power supply, and the first threshold voltage adjusted by the voltage adjustment unit.

[0008] The second transistor unit is used to determine whether it is in an on or off state based on the input voltage of the input unit and the second threshold voltage adjusted by the voltage adjustment unit.

[0009] Compared to existing technologies, this application considers that the dynamic power consumption of the circuit can include the switching power consumption consumed by the charging and discharging of the device and the short-circuit power consumption generated by the short circuit of the device. By setting the first transistor unit and the second transistor unit to be connected to the voltage regulation unit respectively, the voltage regulation unit adjusts the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit respectively, so that the sum of the adjusted first threshold voltage and the adjusted second threshold voltage is greater than the voltage of the external power supply. Moreover, the first transistor unit and the second transistor unit are each determined to be in the on or off state according to the adjusted threshold voltage, so as to avoid the short-circuit power consumption caused by the short circuit of the first transistor unit and the second transistor unit, thereby achieving the purpose of reducing chip power consumption.

[0010] In one possible embodiment, the circuit further includes: an output unit; the output unit is connected to the first transistor unit and the second transistor unit respectively;

[0011] The output unit is used to determine the output result based on the input voltage of the input unit, the state of the first transistor unit, and the state of the second transistor unit.

[0012] This application sets up a first transistor unit and a second transistor unit connected to the output unit respectively. After the first transistor unit and the second transistor unit determine that they are in the open or closed state according to the adjusted threshold voltage, the output result of the output unit can be accurately determined.

[0013] In one possible embodiment, the input unit includes at least one input terminal, the first transistor unit includes at least one first transistor, and the second transistor unit includes at least one second transistor; the number of input terminals, the number of first transistors, and the number of second transistors are the same; each first transistor is connected to a corresponding input terminal, and each second transistor is connected to a corresponding input terminal; one first transistor and one second transistor are connected to the same input terminal;

[0014] Each first transistor is connected in parallel, and each second transistor is connected in series; or, each first transistor is connected in series, and each second transistor is connected in parallel.

[0015] This application, by configuring the specific components contained in the input unit, the first transistor unit, and the second transistor unit, and by varying the connection relationships between these components, can obtain voltage regulation circuits with different functions. For example, a voltage regulation circuit obtained by connecting each first transistor in parallel and each second transistor in series can be a multi-input NAND gate; conversely, a voltage regulation circuit obtained by connecting each first transistor in series and each second transistor in parallel can be a multi-input NOR gate. Simultaneously, the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit can be accurately adjusted, thereby reducing chip power consumption.

[0016] In one possible embodiment, the first transistor is a P-type metal-oxide-semiconductor (PMOS) transistor, and the second transistor is an N-type metal-oxide-semiconductor (NMOS) transistor. By specifying the first and second transistors, this application can accurately adjust the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit using the PMOS and NMOS transistors, thereby reducing chip power consumption.

[0017] In one possible embodiment, the first transistor is a P-type metal-oxide-semiconductor (PMOS) transistor, and the second transistor is an N-type metal-oxide-semiconductor (NMOS) transistor, with each first transistor connected in parallel and each second transistor connected in series.

[0018] The source of each PMOS transistor is connected to the external power supply, the gate of each PMOS transistor is connected to the corresponding input terminal, and the drain of each PMOS transistor is connected to the drain of the first NMOS transistor. The gate of each NMOS transistor is connected to the corresponding input terminal. The source and drain of the at least one NMOS transistor are connected in series. The source of the second NMOS transistor is grounded. The first NMOS transistor and the second NMOS transistor are the two ends of the at least one NMOS transistor connected in series.

[0019] This application, by setting specific devices for the first transistor and the second transistor, as well as the specific connection relationship between the devices, can accurately adjust the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit, thereby achieving the purpose of reducing chip power consumption.

[0020] In one possible embodiment, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor; and when each first transistor is connected in series and each second transistor is connected in parallel,

[0021] The source and drain of the at least one PMOS transistor are connected in series. The source of the first PMOS transistor is connected to the external power supply, and the drain of the second PMOS transistor is connected to the drain of each NMOS transistor. The first PMOS transistor and the second PMOS transistor are the two ends of the at least one PMOS transistor connected in series. The gate of each PMOS transistor is connected to the corresponding input terminal. The source of each NMOS transistor is grounded, and the gate of each NMOS transistor is connected to the corresponding input terminal.

[0022] This application, by setting specific devices for the first transistor and the second transistor, as well as the specific connection relationship between the devices, can accurately adjust the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit, thereby achieving the purpose of reducing chip power consumption.

[0023] In one possible embodiment, each first transistor and each second transistor have an oxide insulator disposed on their respective substrate silicon, and each first transistor and each second transistor are connected to the voltage regulation unit through the oxide insulator;

[0024] The voltage regulation unit is specifically used to obtain at least one adjusted first threshold voltage and at least one adjusted second threshold voltage by adjusting the body bias voltage of each oxide insulator.

[0025] This application provides an oxide insulator on the substrate silicon of each first transistor and each second transistor, enabling the voltage regulation unit to adjust the body bias voltage and thereby adjust the device threshold voltage, thus reducing chip power consumption.

[0026] In one possible embodiment, each first transistor and each second transistor respectively have the oxide insulator disposed on the substrate silicon according to the fully depleted silicon-on-insulator (FDSOI) process.

[0027] This application enables a voltage regulation unit to adjust the corresponding threshold voltage by setting the first transistor and the second transistor to form an oxide insulator on the substrate silicon according to the FDSOI process.

[0028] Secondly, one embodiment of this application provides a chip including a voltage regulation circuit as described in the first aspect and any of its designs.

[0029] Thirdly, one embodiment of this application provides an electronic device, including: a circuit board and a chip as described in the second aspect and any of the designs thereof, the chip being disposed on the circuit board. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a voltage regulation circuit provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of a voltage regulation circuit provided in an embodiment of this application;

[0033] Figure 3 This is a schematic diagram of a voltage regulation circuit provided in an embodiment of this application;

[0034] Figure 4 The first transistor provided in the embodiments of this application is a PMOS transistor, the second transistor is an NMOS transistor, each first transistor is connected in parallel, and each second transistor is connected in series, which is a schematic diagram of a voltage regulation circuit.

[0035] Figure 5 This is a schematic diagram of the inverter circuit provided in an embodiment of this application;

[0036] Figure 6a A schematic diagram illustrating different threshold voltages provided in the embodiments of this application;

[0037] Figure 6b A schematic diagram illustrating different threshold voltages provided in the embodiments of this application;

[0038] Figure 6c A schematic diagram illustrating different threshold voltages provided in the embodiments of this application;

[0039] Figure 7 The first transistor provided in this application embodiment is a PMOS transistor, the second transistor is an NMOS transistor, each first transistor is connected in series, and each second transistor is connected in parallel, which is a schematic diagram of a voltage regulation circuit.

[0040] Figure 8 This is a schematic diagram illustrating how adjusting the source voltage of PMOS1 can adjust the threshold voltage of PMOS1 according to an embodiment of this application.

[0041] Figure 9 The threshold voltage V of PMOS1 provided in the embodiments of this application T A schematic diagram showing the change in source voltage V of PMOS1. Detailed Implementation

[0042] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0043] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data used can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0044] As Moore's Law continues to evolve, chip miniaturization leads to increasingly higher power density. Higher power consumption reduces the battery life of electronic devices containing these chips and causes localized heat buildup, slowing down chip performance. It also increases the difficulty and cost of heat dissipation and packaging.

[0045] Chip power consumption can generally be categorized into two types: static power consumption and dynamic power consumption. Dynamic power consumption refers to the power consumed by the device during its charging and discharging operation. Generally, dynamic power consumption accounts for a larger proportion. Therefore, reducing the dynamic power consumption of chips is a worthwhile research topic.

[0046] Therefore, this application provides a voltage regulation circuit, a chip, and an electronic device. The voltage regulation circuit includes an input unit, a first transistor unit, a second transistor unit, and a voltage regulation unit. By connecting the first transistor unit and the second transistor unit to the voltage regulation unit, the voltage regulation unit adjusts the first threshold voltage of the first transistor unit and the second threshold voltage of the second transistor unit, so that the sum of the adjusted first threshold voltage and the adjusted second threshold voltage is greater than the voltage of the external power supply. The first transistor unit and the second transistor unit are each determined to be in an on / off state according to the adjusted threshold voltage, avoiding short-circuit power consumption caused by short circuit between the first transistor unit and the second transistor unit, thereby reducing chip power consumption.

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0048] One embodiment of this application provides a voltage regulation circuit, such as... Figure 1As shown, it includes: an input unit 101, a first transistor unit 102, a second transistor unit 103, and a voltage regulation unit 104. The first transistor unit 102 is connected to the input unit 101, the second transistor unit 103, the voltage regulation unit 104, and an external power supply 106. The second transistor unit 103 is also connected to the input unit 101 and the voltage regulation unit 104.

[0049] The voltage adjustment unit 104 adjusts the first threshold voltage of the first transistor unit 102 and the second threshold voltage of the second transistor unit 103 so that the sum of the adjusted first threshold voltage and the adjusted second threshold voltage is greater than the voltage of the external power supply. Furthermore, the first transistor unit 102 determines whether it is in an on or off state based on the input voltage of the input unit 101, the power supply voltage of the external power supply 106, and the first threshold voltage adjusted by the voltage adjustment unit 104; and the second transistor unit 103 determines whether it is in an on or off state based on the input voltage of the input unit 101 and the second threshold voltage adjusted by the voltage adjustment unit 104.

[0050] Optionally, the circuit may further include an output unit 105. The output unit 105 is connected to the first transistor unit 102 and the second transistor unit 103, respectively. The output unit 105 determines the output result based on the input voltage of the input unit 101, the state of the first transistor unit 102, and the state of the second transistor unit 103.

[0051] In one possible implementation, such as Figure 2 As shown, the input unit 101 may include at least one input terminal (such as...). Figure 2 The first transistor unit 102, shown as input terminals 1, 2, ..., n, includes at least one first transistor (e.g., input terminals 1, 2, ..., n). Figure 2 The first transistor 102-1, first transistor 102-2, ..., first transistor 102-n shown, and the second transistor unit 103 includes at least one second transistor (e.g., Figure 2 The second transistors 103-1, 103-2, ..., 103-n are shown. Here, n is a positive integer.

[0052] Furthermore, the number of input terminals, the number of first transistors, and the number of second transistors are the same. Each first transistor is connected to a corresponding input terminal, and each second transistor is connected to a corresponding input terminal. One first transistor and one second transistor are connected to the same input terminal. For example, input terminal 1, first transistor 102-1, and second transistor 103-1 are interconnected, and input terminal 2, first transistor 102-2, and second transistor 103-2 are interconnected.

[0053] By configuring the specific components included in the input unit 101, the first transistor unit 102, and the second transistor unit 103, and by varying the connections between these components, voltage regulation circuits with different functions can be obtained. For example, Figure 2 The voltage regulation circuit shown, where each first transistor is connected in parallel and each second transistor is connected in series, can be a multi-input NAND gate. Figure 3 The voltage regulation circuit shown, where each first transistor is connected in series and each second transistor is connected in parallel, can be a multi-input NOR gate. Simultaneously, by utilizing the connection relationship of the devices, the first threshold voltage of the first transistor unit 102 and the second threshold voltage of the second transistor unit 103 can be accurately adjusted, thereby reducing chip power consumption.

[0054] In the embodiments of this application, either the first transistor or the second transistor can be any one of an N-type metal-oxide-semiconductor field-effect transistor (NMOS), a P-type metal-oxide-semiconductor field-effect transistor (PMOS), an NPN transistor, or a PNP transistor. Different transistor types and different connection relationships result in different functions of the voltage regulation circuit. The following describes several connection methods for the voltage regulation circuit based on different transistor types and connection relationships:

[0055] Method 1: The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. Each first transistor is connected in parallel, and each second transistor is connected in series.

[0056] like Figure 4 As shown, the source of each PMOS transistor (e.g., PMOS1, PMOS2, ..., PMOSn) is connected to the external power supply 106, and the gate of each PMOS transistor is connected to the corresponding input terminal; for example, the gate of PMOS1 is connected to input terminal 1, and the gate of PMOS2 is connected to input terminal 2. The drain of each PMOS transistor is connected to the drain of the first NMOS transistor (e.g., NMOS1), and the gate of each NMOS transistor (e.g., NMOS1, NMOS2, ..., NMOSn) is connected to the corresponding input terminal; for example, the gate of NMOS1 is connected to input terminal 1, and the gate of NMOS2 is connected to input terminal 2. The source and drain of at least one NMOS transistor are connected in series, and the source of the second NMOS transistor (e.g., NMOSn) is grounded. The first and second NMOS transistors are the two ends of at least one NMOS transistor connected in series.

[0057] Assuming the external power supply 106 has a voltage VDD = 1V, input unit 101 includes input terminal 1 (input voltage denoted by V1) and input terminal 2, first transistor unit 102 includes PMOS1 and PMOS2, and second transistor unit 103 includes NMOS1 and NMOS2. When both input terminal 1 and input terminal 2 are 1V, NMOS1 and NMOS2 are simultaneously turned on. When input terminal 1 is gradually adjusted from 1V to 0V, while input terminal 2 remains at 1V, PMOS2 is turned off, and NMOS2 is turned on. At this time, the threshold voltages of PMOS1 and NMOS1 are respectively: |V GS-P1 |=|V1-VDD|=VDD-V1, V GS-N1 =V1-VSS=V1. Therefore, |V GS-P1 |+V GS-N1 =VDD. Therefore, when a short circuit occurs in PMOS1 and NMOS1, the threshold voltages of PMOS1 and NMOS1 can be adjusted by the voltage regulation unit 104 to avoid short circuit power consumption and thus reduce the dynamic power consumption of the chip.

[0058] In one embodiment of this application, as Figure 5 As shown, assuming the external power supply 106 has a voltage VDD = 1V, the input unit 101 includes input terminal 1 (input voltage is represented by V1), the first transistor unit 102 includes PMOS1, and the second transistor unit 103 includes NMOS1. In this case, the circuit composed of PMOS1 and NMOS1 can be an inverter circuit. Similarly, the threshold voltages of PMOS1 and NMOS1 are respectively: |V GS-P1 |=|V1-VDD|=VDD-V1, V GS-N1 =V1-VSS=V1. Therefore, |V GS-P1 |+V GS-N1 =VDD. Therefore, when a short circuit occurs in PMOS1 and NMOS1, the voltage regulation unit 104 adjusts the respective threshold voltages |VDD| of PMOS1 and NMOS1. th-P1 |、V th-N1 This can avoid short-circuit power consumption, thereby reducing the dynamic power consumption of the chip.

[0059] like Figure 6a As shown, when V1 = 0.18V, |V GS-P1 |=0.82, V GS-N1 =0.18, |V th-P1 |=0.6V、V th-N1 When V = 0.6V, |V GS-P1 |>|V th-P1 |,V GS-N1 <V th-N1At this time, PMOS1 is in the ON state and NMOS1 is in the OFF state. For example... Figure 6b As shown, when V1 = 0.9V, |V GS-P1 |=0.1, V GS-N1 =0.9, |V th-P1 |=0.6V、V th-N1 When V = 0.6V, |V GS-P1 |<|V th-P1 |,V GS-N1 >V th-N1 At this time, PMOS1 is in the off state and NMOS1 is in the on state. For example... Figure 6c As shown, when V1 = 0.5V, |V GS-P1 |=0.5, V GS-N1 =0.5, |V th-P1 |=0.6V、V th-N1 When V = 0.6V, |V GS-P1 |<|V th-P1 |,V GS-N1 <V th-N1 At this time, PMOS1 is in the off state, and NMOS1 is in the off state. If |V th-P1 |=0.5V、V th-N1 When V = 0.5V, |V GS-P1 |>|V th-P1 |,V GS-N1 >V th-N1 At this time, both PMOS1 and NMOS1 are turned on. Therefore, by adjusting the threshold voltages |V of PMOS1 and NMOS1... th-P1 |、V th-N1 It can reduce short-circuit power consumption.

[0060] Method 2: The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. Each first transistor is connected in series, and each second transistor is connected in parallel.

[0061] like Figure 7As shown, the source and drain of at least one PMOS transistor (e.g., PMOS1, PMOS2, ..., PMOSn) are connected in series. The source of the first PMOS transistor (e.g., PMOS1) is connected to the external power supply 106, and the drain of the second PMOS transistor (e.g., PMOSn) is connected to the drain of each NMOS transistor (e.g., NMOS1, NMOS2, ..., NMOSn). The first and second PMOS transistors are the two ends of at least one PMOS transistor connected in series. The gate of each PMOS transistor is connected to the corresponding input terminal; for example, the gate of PMOS1 is connected to input terminal 1, and the gate of PMOS2 is connected to input terminal 2. The source of each NMOS transistor is grounded, and the gate of each NMOS transistor is connected to the corresponding input terminal; for example, the gate of NMOS1 is connected to input terminal 1, and the gate of NMOS2 is connected to input terminal 2.

[0062] Assuming the external power supply 106 has a voltage VDD = 1V, input unit 101 includes input terminal 1 and input terminal 2 (input voltage is represented by V2), first transistor unit 102 includes PMOS1 and PMOS2, and second transistor unit 103 includes NMOS1 and NMOS2. When both input terminal 1 and input terminal 2 are 0V, PMOS1 and PMOS2 are simultaneously turned on. When input terminal 1 is gradually adjusted from 0V to 1V, and input terminal 2 remains at 1V, NMOS1 is turned off, and PMOS1 is turned on. At this time, the threshold voltages of PMOS2 and NMOS2 are respectively: |V GS-P2 |=|V2-VDD|=VDD-V2, V GS-N2 =V2-VSS=V2. Therefore, |V GS-P2 |+V GS-N2 =VDD. Therefore, when a short circuit occurs in PMOS2 and NMOS2, the threshold voltages of PMOS2 and NMOS2 can be adjusted by the voltage regulation unit 104 to avoid short circuit power consumption and thus reduce the dynamic power consumption of the chip.

[0063] In one embodiment of this application, each first transistor and each second transistor have an oxide insulator disposed on their respective substrate silicon. Each first transistor and each second transistor are connected to a voltage adjustment unit 104 via the oxide insulator. The voltage adjustment unit 104 obtains at least one adjusted first threshold voltage and at least one adjusted second threshold voltage by adjusting the body bias voltage of each oxide insulator. For example, the oxide insulator disposed on the substrate silicon can be achieved using a fully depleted silicon-on-insulator (FDSOI) process, that is, the threshold voltage of each transistor can be adjusted using the FDSOI process. Specifically, the FDSOI process is a planar process technology that can deposit an ultrathin oxide insulator layer on top of the substrate silicon of each transistor. The voltage adjustment unit 104 adjusts the voltage of the substrate to achieve the purpose of adjusting the threshold voltage.

[0064] like Figure 8 As shown, taking the first transistor PMOS1 as an example, the substrate silicon of PMOS1 is made of oxide insulator. Let V represent the source voltage of PMOS1 and Vthreshold voltage. T Therefore, the threshold voltage V of PMOS1 can be adjusted by the following formula. T Adjustments are needed:

[0065]

[0066] Where γ is the volume effect parameter, V T0 These are empirical parameters. This represents the Fermi potential of silicon. Figure 9 The threshold voltage V of PMOS1 is shown. T The short-circuit power dissipation increases with the increase of the source voltage V of PMOS1. Table 1 shows the mapping relationship between the source voltage of different PMOS, the source voltage of the corresponding different NMOS, and the short-circuit power dissipation. As can be seen from Table 1, the larger the source voltage of the PMOS and the larger the source voltage of the corresponding NMOS, the smaller the short-circuit power dissipation.

[0067] Table 1

[0068] PMOS source voltage NMOS source voltage Short-circuit power consumption 0.8 0 32.4 1.5 -0.5 28.09 3 -2.0 20.22 6 -5.0 2.87

[0069] It should be understood that the voltage regulation unit, the first transistor unit, and the second transistor unit described above are all illustrative examples. This application does not limit the specific device composition and can be adjusted according to the actual situation.

[0070] In this application, when the voltage regulation circuit needs to operate in a low-power mode, the threshold voltage can be increased by adjusting the source voltage, thereby reducing short-circuit power consumption. Conversely, when the voltage regulation circuit needs to operate in a high-speed mode, the threshold voltage can be decreased by adjusting the source voltage, thereby increasing the circuit's operating speed.

[0071] In one embodiment of this application, a chip is also provided, including: the voltage regulation circuit provided in any of the above embodiments.

[0072] In one embodiment of this application, an electronic device is also provided, including: a circuit board and a chip provided in any of the above embodiments, wherein the chip is disposed on the circuit board.

[0073] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A voltage regulating circuit, characterized by, The circuit comprises an input unit, a first transistor unit, a second transistor unit and a voltage adjusting unit; the first transistor unit is connected with the input unit, the second transistor unit, the voltage adjusting unit and an external power supply respectively, and the second transistor unit is also connected with the input unit and the voltage adjusting unit respectively; the first transistor unit comprises at least one first transistor, and the second transistor unit comprises at least one second transistor; a base silicon of each first transistor and each second transistor is provided with an oxide insulator, and each first transistor and each second transistor are connected with the voltage adjusting unit through the oxide insulator; the voltage adjusting unit is configured to adjust a first threshold voltage of the first transistor unit and a second threshold voltage of the second transistor unit by adjusting a bulk bias voltage of each oxide insulator, so that a sum of the adjusted first threshold voltage and the adjusted second threshold voltage is greater than a voltage of the external power supply; the first transistor unit is configured to determine a turn-on state or a turn-off state according to an input voltage of the input unit, a power supply voltage of the external power supply and the adjusted first threshold voltage of the voltage adjusting unit; the second transistor unit is configured to determine a turn-on state or a turn-off state according to the input voltage of the input unit and the adjusted second threshold voltage of the voltage adjusting unit; wherein the first transistor unit and the second transistor unit are not in the turn-on state at the same time. The circuit further comprises an output unit connected with the first transistor unit and the second transistor unit respectively; 2. The circuit of claim 1, wherein, the output unit is configured to determine an output result according to the input voltage of the input unit, a state of the first transistor unit and a state of the second transistor unit. The input unit comprises at least one input terminal; the number of input terminals, the number of first transistors and the number of second transistors are the same; each first transistor is connected with a corresponding input terminal, and each second transistor is connected with a corresponding input terminal; one first transistor and one second transistor are connected with one input terminal; 3. The circuit of claim 1, wherein, each first transistor is connected in parallel, and each second transistor is connected in series; or each first transistor is connected in series, and each second transistor is connected in parallel. The first transistor is a P-type metal oxide semiconductor (PMOS) transistor, and the second transistor is an N-type metal oxide semiconductor (NMOS) transistor.

4. The circuit of claim 3, wherein, When the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, and each first transistor is connected in parallel and each second transistor is connected in series, 5. The circuit of claim 4, wherein, ​ The source of each PMOS transistor is connected to the external power supply, the gate of each PMOS transistor is connected to a corresponding input, and the drain of each PMOS transistor is connected to the drain of a first NMOS transistor; the gate of each NMOS transistor is connected to a corresponding input, the source and the drain of the at least one NMOS transistor are connected in series, the source of a second NMOS transistor is connected to ground, and the first NMOS transistor and the second NMOS transistor are connected across the at least one NMOS transistor.

6. The circuit of claim 4, wherein, The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor; and each first transistor is connected in series, and each second transistor is connected in parallel, The source and the drain of the at least one PMOS transistor are connected in series, the source of a first PMOS transistor is connected to the external power supply, the drain of a second PMOS transistor is connected to the drain of each NMOS transistor, the first PMOS transistor and the second PMOS transistor are connected across the at least one PMOS transistor, and the gate of each PMOS transistor is connected to a corresponding input; the source of each NMOS transistor is connected to ground, and the gate of each NMOS transistor is connected to a corresponding input.

7. The circuit of claim 1, wherein Each first transistor and each second transistor is provided with the oxide insulator in a base silicon according to a fully depleted silicon on insulator (FDSOI) process.

8. A chip, characterized by The voltage regulation circuit of any one of claims 1-7. The voltage regulation circuit of any one of claims 1-7.

9. An electronic device, comprising: The circuit board and the chip of claim 8, the chip being provided on the circuit board. ​

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