FIFO memory read and write processing circuit and chip

Abstract

The present invention discloses a FIFO memory read-write processing circuit and chip related to the field of integrated circuit technology, wherein the FIFO memory read-write processing circuit comprises: a write operation control module, a read operation control module, a configurable module, an empty and full state judgment module and a dual-port access FIFO memory, wherein the write operation control module is used to control the operation of the write interface of the communication module, the read operation control module is used to control the operation of the read interface of the communication module, the configurable module is used to configure clock synchronization and allocate the address range of each communication module in the FIFO memory, the empty and full state judgment module is used to judge the empty and full state of the storage space of the communication module, and the dual-port access FIFO memory supports the read and write operations of different communication modules. The FIFO memory read-write processing circuit can dynamically configure the size of the FIFO memory used by the communication module, improve the storage resource utilization of the FIFO memory, and can also support the read and write operations of communication modules in different clock domains.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a FIFO memory read-write processing circuit and chip. Background Art

[0002] In the related technology, in the application field of industrial control and automotive microcontroller units (MCU), multiple types and a considerable number of communication modules are usually involved. For example, in the automotive gateway control MCU, the controller area network bus (CAN, Controller Area Network) controller can be up to 20, the local interconnect network (LIN, Local Interconnect Network) bus controller can be up to 10, and other communication modules also involve a considerable number, including serial peripheral interface (SPI, Serial Peripheral Interface), serial bus interface (I2C, Inter-Integrated Circuit), serial audio interface (I2S, Inter-IC Sound), safe and efficient serial interface (SENT, Single Edge Nibble Transmission), etc. In order to improve the efficiency of communication, communication modules usually use first-in-first-out memory (FIFO memory) to cache the sent and received data. Using FIFO in the communication module can effectively increase the data transmission rate, cache a large amount of data, and reduce the burden on the CPU, thereby improving system performance. In different application scenarios, the FIFO requirements for each communication module are not the same, and in the chip design, each communication module is equipped with its own FIFO memory, which reduces the utilization rate of the FIFO memory. For example, the module with a larger data cache cannot meet the system's requirements for the FIFO cache, and the module with a smaller data cache has its own FIFO memory vacant for a long time, resulting in a waste of resources. Summary of the invention

[0003] Based on this, it is necessary to provide a FIFO memory read and write processing circuit that can improve the utilization rate of FIFO storage resources in response to the above technical problems.

[0004] A FIFO memory read / write processing circuit, the FIFO memory read / write processing circuit comprising: a write operation control module, a read operation control module, a configurable module, an empty / full state judgment module and a dual-port access FIFO memory; the write operation control module and the read operation control module are respectively connected to the configurable module, the empty / full state judgment module and the FIFO memory;

[0005] The configurable module includes a synchronization definition unit and a reallocation unit; the synchronization definition unit is used to manage the clock synchronization of the write interface and the read interface of the communication module in different clock domains; the reallocation unit is used to store the address range allocated to each of the communication modules in the FIFO memory;

[0006] The write operation control module is connected to the write interface of the communication module, and is composed of a write interface synchronization logic unit and a write operation judgment and gating unit connected to each other; the write interface synchronization logic unit is used to perform the write operation synchronization of the write interface according to the clock synchronization determined by the synchronization definition unit; the write operation judgment and gating unit is used to determine the write permission of the write interface and gating the write interface path corresponding to the write interface with the write permission;

[0007] The read operation control module is connected to the read interface of the communication module, and is composed of a read interface synchronization logic unit and a read operation judgment gating unit connected to each other; the read interface synchronization logic unit is used to perform the read operation synchronization of the read interface according to the clock synchronization determined by the synchronization definition unit; the write operation judgment gating unit is used to determine the read permission of the read interface and gating the read interface path corresponding to the read interface with the read permission;

[0008] The empty and full state judgment module is connected to the configurable module, and is used to output a full flag according to the address range of the communication module and the write pointer and the read pointer of the communication module with write permission, and output an empty flag according to the address range of the communication module and the read pointer and the write pointer of the communication module with read permission;

[0009] The FIFO memory is a storage space shared by multiple communication modules, used to store data written by a write interface with write permission in an address range allocated by the communication module with write permission, and to read data read by a read interface with read permission in an address range allocated by the communication module with read permission.

[0010] A chip includes a FIFO memory read and write processing circuit.

[0011] The above-mentioned FIFO memory read and write processing circuit includes a write operation control module, a read operation control module, a configurable module, an empty and full state judgment module and a dual-port storage FIFO memory, which realizes the reconstruction and allocation of FIFO resources of each communication module. The available FIFO size of each communication module can be configured in real time, so that multiple communication modules can share FIFO space and perform read and write operations on the shared FIFO space, effectively improving the utilization rate of FIFO storage resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A schematic diagram of the structure of a FIFO memory read / write processing circuit in one embodiment;

[0013] Figure 2 A schematic diagram of the internal structure of a write operation determination gating unit in one embodiment;

[0014] Figure 3 A schematic diagram of the internal structure of a read operation determination gating unit in one embodiment;

[0015] Figure 4 Schematic diagram of the internal structure of an empty or full state judgment module in an embodiment. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0017] The implementation details of the technical solution of the embodiment of the present application are described in detail below.

[0018] In one embodiment, Figure 1 As shown, Figure 1 FIG. 1 shows a schematic diagram of the structure of the FIFO memory read and write processing circuit. Figure 1 As shown, the FIFO memory read and write processing circuit mainly includes a write operation control module, a read operation control module, a configurable module, an empty and full state judgment module and a FIFO memory, wherein the write operation control module and the read operation control module are respectively connected to the configuration module empty and full state judgment module and the FIFO memory.

[0019] The various components of the FIFO memory read and write processing circuit are described in detail below.

[0020] The FIFO memory read / write processing circuit is equipped with a large FIFO memory, which is a storage space shared by multiple communication modules. Multiple communication modules share a FIFO memory. The FIFO memory is equipped with dual ports and has two independent interfaces, one for writing data (write port) and one for reading data (read port). These two ports can operate simultaneously, and can read and write at the same time. Due to the dual-port characteristics of the FIFO memory, parallel data input and output can be achieved, reducing data delay and improving system throughput. In practical applications, the FIFO memory can be implemented using a dual-port RAM.

[0021] The configurable module can configure the FIFO space and read and write clock of each communication module according to specific requirements or application scenarios. Figure 1,The configurable module consists of a synchronization definition unit and a redistribution unit.

[0022] Among them, in a multi-module system, different communication modules may run in different clock domains, which requires synchronization control of the read and write interfaces of these communication modules. The synchronization definition unit plays a vital role here. The synchronization definition unit is used to manage the clock synchronization of the write interface and read interface of the communication modules in different clock domains. By identifying the clock domains used by the write interface and read interface of each communication module, and deciding whether to enable clock synchronization based on the relationship between these clock domains, the consistency of data and the correctness of timing can be ensured. It can match the different clock requirements of multiple communication modules and meet the read and write requirements of multiple communication modules.

[0023] In this embodiment, the synchronization definition unit can ensure that the same FIFO memory can be effectively used by communication modules in multiple different clock domains by reasonably defining and coordinating the read clock domain and the write clock domain, thereby improving the utilization rate of the FIFO storage resources.

[0024] In one embodiment, the clock synchronization of the synchronization definition unit is determined by a reference write clock and a reference read clock, which are standard clocks selected by the synchronization definition unit to assist and manage data transmission and synchronization between different clock domains in the system.

[0025] The synchronization definition unit selects the write clock with higher frequency and more involved communication modules among all communication modules as the reference write clock, and takes the reference write clock as a reference. If the write clock of the communication module is consistent with the reference write clock, it indicates that the write interface of the communication module is performing write operations in the same write clock domain, and the write interface of the communication module does not involve cross-clock domain operations, so no additional synchronization operations are required, so the synchronization definition unit removes the write clock synchronization logic of the communication module. If the write clock of the communication module is inconsistent with the reference write clock, it indicates that the write interface of the communication module is performing write operations in different write clock domains. In order to ensure the integrity and correctness of data transmission between different write clock domains, the write clock synchronization logic of the communication module needs to be enabled.

[0026] Similarly, the synchronization definition unit selects a read clock with a higher frequency and involving more communication modules among all communication modules as a reference read clock, and decides whether to enable read clock synchronization according to the consistency between the read clock of the communication module and the selected reference read clock. If the read clock of the communication module is consistent with the reference read clock, the synchronization definition unit removes the read clock synchronization logic of the communication module; if the read clock of the communication module is inconsistent with the reference clock, the synchronization definition unit enables the read clock synchronization logic of the communication module.

[0027] In this embodiment, the synchronization definition unit allows the system to work in a multi-clock domain scenario by setting whether to enable clock synchronization.

[0028] The reallocation unit is used to store the address range in the FIFO memory allocated to each communication module, and the address range is defined by a start address and an end address, that is, the storage space from the start address to the end address in the FIFO memory is allocated to a communication module. It can be understood that all the storage space of the FIFO memory is shared by all the communication modules. In order to better utilize the storage resources of the FIFO memory, all the storage space of the FIFO memory needs to be reasonably allocated to each communication module, wherein each communication module can use the address range allocated to the communication module in the FIFO memory.

[0029] In actual applications, the address range allocated to each communication module is configured by system software, and the reallocation unit is connected to the system bus to obtain and store the allocated address range through the system bus.

[0030] In one embodiment, the reallocation unit is mainly composed of a general configuration register. The system software configures the value of the configuration register, and the value of the configuration register corresponds to the address of the FIFO memory, thereby allocating corresponding storage space to each communication module. The structure of the configuration register is defined as follows:

[0031] Communication module 1 FIFO start address and end address;

[0032] Communication module 2 FIFO start address and end address;

[0033] …

[0034] Communication module n FIFO start address and end address.

[0035] Among them, the address range of each communication module defined in the configuration register is independent of each other, that is, the address range assigned to each communication module does not overlap to prevent FIFO access conflicts. At the same time, the address boundary of each address range stored in the configuration register cannot exceed the valid range of the FIFO memory to prevent invalid FIFO access operations, resulting in data loss and wrong access.

[0036] In the FIFO memory read and write processing circuit of this embodiment, read control and write control are separated, so as to support parallel execution of FIFO write operation and read operation through a write operation control module and a read operation control module respectively, thereby improving the execution efficiency of the system.

[0037] It should be noted that the write operation control module and the read operation control module can use different clocks to meet the needs of read and write clock domain separation of multiple communication modules. For example, the write interface may use the function clock to receive data from the external interface of the chip and store it in the FIFO according to the configurable baud rate, while the read interface may use the system bus clock to read the FIFO data to the CPU processor. Based on this, the write operation control module and the read operation control module are of great significance in processing asynchronous operations and improving system performance and flexibility.

[0038] See also Figure 1 As shown, the write operation control module is composed of a write interface synchronization logic unit and a write operation judgment and selection unit which are connected to each other.

[0039] The write operation control module is connected to the write interfaces (write interface 1, write interface 2, ..., write interface n) of different communication modules, where the write interfaces of different communication modules may use different clock signals, which will result in different timings between different write interfaces when data is written into the FIFO memory, and there may be a risk of data conflict or loss. The main function of the write interface synchronization logic unit is to synchronize the different connected write clock signals. The write interface synchronization logic unit is connected to the synchronization definition unit. The write interface synchronization logic unit performs the write operation synchronization of the write interface according to the clock synchronization determined by the synchronization definition unit, ensuring that the data of the write interface of the communication module (including the write enable signal and the write data) can be correctly transmitted to the write interface synchronization logic unit.

[0040] Specifically, when the synchronization definition unit removes the write clock synchronization logic of the communication module, the write interface synchronization logic unit can directly receive the data transmitted by the write interface of the communication module. When the synchronization definition unit enables the write clock synchronization logic of the communication module, the write interface synchronization logic unit can use a two-level synchronous and asynchronous handshake mechanism to ensure that the data of the write interface is correctly transmitted and processed between asynchronous clock domains, so that the write interface synchronization logic unit can receive the data of the write interface.

[0041] It can be understood that the write operation control module is connected to the write interfaces of all communication modules. In one operation cycle, there may be multiple write interfaces initiating write operation requests. For the sake of data security and integrity, it is necessary to arbitrate the write permission of the write interface that initiates the write operation of the communication module. The write operation judgment gating unit in the write operation control module is used to determine the write permission of the write interface synchronized by the write interface synchronization logic unit, judge whether the write interface has the write permission, that is, whether it is allowed to write data to the FIFO memory, and select the write interface path corresponding to the write interface with the write permission, wherein the write operation judgment gating unit is respectively connected to the FIFO memory and the empty and full state judgment module. The path selection here can be understood as selecting the output path of the write operation control module, so that the selected write interface path can output the data related to the write interface with the write permission to the FIFO memory to complete the writing of the data, and output it to the empty and full state judgment module to judge the full state. For example, both communication module 1 and communication module 2 initiate write requests. After the write operation is judged, the selection unit confirms that the write interface of communication module 1 has write permission. At this time, the write interface path corresponding to communication module 1 is selected, and the relevant data of the write interface of communication module 1 is output to the FIFO memory and the empty and full status judgment module, while the relevant data of the write interface of communication module 2 is not transmitted to other modules.

[0042] In one embodiment, the write operation judgment gating unit only determines one write interface with write permission in one operation cycle. If multiple write interfaces write data to the FIFO memory at the same time in the same operation cycle, data conflicts may occur, causing problems with data integrity. The write operation judgment gating unit ensures that only one write interface obtains write permission in each operation cycle, and can ensure that each write operation is performed without interference, thereby ensuring the integrity of the written data.

[0043] See also Figure 2 , Figure 2 The internal structure diagram of the write operation judgment gating unit is shown. The write operation judgment gating unit includes n groups of write pointer counters and n first waiting control units, a write operation arbitration judgment unit and a first path selector. Among them, the n write pointer counting units and the n first waiting control units are respectively configured for n communication modules, the write pointer counting unit can track the data writing position of a communication module, the first waiting control unit controls the execution state of the write operation of a communication module, and a write pointer counting unit and a first waiting control unit constitute a write interface input circuit. The write operation arbitration judgment unit and the first path selector constitute the interface output circuit of the write operation judgment gating unit.

[0044] The write operation judgment selection unit receives the write enable signal and write data output by the write interface synchronization logic unit. The write enable signal triggers the write pointer counting unit to count and obtain the write pointer of the communication module. In practical applications, the address range allocated by the reallocation unit to the communication module will be connected to the write pointer counting unit allocated to the corresponding communication module. For example, the start address 1 and end address 1 of communication module 1 will be passed to the write pointer counting unit configured for communication module 1. The write pointer counting unit counts within the address range allocated by the communication module, that is, the range of changes in the write pointer is within the address range formed by the start address and end address allocated by the communication module. The write pointer counting unit outputs the obtained write pointer to the first channel selector and the outside of the module (FIFO memory and empty and full status judgment module).

[0045] The write operation arbitration judgment unit receives the write enable signals sent by all write interfaces for arbitration judgment, ensures that only one write interface obtains the write permission in each operation cycle, and feeds back the arbitration result to the corresponding first waiting control unit, wherein the arbitration result here refers to the write permission of the write interface of the communication module. For example, the write operation arbitration judgment unit performs permission arbitration on the received write enable signal 1 of the communication module 1, obtains arbitration feedback 1, and returns the arbitration feedback 1 to the communication module 1 through the first waiting control unit.

[0046] In one embodiment, the write operation arbitration judgment unit determines the write permission of the write interface according to the arbitration judgment priority. The write operation arbitration judgment unit determines which write interface can obtain the write permission according to the arbitration judgment priority. This process ensures that when multiple write interfaces request write operations at the same time, arbitration can be carried out in an orderly manner to avoid conflicts and maintain data consistency. The write operation arbitration judgment unit performs arbitration judgment on the write interface that sends the write enable signal according to the preset arbitration judgment priority, wherein the priority rule can be a fixed priority method or a cyclic priority, etc.

[0047] In one embodiment, the arbitration judgment priority of the write operation arbitration judgment unit is controlled by the reallocation unit, and one of the fixed priority and the cyclic priority is selected as the arbitration judgment priority of the write operation arbitration judgment unit. In actual applications, the reallocation unit can set a default arbitration judgment priority when the system is initialized, and can also receive configuration commands through an external interface, which are used to modify the arbitration judgment priority, so that the reallocation unit can set different arbitration judgment priorities and dynamically adjust the arbitration judgment priority at runtime to adapt to different application scenarios and requirements.

[0048] The first waiting control unit determines the judgment result (i.e. Figure 2The arbitration feedback in the FIFO determines whether the write interface has obtained the write permission. If the write interface does not obtain the write permission, a wait signal is output to put the write interface into a wait state until the write interface obtains the write permission. If the write interface obtains the write permission, the write interface can perform a write operation and write data to the FIFO memory.

[0049] After performing arbitration, the write operation arbitration judgment unit further outputs an identifier corresponding to the write interface that has obtained the write permission (ie, the write interface ID).

[0050] The first path selector receives an identifier from the write operation arbitration judgment unit, and selects the corresponding write interface path according to the received identifier, and transmits the relevant data of the write interface with write permission to other modules or units. Figure 2 As shown, the first path selector is connected to the relevant data of the write interfaces of all communication modules. Assuming that the write interface of communication module 1 obtains the write permission, the first path selector selects the relevant write interface path of communication module 1, and the first path selector outputs the relevant data about the write interface of communication module 1.

[0051] The output of the first path selector can be received by the FIFO memory, so that data can be written into the FIFO memory according to the data. In addition, the output of the first path selector can also be received by the empty and full state judgment module, so that the empty and full state judgment module can correctly update the empty and full state of the storage space allocated by the communication module to ensure the correct storage and reading of data.

[0052] The read operation control module is very similar to the write operation control module in terms of function and structure. Figure 1 As shown, the read operation control module is composed of an interface synchronization logic unit and a read operation judgment selection unit which are connected to each other.

[0053] The read operation control module is connected to the read interface (read interface 1, read interface 2, ..., read interface n) of the communication module, where the read interfaces of different communication modules may use different clock signals, which will result in different timings between different read interfaces when reading data from the FIFO memory, which may lead to erroneous reading or loss of data. The main function of the read interface synchronization logic unit is to synchronize the different read clock signals connected. The read interface synchronization logic unit is connected to the synchronization definition unit. The read interface synchronization logic unit performs the read operation synchronization of the read interface according to the clock synchronization determined by the synchronization definition unit, ensuring that the data of the read interface of the communication module (including the read enable signal) can be correctly transmitted to the read interface synchronization logic unit.

[0054] Specifically, when the synchronization definition unit removes the read clock synchronization logic of the communication module, the read interface synchronization logic unit can directly receive the data transmitted by the read interface of the communication module. When the synchronization definition unit enables the read clock synchronization of the communication module, the read interface synchronization logic unit can use a two-level synchronous and asynchronous handshake mechanism to ensure that the data of the read interface is correctly transmitted and processed between asynchronous clock domains, so that the read interface synchronization logic unit can receive the data of the read interface.

[0055] It can be understood that the read operation control module is connected to the read interface of all communication modules. In one operation cycle, there may be multiple read interfaces initiating read operation requests. For the sake of data security, it is necessary to perform read permission arbitration on the read interface that initiates the read operation of the communication module. The read operation judgment gating unit in the read operation control module is used to determine the read permission of the read interface synchronized by the read interface synchronization logic unit, judge whether the read interface obtains the read permission, that is, whether it is allowed to read the relevant data in the FIFO memory, and select the read interface path corresponding to the read interface with read permission, wherein the read operation judgment gating unit is respectively connected to the FIFO memory and the empty and full state judgment module. The path selection here can be understood as selecting the output path of the read operation control module, so that the selected read interface path can output the data related to the read interface with read permission to the FIFO memory to complete the data reading, and output it to the empty and full state judgment module to judge the empty state. For example, both communication module 1 and communication module 2 initiate a read request. After the read operation is judged, the enabling unit confirms that the read interface of communication module 1 has read permission. At this time, the read interface path corresponding to communication module 1 is enabled, and the relevant data of the read interface of communication module 1 is output to the FIFO memory and the empty and full status judgment module, while the relevant data of the read interface of communication module 2 is not transmitted to other modules.

[0056] In one embodiment, the read operation judgment gating unit only determines one read interface with read permission in one operation cycle. If multiple read interfaces simultaneously access the FIFO memory in the same operation cycle, data conflicts may occur, causing data integrity problems, and causing the system to read incorrect data. The read operation judgment gating unit ensures that only one read interface obtains read permission in each operation cycle, and can ensure that each read operation is performed without interference, thereby ensuring data consistency.

[0057] See also Figure 3 , Figure 3The internal structure diagram of the read operation judgment gating unit is shown. The read operation judgment gating unit includes n groups of read pointer counters and n second waiting control units, a read operation arbitration judgment unit and a second path selector. Among them, the n groups of read pointer counting units and the n second waiting control units are respectively configured for n communication modules, the read pointer counting unit can track the data read position of a communication module, and the second waiting control unit controls the execution state of the read operation of a communication module. A read pointer counting unit and a second waiting control unit constitute a read interface input circuit. The read operation arbitration judgment unit and the second path selector constitute the interface output circuit of the read operation judgment gating unit.

[0058] The read operation judgment selection unit receives the read enable signal output by the read interface synchronization logic unit, and the read enable signal triggers the read pointer counting unit to count and obtain the read pointer of the communication module. In practical applications, the address range allocated by the reallocation unit to the communication module will be connected to the read pointer counting unit allocated to the corresponding communication module. For example, the start address 1 and end address 1 of communication module 1 will be passed to the read pointer counting unit configured for communication module 1. The read pointer counting unit counts within the address range allocated by the communication module, that is, the change range of the read pointer is within the address range composed of the start address and end address allocated by the communication module. The read pointer counting unit outputs the obtained read pointer to the second path selector.

[0059] The read operation arbitration judgment unit receives the read enable signals sent by all read interfaces for arbitration judgment, and feeds back the arbitration result to the corresponding second waiting control unit, wherein the arbitration result here refers to the read permission of the read interface of the communication module. For example, the read operation arbitration judgment unit performs permission arbitration on the received read enable signal 1 of the communication module, obtains arbitration feedback 1, and returns arbitration feedback 1 to the communication module 1 through the second waiting control unit.

[0060] In one embodiment, the read operation arbitration judgment unit determines the read permission of the read interface according to the arbitration judgment priority. The read operation arbitration judgment unit determines which read interface can obtain the read permission according to the arbitration judgment priority. This process ensures that when multiple read interfaces request read operations at the same time, arbitration can be performed in an orderly manner to avoid conflicts and maintain data consistency. The read operation arbitration judgment unit performs arbitration judgment on the read interface that sends the read enable signal according to the preset arbitration judgment priority, wherein the priority rule can be a fixed priority method or a cyclic priority, etc.

[0061] In one embodiment, the arbitration judgment priority used by the read operation arbitration judgment unit is controlled by the reallocation unit, and one of the fixed priority and the cyclic priority is selected as the arbitration judgment priority of the read operation arbitration judgment unit. In practical applications, the reallocation unit can set a default arbitration judgment priority when the system is initialized, and can also receive configuration commands through an external interface, which are used to modify the arbitration judgment priority, so that the reallocation unit can set different arbitration judgment priorities and dynamically adjust the arbitration judgment priority at runtime to adapt to different application scenarios and requirements.

[0062] The second waiting control unit reads the read permission of the read interface (i.e. Figure 3 The arbitration feedback in the FIFO determines whether the read interface obtains the read permission. If the read interface does not obtain the read permission, a wait signal is output to put the read interface into a wait state until the read interface obtains the read permission. If the read interface obtains the read permission, the read interface can perform a read operation and read data from the FIFO memory.

[0063] After performing arbitration, the read operation arbitration judgment unit further outputs an identifier corresponding to the read interface that has obtained the read permission (ie, the read interface ID).

[0064] The second path selector receives the identifier from the read operation arbitration judgment unit, and selects the corresponding read interface path according to the received identifier, and transmits the relevant data of the read interface with read permission to other modules or units. Figure 2 As shown, the second path selector is connected to the relevant data of the read interfaces of all communication modules. Assuming that the read interface of communication module 1 has read permission, the second path selector selects the relevant read interface path of communication module 1, and the second path selector outputs the relevant data about the read interface of communication module 1.

[0065] The output of the second path selector can be received by the FIFO memory, so that relevant data can be read from the FIFO memory according to the data. In addition, the output of the second path selector can also be received by the empty and full state judgment module, so that the empty and full state judgment module can correctly update the empty and full state of the storage space allocated by the communication module to ensure the correct storage and reading of data.

[0066] The FIFO memory is connected to the write operation judgment gating unit, and can obtain the relevant data of the write interface with write permission, so that the FIFO memory can store the data written by the write interface with write permission in the address range allocated by the communication module with write permission. Figure 1As shown, the relevant data of the write interface with write permission includes the write pointer, write data and write enable signal of the communication module with write permission. These three parameters can realize writing data to the FIFO memory, wherein the write pointer address is the specific address where the data needs to be written in the FIFO memory, the write data is the data information actually to be written into the FIFO memory, and the write enable signal is a control signal used to indicate whether the FIFO memory is allowed to perform a write operation. When the write enable signal is high (logic 1), the FIFO memory allows data to be written; when the write enable signal is low (logic 0), the FIFO memory will ignore the write request.

[0067] The FIFO memory is connected to the read operation judgment gating unit, and can obtain the relevant data of the read interface with read permission, so that the FIFO memory can read the data read by the read interface with read permission in the address range allocated by the communication module with read permission. Figure 1 As shown, the relevant data of the read interface with read permission includes a read pointer address and a read enable signal. These two parameters can realize reading data from the FIFO memory, wherein the read pointer address points to the location of the data to be read in the FIFO memory, and the read enable signal is a control signal used to indicate whether the FIFO memory is allowed to perform a read operation. When the read enable is high (logic 1), the FIFO memory allows data to be read; when the read enable is low (logic 0), the FIFO memory does not allow data to be read.

[0068] In practical applications, each communication module uses the same type of write interface and read interface, wherein the bit width of the read and write data of the communication module needs to be equal to or smaller than the effective bit width of the FIFO memory.

[0069] See also Figure 1 As shown, the empty and full state judgment module is connected to the write operation judgment gating unit in the write operation control module, and obtains the relevant data of the write interface that has obtained the write permission, including the write pointer of the communication module that has obtained the write permission, through the write interface path selected by the write operation judgment gating unit. The empty and full state judgment module is also connected to the reconfiguration unit to obtain the address range of the communication module that has obtained the write permission.

[0070] It can be understood that the address range of the communication module is the space where the write interface of the communication module can write data to the FIFO memory, and the write pointer address is the location where the latest written data is recorded. Based on this, the empty and full status judgment module can determine whether the storage space of the communication module is full by comparing the write pointer and the read pointer within the address range of the communication module that has obtained write permission.

[0071] In actual applications, the full flag output by the empty and full status judgment module will be returned to the communication module. The full flag can indicate that the storage space allocated by the communication module has reached its capacity limit and can no longer be written. This is very important for ensuring data integrity and normal operation of the system.

[0072] Similarly, the empty and full status judgment module is also connected to the read operation judgment gating unit in the read operation control module, and obtains the relevant data of the read interface that has obtained the read permission, including the read pointer of the communication module that has obtained the read permission, through the read interface path selected by the read operation judgment gating unit, and the read pointer is the location where the latest data is read. Based on this, the empty and full status judgment module determines whether the communication module is empty by comparing the read pointer with the write pointer within the address range of the communication module that has obtained the read permission.

[0073] In actual applications, the empty flag output by the empty and full status judgment module will be returned to the communication module. The empty flag can indicate that the storage space allocated by the communication module does not store any data and can no longer be read, thereby avoiding reading invalid or erroneous data.

[0074] In this embodiment, writing data may cause the storage space of the communication module to change from a never-full state to a full state, and reading data may cause the storage space of the communication module to change from a non-empty state to an empty state. Therefore, the empty and full state judgment module can judge the empty and full state of the storage space of the communication module after each write operation and read operation, thereby being able to timely and accurately reflect the actual usage status of the storage space and ensure the correct processing of data.

[0075] See also Figure 4 As shown, Figure 4 The internal structure diagram of the empty and full state judgment module is shown. The empty and full state judgment module can be divided into a full state judgment circuit and an empty state judgment circuit according to its function.

[0076] The structure of the full state judgment circuit is described in detail below.

[0077] See also Figure 4As shown, the full state judgment circuit is composed of a third channel selector, a fourth channel selector, a first Gray code synchronizer and a full state judgment unit. The third channel selector and the fourth channel selector are both n-to-one channel selectors. The identifier (write interface ID) corresponding to the write interface with write permission obtained by the write operation arbitration judgment unit is output to the third channel selector and the fourth channel selector, so that the third channel selector and the fourth channel selector can select the write interface channel corresponding to the write interface with write permission according to the identifier. Among them, the third channel selector is connected to the address range of n communication modules, and each channel corresponds to the address range of a communication module. By selecting the channel corresponding to the identifier in the third channel selector, the address range of the communication module with write permission is output. The fourth channel selector is connected to the read pointers of n communication modules, and each channel corresponds to the read pointer of a communication module. Among them, the read pointers of the n communication modules here are in Figure 1 The read pointers 1-n (representing the read pointers of communication modules 1 to n) output by the read operation control module are selected by the path corresponding to the identifier in the fourth path selector to output the read pointer of the communication module that obtains the write permission.

[0078] Since the read pointer of the communication module with write permission is generated by the read clock domain and is a multi-bit signal, appropriate synchronization processing is required when transferring between different clock domains to avoid metastability and inconsistency. The first Gray code synchronizer synchronizes the read pointer and generates a full judgment read pointer. The basic processing of the first Gray code synchronizer is: 1) The read pointer is converted to Gray code data and sampled once with the read clock; 2) Two-level synchronous sampling is performed with the write clock; 3) Gray code data is converted to hexadecimal data.

[0079] In the write clock domain, the full state judgment unit can determine the full state of the storage space allocated by the communication module by judging the full judgment read pointer and the write pointer of the communication module that has obtained the write permission within the address range of the communication module that has obtained the write permission, wherein the write pointer here is output by the write pointer counting unit in the write operation control module. In the write operation, when the write pointer is equal to or less than but close to the full judgment read pointer, it is considered that the storage space allocated by the communication module is full, and a valid full mark is output.

[0080] In practical applications, the full flag output by the full state judgment circuit will be returned to the communication module with write permission via the path selected by the first path selector in the write operation control module.

[0081] refer to Figure 4 , the structure of the empty state judgment circuit is described in detail.

[0082] The empty state judgment circuit is composed of a fifth channel selector, a sixth channel selector, a second Gray code synchronizer and an empty state judgment unit. The fifth channel selector and the sixth channel selector are both n-to-one channel selectors. The identifier (read interface ID) corresponding to the read interface that obtains the read permission obtained by the arbitration of the read operation arbitration judgment unit is output to the fifth channel selector and the sixth channel selector, so that the fifth channel selector and the sixth channel selector can select the read interface channel corresponding to the read interface that obtains the read permission according to the identifier. Among them, the fifth channel selector is connected to the address range of n communication modules, and each channel corresponds to the address range of a communication module, wherein the write pointers of the n communication modules here are in Figure 1 The write pointers 1-n (representing the write pointers of communication modules 1 to n) output by the write operation control module are selected by the path corresponding to the identifier in the fifth path selector to output the address range of the communication module that has obtained the read permission. The sixth path selector is connected to the write pointers of n communication modules, each path corresponds to the write pointer of a communication module, and the path corresponding to the identifier in the sixth path selector is selected to output the write pointer of the communication module that has obtained the read permission.

[0083] Since the write pointer of the communication module that obtains read permission is generated by the write clock domain and is a multi-bit signal, appropriate synchronization processing is required when transferring between different clock domains to avoid metastability and inconsistency. The second Gray code synchronizer synchronizes the write pointer and generates a null judgment read pointer. Among them, the basic processing process of the second Gray code synchronizer is: 1) The write pointer is converted to Gray code data and sampled once with the write clock; 2) Two-level synchronous sampling is performed with the read clock; 3) Gray code data is converted to hexadecimal data.

[0084] In the write clock domain, the empty state judgment unit judges through the empty judgment write pointer and the read pointer of the communication module that obtains the read permission, wherein the read pointer is output by the read pointer counter in the read operation control module, and the empty state of the storage space allocated by the communication module can be determined. In the read operation, when the read pointer is equal to the empty judgment write pointer, it is considered that the storage space allocated by the communication module is empty, and the output empty flag is valid.

[0085] In practical applications, the empty flag output by the empty state judgment circuit will be returned to the communication module with read permission via the read interface path selected by the second path selector in the write operation control module.

[0086] In the above embodiment, the FIFO memory read and write processing circuit is configured with a FIFO memory shared by all communication modules. The storage space allocated to each communication module in the FIFO memory is divided by a configurable module, and the clock synchronization is performed on the read and write interfaces of different clock domains. An independent write operation control module and a read operation control module are configured to control the read and write operations of different clock domains, so that the communication modules in different clock domains can initiate read and write operations on the FIFO memory, which effectively improves the utilization rate of the storage resources of the FIFO memory and reduces the total size of the FIFO memory.

[0087] In one embodiment, a chip is provided, the chip including a FIFO memory read and write processing circuit.

[0088] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or equipment (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or equipment and execute instructions), or in combination with these instruction execution systems, devices or equipment. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or equipment, or in combination with these instruction execution systems, devices or equipment. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and editable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0089] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0090] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0091] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0092] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A FIFO memory read and write processing circuit, characterized in that: The FIFO memory read and write processing circuit comprises: a write operation control module, a read operation control module, a configurable module, an empty and full state judgment module and a dual-port access FIFO memory; the write operation control module and the read operation control module are respectively connected to the configurable module, the empty and full state judgment module and the FIFO memory; The configurable module includes a synchronization definition unit and a reallocation unit; the synchronization definition unit is used to manage the clock synchronization of the write interface and the read interface of the communication module in different clock domains; the reallocation unit is used to store the address range allocated to each of the communication modules in the FIFO memory; The write operation control module is connected to the write interface of the communication module, and is composed of a write interface synchronization logic unit and a write operation judgment and gating unit connected to each other; the write interface synchronization logic unit is used to perform the write operation synchronization of the write interface according to the clock synchronization determined by the synchronization definition unit; the write operation judgment and gating unit is used to determine the write permission of the write interface and gating the write interface path corresponding to the write interface with the write permission; The read operation control module is connected to the read interface of the communication module, and is composed of a read interface synchronization logic unit and a read operation judgment gating unit connected to each other; the read interface synchronization logic unit is used to perform the read operation synchronization of the read interface according to the clock synchronization determined by the synchronization definition unit; the write operation judgment gating unit is used to determine the read permission of the read interface and gating the read interface path corresponding to the read interface with the read permission; The empty and full state judgment module is connected to the configurable module, and is used to output a full flag according to the address range of the communication module and the write pointer and the read pointer of the communication module with write permission, and output an empty flag according to the address range of the communication module and the read pointer and the write pointer of the communication module with read permission; The FIFO memory is a storage space shared by multiple communication modules, and is used to store data written by a write interface with write permission in an address range allocated by the communication module with write permission, and to read data read by a read interface with read permission in an address range allocated by the communication module with read permission; Wherein, the clock synchronization is determined by the synchronization definition unit based on a reference write clock and a reference read clock; the reference write clock is a write clock with the highest frequency and the highest occurrence frequency among the write clocks corresponding to all the communication modules; wherein, if the write clock of the communication module is the same as the reference write clock, the synchronization definition unit removes the write clock synchronization logic of the communication module; if the write clock of the communication module is not the same as the reference write clock, the synchronization definition unit enables the write clock synchronization logic of the communication module; The reference read clock is the read clock with the highest frequency and occurrence frequency among the read clocks corresponding to all the communication modules; wherein, if the read clock of the communication module is the same as the reference read clock, the synchronization definition unit removes the read clock synchronization logic of the communication module; if the read clock of the communication module is not the same as the reference read clock, the synchronization definition unit enables the read clock synchronization logic of the communication module.

2. The FIFO memory read / write processing circuit according to claim 1, characterized in that: The write operation judgment gating unit receives the write enable signal and write data output by the write interface synchronization logic unit; the write operation judgment gating unit includes a write pointer counting unit and a first waiting control unit, a write operation arbitration judgment unit and a first path selector configured for the write interface of each communication module; wherein, The write pointer counting unit is triggered to count by a write enable signal, and outputs a write pointer to the first path selector; The write operation arbitration judgment unit is used to perform arbitration judgment according to the write enable signal, feedback the write permission of the write interface to the first waiting control unit, and output an identifier corresponding to the write interface that obtains the write permission; The first waiting control unit is used to output a waiting signal according to the write permission of the write interface; The first path selector is used to select the corresponding write interface path according to the identifier.

3. The FIFO memory read / write processing circuit according to claim 1, characterized in that: The read operation judgment gating unit receives the read enable signal and the read data output by the read interface synchronization logic unit during the synchronous read operation; the read operation judgment gating unit includes a read pointer counting unit and a second waiting control unit configured for the read interface of each communication module, a read operation arbitration judgment unit and a second path selector; wherein, The read pointer counting unit is triggered to count by a read enable signal, and outputs a read pointer to the path selector; The read operation arbitration judgment unit is used to perform arbitration judgment according to the read enable signal, feedback the read permission of the read interface to the second waiting control unit, and output an identifier corresponding to the read interface that obtains the read permission; The second waiting control unit is used to execute a read operation or output a waiting signal according to the read permission of the read interface; The second path selector is used to select the corresponding read interface path according to the identifier.

4. The FIFO memory read / write processing circuit according to claim 1, characterized in that: The empty and full state judgment module is composed of a full state judgment circuit and an empty state judgment circuit; The full state judgment circuit comprises a third path selector, a fourth path selector, a first Gray code synchronizer and a full state judgment unit; the third path selector and the fourth path selector are used to select the write interface path corresponding to the write interface with write permission; wherein one path in the third path selector corresponds to an address range of the communication module; one path in the fourth path selector corresponds to a read pointer of the communication module; the first Gray code synchronizer is used to convert the read pointer output by the fourth path selector into a full judgment read pointer; the full state judgment unit is used to judge the full judgment read pointer and the write pointer corresponding to the communication module with write permission, and output a full flag; The empty state judgment circuit includes a fifth path selector, a sixth path selector, a second Gray code synchronizer and an empty state judgment unit; the fifth path selector and the sixth path selector are used to select the read interface path corresponding to the read interface with read and write permissions; wherein one path in the fifth path selector corresponds to an address range of the communication module; one path in the sixth path selector corresponds to a write pointer of the communication module; the second Gray code synchronizer is used to convert the write pointer output by the sixth path selector into an empty judgment write pointer; the empty state judgment unit is used to judge the empty judgment write pointer and the read pointer corresponding to the communication module with read permissions, and output an empty flag.

5. The FIFO memory read / write processing circuit according to claim 1, characterized in that: The reallocation unit is a configuration register; the address range of each communication module defined in the configuration register is independent of each other.

6. The FIFO memory read / write processing circuit according to claim 2, characterized in that: The read permission of the read interface and the write permission of the write interface are determined by arbitration priorities.

7. The FIFO memory read / write processing circuit according to claim 6, characterized in that: The arbitration priority is controlled by the reallocation unit.

8. The FIFO memory read / write processing circuit according to claim 1, characterized in that: The write operation determination gating unit determines a write interface with write permission within an operation cycle; the read operation determination gating unit determines a read interface with read permission within an operation cycle.

9. A chip, characterized in that: A FIFO memory read / write processing circuit comprising any one of claims 1 to 8.

Images