Semiconductor chip dicing method

Abstract

The present invention discloses a semiconductor chip dicing method, which relates to the field of semiconductor technology. The method comprises: placing a target semiconductor wafer on a dicing machine to obtain a positioning authentication result; when the positioning authentication result is authentication passed, activating a high-speed camera to obtain a wafer surface image; performing mountain simulation to determine multiple shape features and multiple warping features of multiple divided areas; performing dicing path identification to determine a first dicing path; performing dicing parameter determination at multiple key dicing points to obtain multiple key dicing parameter sets, and performing chip dicing of the target semiconductor wafer. The present invention solves the technical problem of low dicing accuracy and efficiency in the prior art when processing irregularly shaped or warped semiconductor chips, and achieves the technical effect of significantly improving dicing accuracy and efficiency through precise positioning and feature identification.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a semiconductor chip dicing method. Background Art

[0002] Semiconductor chip dicing is an important link in semiconductor manufacturing, and its purpose is to divide the wafer into individual chips. Traditional dicing methods often have some problems when facing irregularly shaped or warped semiconductor chips, such as unstable cutting quality and low production efficiency. With the continuous development of semiconductor technology, the integration and performance requirements of chips are getting higher and higher, which also poses higher challenges to the accuracy and reliability of dicing technology. For example, when dealing with highly curved chips, traditional methods may have difficulty in ensuring cutting accuracy, resulting in chip damage or performance degradation. In addition, modern semiconductor manufacturing usually requires large-scale production, so improving production efficiency is also crucial. Traditional dicing methods may have shortcomings in production speed and degree of automation, and cannot meet market demand.

[0003] The prior art has technical problems of low dicing accuracy and efficiency when processing irregularly shaped or warped semiconductor chips. Summary of the invention

[0004] The present application provides a semiconductor chip dicing method, which is used to solve the technical problems of low dicing accuracy and efficiency when processing irregularly shaped or warped semiconductor chips in the prior art.

[0005] In view of the above problems, the present application provides a semiconductor chip dicing method, the method comprising:

[0006] A target semiconductor wafer is placed on a dicing machine using a multi-material clamp, and wafer positioning authentication is performed after placement to obtain a positioning authentication result; when the positioning authentication result is authentication passed, a high-speed camera is activated to collect a surface image of the target semiconductor wafer to obtain a wafer surface image; a mountain simulation is performed on the wafer surface image, and the obtained simulated mountain is divided into regions to determine multiple shape features and multiple warping features of multiple divided regions; a chip dicing task of the target semiconductor wafer is interactively performed, and a dicing path is identified in combination with the multiple shape features and multiple warping features of the wafer surface image to determine a first dicing path, wherein the first dicing path includes multiple key dicing points; dicing parameters are determined at the multiple key dicing points according to the direction of the first dicing path to obtain multiple key dicing parameter sets; and chip dicing of the target semiconductor wafer is performed according to the first dicing path, the multiple key dicing points, and the multiple key dicing parameter sets.

[0007] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0008] The target semiconductor wafer is placed on the dicing machine using a multi-material clamp, and wafer positioning certification is performed to obtain a positioning certification result; when the positioning certification result is a certification pass, a high-speed camera is activated to obtain a wafer surface image; a mountain simulation is performed, and the obtained simulated mountain is divided into regions to determine multiple shape features and multiple warping features of multiple divided regions; the chip dicing task of the target semiconductor wafer is interactively performed to determine the first dicing path; the dicing parameters are determined at the multiple key dicing points according to the direction of the first dicing path to obtain multiple key dicing parameter sets; the chip dicing of the target semiconductor wafer is performed according to the first dicing path, multiple key dicing points and multiple key dicing parameter sets. The technical effect of significantly improving the accuracy and efficiency of dicing is achieved through precise positioning and feature recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 A schematic diagram of a process flow of a semiconductor chip dicing method provided in an embodiment of the present application;

[0011] Figure 2 A schematic diagram of a process for determining a first cutting path in a semiconductor chip cutting method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] The present application provides a semiconductor chip dicing method, which is used to solve the technical problems of low dicing accuracy and efficiency when processing irregularly shaped or warped semiconductor chips in the prior art.

[0013] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0014] Examples, such as Figure 1 As shown, the present application provides a semiconductor chip dicing method, the method comprising:

[0015] Step S100: placing the target semiconductor wafer on a dicing machine using a multi-material clamp, and performing wafer positioning authentication after the placement is completed to obtain a positioning authentication result.

[0016] Specifically, a multi-material clamp is used to clamp the target semiconductor wafer and place it on the dicing machine. After placement, the wafer is positioned and certified to ensure that the wafer is accurately positioned on the dicing machine. Multiple positioning points are determined based on the size and model of the target semiconductor wafer. When the wafer is placed, the position information of these positioning points is collected to obtain multiple positioning information. Then, wafer positioning certification is performed based on these positioning information, and the position of the wafer meets the requirements by comparing and analyzing with the preset standard position information. Finally, the positioning certification result is obtained, which will indicate whether the positioning of the wafer has passed the certification. If the certification is passed, subsequent operations can be performed; if the certification is not passed, it is necessary to readjust the position of the wafer or check whether the relevant equipment is normal.

[0017] Step S200: When the positioning authentication result is authentication passed, a high-speed camera is activated to collect a surface image of the target semiconductor wafer to obtain a wafer surface image.

[0018] Specifically, when the positioning certification result shows that the certification is passed, the operation of activating the high-speed camera will be started. At this time, the high-speed camera begins to collect surface images of the target semiconductor wafer. The high-speed camera has the ability to capture images quickly and can obtain detailed information on the wafer surface in a short time. During the acquisition process, the camera will shoot the entire surface of the wafer to ensure that no important areas are missed. Through the precise shooting of the high-speed camera, the image of the wafer surface is finally obtained. These images will contain various features of the wafer surface, such as texture, defects, flatness, etc., which provide an important basis for subsequent analysis and processing.

[0019] Step S300: performing mountain simulation on the wafer surface image, dividing the obtained simulated mountain into regions, and determining a plurality of shape features and a plurality of warping features of a plurality of divided regions.

[0020] Specifically, a mountain simulation is performed on the wafer surface image, and the pixel points and pixel values ​​of the pixel points are extracted from the wafer surface image to obtain multiple pixel points and multiple pixel values, wherein the multiple pixel points include multiple position identifiers, and each pixel point corresponds to a pixel value. Then, the wafer surface image is regarded as a simulated mountain, and the multiple pixel values ​​are used as the multiple mountain heights of the multiple mountains in the simulated mountain. Next, the mountain corresponding to the minimum value of the multiple mountain heights is taken as the first mountain, and the first mountain is used as the watering point to fill the simulated mountain with water. As the amount of water filling increases, the water level rises accordingly. When it covers any mountain, the difference in mountain height between it and the first mountain is calculated. If the calculated result is less than or equal to the preset mountain height difference, continue to fill the simulated mountain with water; if the calculated result is greater than or equal to the preset mountain height difference, generate a dividing ridge line between it and the first mountain, and continue to fill the simulated mountain with water. As the amount of water increases, the water surface and the dividing ridge line rise accordingly. When it submerges any mountain again, the mountain height difference calculation continues until it submerges the mountain corresponding to the maximum value of the height of multiple mountains, and multiple dividing ridge lines are obtained. The simulated mountain is divided into regions according to these dividing ridge lines to obtain multiple simulated mountain division regions, and based on the mapping positions of the multiple simulated mountain division regions in the wafer surface image, multiple division regions of the wafer surface image are obtained. After the region division is completed, multiple division regions are traversed to search for neighbor regions to obtain multiple first-level neighbor division region sets, where the first-level neighbor division region is the region adjacent to each division region, and each neighbor division region set corresponds to a division region. Based on multiple first-level neighbor division region sets, neighbor region searches are performed to obtain multiple second-level neighbor region sets. A feature recognition module is used to traverse multiple partitioned areas, multiple first-level neighbor partitioned area sets, and multiple second-level neighbor partitioned area sets to identify shape features and warping features, and multiple partitioned area shape features, multiple first-level neighbor partitioned area shape feature sets, and multiple second-level neighbor partitioned area shape feature sets, as well as multiple partitioned area warping features, multiple first-level neighbor partitioned area warping feature sets, and multiple neighbor partitioned area warping feature sets are obtained. According to the initial multi-level weights, weighted calculations are performed on the multiple partitioned area shape features, multiple first-level neighbor partitioned area shape feature sets, and multiple second-level neighbor partitioned area shape feature sets, as well as multiple partitioned area warping features, multiple first-level neighbor partitioned area warping feature sets, and multiple neighbor partitioned area warping feature sets to obtain multiple initial shape features and multiple initial warping features of the multiple partitioned areas. Feature fuzzy authentication is performed on the multiple initial shape features and the multiple initial warping features. If the authentication is passed, the multiple initial shape features and the multiple initial warping features are used as multiple shape features and multiple warping features respectively.

[0021] Step S400: interacting with the chip dicing task of the target semiconductor wafer, identifying a dicing path in combination with a plurality of shape features and a plurality of warping features of the wafer surface image, and determining a first dicing path, wherein the first dicing path includes a plurality of key dicing points.

[0022] Specifically, the chip dicing task, multiple shape features and multiple warping features are analyzed by a dicing path identifier. By comprehensively considering these factors, the identifier can determine the optimal dicing path, that is, the first dicing path. In the process of determining the first dicing path, multiple key dicing points are also determined. First, the first dicing path is segmented according to multiple divided areas to obtain a set of segmentation points. Then, in combination with multiple shape features and multiple warping features, the segmentation point set is traversed to perform feature difference analysis of the front and rear sections, thereby obtaining a difference set. Finally, the difference set is sorted in order from large to small, and the segmentation points corresponding to the differences in the first m positions are used as multiple key dicing points, where m is an integer greater than or equal to 3. The first dicing path and multiple key dicing points determined in this way can better adapt to the shape and warping characteristics of the wafer and improve the accuracy and efficiency of dicing.

[0023] Step S500: determining scribing parameters at the plurality of key scribing points according to the direction of the first scribing path to obtain a plurality of key scribing parameter sets.

[0024] Specifically, the marking sections located after the multiple key marking points according to the direction of the first marking path are used as the marking sections corresponding to the multiple key marking points, thereby obtaining multiple marking sections. According to the positions of the multiple divided areas, the multiple divided area sets included in the multiple marking sections are determined, wherein the multiple divided area sets include multiple shape feature sets and multiple warping feature sets. Then, the multiple shape feature sets and the multiple warping feature sets are traversed to perform feature concentration processing to obtain multiple concentrated shape features and multiple concentrated warping features of the multiple marking sections. Finally, based on the multiple concentrated shape features and the multiple concentrated warping features, a marking parameter analysis is performed, and the most appropriate marking parameters are determined by comprehensively considering factors such as shape and warping. These marking parameters are combined together to obtain multiple key marking parameter sets.

[0025] Step S600: performing chip dicing of the target semiconductor wafer according to the first dicing path, a plurality of key dicing points and a plurality of key dicing parameter sets.

[0026] Specifically, strictly follow the guidance of the first dicing path and diced the wafer along the path. During the dicing process, when multiple key dicing points are reached, the specific method of dicing is adjusted according to the parameters in the corresponding multiple key dicing parameter sets to ensure the accuracy and quality of dicing. These key dicing parameter sets are carefully determined based on factors such as the shape characteristics and warping characteristics of the wafer, which can make the dicing process better adapt to the characteristics of the wafer, thereby improving the accuracy and effect of chip dicing. In this way, the chip dicing work of the target semiconductor wafer can be completed efficiently and accurately to meet production needs.

[0027] In a possible implementation, step S300 further includes:

[0028] Step S310: extracting pixels and pixel values ​​of the wafer surface image to obtain a plurality of pixels and a plurality of pixel values, wherein the plurality of pixels include a plurality of position identifiers, and each pixel corresponds to a pixel value.

[0029] Step S320: using the wafer surface image as a simulated mountain, and using the plurality of pixel values ​​as a plurality of mountain heights of a plurality of mountains in the simulated mountain.

[0030] Step S330: The mountain corresponding to the minimum value of the heights of the multiple mountains is taken as the first mountain, and the first mountain is used as the watering point to fill the simulated mountain with water. As the watering amount increases, the water level rises accordingly. When any mountain is submerged, the difference in mountain height between the first mountain and the first mountain is calculated. If the calculated result is less than or equal to the preset mountain height difference, continue to fill the simulated mountain with water.

[0031] Step S340: If the calculated result is greater than or equal to the preset mountain height difference, a dividing ridge line is generated between it and the first mountain, and water is continued to be poured into the simulated mountain. As the amount of water poured increases, the water level and the dividing ridge line rise accordingly. When any mountain is submerged again, the mountain height difference calculation continues until the mountains corresponding to the maximum values ​​of multiple mountain heights are submerged, and multiple dividing ridge lines are obtained.

[0032] Step S350: Divide the simulated mountain into regions according to the multiple dividing ridge lines to obtain multiple simulated mountain divided regions, and map the positions of the multiple simulated mountain divided regions in the wafer surface image to obtain multiple divided regions of the wafer surface image.

[0033] Specifically, the watershed algorithm is used to process the wafer surface image in detail. The watershed algorithm is an effective method commonly used for image segmentation. It can segment the image into different areas according to the grayscale, texture and other features of the image. First, the algorithm scans and analyzes the wafer surface image pixel by pixel. For each pixel, the algorithm detects the features of the surrounding pixels, including grayscale value, color and other information. Based on these features, the algorithm determines the similarity and difference between the pixel and the surrounding pixels. If the feature differences between the pixels are large, the algorithm will consider that they belong to different areas, and thus establish a segmentation line between these pixels, just like a watershed to segment the image into different parts. In this way, the algorithm can accurately identify each pixel in the wafer surface image and obtain their location identifiers. At the same time, the algorithm also records the pixel value of each pixel. The pixel value reflects the specific information of the pixel in the image, such as brightness and color. For example, if the pixel value of some pixels is high, it means that there is a strong reflection or a bright object in the area; while the area with a low pixel value may indicate the presence of a shadow or a darker object. By using the watershed algorithm to extract pixel points and pixel values, detailed information on the wafer surface image can be obtained, providing an accurate data basis for subsequent steps such as area division, shape feature and warpage feature analysis.

[0034] The wafer surface image is uniquely simulated and processed, and the wafer surface image is imagined as a simulated mountain scene, in which each pixel in the image corresponds to a position in the simulated mountain, and the multiple pixel values ​​extracted previously are given new meanings, which are regarded as the mountain heights of multiple mountains in the simulated mountain. This simulation method allows the characteristics of the wafer surface to be presented in an image-based way. The pixel value of each pixel determines the height of the corresponding mountain in the simulated mountain. The pixel with a larger pixel value corresponds to a higher mountain height; the pixel with a smaller pixel value corresponds to a lower mountain height. In this way, the ups and downs, light and dark changes of the wafer surface are converted into the difference in mountain height in the simulated mountain. This simulation provides an intuitive model for subsequent regional division and feature analysis, which helps to understand the structure and characteristics of the wafer surface more deeply, thereby providing a more accurate basis for operations such as chip dicing.

[0035] Determine the mountain corresponding to the minimum value among multiple mountain heights, and mark it as the first mountain. Then, take the first mountain as the watering point and start watering the simulated mountain. As the amount of water gradually increases, the water level will rise accordingly. When the water surface covers any mountain, the mountain height difference between the mountain and the first mountain will be calculated. Compare the calculated mountain height difference with the preset mountain height difference. If the calculated result is less than or equal to the preset mountain height difference, it means that the height difference between the mountain and the first mountain is within an acceptable range. At this time, water will continue to be poured into the simulated mountain to further observe and analyze the situation of the mountain. Through such steps, the relative height relationship of each mountain in the simulated mountain is gradually understood, which provides an important basis for subsequent regional division and feature analysis. At the same time, the setting of the preset mountain height difference can be adjusted according to actual needs and experience to ensure the accuracy and reliability of the analysis results.

[0036] If the calculated mountain height difference is greater than or equal to the preset mountain height difference, it means that the height difference between the mountain and the first mountain exceeds the acceptable range. At this time, a dividing ridge line will be generated between the mountain and the first mountain to divide different areas. Continue to pour water into the simulated mountain. As the amount of water increases, the water surface and the dividing ridge line will rise accordingly. When the water surface submerges any mountain again, the mountain height difference is calculated again. This process will continue until the water surface submerges the mountain corresponding to the maximum value of the height of multiple mountains. In this process, dividing ridge lines will be continuously generated to obtain multiple dividing ridge lines. The generation of these dividing ridge lines helps to simulate the mountain for regional division, separates mountains with different height characteristics, and provides an important basis for the subsequent determination of multiple divided areas of the wafer surface image. In this way, the terrain characteristics of the wafer surface can be analyzed and understood more accurately, thereby providing more precise guidance for operations such as semiconductor chip dicing.

[0037] The simulated mountain is divided into regions according to the multiple dividing ridge lines generated previously. These dividing ridge lines divide the simulated mountain into multiple different parts, thereby obtaining multiple simulated mountain division regions. Each division region has relatively unique terrain features and is surrounded by dividing ridge lines. Based on the determination of the mapping positions of these multiple simulated mountain division regions in the wafer surface image, by corresponding the division regions of the simulated mountain with the wafer surface image, the specific positions of these division regions on the wafer surface image can be accurately found. In this way, multiple division regions of the wafer surface image are obtained, which correspond to the division regions of the simulated mountain, reflecting the characteristics and properties of different parts of the wafer surface. In this way, the conversion from the regional division of the simulated mountain to the wafer surface image is realized, which provides a basis for the subsequent further analysis and processing of the wafer surface image. For example, the shape characteristics and warping characteristics of each division region can be analyzed to better understand the characteristics of the wafer, thereby providing a more accurate basis for operations such as semiconductor chip dicing.

[0038] In a possible implementation, step S300 further includes:

[0039] Step S360: traverse the multiple divided areas to perform neighbor area search, and obtain multiple first-level neighbor divided area sets, wherein the first-level neighbor divided area is an area adjacent to each divided area, and each neighbor divided area set corresponds to one divided area; based on the multiple first-level neighbor divided area sets, perform neighbor area search to obtain multiple second-level neighbor area sets; use the feature recognition module to traverse the multiple divided areas, multiple first-level neighbor divided area sets, and multiple second-level neighbor divided area sets to perform shape feature and warping feature recognition, and obtain multiple divided area shape features, multiple first-level neighbor divided area shape feature sets, and multiple second-level neighbor divided area shape feature sets, as well as multiple divided area warping features, multiple A first-level nearest neighbor division area warping feature set and multiple nearest neighbor division area warping feature sets; performing weighted calculations on the multiple division area shape features, multiple first-level nearest neighbor division area shape feature sets and multiple second-level nearest neighbor division area shape feature sets, as well as multiple division area warping features, multiple first-level nearest neighbor division area warping feature sets and multiple nearest neighbor division area warping feature sets according to initial multi-level weights to obtain multiple initial shape features and multiple initial warping features of multiple division areas; performing feature fuzzy authentication on the multiple initial shape features and the multiple initial warping features, and if the authentication is passed, the multiple initial shape features and the multiple initial warping features are respectively used as the multiple shape features and the multiple warping features.

[0040] Specifically, neighboring regions are searched for multiple partitioned regions one by one, and for each partitioned region, adjacent regions are searched. These adjacent regions constitute the first-level neighboring partitioned regions. It should be noted that each partitioned region has a corresponding set of neighboring partitioned regions, which includes all regions adjacent to the partitioned region. Through such a search, the first-level neighboring partitioned region set of each partitioned region is determined, providing a basis for subsequent analysis and processing. For example, if there is a partitioned region A, then the regions adjacent to A will be searched, and these regions will be combined into the first-level neighboring partitioned region set of A. Similarly, similar operations will be performed on other partitioned regions, and multiple first-level neighboring partitioned region sets will eventually be obtained.

[0041] Taking the multiple first-level neighbor partition area sets obtained previously as the benchmark, further search for neighbor areas is performed. For each area in the first-level neighbor partition area set, their adjacent areas are searched again. These adjacent areas constitute the second-level neighbor areas. All these second-level neighbor areas are combined together to obtain multiple second-level neighbor area sets. For example, for area B in a first-level neighbor partition area set, the adjacent areas of B will be searched. These adjacent areas may be different from the previously divided areas, and they constitute the second-level neighbor areas of B. The same operation is performed on the areas in other first-level neighbor partition area sets, and finally multiple second-level neighbor area sets are obtained. Such operations can further expand the understanding of the adjacent relationship between regions and provide more comprehensive information for subsequent analysis and processing.

[0042] After the divided areas have been obtained, in order to more accurately analyze the shape and warping characteristics of each divided area, a series of operations are started using the feature recognition module. The feature recognition module traverses multiple divided areas, and for each divided area, its shape and warping characteristics are deeply analyzed by the graph neural network. The graph neural network can take into account the connection relationship between the divided areas, because in the cutting process, the divided areas are usually connected, and there is a mutual influence relationship between adjacent divided areas. This connection relationship can be represented by the nodes and edges of the graph, each divided area as a node, and the connection between adjacent areas as an edge. Next, the feature recognition module traverses multiple first-level neighbor divided area sets. For each area in each set, the graph neural network is also used to identify its shape features, and these features are combined to form multiple first-level neighbor divided area shape feature sets. Similar operations are also performed on the warping features to obtain multiple first-level neighbor divided area warping feature sets. Then, multiple second-level neighbor divided area sets are traversed, and the graph neural network is used to identify the shape features of these areas to obtain multiple second-level neighbor divided area shape feature sets, and the warping features are identified to obtain multiple neighbor divided area warping feature sets. In this way, graph neural networks can more accurately capture the shape and warping characteristics of each divided area and its adjacent areas, providing more reliable data support for subsequent operations.

[0043] The initial multi-level weights are determined, and these weights will be used to perform weighted calculations on shape features and warping feature sets at different levels. For multiple partitioned area shape features, corresponding weights are assigned according to their importance. These shape features directly reflect the shape characteristics of each partitioned area. For multiple first-level neighbor partitioned area shape feature sets, specific weights are also given considering their adjacent relationship with each partitioned area and the possible impact on it. These sets contain shape feature information of areas adjacent to each partitioned area. Similarly, for multiple second-level neighbor partitioned area shape feature sets, corresponding weights are also assigned in view of their association with the partitioned area in a wider range. In terms of warping features, weights are also assigned to multiple partitioned area warping features, multiple first-level neighbor partitioned area warping feature sets, and multiple neighbor partitioned area warping feature sets according to their importance and influence. Then, through weighted calculation, the shape features and warping feature sets at different levels are integrated. For each partitioned area, its own shape features are weightedly fused with the shape feature sets of the first-level and second-level neighbor partitioned areas to obtain multiple initial shape features of the partitioned area. Similarly, a similar weighted fusion is performed on the warping features to obtain multiple initial warping features. Such a weighted calculation process can fully consider the feature information at different levels and their interrelationships, providing more accurate and comprehensive initial feature data for subsequent feature analysis and processing.

[0044] The obtained multiple initial shape features and multiple initial warpage features are subjected to feature fuzzy authentication, and a set of authentication standards and methods are established to evaluate the reliability and applicability of these initial features. For multiple initial shape features, they are analyzed and compared one by one to check whether they conform to the actual shape feature performance of the wafer surface and whether there are any abnormal or unreasonable situations. At the same time, considering the fuzziness and uncertainty of the shape features, an appropriate fuzzy authentication method is adopted to allow a certain degree of error and change. Similarly, the authentication process is also carried out for multiple initial warpage features to check whether the warpage features are consistent with the actual warpage of the wafer and whether they can accurately reflect the deformation state of the wafer. If these initial shape features and initial warpage features meet the authentication standards after authentication, the authentication is passed. Then, these multiple initial shape features and multiple initial warpage features are respectively used as the final multiple shape features and multiple warpage features, which will be used in subsequent semiconductor wafer chip dicing and other operations to provide an important basis for decision-making. Through feature fuzzy authentication, it is ensured that the obtained shape features and warpage features have a certain degree of accuracy and reliability, and reduce the wrong decisions and adverse consequences caused by inaccurate features.

[0045] In a possible implementation, step S360 further includes:

[0046] Step S361: perform feature recognition on the wafer surface image using a feature recognition module to obtain shape features and warpage features of the wafer surface image.

[0047] Step S362: performing fuzzy similarity authentication on the multiple initial shape features and the multiple initial warpage features based on the wafer surface image shape features and the wafer surface image warpage features to obtain fuzzy similarity.

[0048] Step S363: When the fuzzy similarity meets the preset similarity threshold, the authentication is successful.

[0049] Specifically, the feature recognition module uses the Canny edge detection algorithm to identify the shape features of the wafer surface image, performs Gaussian filtering on the wafer surface image to remove noise, then calculates the gradient amplitude and direction of the image, determines the potential position of the edge through non-maximum suppression, and finally uses double threshold detection and edge connection to determine the final edge. The shape of the wafer is outlined by the detected edges, and then its shape features are analyzed, such as round, square or other irregular shapes, and whether there are bumps, depressions, scratches and other detail features. For warp feature recognition, a template matching-based method is used to prepare an ideal non-warp wafer surface template image, compare the wafer surface image to be identified with the template, determine the warp feature by calculating the difference between the two, and use image subtraction, mean square error and other methods to quantify the difference. If the difference is large, it indicates that the wafer is warped.

[0050] When fuzzy similarity authentication is performed on multiple initial shape features and initial warping features based on the shape features and warping features of the wafer surface image, the weighted algorithm can effectively comprehensively consider the importance of different features, so as to more accurately calculate the fuzzy similarity. Different weights are assigned to shape features and warping features. For example, if the shape feature is considered more important in a specific application, a higher weight can be given to the shape feature. Similarly, different initial shape features and initial warping features can also be assigned different weights according to their influence on the overall similarity, and the weights of the shape features and warping features, as well as the weights of each initial shape feature and initial warping feature, are determined. Then, the similarity between the shape features of the wafer surface image and each initial shape feature, and the similarity between the warping features of the wafer surface image and each initial warping feature are calculated respectively. For the similarity calculation of the shape features, the Euclidean distance is used, and for the similarity of the warping features, the calculation is performed based on factors such as the amplitude and direction of the warping. Then, each similarity value is multiplied by the corresponding weight and summed. For example, fuzzy similarity = shape feature weight × shape feature similarity + warping feature weight × warping feature similarity. For multiple initial shape features and initial warpage features, their similarities with the wafer surface image features are calculated respectively, and weighted summation is performed according to their weights. Through this weighted algorithm, the contribution of different features in the fuzzy similarity calculation can be adjusted more flexibly, so as to better reflect the true similarity between the wafer surface image features and the initial features of each divided area. At the same time, the weighted algorithm can also be adjusted and optimized according to the needs of actual applications to improve the accuracy and reliability of fuzzy similarity authentication.

[0051] The preset similarity threshold is a value set in advance based on specific application requirements and experience. This threshold represents the minimum requirement for the similarity between the wafer surface image features and multiple initial shape features and initial warp features. If the calculated fuzzy similarity reaches or exceeds this preset similarity threshold, it means that the wafer surface image features are sufficiently similar to the initial features of each divided area, which means that the previous extraction of shape features and warp features of multiple divided areas and the subsequent fuzzy similarity authentication are reliable. At this time, the authentication is passed, indicating that these initial shape features and initial warp features can be considered to accurately reflect the actual features of each divided area on the wafer surface. Conversely, if the fuzzy similarity is lower than the preset similarity threshold, the authentication fails.

[0052] In one possible implementation, Figure 2 As shown, step S400 also includes:

[0053] Step S410: Analyze the chip dicing task, multiple shape features, and multiple warpage features using a dicing path identifier to obtain a first dicing path.

[0054] Step S420: segment the first cutting path according to the multiple divided areas to obtain a segmentation point set.

[0055] Step S430: combining the multiple shape features and the multiple warping features, traversing the segmentation point set to perform feature difference analysis of the previous and next road sections to obtain a difference set.

[0056] Step S440: sort the difference degree sets in descending order, and use the segmentation points corresponding to the first m differences as the multiple key dividing points, where m is an integer greater than or equal to 3.

[0057] Specifically, the chip dicing task is converted into an objective function in a mathematical model. For example, the goal can be to minimize the length of the dicing path, minimize the energy consumption during the dicing process, or meet specific chip size and shape requirements. For multiple shape features and multiple warping features, they are added to the model as constraints. The shape features can be represented by parameters of the geometric shape, and the warping features can be described by the numerical value of the degree of bending. Then, the least squares method is used to solve this optimization problem. The least squares method finds the best fitting curve or path by minimizing the sum of squares of the errors. In this process, the dicing path is represented as a series of parametric equations. The objective function is minimized by adjusting the parameters while satisfying the constraints of the shape and warping features. The wafer surface is divided into grids, each grid point corresponds to a coordinate, and a weight is assigned to each grid point according to the shape features and warping features to indicate the importance of the point in the dicing path. Then, the least squares method is used to fit a curve passing through these grid points so that the error between the curve and the objective function is minimized. Through continuous iteration and optimization, the least squares method can find a first dicing path that meets the requirements of the chip dicing task and fully considers multiple shape features and multiple warping features. For example, suppose the shape feature of the wafer surface is that there are some raised and recessed areas, and the warping feature is that there are large bends in some areas. When using the least squares method, the grid points in these areas are given lower weights so that the dicing path avoids these unfavorable areas as much as possible. At the same time, according to the requirements of the chip dicing task, the length and direction of the path are adjusted to achieve the optimal dicing effect.

[0058] It is clear that multiple divided areas are different areas obtained after dividing the wafer surface. These areas have different shape characteristics, warping characteristics and other specific properties. After the first dicing path is determined, the path is segmented according to these divided areas. The positions where it intersects with the boundaries of each divided area are checked in turn along the first dicing path. These intersection points are segmentation points. Collecting all such segmentation points forms a segmentation point set. For example, assuming that the wafer surface is divided into three areas A, B and C, when the first dicing path passes through these areas, it intersects with the boundaries of areas A and B at point P1, and intersects with the boundaries of areas B and C at point P2. Then points P1 and P2 become elements in the segmentation point set. Through this segmentation operation, the first dicing path is divided into multiple sections, each section corresponds to a different divided area. The advantage of this is that the characteristics and problems of the dicing path in different areas can be analyzed more carefully, providing a basis for subsequent analysis and optimization.

[0059] Collect and organize multiple shape features and multiple warpage feature data of the wafer so that they exist in a form that is easy to analyze, such as representing the shape features as a set of descriptive parameters or vectors, and representing the warpage features in numerical or specific vector form. At the same time, clarify the specific position of each segmentation point in the segmentation point set on the dicing path. For a specific segmentation point, determine the wafer area range corresponding to the sections before and after the segmentation point. Extract the shape feature parameters or vectors corresponding to the front and rear sections, calculate the similarity measure of the shape features, and calculate the cosine similarity of the two shape feature vectors. If the cosine similarity is close to 1, it means that the shapes are relatively similar and the difference is low; if it is close to 0, the difference is high. Extract the warpage feature values ​​or vectors corresponding to the front and rear sections, calculate the difference of the warpage features, and measure it with the absolute difference of the warpage values ​​of the front and rear sections. The larger the difference, the higher the difference of the warpage features. Set a weight value for each shape feature and warpage feature to reflect their importance in the overall difference, and calculate the total feature difference of the front and rear sections at the segmentation point by weighted summation. Total feature difference = shape feature weight × shape feature difference + warping feature weight × warping feature difference. The above analysis process is performed on each segmentation point in the segmentation point set to obtain the feature difference between the previous and next road sections corresponding to each segmentation point. These differences are summarized to form a difference set.

[0060] The difference set is processed, and each difference in the difference set is sorted from large to small, which means that the values ​​with larger differences will be ranked in front. Such sorting can quickly determine which segmentation points on the cutting path have the most significant feature differences between the front and rear sections. Next, the segmentation points corresponding to the differences in the first m positions are selected as multiple key cutting points, where m is an integer greater than or equal to 3, and the specific value can be adjusted according to the actual situation. The segmentation points corresponding to the first m differences are selected because these points represent the positions where the features on the cutting path change most dramatically. For example, if m is set to 5, then in the sorted difference set, the first five corresponding segmentation points with the largest differences are selected as key cutting points. These key cutting points are of great significance in the subsequent chip cutting process and require special attention and processing to ensure the accuracy and quality of the cutting. During the cutting process, the cutting parameters are adjusted for these key cutting points, and additional measures are taken to deal with the larger feature differences, thereby improving the efficiency and success rate of the entire chip cutting.

[0061] In a possible implementation, step S500 further includes:

[0062] Step S510: Divide the first marking path based on the multiple key marking points, and use the marking sections located after the multiple key marking points in the direction of the first marking path as the marking sections corresponding to the multiple key marking points to obtain multiple marking sections.

[0063] Step S520: determining a plurality of divided area sets included in the plurality of cut sections according to the positions of the plurality of divided areas, wherein the plurality of divided area sets include a plurality of shape feature sets and a plurality of warping feature sets.

[0064] Step S530: traverse the multiple shape feature sets and the multiple warping feature sets to perform feature concentration processing to obtain multiple concentrated shape features and multiple concentrated warping features of the multiple cut road sections.

[0065] Step S540: performing a cutting parameter analysis based on the multiple concentrated shape features and the multiple concentrated warpage features to determine the multiple key cutting parameter sets.

[0066] Specifically, it is clear that a plurality of key marking points have been determined, and these key marking points are important position points obtained by analyzing the characteristic differences on the marking path. The first marking path is divided based on these key marking points. According to the direction of the first marking path, the key marking points divide the path into a plurality of different sections. For each key marking point, the marking section located after the point is determined as the marking section corresponding to the key marking point.

[0067] Since the wafer has been divided into multiple areas, it is now necessary to determine the set of divided areas contained in multiple dicing sections based on the positions of these divided areas. Clarify the specific positions of each divided area on the wafer, then check each dicing section in turn to determine which divided areas the section passes through, and collect the divided areas passed by these diced sections to form a set of divided areas corresponding to each dicing section. At the same time, each divided area has its corresponding shape feature and warping feature, so this set of divided areas not only includes specific divided areas, but also includes multiple shape feature sets and multiple warping feature sets accordingly. The shape feature set is composed of the shape features of each divided area contained in the dicing section, and the warping feature set is composed of the warping features of each divided area. The advantage of this is that the specific characteristics of each dicing section can be understood more clearly. In subsequent processing, more targeted analysis and decision-making are carried out based on these shape feature sets and warping feature sets to ensure the quality and efficiency of chip dicing.

[0068] Traverse these shape feature sets and warp feature sets, and for each shape feature set corresponding to the cut section, use the method of finding the average to perform feature concentration processing. Summarize the shape features of each divided area contained in the cut section, and then calculate the average value of these shape features. The shape features include parameters such as the length, curvature, and area of ​​the contour. By finding the average, a concentrated shape feature that can represent the overall shape feature of the cut section is obtained. Similarly, for the warp feature set, the average is also processed. The warp feature values ​​of each divided area involved in the cut section are summarized, and then their average value is calculated. The warp features include the degree of curvature, the direction of warping, etc. By finding the average, a concentrated warp feature is obtained to reflect the overall warping of the cut section.

[0069] Based on multiple concentrated shape features and multiple concentrated warpage features, the dicing parameter analysis is performed. Taking into account that different shape features and warpage features will have different effects on the dicing process, appropriate dicing parameters are determined based on these features. The dicing parameters include dicing speed, dicing depth, tool pressure, etc. By analyzing multiple concentrated shape features and multiple concentrated warpage features, a set of key dicing parameters suitable for each dicing section is determined. In this way, in the actual chip dicing process, accurate dicing operations can be performed according to the characteristics of different dicing sections and the corresponding dicing parameters, thereby improving the quality and efficiency of dicing.

[0070] In a possible implementation, step S600 further includes:

[0071] Step S610: Performing scribing quality stage certification at the plurality of key scribing points.

[0072] Step S620: If the authentication is successful, continue with the cutting process.

[0073] Step S630: If the authentication fails, a cutting warning instruction is generated and processing is performed according to the cutting warning instruction.

[0074] Specifically, the key scribing points are the locations with important characteristic differences on the scribing path determined in the previous steps, which have a key impact on the quality and accuracy of chip scribing. A variety of methods and techniques are used for scribing quality stage certification. High-precision measuring instruments are used to measure the scribing depth, width, flatness and other parameters at the key scribing points, and by comparing with the preset quality standards, it is determined whether the scribing quality meets the requirements. In addition, image analysis technology is used to take pictures and analyze the scribing surface at the key scribing points to check whether there are defects such as cracks, notches, burrs, etc. Image analysis automatically detects these defects through computer vision algorithms to improve the efficiency and accuracy of certification. At the same time, combined with sensor data, such as force sensors, vibration sensors, etc., to monitor the force and vibration during the scribing process. If abnormal force or vibration occurs at the key scribing points, it means that there is a problem with the scribing quality. Through comprehensive and detailed scribing quality stage certification of multiple key scribing points, quality problems in the scribing process can be discovered and solved in a timely manner to ensure the quality and reliability of chip scribing.

[0075] If the dicing quality stage certification at the key dicing points is passed, it means that the current dicing work meets the quality requirements at these key locations. At this point, the subsequent dicing operations can continue according to the established dicing path and parameters. This ensures the consistency and stability of the dicing process and can efficiently complete the chip dicing task.

[0076] If the certification fails, it means that there is a quality problem at the key cutting point. At this time, a cutting warning instruction will be generated. This instruction triggers a series of treatment measures, such as suspending the cutting operation and notifying the operator to check and adjust. The operator analyzes the cause of the problem based on the warning information, such as tool wear, improper parameter setting, etc. Then take appropriate measures to repair it, such as replacing the tool, adjusting the cutting parameters, etc. After the problem is solved, the cutting quality stage certification can be re-performed to ensure that the cutting work can continue and meet the quality requirements.

[0077] In a possible implementation, step S100 further includes:

[0078] Step S110: determining a plurality of positioning points based on the size and model of the target semiconductor wafer.

[0079] Step S120: After the placement is completed, the location information of the multiple positioning points is collected to obtain multiple positioning information.

[0080] Step S130: performing wafer positioning authentication according to the plurality of positioning information to obtain the positioning authentication result.

[0081] Specifically, the size and model of the target semiconductor wafer should be considered first to determine multiple positioning points. For wafers of different sizes, their shapes and sizes vary. Larger wafers may require more positioning points to ensure stability and accuracy during processing. Different types of wafers have different structural characteristics. Some types of wafers have special marks or structures at the edges, which can be used as suitable positioning points. For example, some wafer models may have tiny grooves or protrusions on the edges, and these feature points can be used to determine the positioning points. The process of determining the positioning points usually needs to be combined with the actual processing requirements and the characteristics of the equipment. For example, if the processing equipment adopts a specific clamping method, the position of the positioning point should match the position of the clamping device to ensure that the wafer can be firmly fixed on the equipment. By comprehensively considering the size and model of the target semiconductor wafer, multiple positioning points that meet the processing requirements and ensure the accurate position of the wafer are determined.

[0082] Once the target semiconductor wafer is placed, it is necessary to collect the position information of the previously determined multiple positioning points. Start the corresponding position information collection equipment, optical sensors, and laser rangefinders. These devices can accurately measure the position coordinates of the positioning points in a specific coordinate system. For each positioning point, the collection equipment will accurately determine its position in three-dimensional space. The optical sensor can measure the plane coordinates (X, Y axis coordinates) of the positioning point, while the laser rangefinder measures the height coordinates (Z axis coordinates) of the positioning point. In this way, the complete position information of each positioning point can be obtained. During the collection process, it is necessary to ensure the accuracy and stability of the collection equipment. Multiple measurements are required to improve the accuracy of the position information, and the measurement results are processed and filtered to remove possible noise and errors. Finally, multiple positioning information is obtained by collecting the position information of multiple positioning points. These positioning information will serve as an important basis for subsequent wafer positioning certification to determine whether the wafer is placed in the correct position and whether it meets the processing requirements.

[0083] The collected multiple positioning information are compared with the preset standard positioning information. The standard positioning information is the ideal position information predetermined according to the size, model and processing requirements of the target semiconductor wafer. During the comparison process, the difference between the actual position and the standard position of each positioning point is calculated, and the difference is quantified by calculating the coordinate difference, distance deviation, etc. If the difference between the actual position and the standard position of all positioning points is within the acceptable error range, then the wafer positioning certification is considered to have passed. This acceptable error range is usually determined based on the processing accuracy requirements and equipment performance. If the actual position of one or more positioning points exceeds the error range, then the wafer positioning certification is considered to have failed. Finally, the positioning certification result is obtained, which is a binary judgment of pass or fail, including specific difference information and adjustment suggestions. If the certification passes, the subsequent processing steps can be continued; if the certification fails, corresponding measures need to be taken to make adjustments, such as re-placing the wafer, calibrating the equipment, or checking the acquisition system.

[0084] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description and does not represent the advantages and disadvantages of the embodiments. And the above-mentioned specific embodiments of this specification are described. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0085] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

[0086] This specification and the drawings are merely exemplary illustrations of the present application and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, a person skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application and its equivalents, the present application intends to include these modifications and variations.

Claims

1. A semiconductor chip dicing method, characterized in that: The method comprises: The target semiconductor wafer is placed on the dicing machine using a multi-material clamp, and after the placement is completed, the wafer positioning certification is performed to obtain the positioning certification result; When the positioning authentication result is authentication passed, activating a high-speed camera to collect a surface image of the target semiconductor wafer to obtain a wafer surface image; Performing mountain simulation on the wafer surface image, dividing the obtained simulated mountain into regions, and determining a plurality of shape features and a plurality of warpage features of a plurality of divided regions; Interacting with the chip dicing task of the target semiconductor wafer, identifying a dicing path in combination with a plurality of shape features and a plurality of warping features of the wafer surface image, and determining a first dicing path, wherein the first dicing path includes a plurality of key dicing points; Determine scribing parameters at the plurality of key scribing points according to the direction of the first scribing path to obtain a plurality of key scribing parameter sets; Chip dicing of the target semiconductor wafer is performed according to the first dicing path, a plurality of key dicing points and a plurality of key dicing parameter sets.

2. A semiconductor chip dicing method according to claim 1, characterized in that: Performing mountain simulation on the wafer surface image, dividing the obtained simulated mountain into regions, and determining multiple shape features and multiple warpage features of multiple divided regions, including: Extracting pixels and pixel values ​​of the pixels from the wafer surface image to obtain a plurality of pixels and a plurality of pixel values, wherein the plurality of pixels include a plurality of position identifiers, and each pixel corresponds to a pixel value; Using the wafer surface image as a simulated mountain, and using the multiple pixel values ​​as multiple mountain heights of multiple mountains in the simulated mountain; The mountain corresponding to the minimum value of the heights of the multiple mountains is taken as the first mountain, and the first mountain is used as the watering point to water the simulated mountain. As the watering amount increases, the water level rises accordingly. When any mountain is submerged, the height difference between the mountain and the first mountain is calculated. If the calculated result is less than or equal to the preset mountain height difference, continue to water the simulated mountain; If the calculated result is greater than the preset mountain height difference, a dividing ridge line is generated between it and the first mountain, and water is continuously poured into the simulated mountain. As the amount of water poured increases, the water level and the dividing ridge line rise accordingly. When any mountain is submerged again, the mountain height difference calculation is continued until the mountains corresponding to the maximum values ​​of the mountain heights are submerged, thereby obtaining multiple dividing ridge lines. The simulated mountain is divided into regions according to the multiple dividing ridge lines to obtain multiple simulated mountain divided regions, and multiple divided regions of the wafer surface image are obtained based on the mapping positions of the multiple simulated mountain divided regions in the wafer surface image.

3. A semiconductor chip dicing method as claimed in claim 2, characterized in that: Performing mountain simulation on the wafer surface image, dividing the obtained simulated mountain into regions, and determining multiple shape features and multiple warpage features of multiple divided regions, including: Traversing the plurality of partitioned areas to search for neighboring areas, and obtaining a plurality of first-level neighboring partitioned area sets, wherein the first-level neighboring partitioned areas are areas adjacent to each partitioned area, and each neighboring partitioned area set corresponds to one partitioned area; Based on the plurality of first-level neighboring divided area sets, a neighboring area search is performed to obtain a plurality of second-level neighboring area sets; Using a feature recognition module to traverse the multiple divided areas, multiple first-level neighbor divided area sets, and multiple second-level neighbor divided area sets to perform shape feature and warping feature recognition, and obtain multiple divided area shape features, multiple first-level neighbor divided area shape feature sets, and multiple second-level neighbor divided area shape feature sets, as well as multiple divided area warping features, multiple first-level neighbor divided area warping feature sets, and multiple neighbor divided area warping feature sets; According to the initial multi-level weights, weighted calculations are performed on the multiple divided area shape features, the multiple first-level neighbor divided area shape feature sets, the multiple second-level neighbor divided area shape feature sets, the multiple divided area warping features, the multiple first-level neighbor divided area warping feature sets, and the multiple neighbor divided area warping feature sets, respectively, to obtain multiple initial shape features and multiple initial warping features of the multiple divided areas; The multiple initial shape features and the multiple initial warping features are subjected to feature fuzzy authentication. If the authentication is passed, the multiple initial shape features and the multiple initial warping features are used as the multiple shape features and the multiple warping features, respectively.

4. A semiconductor chip dicing method as claimed in claim 3, characterized in that: include: Performing feature recognition on the wafer surface image using a feature recognition module to obtain shape features and warpage features of the wafer surface image; Performing fuzzy similarity authentication on the multiple initial shape features and the multiple initial warping features based on the wafer surface image shape features and the wafer surface image warping features to obtain fuzzy similarity; When the fuzzy similarity meets the preset similarity threshold, the authentication is successful.

5. A semiconductor chip dicing method as claimed in claim 1, characterized in that: The chip dicing task of the target semiconductor wafer is interactively performed, and a dicing path is identified in combination with a plurality of shape features and a plurality of warping features of the wafer surface image to determine a first dicing path, wherein the first dicing path includes a plurality of key dicing points, including: Analyzing the chip dicing task, a plurality of shape features, and a plurality of warpage features using a dicing path identifier to obtain a first dicing path; Segmenting the first cutting path according to the multiple division areas to obtain a segmentation point set; Combining the multiple shape features and the multiple warping features, traversing the segmentation point set to perform feature difference analysis of the front and rear road sections to obtain a difference set; The difference degree sets are sorted in descending order, and the segmentation points corresponding to the first m differences are used as the multiple key dividing points, where m is an integer greater than or equal to 3.

6. A semiconductor chip dicing method as claimed in claim 1, characterized in that: Determining scribing parameters at the plurality of key scribing points according to the direction of the first scribing path to obtain a plurality of key scribing parameter sets, including: Dividing the first marking path based on the multiple key marking points, taking the marking sections located after the multiple key marking points according to the direction of the first marking path as the marking sections corresponding to the multiple key marking points, to obtain multiple marking sections; Determining a plurality of divided area sets included in the plurality of cut sections according to the positions of the plurality of divided areas, wherein the plurality of divided area sets include a plurality of shape feature sets and a plurality of warping feature sets; Traversing the plurality of shape feature sets and the plurality of warping feature sets to perform feature concentration processing, and obtaining a plurality of concentrated shape features and a plurality of concentrated warping features of a plurality of cut road sections; A cutting parameter analysis is performed based on the multiple concentrated shape features and the multiple concentrated warpage features to determine the multiple key cutting parameter sets.

7. A semiconductor chip dicing method as claimed in claim 1, characterized in that: include: Performing stage certification of scribing quality at the aforementioned multiple critical scribing points; If the certification is passed, the cutting will continue; If the authentication fails, a cutting warning instruction is generated and processing is performed according to the cutting warning instruction.

8. A semiconductor chip dicing method as claimed in claim 1, characterized in that: The target semiconductor wafer is placed on the dicing machine using a multi-material clamp. After placement, the wafer positioning certification is performed to obtain the positioning certification results, including: Determining a plurality of positioning points based on the size and model of the target semiconductor wafer; After the placement is completed, position information of the multiple positioning points is collected to obtain multiple positioning information; Wafer positioning authentication is performed according to the multiple positioning information to obtain the positioning authentication result.

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