An image sensor based on silicon germanium PIN structure and a manufacturing method thereof
By adopting silicon germanium PIN structure and shallow groove isolation technology in the image sensor, the material compatibility problem in the vertical architecture is solved, the manufacturing cost is reduced and the performance is improved, and the efficient manufacturing of visible-short-wave infrared image sensor is achieved.
Patent Information
- Application Number
- CN202411412684.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2044-10-11
AI Technical Summary
In the prior art, silicon and indium gallium arsenic materials have lattice mismatch, thermal mismatch and polar mismatch problems in vertical architectures, resulting in high manufacturing cost of visible-short-wave infrared image sensors and III-V indium gallium The market price of arsenic short-wave infrared optoelectronic materials is high, affecting the performance and cost of image sensors.
Using an image sensor based on silicon-germanium PIN structure, a vertically stacked PIN structure is formed by setting shallow grooves between the silicon pixel area and the germanium pixel area to avoid heterogeneous interface compatibility, interface reaction, lattice mismatch and thermal mismatch Problems and uses germanium materials to reduce manufacturing costs.
This improves the performance indicators of image sensors, reduces manufacturing costs, enhances production efficiency, and reduces the active interval through shallow trough isolation technology to improve integration.
Smart Images
Figure CN118943152B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor process technology, and in particular to an image sensor based on a silicon germanium PIN structure and a manufacturing method thereof. Background Art
[0002] Visible light-shortwave infrared image sensor is a photoelectric detection device that can respond to optical signals in both visible light and shortwave infrared bands. It has a wider spectral response range and is widely used in aerospace, industrial detection, medical diagnosis and other fields. However, vertically structured image sensors have encountered a series of technical bottlenecks in the process of development:
[0003] 1) Silicon and InGaAs are commonly used sensing materials in the visible light band and short-wave infrared band, respectively, but they have large lattice mismatch, thermal mismatch and polarity mismatch problems, and cannot be directly combined into a visible light-short-wave infrared image sensor using a vertical architecture; 2) The interface compatibility and interface reaction between vertically stacked visible light-short-wave infrared sensing materials need to be additionally considered to avoid affecting the overall performance degradation or failure of the image sensor; 3) Due to the high market price of III-V InGaAs short-wave infrared optoelectronic materials, visible light-short-wave infrared image sensors face the problem of high manufacturing costs. Summary of the invention
[0004] The present application provides an image sensor based on a silicon-germanium PIN structure and a method for manufacturing the same, which can avoid problems such as heterogeneous interface compatibility, interface reaction, lattice mismatch and thermal mismatch introduced during the vertical stacking process. At the same time, the application of germanium material reduces the manufacturing cost of the visible light-short-wave infrared image sensor.
[0005] In a first aspect, an embodiment of the present application provides an image sensor based on a silicon germanium PIN structure, comprising:
[0006] A readout circuit, a glass substrate, a silicon oxide layer and an aluminum oxide layer stacked in sequence, and at least one silicon pixel region and at least one germanium pixel region disposed on the aluminum oxide layer and located on the same horizontal plane;
[0007] A shallow groove is provided between adjacent silicon pixel regions or germanium pixel regions;
[0008] The silicon pixel region includes a first heavily doped silicon contact layer, an intrinsic silicon visible light sensing layer, and a second heavily doped silicon contact layer stacked in sequence, as well as a passivation layer, an N-type electrode, a P-type electrode, and a rectangular groove;
[0009] The rectangular groove runs through the second heavily doped silicon contact layer and the intrinsic silicon visible light sensing layer; the passivation layer is superimposed on the second heavily doped silicon contact layer and the inner wall of each rectangular groove; the N-type electrode is arranged at the bottom of the rectangular groove, passes through the passivation layer to connect to the first heavily doped silicon contact layer; the P-type electrode passes through the passivation layer to connect to the second heavily doped silicon contact layer;
[0010] The germanium pixel region includes a first heavily doped silicon contact layer, an intrinsic germanium short-wave infrared sensing layer and a heavily doped germanium contact layer, which are sequentially stacked, as well as a passivation layer, an N-type electrode, a P-type electrode and a rectangular groove;
[0011] The rectangular grooves penetrate the heavily doped germanium contact layer and the intrinsic germanium short-wave infrared sensing layer; the passivation layer is superimposed on the heavily doped germanium contact layer and the inner wall of each rectangular groove; the N-type electrode is arranged at the bottom of the rectangular groove, passes through the passivation layer and is connected to the first heavily doped silicon contact layer; the P-type electrode passes through the passivation layer and is connected to the heavily doped germanium contact layer;
[0012] Each N-type electrode and each P-type electrode are connected to a readout circuit.
[0013] Furthermore, the first heavily doped silicon contact layer in the silicon pixel area is a P-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer is an N-type heavily doped silicon contact layer; or, the first heavily doped silicon contact layer is an N-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer is a P-type heavily doped silicon contact layer.
[0014] Furthermore, the first heavily doped silicon contact layer in the germanium pixel area is a P-type heavily doped silicon contact layer, and the heavily doped germanium contact layer is an N-type heavily doped germanium contact layer; or, the first heavily doped silicon contact layer is an N-type heavily doped silicon contact layer, and the heavily doped germanium contact layer is a P-type heavily doped germanium contact layer.
[0015] Further, the number of the rectangular grooves in the silicon pixel region or the rectangular grooves in the germanium pixel region is two.
[0016] Furthermore, the glass substrate is replaced with a sapphire substrate.
[0017] Furthermore, the thickness of the first heavily doped silicon contact layer in the silicon pixel region and the germanium pixel region is in the range of 100-500 nm.
[0018] Furthermore, the thickness of the second heavily doped silicon contact layer in the silicon pixel region is in the range of 100-500 nm.
[0019] Furthermore, the thickness of the heavily doped germanium contact layer in the germanium pixel region is in the range of 100-500 nm.
[0020] Furthermore, the thickness of the intrinsic silicon visible light sensing layer in the silicon pixel region ranges from 500 to 2000 nm.
[0021] Furthermore, the thickness of the intrinsic germanium short-wave infrared sensing layer in the germanium pixel region is in the range of 600-2500 nm.
[0022] In a second aspect, an embodiment of the present application provides a method for manufacturing an image sensor based on a silicon germanium PIN structure, comprising:
[0023] Providing a silicon substrate; and sequentially stacking an intrinsic silicon buffer layer, an intrinsic silicon visible light sensing layer, a first heavily doped silicon contact layer and an aluminum oxide layer on the silicon substrate to obtain a donor substrate;
[0024] Providing a glass substrate; stacking a silicon oxide layer on the glass substrate to obtain an acceptor substrate;
[0025] bonding the donor substrate and the acceptor substrate wafers and removing the silicon substrate;
[0026] Ion implantation is performed on the intrinsic silicon buffer layer to form a second heavily doped silicon contact layer, thereby obtaining a sensor wafer;
[0027] Shallow trench isolation is used on the sensor wafer to form silicon pixel areas and germanium pixel areas;
[0028] removing the second heavily doped silicon contact layer and the intrinsic silicon visible light sensing layer in the germanium pixel region, and sequentially stacking the intrinsic germanium short-wave infrared sensing layer and the heavily doped germanium contact layer on the first heavily doped silicon contact layer;
[0029] An equal number of rectangular grooves of the same shape are respectively arranged in the silicon pixel region and the germanium pixel region;
[0030] A passivation layer is covered on the second heavily doped silicon contact layer, the heavily doped germanium contact layer and the inner walls of each rectangular groove;
[0031] An N-type electrode and a P-type electrode are provided, and a readout circuit is connected to the N-type electrode and the P-type electrode.
[0032] Furthermore, the thickness of the intrinsic silicon buffer layer is in the range of 100-500 nm.
[0033] Furthermore, the silicon substrate is removed by machine polishing or dry etching.
[0034] Furthermore, the number of rectangular grooves arranged in the silicon pixel region and the germanium pixel region are both 2.
[0035] Furthermore, the glass substrate is replaced with a sapphire substrate.
[0036] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:
[0037] An image sensor based on a silicon-germanium PIN structure is provided in an embodiment of the present application. Firstly, the "first heavily doped silicon contact layer, the intrinsic silicon visible light sensing layer and the second heavily doped silicon contact layer" of the silicon pixel area for collecting visible light and the "first heavily doped silicon contact layer, the intrinsic germanium short-wave infrared sensing layer and the heavily doped germanium contact layer" of the germanium pixel area for collecting short-wave infrared light respectively constitute a vertically stacked PIN structure, and the two pixel areas are located on the same horizontal plane, thereby avoiding the problems of heterogeneous interface compatibility, interface reaction, lattice mismatch and thermal mismatch introduced in the vertical stacking process, and being beneficial to simultaneously improving the performance indicators of the silicon pixel area and the germanium pixel area; secondly, compared with III-V group indium gallium arsenide short-wave infrared photoelectric materials, germanium materials have significant advantages such as selective epitaxy, high compatibility with CMOS process production lines, and excellent photoelectric response in the short-wave infrared band, thereby reducing the manufacturing cost of visible light-short-wave infrared image sensors and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A cross-sectional view of an image sensor based on a silicon germanium PIN structure provided by one embodiment of the present application;
[0039] Figure 2 A flow chart of a method for manufacturing an image sensor based on a silicon germanium PIN structure provided in one embodiment of the present application;
[0040] Figure 3 A schematic diagram of a donor substrate and a receiver substrate wafer bonding step provided in one embodiment of the present application;
[0041] Figure 4 A schematic diagram of a sensor wafer obtained after ion implantation according to an embodiment of the present application;
[0042] Figure 5 A schematic diagram of a sensor wafer after shallow trench isolation provided by an embodiment of the present application;
[0043] Figure 6 A schematic diagram of a wafer after pre-processing of a germanium pixel region provided in one embodiment of the present application;
[0044] Figure 7 A schematic diagram of a wafer after the germanium pixel region is constructed according to an embodiment of the present application;
[0045] Figure 8 A schematic diagram of a wafer after a rectangular groove is provided according to an embodiment of the present application;
[0046] Fig. 9 A schematic diagram of a wafer after providing an N-type electrode, a P-type electrode and a passivation layer is provided in one embodiment of the present application.
[0047] Description of reference numerals:
[0048] 001, silicon substrate; 002, intrinsic silicon buffer layer; 101, glass substrate; 102, silicon oxide layer; 103, aluminum oxide layer; 104, first heavily doped silicon contact layer; 105, intrinsic silicon visible light sensing layer; 106, second heavily doped silicon contact layer; 107, passivation layer; 108, intrinsic germanium short-wave infrared sensing layer; 109, heavily doped germanium contact layer; 201, readout circuit; 202, shallow groove. DETAILED DESCRIPTION
[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0050] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.
[0051] See also Figure 1 The present application embodiment provides an image sensor based on a silicon germanium PIN structure, including:
[0052] The readout circuit 201 comprises a glass substrate 101, a silicon oxide layer 102 and an aluminum oxide layer 103 stacked in sequence, and at least one silicon pixel region and at least one germanium pixel region disposed on the aluminum oxide layer 103 and located on the same horizontal plane.
[0053] Specifically, during actual operation, the visible light-short-wave infrared image sensor has serious dark current noise, high operating voltage and other problems. These noises will interfere with the signal, reduce the signal-to-noise ratio, and increase the difficulty of subsequent noise suppression. Therefore, the substrate of the image sensor proposed in this application adopts a glass substrate 101. The glass substrate 101 has good light transmittance in both the visible light band and the short-wave infrared band, and can capture visible light signals and short-wave infrared radiation at the same time. The visible light signal and short-wave infrared radiation are then captured by the silicon pixel area and the germanium pixel area respectively, ensuring that the light signals of the two bands can be effectively absorbed and converted into electrical signals, solving the interference and energy loss problems between the light signals of the two bands, ensuring the transmission and transmission of visible light and short-wave infrared radiation, and improving the dark current, sensitivity and accuracy of the image sensor.
[0054] Furthermore, the glass substrate 101 may also be replaced by a sapphire substrate, which can also achieve the above-mentioned technical effects.
[0055] Shallow trenches 202 are provided between adjacent silicon pixel regions or germanium pixel regions.
[0056] Among them, shallow trenches 202 are provided between the silicon pixel area and the germanium pixel area, between the silicon pixel area and the silicon pixel area, and between the germanium pixel area and the germanium pixel area of the present application; shallow trenches are a key isolation technology in semiconductor processes, mainly used for process nodes of 0.25um and below. The shallow trench isolation technology (STI) adopted in the present application forms shallow trenches 202 on the semiconductor and then fills them with oxide to achieve isolation between devices, thereby reducing the spacing between active areas and improving integration. Compared with the traditional LOCOS (Local Oxidation of Silicon) isolation technology, STI technology has no bird's beak effect, can prevent the oxide layer from extending into the active area, reduce the effective width of the device, and improve the device speed.
[0057] The silicon pixel region includes a first heavily doped silicon contact layer 104, an intrinsic silicon visible light sensing layer 105 and a second heavily doped silicon contact layer 106 which are sequentially stacked, as well as a passivation layer 107, an N-type electrode, a P-type electrode and a rectangular groove.
[0058] The first heavily doped silicon contact layer 104 in the silicon pixel region is a P-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer 106 is an N-type heavily doped silicon contact layer; or, the first heavily doped silicon contact layer 104 is an N-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer 106 is a P-type heavily doped silicon contact layer. That is, the types of the two heavily doped silicon contact layers are different.
[0059] The thickness of the first heavily doped silicon contact layer 104 and the second heavily doped silicon contact layer 106 in the silicon pixel region are both in the range of 100-500 nm, and the thickness of the intrinsic silicon visible light sensing layer 105 is in the range of 500-2000 nm.
[0060] Specifically, the first heavily doped silicon contact layer 104 , the intrinsic silicon visible light sensing layer 105 , and the second heavily doped silicon contact layer 106 in the silicon pixel region constitute a vertically stacked PIN structure, which is usually formed by selective epitaxy.
[0061] The rectangular grooves penetrate the second heavily doped silicon contact layer 106 and the intrinsic silicon visible light sensing layer 105; the passivation layer 107 is superimposed on the second heavily doped silicon contact layer 106 and the inner walls of each rectangular groove; the N-type electrode is arranged at the bottom of the rectangular groove, passing through the passivation layer 107 to connect to the first heavily doped silicon contact layer 104; the P-type electrode passes through the passivation layer 107 to connect to the second heavily doped silicon contact layer 106.
[0062] like Figure 1 As shown, the rectangular groove in the silicon pixel area actually opens up the second heavily doped silicon contact layer 106 and the intrinsic silicon visible light sensing layer 105 until the first heavily doped silicon contact layer 104 underneath is exposed.
[0063] The germanium pixel region includes a first heavily doped silicon contact layer 104, an intrinsic germanium short-wave infrared sensing layer 108 and a heavily doped germanium contact layer 109, which are sequentially stacked, as well as a passivation layer 107, an N-type electrode, a P-type electrode and a rectangular groove.
[0064] The first heavily doped silicon contact layer 104 in the germanium pixel region is a P-type heavily doped silicon contact layer, and the heavily doped germanium contact layer 109 is an N-type heavily doped germanium contact layer; or the first heavily doped silicon contact layer 104 is an N-type heavily doped silicon contact layer, and the heavily doped germanium contact layer 109 is a P-type heavily doped germanium contact layer. That is, the first heavily doped silicon contact layer 104 and the heavily doped germanium contact layer 109 in the germanium pixel region are of different types.
[0065] The thickness of the first heavily doped silicon contact layer 104 and the heavily doped germanium contact layer 109 in the germanium pixel region are both in the range of 100-500 nm, and the thickness of the intrinsic germanium short-wave infrared sensing layer 108 is in the range of 600-2500 nm.
[0066] Specifically, the first heavily doped silicon contact layer 104, the intrinsic germanium short-wave infrared sensing layer 108 and the heavily doped germanium contact layer 109 in the germanium pixel region form a vertically stacked PIN structure, which is suitable for manufacturing high-frequency and high-speed electronic devices.
[0067] The rectangular grooves penetrate the heavily doped germanium contact layer 109 and the intrinsic germanium short-wave infrared sensing layer 108; the passivation layer 107 is superimposed on the heavily doped germanium contact layer 109 and the inner walls of each rectangular groove; the N-type electrode is arranged at the bottom of the rectangular groove, passing through the passivation layer 107 to connect to the first heavily doped silicon contact layer 104; the P-type electrode passes through the passivation layer 107 to connect to the heavily doped germanium contact layer 109.
[0068] like Figure 1 As shown, the rectangular groove in the germanium pixel area actually penetrates the heavily doped germanium contact layer 109 and the intrinsic germanium short-wave infrared sensing layer 108 until the first heavily doped silicon contact layer 104 underneath is exposed.
[0069] The short-wave infrared in this application generally refers to infrared light with a wavelength below 1700 nm, which is greater than the maximum wavelength of visible light.
[0070] The operating voltages of the silicon pixel region and the germanium pixel region of the present application are both within the range of 0.5-1V.
[0071] Each N-type electrode and each P-type electrode are connected to the readout circuit 201. Specifically, the number of rectangular grooves in the silicon pixel region or the rectangular grooves in the germanium pixel region is 2. The P-type electrode is arranged on the table surface between the two rectangular grooves, that is, two N-type electrodes and one P-type electrode are arranged in one silicon pixel region or one germanium pixel region.
[0072] The above embodiment provides an image sensor based on a silicon-germanium PIN structure. First, the "first heavily doped silicon contact layer 104, the intrinsic silicon visible light sensing layer 105 and the second heavily doped silicon contact layer 106" of the silicon pixel area for collecting visible light and the "first heavily doped silicon contact layer 104, the intrinsic germanium short-wave infrared sensing layer 108 and the heavily doped germanium contact layer 109" of the germanium pixel area for collecting short-wave infrared light respectively constitute a vertically stacked PIN structure, and the two pixel areas are located on the same horizontal plane, avoiding the problems of heterogeneous interface compatibility, interface reaction, lattice mismatch and thermal mismatch introduced in the vertical stacking process, which is beneficial to simultaneously improve the performance indicators of the silicon pixel area and the germanium pixel area; secondly, compared with III-V group indium gallium arsenide short-wave infrared photoelectric materials, germanium materials have significant advantages such as selective epitaxy, high compatibility with CMOS process production lines, and excellent photoelectric response in the short-wave infrared band, which reduces the manufacturing cost of visible light-short-wave infrared image sensors and improves production efficiency.
[0073] See also Figure 2 Another embodiment of the present application provides a method for manufacturing an image sensor based on a silicon germanium PIN structure, which method may specifically include the following steps:
[0074] Step S1, providing a silicon substrate 001; sequentially stacking an intrinsic silicon buffer layer 002, an intrinsic silicon visible light sensing layer 105, a first heavily doped silicon contact layer 104 and an aluminum oxide layer 103 on the silicon substrate 001 to obtain a donor substrate.
[0075] See also Figure 3 , wherein the thickness of the intrinsic silicon buffer layer 002 is in the range of 100-500 nm; the thickness of the intrinsic silicon visible light sensing layer 105 is in the range of 500-2000 nm, and the thickness of the first heavily doped silicon contact layer 104 is in the range of 100-500 nm.
[0076] Step S2, providing a glass substrate 101; stacking a silicon oxide layer 102 on the glass substrate 101 to obtain a receptor substrate.
[0077] The glass substrate 101 may be replaced by a sapphire substrate.
[0078] Step S3 , bonding the donor substrate and the acceptor substrate wafers, and removing the silicon substrate 001 .
[0079] Specifically, the silicon substrate 001 may be removed by machine polishing, dry etching or CMP (chemical mechanical polishing).
[0080] Step S4, ion implantation is performed on the intrinsic silicon buffer layer 002 to form a second heavily doped silicon contact layer 106, thereby obtaining a sensor wafer. Figure 4The first heavily doped silicon contact layer 104 and the second heavily doped silicon contact layer 106 are of different types. The first heavily doped silicon contact layer 104 is a P-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer 106 is an N-type heavily doped silicon contact layer; or, the first heavily doped silicon contact layer 104 is an N-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer 106 is a P-type heavily doped silicon contact layer.
[0081] Since the second heavily doped silicon contact layer 106 is obtained from the intrinsic silicon buffer layer 002 , the thickness range of the second heavily doped silicon contact layer 106 is the same as that of the intrinsic silicon buffer layer 002 , that is, the thickness range of the second heavily doped silicon contact layer 106 is 100-500 nm.
[0082] Step S5, shallow trench isolation is used on the sensor wafer to form a silicon pixel region and a germanium pixel region.
[0083] Specifically, see Figure 5 A pixel region is located between two shallow grooves 202 . At least one silicon pixel region and at least one germanium pixel region are divided by setting the shallow groove 202 . The shallow groove 202 is filled with oxide.
[0084] Step S6 , removing the second heavily doped silicon contact layer 106 and the intrinsic silicon visible light sensing layer 105 in the germanium pixel region, and sequentially stacking the intrinsic germanium short-wave infrared sensing layer 108 and the heavily doped germanium contact layer 109 on the first heavily doped silicon contact layer 104 .
[0085] Specifically, see Figure 6 and Figure 7 The first heavily doped silicon contact layer 104 and the heavily doped germanium contact layer 109 in the germanium pixel region are grown by selective epitaxy, and the two are of different types.
[0086] The first heavily doped silicon contact layer 104 in the germanium pixel region is a P-type heavily doped silicon contact layer, and the heavily doped germanium contact layer 109 is an N-type heavily doped germanium contact layer; or, the first heavily doped silicon contact layer 104 is an N-type heavily doped silicon contact layer, and the heavily doped germanium contact layer 109 is a P-type heavily doped germanium contact layer. The thickness of the intrinsic germanium short-wave infrared sensing layer 108 is in the range of 600-2500nm, and the thickness of the heavily doped germanium contact layer 109 is in the range of 100-500nm.
[0087] Step S7, setting equal numbers of rectangular grooves of the same shape in the silicon pixel region and the germanium pixel region respectively.
[0088] The number of rectangular grooves provided in the silicon pixel region and the germanium pixel region can both be two.
[0089] See also Figure 8In the silicon pixel area, the rectangular groove penetrates the second heavily doped silicon contact layer 106 and the intrinsic silicon visible light sensing layer 105 ; in the germanium pixel area, the rectangular groove penetrates the heavily doped germanium contact layer 109 and the intrinsic germanium short-wave infrared sensing layer 108 .
[0090] Step S8 , covering the second heavily doped silicon contact layer 106 , the heavily doped germanium contact layer 109 and the inner walls of each rectangular groove with the passivation layer 107 .
[0091] Step S9 , setting an N-type electrode and a P-type electrode, and making the readout circuit 201 connect the N-type electrode and the P-type electrode.
[0092] Specifically, see Fig. 9 , the N-type electrode is arranged at the bottom of the rectangular groove, and the P-type electrode is arranged on the table between the two rectangular grooves; the N-type electrodes of the two pixel areas are connected to the first heavily doped silicon contact layer 104 through the passivation layer 107; in the silicon pixel area, the P-type electrode is connected to the second heavily doped silicon contact layer 106 through the passivation layer 107, and in the germanium pixel area, the P-type electrode is connected to the heavily doped germanium contact layer 109 through the passivation layer 107.
[0093] Finally, the readout circuit 201 is bonded to the visible light-shortwave infrared focal plane array chip on the glass substrate 101 by In bump bonding or Cu bump bonding using flip-chip technology.
[0094] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0095] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. An image sensor based on a silicon germanium PIN structure, characterized in that: include: A readout circuit, a glass substrate, a silicon oxide layer and an aluminum oxide layer stacked in sequence, and at least one silicon pixel region and at least one germanium pixel region disposed on the aluminum oxide layer and located on the same horizontal plane; A shallow groove is provided between adjacent silicon pixel regions or germanium pixel regions; The silicon pixel region includes a first heavily doped silicon contact layer, an intrinsic silicon visible light sensing layer, and a second heavily doped silicon contact layer stacked in sequence, as well as a passivation layer, an N-type electrode, a P-type electrode, and a rectangular groove; the rectangular groove runs through the second heavily doped silicon contact layer and the intrinsic silicon visible light sensing layer; the passivation layer is stacked on the second heavily doped silicon contact layer and the inner wall of each of the rectangular grooves; The N-type electrode is disposed at the bottom of the rectangular groove, passing through the passivation layer and connected to the first heavily doped silicon contact layer; The P-type electrode passes through the passivation layer and connects to the second heavily doped silicon contact layer; The germanium pixel region includes a first heavily doped silicon contact layer, an intrinsic germanium short-wave infrared sensing layer and a heavily doped germanium contact layer, as well as a passivation layer, an N-type electrode, a P-type electrode and a rectangular groove, which are sequentially stacked; the rectangular groove runs through the heavily doped germanium contact layer and the intrinsic germanium short-wave infrared sensing layer; the passivation layer is stacked on the heavily doped germanium contact layer and the inner wall of each of the rectangular grooves; The N-type electrode is disposed at the bottom of the rectangular groove, passing through the passivation layer to connect to the first heavily doped silicon contact layer; the P-type electrode passes through the passivation layer to connect to the heavily doped germanium contact layer; Each of the N-type electrodes and each of the P-type electrodes is connected to a readout circuit.
2. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The first heavily doped silicon contact layer in the silicon pixel area is a P-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer is an N-type heavily doped silicon contact layer; or, the first heavily doped silicon contact layer is an N-type heavily doped silicon contact layer, and the second heavily doped silicon contact layer is a P-type heavily doped silicon contact layer.
3. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The first heavily doped silicon contact layer in the germanium pixel area is a P-type heavily doped silicon contact layer, and the heavily doped germanium contact layer is an N-type heavily doped germanium contact layer; or, the first heavily doped silicon contact layer is an N-type heavily doped silicon contact layer, and the heavily doped germanium contact layer is a P-type heavily doped germanium contact layer.
4. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The number of the rectangular grooves in the silicon pixel region or the rectangular grooves in the germanium pixel region is 2.
5. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The glass substrate is replaced by a sapphire substrate.
6. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The thickness of the first heavily doped silicon contact layer in the silicon pixel region and the germanium pixel region is in the range of 100-500 nm.
7. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The thickness of the second heavily doped silicon contact layer in the silicon pixel region is in the range of 100-500 nm.
8. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The thickness of the heavily doped germanium contact layer in the germanium pixel region is in the range of 100-500 nm.
9. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The thickness of the intrinsic silicon visible light sensing layer in the silicon pixel region is in the range of 500-2000 nm.
10. The image sensor based on silicon germanium PIN structure according to claim 1, characterized in that: The thickness of the intrinsic germanium short-wave infrared sensing layer in the germanium pixel area is in the range of 600-2500nm.
11. A method for manufacturing an image sensor based on a silicon germanium PIN structure, characterized in that: include: providing a silicon substrate; An intrinsic silicon buffer layer, an intrinsic silicon visible light sensing layer, a first heavily doped silicon contact layer and an aluminum oxide layer are sequentially stacked on the silicon substrate to obtain a donor substrate; Providing a glass substrate; stacking a silicon oxide layer on the glass substrate to obtain an acceptor substrate; Wafer bonding the donor substrate and the acceptor substrate, and removing the silicon substrate; Performing ion implantation on the intrinsic silicon buffer layer to form a second heavily doped silicon contact layer to obtain a sensor wafer; Shallow trench isolation is used on the sensor wafer to form a silicon pixel region and a germanium pixel region; removing the second heavily doped silicon contact layer and the intrinsic silicon visible light sensing layer in the germanium pixel region, and sequentially stacking an intrinsic germanium short-wave infrared sensing layer and a heavily doped germanium contact layer on the first heavily doped silicon contact layer; An equal number of rectangular grooves of the same shape are respectively provided in the silicon pixel region and the germanium pixel region; Covering the second heavily doped silicon contact layer, the heavily doped germanium contact layer and the inner wall of each of the rectangular grooves with a passivation layer; An N-type electrode and a P-type electrode are provided, and a readout circuit is connected to the N-type electrode and the P-type electrode.
12. The method for manufacturing an image sensor based on a silicon germanium PIN structure according to claim 11, characterized in that: The thickness of the intrinsic silicon buffer layer is in the range of 100-500 nm.
13. The method for manufacturing an image sensor based on a silicon germanium PIN structure according to claim 11, characterized in that: The silicon substrate is removed by mechanical polishing or dry etching.
14. The method for manufacturing an image sensor based on a silicon germanium PIN structure according to claim 11, characterized in that: The number of the rectangular grooves arranged in the silicon pixel region and the germanium pixel region is 2.
15. The method for manufacturing an image sensor based on a silicon germanium PIN structure according to claim 11, characterized in that: The glass substrate is replaced by a sapphire substrate.