Multi-time programmable device and manufacturing method thereof

Abstract

The present application discloses a multi-time programmable device and a manufacturing method thereof, wherein the multi-time programmable device comprises: a substrate, the substrate comprises a well region and an isolation region, the isolation region is arranged adjacent to the well region, the well region comprises a source region and a drain region arranged in the extension direction of the well region and having a conductivity type different from that of the well region, and a channel region therebetween; a gate stack, comprising a stacked gate dielectric layer and a floating gate structure, located on the surface of the channel region, and the gate dielectric layer is located between the channel region and the floating gate structure; a control gate, located on the surface of the isolation region at a position opposite to the floating gate structure, and separated from the floating gate structure by an inter-gate dielectric layer. The present application realizes the miniaturization of the multi-time programmable device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a multi-time programmable device and a manufacturing method thereof. Background Art

[0002] A Multi Time Programming (MTP) device is a type of storage device. Compared with a One Time Programming (OTP) device, its programming process is reversible and it can be programmed multiple times. It is suitable for use in a variety of occasions and has therefore been widely used.

[0003] In the related art, a multi-time programmable device can be implemented using a Flash structure. The Flash structure is to set a control gate on a floating gate structure, apply a forward voltage to the control gate to store electrons in the floating gate structure, and apply a reverse voltage to the control gate to erase the electrons in the floating gate structure, thereby realizing binary conversion between 0 and 1. However, the use of a Flash structure to implement a multi-time programmable device will result in a larger size of the multi-time programmable device, thereby limiting the use scenarios of the multi-time programmable device. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a multi-time programmable device and a manufacturing method thereof, so as to achieve miniaturization of the multi-time programmable device by improving the structure of the multi-time programmable device.

[0005] According to a first aspect of the present application, a multi-time programmable device is provided, comprising:

[0006] A substrate, the substrate comprising a well region and an isolation region, the isolation region being arranged adjacent to the well region, the well region comprising a source region and a drain region arranged in an extending direction of the well region and having a conductivity type different from that of the well region, and a channel region therebetween;

[0007] A gate stack, comprising a gate dielectric layer and a floating gate structure stacked together, located on the surface of the channel region, and the gate dielectric layer is located between the channel region and the floating gate structure;

[0008] The control gate is located on the surface of the isolation region at a position opposite to the floating gate structure and is separated from the floating gate structure by an inter-gate dielectric layer.

[0009] Optionally, the isolation region is located at two sides of the well region, and one control gate is respectively arranged on the surface of the isolation region at two sides of the well region.

[0010] Optionally, the inter-gate dielectric layer is an oxide-nitride-oxide structure, and the inter-gate dielectric layer is adjacent to the floating gate structure through one oxide film layer and the inter-gate dielectric layer is adjacent to the control gate through another oxide film layer.

[0011] Optionally, the isolation region further separates the well region into a first active region and a second active region in an extension direction of the well region, and the first active region includes the source region and the drain region;

[0012] The multi-time programmable device further includes: a first conductive plug electrically connected to the source region, a second conductive plug electrically connected to the drain region, a third conductive plug electrically connected to the control gate, and a fourth conductive plug electrically connected to the second active region.

[0013] According to a second aspect of the present application, a method for manufacturing a multi-time programmable device is provided, comprising:

[0014] forming a well region and an isolation region in the substrate, wherein the well region and the isolation region are adjacently arranged;

[0015] A source region and a drain region having a conductivity type different from that of the well region are formed in the well region and arranged in the extending direction of the well region, wherein a channel region is formed between the source region and the drain region;

[0016] forming a gate stack on the surface of the channel region, wherein the gate stack comprises a gate dielectric layer and a floating gate structure which are stacked, and the gate dielectric layer is located between the channel region and the floating gate structure;

[0017] A control gate is formed on the surface of the isolation region at a position opposite to the floating gate structure, and the control gate is separated from the floating gate structure by an inter-gate dielectric layer.

[0018] Optionally, forming a well region and an isolation region in the substrate includes:

[0019] Etching regions on both sides of the central region of the substrate to form two grooves located on both sides of the central region;

[0020] Filling the two trenches with an isolation dielectric to form the isolation regions included in the substrate located on both sides of the central region;

[0021] And, doping ions are implanted into the central region to form the well region included in the substrate.

[0022] Optionally, forming a gate stack on the surface of the channel region includes:

[0023] forming a first mask layer on the surface of the substrate, wherein the first mask layer has a first opening region in the channel region and an edge region of the isolation region adjacent to the channel region;

[0024] Etching the isolation region through the first opening region to form a shallow trench adjacent to the channel region;

[0025] An oxide layer is grown on the surface of the shallow trench and the channel region to form the gate dielectric layer surrounding the channel region.

[0026] Optionally, the substrate includes an oxide pad layer on the surface thereof, and the isolation region formed by filling the isolation medium in the two trenches is flush with the oxide pad layer on the surface of the central region of the substrate;

[0027] While etching the isolation region through the first opening region, the pad oxide layer on the surface of the central region is also etched to remove the pad oxide layer on the surface of the central region;

[0028] The oxide layer grown on the surface of the shallow trench and the channel region is flush with the isolation region.

[0029] Optionally, forming a gate stack on the surface of the channel region, and forming a control gate on the surface of the isolation region at a position opposite to the floating gate structure, comprises:

[0030] forming a gate conductor layer covering the gate dielectric layer and the region of the isolation region opposite to the gate dielectric layer;

[0031] forming a second mask layer on the gate conductor layer, wherein the second mask layer has second opening areas on both sides of the gate dielectric layer;

[0032] The gate conductor layer is etched through the second opening region to form the gate stack including the floating gate structure located on the surface of the gate dielectric layer and the control gate on the surface of the isolation region.

[0033] Optionally, the manufacturing method further comprises:

[0034] Growing an oxide film layer included in the inter-gate dielectric layer on the formed sidewalls of the floating gate structure and the control gate, and a gap exists between the oxide film layer grown on the sidewall of the floating gate structure and the oxide film layer grown on the sidewall of the control gate;

[0035] The gap is filled with nitride to form a nitride film layer included in the inter-gate dielectric layer.

[0036] The unexpected technical effects of this application are:

[0037] According to the embodiment of the present application, the multi-time programmable device includes a substrate, the substrate includes a well region and an isolation region, the well region includes a source region and a drain region arranged in the extension direction of the well region and having a different conductivity type from the well region and a channel region therebetween, the multi-time programmable device also includes a gate stack located on the surface of the channel region, so that the well region forms a structure similar to a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The multi-time programmable device also includes a control gate, the control gate and the floating gate structure are separated by an inter-gate dielectric layer, the inter-gate dielectric layer acts as a capacitor between the control gate and the floating gate structure, so when a voltage is applied to the control gate, a certain coupling voltage will be generated on the floating gate structure, so that the writing, reading and erasing of the multi-time programmable device can be achieved by adjusting the voltages on the source region, the drain region and the control gate. The control gate and the MOSFET device in the multi-time programmable device are not a stacked structure, so the thickness of the multi-time programmable device is small and does not require two processes to form the control gate and the floating gate structure included in the MOSFET device, thereby reducing the manufacturing cost of the multi-time programmable device; in addition, the well region and the isolation region are adjacent, and the control gate is located on the surface of the isolation region and at a position opposite to the floating gate structure in the gate stack on the surface of the well region, so the control gate and the MOSFET device formed by the well region are relatively compact, so that the structure of the storage unit in the multi-time programmable device can be further reduced as the process platform is reduced, thereby realizing the miniaturization of the multi-time programmable device.

[0038] Furthermore, the isolation region is located on both sides of the well region and a control gate is arranged on the surface of the isolation region on both sides of the well region, so that the threshold voltage of the MOSFET device formed in the well region can be shifted over a larger range by increasing the number of control gates, thereby allowing multiple programmable devices to achieve different operating voltages within a larger range, which is conducive to realizing the multi-functional use of the product.

[0039] According to the manufacturing method of the multi-time programmable device of the embodiment of the present application, the method includes: forming a well region and an isolation region in a substrate, the well region and the isolation region are arranged adjacent to each other; forming a source region and a drain region in the well region and arranged in the extension direction of the well region, and having a conductivity type different from that of the well region, and a channel region is formed between the source region and the drain region; forming a gate stack on the surface of the channel region, the gate stack including a gate dielectric layer and a floating gate structure that are stacked, and the gate dielectric layer is located between the channel region and the floating gate structure; forming a control gate at a position opposite to the floating gate structure on the surface of the isolation region, and separating the control gate from the floating gate structure by an inter-gate dielectric layer, thereby realizing the manufacturing of a multi-time programmable device with a miniaturized volume.

[0040] Furthermore, a gate stack is formed on the surface of the channel region, including: forming a first mask layer on the surface of the substrate, the first mask layer having a first opening area in the channel region and the edge area of ​​the isolation region adjacent to the channel region; etching the isolation region through the first opening area to form a shallow trench adjacent to the channel region; growing an oxide layer on the surface of the shallow trench and the channel region to form a gate dielectric layer surrounding the channel region, so that the area of ​​the gate dielectric layer is further expanded to both sides of the channel region on the basis of the area of ​​the channel region, and the contact area between the gate dielectric layer and the floating gate structure is expanded accordingly, so that the speed of the multi-time programmable device during writing can be faster.

[0041] Furthermore, the manufacturing method of the above-mentioned multi-time programmable device also includes: growing an oxide film layer included in the inter-gate dielectric layer on the side walls of the formed floating gate structure and the control gate, and there is a gap between the oxide film layer grown on the side walls of the floating gate structure and the oxide film layer grown on the side walls of the control gate, and then filling nitride in the gap to form a nitride film layer included in the inter-gate dielectric layer, so that by reasonably controlling the thickness of the oxide film layer grown on the side walls of the floating gate structure and the oxide film layer grown on the side walls of the control gate and using existing processes, an oxide-nitride-oxide structure serving as an inter-gate dielectric layer between the floating gate structure and the control gate can be manufactured, without the need for additional masks and related processes, thereby reducing the manufacturing cost of the multi-time programmable device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0043] Figure 1 A schematic top view of a multi-time programmable device provided by an embodiment of the present application is shown;

[0044] Figure 2 A schematic three-dimensional diagram of a multi-time programmable device provided by an embodiment of the present application is shown;

[0045] Figure 3 A flow chart of a method for manufacturing a multi-time programmable device provided by another embodiment of the present application is shown;

[0046] Figure 4 A schematic cross-sectional view of a substrate according to another embodiment of the present application is shown;

[0047] Figure 5 A schematic cross-sectional view showing a photolithography step of forming a trench according to another embodiment of the present application;

[0048] Figure 6 A schematic cross-sectional view showing an etching step of forming a trench according to another embodiment of the present application;

[0049] Figure 7 A schematic cross-sectional view showing the formation of an isolation region according to another embodiment of the present application;

[0050] Figure 8 A schematic cross-sectional view showing a film after an initial mask layer is removed according to another embodiment of the present application;

[0051] Fig. 9 A schematic cross-sectional view showing the formation of a well region according to another embodiment of the present application;

[0052] Fig.10 A schematic cross-sectional view showing a photolithography step and an etching step for forming a gate dielectric layer according to another embodiment of the present application;

[0053] Fig.11 A schematic cross-sectional view showing a state after the first photoresist layer is removed according to another embodiment of the present application;

[0054] Fig.12 A schematic cross-sectional view showing a gate dielectric layer after being formed according to another embodiment of the present application;

[0055] Fig.13 A schematic cross-sectional view showing a gate conductor layer after formation according to another embodiment of the present application;

[0056] Fig.14 A schematic cross-sectional view showing a photolithography step of forming a floating gate structure and a control gate according to another embodiment of the present application;

[0057] Fig.15 A schematic cross-sectional view showing an etching step of forming a floating gate structure and a control gate according to another embodiment of the present application;

[0058] Fig.16 A schematic cross-sectional view showing a floating gate structure and a control gate after forming according to another embodiment of the present application;

[0059] Fig.17 A schematic cross-sectional view showing a structure after an oxide film layer is formed according to another embodiment of the present application;

[0060] Fig.18 A schematic cross-sectional view showing a nitride film layer after being formed according to another embodiment of the present application;

[0061] Fig.19 A schematic cross-sectional view showing a process after forming an inter-gate dielectric layer according to another embodiment of the present application;

[0062] Fig. 20 A schematic cross-sectional view showing a contact layer after forming according to another embodiment of the present application;

[0063] Fig.21A schematic cross-sectional view showing a photolithography step of forming a contact hole according to another embodiment of the present application;

[0064] Fig. 22 A schematic cross-sectional view showing an etching step for forming a contact hole according to another embodiment of the present application;

[0065] Fig.23 A schematic cross-sectional view showing a state after an adhesion layer is deposited in a contact hole according to another embodiment of the present application;

[0066] Fig.24 Show Figure 1 A schematic cross-sectional view of the multi-time programmable device along line A1A2;

[0067] Fig.25 Show Figure 1 The multi-time programmable device is shown as a schematic cross-sectional view along line C1C2.

[0068] Description of reference numerals: 100-multiple programmable device; 101-silicon substrate; 102-deep N well; 103-pad oxide layer; 104-initial mask layer; 105-initial photoresist layer; 106-isolation region; 107-well region; 107a-first active region; 107b-second active region; 108-first photoresist layer; 109-gate dielectric layer; 110-gate conductor layer; 111-initial oxide layer; 112-second mask layer; 112a-first silicon nitride layer; 112b-first oxide layer; 112 c-first amorphous carbon layer; 112d-first antireflective coating; 112e-first bottom antireflective coating; 113-second photoresist layer; 114-oxide film layer; 115-nitride film layer; 116-contact layer; 117-third mask layer; 117a-second silicon nitride layer; 117b-second oxide layer; 117c-second amorphous carbon layer; 117d-second antireflective coating; 117e-second bottom antireflective coating; 118-third photoresist layer; 119-adhesion layer; 120-metal. DETAILED DESCRIPTION

[0069] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0070] This application may be presented in a variety of forms, some examples of which are described below.

[0071] Figure 1 FIG. 1 is a schematic top view of a multi-time programmable device provided by an embodiment of the present application. Figure 1The multi-time programmable device 100 includes a substrate, the substrate includes a well region and an isolation region, the well region extends in the direction indicated by the X-axis of the coordinate system in the figure, the isolation region is arranged adjacent to the well region, that is, the isolation region and the well region are arranged in the direction indicated by the Y-axis of the coordinate system in the figure, wherein the well region includes a source region S and a drain region D of a conductivity type different from that of the well region and arranged in the extending direction of the well region, and a channel region between the source region S and the drain region D, the multi-time programmable device 100 also includes a gate stack located on the surface of the channel region, the gate stack includes a gate dielectric layer and a floating gate structure FG arranged in a stacked manner, and the gate dielectric layer is located between the above-mentioned channel region and the floating gate structure FG, and the gate dielectric layer is not in the channel region because it is blocked by the floating gate structure FG. Figure 1 As shown in FIG. 1 , the well region is a P-type well region and the source region S and the drain region D are N-type doped regions, so that the well region forms a structure similar to an N-type MOSFET. In this case, the substrate can be a P-type substrate to adjust the channel performance of the N-type MOSFET device formed by the well region.

[0072] like Figure 1 As shown, the multi-time programmable device 100 further includes a control gate CG, which is located on the surface of the isolation region opposite to the floating gate structure FG and is separated from the floating gate structure FG by an inter-gate dielectric layer. Both the control gate CG and the floating gate structure FG belong to the gate conductor layer. Figure 1 The structural layout of the multi-time programmable device 100 on the XY plane is only briefly illustrated, and therefore the inter-gate dielectric layer between the control gate CG and the floating gate structure FG is not shown. In some examples, the inter-gate dielectric layer is an oxide-nitride-oxide (ONO) structure, and the inter-gate dielectric layer is adjacent to the floating gate structure FG as one of the oxide film layers, and the inter-gate dielectric layer is adjacent to the control gate CG as another of the oxide film layers. The inter-gate dielectric layer acts as a capacitor between the control gate CG and the floating gate structure FG, so when a voltage is applied to the control gate CG, a certain coupling voltage will be generated on the floating gate structure FG, so that the multi-time programmable device 100 can be written, read and erased by adjusting the source voltage Vs on the source region S, the drain voltage Vd on the drain region D, and the control voltage Vg on the control gate CG.

[0073] In some embodiments, the isolation region further separates the well region into a first active region and a second active region in the extension direction of the well region, the first active region includes the source region S and the drain region D, the second active region is used as the device substrate B of the MOSFET device formed by the well region, and the multi-time programmable device 100 further includes the following multiple conductive plugs: a first conductive plug electrically connected to the source region S for transmitting a source voltage Vs, a second conductive plug electrically connected to the drain region D for transmitting a drain voltage Vd, a third conductive plug electrically connected to the control gate CG for the control gate CG to receive a control voltage Vg, and a fourth conductive plug electrically connected to the device substrate B for the device substrate B to receive a substrate voltage Vb. The above conductive plugs can be formed by filling a metal material in a contact hole. In this embodiment, the source voltage Vs, the drain voltage Vd, the control voltage Vg, and the substrate voltage Vb are provided to the multi-time programmable device 100 from the same side of the multi-time programmable device 100.

[0074] In order to better understand the spatial layout of the above-mentioned structure of the multi-time programmable device 100, Figure 2 FIG. 1 shows a schematic three-dimensional diagram of a multi-time programmable device 100 provided in an embodiment of the present application. Figure 2 As shown, the first active region including the source region S and the drain region D and the second active region used as the device substrate B all belong to the well region and are located in the same layer, the floating gate structure FG and the control gate CG all belong to the gate conductor layer and are located in the same layer, and the gate conductor layer is located on the surface of the well region, and a plurality of conductive plugs are arranged on the surface of the corresponding structure. It should be understood that the isolation region adjacent to the well region is located in the same layer as the well region, the isolation region and the well region are located in the substrate, and the control gate CG is located on the surface of the isolation region.

[0075] Combination Figure 1 and Figure 2 In the multi-time programmable device 100 provided in the embodiment of the present application, the control gate CG, the source region S and the drain region D of the MOSFET device formed by the well region, and the floating gate structure FG are all arranged around the channel region of the MOSFET device formed by the well region. The overall structure is relatively compact, so that the structure of the storage unit in the multi-time programmable device 100 can be reduced as much as possible as the process platform is reduced, thereby realizing the miniaturization of the multi-time programmable device 100.

[0076] The following takes the MOSFET device formed in the well region of the multi-time programmable device 100 as an N-type MOSFET device as an example to explain the working principle of the multi-time programmable device 100 in detail. When the multi-time programmable device 100 is working, when a strong voltage is applied to the control gate CG and the drain region D, the floating gate structure FG will generate a coupling voltage and form a strong electric field, so that the floating gate structure FG will absorb a large number of electrons based on the hot carrier injection effect. Since there is a gate dielectric layer under the floating gate structure FG, the electrons are bound in the floating gate structure FG and cannot flow out freely, so that the threshold voltage (Threshold Voltage, referred to as VT) of the MOSFET device formed in the well region is offset. In this case, applying the initial turn-on voltage to the control gate CG cannot turn on the MOSFET device formed in the well region, so no current will pass through the MOSFET device, that is, the output of binary 0 is realized at the initial turn-on voltage. In the case that the floating gate structure FG does not store electrons, the threshold voltage of the MOSFET device formed in the well region does not shift, and the initial turn-on voltage can turn on the MOSFET device formed in the well region, and the MOSFET device has current passing through, that is, the output of binary 1 is realized at the initial turn-on voltage. Therefore, by controlling the floating gate structure FG to store electrons and controlling the floating gate structure FG to be erased, the data stored in the storage unit corresponding to the floating gate structure FG in the multi-time programmable device 100 can be converted between binary 1 and binary 0, thereby also realizing multiple compilations of the storage unit corresponding to the floating gate structure FG.

[0077] Table 1 shows a plurality of exemplary operating voltage groups of the multi-time programmable device 100, wherein the MOSFET device formed in the well region of the multi-time programmable device 100 is an N-type MOSFET device. Referring to Table 1, the plurality of exemplary operating voltage groups are as follows:

[0078] (1) The operating voltage group marked as PGM is the operating voltage group when the floating gate structure FG stores electrons, that is, when the control voltage Vg=9.45V, the drain voltage Vd=3.7V, and the source voltage Vs and the substrate voltage Vb are each 0V, the floating gate structure FG will form a very strong electric field so that the floating gate structure FG absorbs a large number of electrons. The electrons absorbed by the floating gate structure FG cause the threshold voltage of the MOSFET device to shift accordingly. For example, the initial turn-on voltage is 3.3V, and the threshold voltage after the shift increases to be greater than the initial turn-on voltage;

[0079] (2) The operating voltage group identified as Read PGM is an operating voltage group for reading after the operating voltage group identified as PGM causes the floating gate structure FG to store electrons, that is, when the drain voltage Vd=0.9V and the source voltage Vs and the substrate voltage Vb are each 0V, a control voltage Vg of 0-15V is applied to the control gate CG to scan and determine the threshold voltage of the MOSFET device after the offset. For example, when the control voltage Vg increases from 0V to 4.5V, the MOSFET device is turned on, thereby determining that the threshold voltage of the MOSFET device after the offset is 4.5V;

[0080] (3) The operating voltage group marked as ERS is the operating voltage group for erasing the electrons stored in the floating gate structure FG, that is, by setting the control voltage Vg=-8.1V and making the drain floating (Floating) and setting the source voltage Vs and the substrate voltage Vb to 7.7V respectively, an electric field in the opposite direction to that when the floating gate structure FG stores electrons is formed, so that the electrons stored in the floating gate structure FG are separated from the floating gate structure FG, thereby achieving erasure of the electrons stored in the floating gate structure FG;

[0081] (4) The operating voltage group identified as Read ERS is an operating voltage group that is read after the operating voltage group identified as ERS performs an erase operation, that is, when the drain voltage Vd=0.9V and the source voltage Vs and the substrate voltage Vb are each 0V, a control voltage Vg of 0-6V is applied to the control gate CG for scanning to determine the turn-on voltage of the MOSFET device at this time. For example, when the control voltage Vg increases from 0V to the initial turn-on voltage, the MOSFET device is turned on, and the turn-on voltage of the MOSFET device at this time is determined to be the initial turn-on voltage, thereby also determining that the threshold voltage of the MOSFET device has recovered.

[0082] Table 1

[0083] Logo Vg Vd Vs Vb PGM 9.45V 3.7V 0V 0V Read PGM 0-15V 0.9V 0V 0V ERS -8.1V Floating 7.7V 7.7V Read ERS 0-6V 0.9V 0V 0V

[0084] It should be noted that the non-suspended and non-0V voltage values ​​in the multiple operating voltage groups in Table 1 are only exemplary voltage values ​​and do not represent limitations on the embodiments of the present application. The initial turn-on voltage as the working voltage is pre-associated with the non-suspended and non-0V voltage values ​​in the above multiple operating voltage groups. After adjusting the non-suspended and non-0V voltage values ​​in the above multiple operating voltage groups, the pre-set initial turn-on voltage should also be reset according to the requirements. For example, the control voltage Vg and the drain voltage Vd in the operating voltage group identified as PGM are both increased so that the threshold voltage of the MOSFET device is shifted to 5V, and the control voltage Vg in the operating voltage group identified as ERS is also increased so that the floating gate structure FG still has some electrons after the erase operation so that the threshold voltage can only be restored to 4V. In this case, the working voltage of the multi-time programmable device 100 is no longer the initial turn-on voltage of 3.3V, but a voltage greater than 4V and less than 5V. At this time, it is necessary to erase the pre-set initial turn-on voltage of 3.3V and then write a voltage value between 4V and 5V as the reset initial turn-on voltage. It should be understood that the operating voltage is determined by the operating requirements of the multi-time programmable device 100 , and the non-floating and non-0V voltage values ​​in the plurality of operating voltage groups are also determined by the operating requirements of the multi-time programmable device 100 .

[0085] In addition, the control voltage Vg shown in Table 1 is for the case where the multi-time programmable device 100 includes two control gates CG, that is, Figure 1 The isolation region shown is adjacent to the well region and is located on the left and right sides of the well region, and a control gate CG is respectively arranged on the surface of the isolation region on the left and right sides of the well region, and each control gate CG is applied with a control voltage Vg, so that the threshold voltage of the MOSFET device formed in the well region is shifted to a larger range due to the floating gate structure FG being able to generate a larger coupling voltage and absorb more electrons, and since the threshold voltage after the shift is the upper limit of the operating voltage of the multi-time programmable device 100, the multi-time programmable device 100 allows different operating voltages to be realized in a larger range, which is conducive to realizing the multifunctional use of the product.

[0086] The multi-time programmable device 100 provided in the embodiment of the present application can apply a substrate voltage Vb directly to the substrate, and then apply a strong voltage to the control gate CG and the drain region D, so that the floating gate structure FG can generate a strong coupling voltage through the inter-gate dielectric layer between the control gate CG and the floating gate structure FG, and does not need to be coupled through another MOS capacitor. Therefore, there is no need to add a photolithography mask to form another MOS capacitor, thereby reducing the manufacturing cost of the multi-time programmable device.

[0087] Corresponding to the multi-time programmable device provided in the above embodiment, another embodiment of the present application further provides a method for manufacturing the multi-time programmable device. Figure 3 FIG. 1 is a flow chart of the manufacturing method. Figure 3 , the manufacturing method comprises:

[0088] Step S110, forming a well region and an isolation region in the substrate, wherein the well region and the isolation region are adjacent to each other;

[0089] Step S120, forming a source region and a drain region in the well region and arranged in the extension direction of the well region, and having a conductivity type different from that of the well region, with a channel region between the source region and the drain region;

[0090] Step S130, forming a gate stack on the surface of the channel region, the gate stack comprising a gate dielectric layer and a floating gate structure stacked together, and the gate dielectric layer is located between the channel region and the floating gate structure;

[0091] Step S140 , forming a control gate on the surface of the isolation region at a position opposite to the floating gate structure, and separating the control gate from the floating gate structure by an inter-gate dielectric layer.

[0092] Figures 4 to 25 1 is a schematic diagram of each step of an exemplary method for manufacturing a multi-time programmable device provided in an embodiment of the present application, wherein the MOSFET device formed by the well region of the exemplary multi-time programmable device is an N-type MOSFET device. In other examples, if the MOSFET device formed by the well region of the multi-time programmable device is a P-type MOSFET device, the manufacturing of the multi-time programmable device can be achieved by replacing the N-type doping in the following description with the P-type doping and replacing the P-type doping in the following description with the N-type doping.

[0093] Combine the following Figure 3 as well as Figures 4 to 25 The manufacturing method of the multi-time programmable device provided in the embodiment of the present application is described in detail.

[0094] In step S110, forming a well region and an isolation region in the substrate may include: etching the regions on both sides of the central region of the substrate to form two grooves located on both sides of the central region, filling the two grooves with an isolation medium to form isolation regions located on both sides of the central region, and injecting doping ions into the central region to form a well region included in the substrate. Here, the isolation regions are formed on both sides of the central region in order to set a control gate CG on the surface of each isolation region so that the manufactured multi-time programmable device has two control gates CG, thereby facilitating the multi-functional use of the product.

[0095] Specifically, you can Figure 4As shown, a pad oxide (Pad Oxide) is first grown on the surface of a silicon substrate 101 using a furnace tube to form a pad oxide layer 103, and then N-type doping ions are injected into the silicon substrate 101 below the pad oxide layer 103 to form a deep N well 102 located at the bottom of the pad oxide layer 103, thereby forming the above-mentioned substrate.

[0096] Afterwards, you can Figure 5 As shown in FIG. 1 , an initial mask layer 104 is formed on the surface of the substrate and an initial photoresist layer 105 is formed on the initial mask layer 104 by a photolithography step. The initial photoresist layer 105 covers the central area of ​​the substrate. Thus, the areas on both sides of the central area of ​​the substrate are etched through the initial photoresist layer 105 to form the areas on both sides of the central area. Figure 6 After the grooves are formed, the initial photoresist layer 105 is as shown. Figure 6 As shown, the pad oxide layer 103 and the initial mask layer 104 have been removed and only the portions originally covered by the initial photoresist layer 105 remain.

[0097] Next, you can use the furnace tube to Figure 6 A thin layer of liner oxide (Liner Oxide) is grown on the surface of the two trenches shown to form a liner oxide layer. The liner oxide layer repairs the damage to the edge surface of the trench caused by the above etching process, thereby improving the electrical properties and yield of the device. Afterwards, a high aspect ratio process (High Aspect Ratio Process, abbreviated as HARP) can be used to deposit tetraethoxysilane (Tetraethoxysilane, abbreviated as TEOS) in the two trenches where the liner oxide layer is formed. Since tetraethoxysilane reacts with oxygen to generate silicon dioxide and volatile ethanol, the trench will be filled with silicon dioxide. The filled silicon dioxide and the previously formed liner oxide layer are the isolation dielectrics filled into the trench, thereby forming a structure as shown in the figure. Figure 7 The initial mask layer 104 may be made of silicon nitride, and the pad oxide layer 103 may be made of silicon dioxide. Therefore, the isolation region 106 may be subjected to chemical mechanical planarization (CMP) and phosphoric acid may be used to remove the remaining portion of the initial mask layer 104, thereby obtaining the following: Figure 8 An isolation region 106 is shown flush with the remainder of the pad oxide layer 103 .

[0098] Then, if Fig. 9 As shown, P-type doping ions are implanted into the central area of ​​the substrate by an ion implantation (IMP) process to form a P-type well region 107 , thereby achieving the formation of the isolation region 106 and the well region 107 in the substrate as described in step S110 .

[0099] It should be noted that in some examples, the isolation area 106 is Figure 1 As shown, the well region 107 is separated into a first active region and a second active region in the extension direction of the well region 107. In this case, in the process of forming the isolation region 106 in step S110, trenches are formed in the regions outside the preset position of the well region 107. The formation of the trenches in this embodiment can be achieved by controlling the opening region of the initial photoresist layer 105 through the design of the mask. In this case, the photoresist covering the isolation region 106 can be controlled by the design of the mask not to cover the region where the well region 107 is expected to be formed, so that the P-type doping ions are subsequently implanted into these uncovered regions.

[0100] Step S120, forming a source region and a drain region in the well region that are arranged in the extending direction of the well region and have a conductivity type different from that of the well region, and a channel region is formed between the source region and the drain region. Specifically, for a multi-time programmable device in which the MOSFET device formed in the well region 107 is an N-type MOSFET device, that is, an N-type doping ion is implanted by an ion implantation (IMP) process to form Figure 1 and Figure 2 The source region S and drain region D are shown. Subsequently, a pocket implantation process may be performed on one side of the source region S and the drain region D close to the floating gate structure FG to form a pocket doping region, which is used to protect the channel region between the source region S and the drain region D from the hot electron effect.

[0101] Step S130, forming a gate stack on the surface of the channel region, may include: forming a first mask layer on the surface of the substrate, the first mask layer having a first opening area in the channel region and the edge area of ​​the isolation region adjacent to the channel region; etching the isolation region through the first opening area to form a shallow trench adjacent to the channel region; then growing an oxide layer on the surface of the shallow trench and the channel region to form a gate dielectric layer surrounding the channel region, so that the width of the gate dielectric layer is greater than the channel region, so that the area of ​​the gate dielectric layer is further expanded to both sides of the channel region on the basis of the area of ​​the channel region, and the contact area between the gate dielectric layer and the floating gate structure FG formed later is expanded accordingly, so that the speed of the multi-time programmable device during writing can be faster.

[0102] Specifically, in the substrate such as Fig. 9 In the case of including the remaining portion of the pad oxide layer 103 and the isolation region 106 flush with the remaining portion of the pad oxide layer 103, a substrate such as Fig.10The first photoresist layer 108 is shown in FIG. 1 and the pad oxide layer 103 and the isolation region 106 are etched through the opening region of the first photoresist layer 108. Here, a layer on the substrate surface including the remaining portion of the pad oxide layer 103 can be understood as the first mask layer. Since the opening region of the first photoresist layer 108 is in the edge region of the channel region and the adjacent channel region of the isolation region 106, the etching selectivity is utilized to accurately stop the etching at the surface of the remaining portion of the deep N well 102 and the surface of the well region 107, and then the substrate can be formed into a thin film. Fig.10 As shown, the remaining portion of the pad oxide layer 103 is etched away and shallow trenches adjacent to the channel region are formed on both sides of the well region 107 .

[0103] Afterwards, if Fig.11 The first photoresist layer 108 is removed as shown, and then Fig.12 As shown, an oxide layer is grown on the surface of the shallow trench and the channel region to serve as the gate dielectric layer 109, and the width w1 of the gate dielectric layer 109 is greater than the width w2 of the channel region. Fig. 9 The remaining portion of the pad oxide layer 103 in the substrate shown is flush with the isolation region 106, so that the gate dielectric layer 109 grown in the space after the remaining portion of the pad oxide layer 103 is removed can be flush with the isolation region 106, so that the floating gate structure FG formed on the gate dielectric layer 109 and the control gate CG formed on the isolation region 106 can be completely aligned in the vertical direction.

[0104] The step S130 of forming a gate stack on the surface of the channel region and the step S140 of forming a control gate on the surface of the isolation region at a position opposite to the floating gate structure may include: Fig.13 As shown, a gate conductor layer 110 is formed covering the gate dielectric layer 109 and the region opposite to the isolation region 106 and the gate dielectric layer 109; Fig.14 As shown in FIG. 1 , a second mask layer 112 is formed on the gate conductor layer 110, and then the second mask layer 112 is etched through the second photoresist layer 113 so that the second mask layer 112 is as shown in FIG. Fig.15 As shown, there are second opening regions on both sides of the gate dielectric layer 109; the gate conductor layer 110 is etched through the second opening region to simultaneously form the following through one process: Fig.15 The gate stack shown includes a floating gate structure FG located on the surface of the gate dielectric layer 109 and a control gate CG on the surface of the isolation region 106, thereby achieving the purpose of reducing the manufacturing cost of the multi-time programmable device.

[0105] It should be noted that, since the gate dielectric layer 109 is located on the surface of the channel region between the source region S and the drain region D included in the well region 107, the gate conductor layer 110 is limited to the area above the channel region and does not extend to the areas above the source region S and the drain region D respectively.

[0106] Specifically, Fig.14The second mask layer 112 shown can be formed by depositing a first silicon nitride layer 112a, a first oxide layer 112b, a first amorphous carbon (aC) layer 112c, a first anti-reflective coating (ARC) 112d and a first bottom anti-reflective coating (BARC) 112e in sequence from bottom to top. The first anti-reflective coating 112d can also be formed by depositing a silicon oxynitride layer and an oxide layer in sequence from bottom to top. In addition, after the gate conductor layer 110 is formed, it can be as follows Fig.13 As shown in the figure, an initial oxide layer 111 is formed on the gate conductor layer 110, and the second mask layer 112 is formed on the surface of the initial oxide layer 111. After the floating gate structure FG and the control gate CG are formed, phosphoric acid can be used to Fig.15 As shown in FIG. 1 , the remaining portion of the bottommost first silicon nitride layer 112a in the second mask layer 112 is removed, and in this process, the concentration of phosphoric acid is controlled so that the phosphoric acid does not react with the initial oxide layer 111. Fig.15 The remaining portion of the initial oxide layer 111 shown in FIG. 1 plays a role in protecting the floating gate structure FG and the control gate CG formed. After the remaining portion of the first silicon nitride layer 112a is removed, the following is obtained: Fig.16 The structure shown.

[0107] Furthermore, the manufacturing method provided in the embodiment of the present application may also include: Fig.17 As shown in FIG. 1 , an oxide film layer 114 including an inter-gate dielectric layer is grown on the sidewalls of the floating gate structure FG and the control gate CG, and a gap exists between the oxide film layer 114 grown on the sidewalls of the floating gate structure FG and the oxide film layer 114 grown on the sidewalls of the control gate CG. Then, as shown in FIG. Fig.18 As shown, the inter-gate dielectric layer includes a nitride film layer 115 formed by depositing nitride so that the gap is filled with nitride. In this way, by reasonably controlling the thickness of the oxide film layer 114 grown on the side wall of the floating gate structure FG and the oxide film layer 114 grown on the side wall of the control gate CG, an oxide-nitride-oxide structure as an inter-gate dielectric layer between the floating gate structure FG and the control gate CG can be manufactured using existing processes. No additional masks and related processes are required, so that the manufacturing cost of multi-time programmable devices can be reduced. The above-mentioned oxide film layer 114 can be formed by growing residual oxide (Remain oxide, referred to as Rox) on the side walls of the floating gate structure FG and the control gate CG using a furnace tube, and the spacing between the floating gate structure FG and the control gate CG can be controlled at 40-50nm to facilitate the formation of an inter-gate dielectric layer using the above-mentioned structure that acts as a capacitor. It should be understood that Fig.18In the structure shown in FIG. 1 , there are oxides and nitrides outside the inter-gate dielectric layer including the initial oxide layer 111. Therefore, these excess oxides and nitrides can be removed by a CMP (Chemical Mechanical Polishing) process to obtain a structure as shown in FIG. Fig.19 The structure shown.

[0108] Further, we can Fig. 20 As shown, metal silicide is grown on the surface of the control gate CG, the source region S, the drain region D, and even the second active region included in the well region 107 in some embodiments to form a contact layer 116. The metal silicide as a contact layer has the function of reducing contact resistance. Specifically, a self-aligned silicide barrier (SAB) can be formed first, that is, oxide and silicon nitride are deposited to cover the area where metal silicide does not need to be formed, and then the metal silicide is formed, including: first performing a SiCoNi pre-cleaning process to selectively remove the original material of the area where metal silicide needs to be formed with a thickness of about 60 angstroms, and then depositing a nickel-platinum alloy layer with a thickness of about 120 angstroms and a titanium nitride layer with a thickness of about 50 angstroms in the area where metal silicide needs to be formed, and then performing a first rapid thermal processing (RTP) at 290°C for 30S to form a high-resistance metal silicide Ni2PtSi, and then performing a second rapid thermal processing to convert the high-resistance metal silicide Ni2PtSi into a low-resistance metal silicide NiPtSi2, and after completion, the metal in the area where the metal silicide NiPtSi2 is not formed is eliminated.

[0109] Further, we can Figure 21 to Figure 25 As shown in FIG. 1 , each conductive plug connected to the contact layer 116 in the multi-time programmable device is formed. Specifically, the conductive plug can be firstly Fig.21 As shown in FIG. 1 , a third mask layer 117 and a third photoresist layer 118 are deposited. The third photoresist layer 118 is provided with a third opening region. The third mask layer 117 is etched through the third opening region to form a Fig. 22 The third mask layer 117 may be formed as shown in FIG. Fig.21 As shown, from bottom to top, it includes a second silicon nitride layer 117a with a thickness of 330 angstroms, a second oxide layer 117b with a thickness of 2100 angstroms, a second amorphous carbon layer 117c with a thickness of 1900 angstroms, a second anti-reflective coating layer 117d with a thickness of 370 angstroms, and a second bottom anti-reflective coating layer 117e with a thickness of 200 angstroms. The second anti-reflective coating layer 117d can be formed by sequentially depositing a 320 angstrom silicon oxynitride layer and a 50 angstrom oxide layer from bottom to top, and the thickness of the third photoresist layer 118 can be 1000 angstroms. Fig. 22The contact hole shown is constructed by etching the second silicon nitride layer 117a and the second oxide layer 117b. Fig.23 As shown, an adhesion layer 119 is deposited on the hole wall of the contact hole, for example, titanium with a thickness of about 100 angstroms and titanium nitride with a thickness of about 50 angstroms are deposited in sequence to form the adhesion layer 119. Next, a chemical vapor deposition (CVD) process can be used to fill a metal 120 such as tungsten in the connection hole where the adhesion layer 119 is deposited, and the adhesion layer 119 on the surface of the second oxide layer 117b is removed by a chemical mechanical polishing process so that the metal 120 in the connection hole is flush with the second oxide layer 117b, thereby forming various conductive plugs connected to the contact layer 116 in the multi-time programmable device, including Fig.24 The conductive plug and the contact layer 116 connected to the control gate CG are shown. Fig.25 The conductive plug connecting the contact layer 116 on the source region S and the contact layer 116 on the drain region D is shown in the well region 107. Fig.25 The embodiment shown in which the first active region 107 a and the second active region 107 b are separated by the isolation region 106 further includes a conductive plug connected to the contact layer 116 on the second active region 107 b .

[0110] It should be noted that Fig.24 Shown Figure 1 The cross-sectional view of the multi-time programmable device 100 along line A1A2 is shown. Fig.25 Shown Figure 1 The multi-time programmable device 100 is a cross-sectional view along line C1C2, and thus can be referred to as Fig.24 and Fig.25 The device structure of the multi-time programmable device 100 provided above is understood.

[0111] Finally, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. According to the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that technicians in the relevant technical field can make good use of the present application and the modified use based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A multi-time programmable device, comprising: A substrate, the substrate comprising a well region and an isolation region, the isolation region being arranged adjacent to the well region, the well region comprising a source region and a drain region arranged in an extending direction of the well region and having a conductivity type different from that of the well region, and a channel region therebetween; A gate stack, comprising a gate dielectric layer and a floating gate structure stacked together, located on the surface of the channel region, and the gate dielectric layer is located between the channel region and the floating gate structure; The control gate is located on the surface of the isolation region at a position opposite to the floating gate structure and is separated from the floating gate structure by an inter-gate dielectric layer.

2. The multi-time programmable device according to claim 1, wherein: The isolation region is located at two sides of the well region, and one control gate is respectively arranged on the surface of the isolation region at two sides of the well region.

3. The multi-time programmable device according to claim 1, wherein: The inter-gate dielectric layer is an oxide-nitride-oxide structure, and one oxide film layer is adjacent to the floating gate structure and another oxide film layer is adjacent to the control gate.

4. The multi-time programmable device according to claim 1, wherein: The isolation region further separates the well region into a first active region and a second active region in an extension direction of the well region, wherein the first active region includes the source region and the drain region; The multi-time programmable device further includes: a first conductive plug electrically connected to the source region, a second conductive plug electrically connected to the drain region, a third conductive plug electrically connected to the control gate, and a fourth conductive plug electrically connected to the second active region.

5. A method for manufacturing a multi-time programmable device, comprising: forming a well region and an isolation region in the substrate, wherein the well region and the isolation region are adjacently arranged; A source region and a drain region having a conductivity type different from that of the well region are formed in the well region and arranged in the extending direction of the well region, wherein a channel region is formed between the source region and the drain region; forming a gate stack on the surface of the channel region, wherein the gate stack comprises a gate dielectric layer and a floating gate structure which are stacked, and the gate dielectric layer is located between the channel region and the floating gate structure; A control gate is formed on the surface of the isolation region at a position opposite to the floating gate structure, and the control gate is separated from the floating gate structure by an inter-gate dielectric layer.

6. The manufacturing method according to claim 5, wherein: A well region and an isolation region are formed in the substrate, including: Etching regions on both sides of the central region of the substrate to form two grooves located on both sides of the central region; Filling the two trenches with an isolation dielectric to form the isolation regions included in the substrate located on both sides of the central region; And, doping ions are implanted into the central region to form the well region included in the substrate.

7. The manufacturing method according to claim 6, wherein: A gate stack is formed on the surface of the channel region, comprising: forming a first mask layer on the surface of the substrate, wherein the first mask layer has a first opening region in the channel region and an edge region of the isolation region adjacent to the channel region; Etching the isolation region through the first opening region to form a shallow trench adjacent to the channel region; An oxide layer is grown on the surface of the shallow trench and the channel region to form the gate dielectric layer surrounding the channel region.

8. The manufacturing method according to claim 7, wherein: The substrate includes an oxide pad layer on its surface, and the upper surface of the isolation region formed by filling the isolation dielectric in the two trenches is flush with the upper surface of the oxide pad layer on the surface of the central region of the substrate; While etching the isolation region through the first opening region, the pad oxide layer on the surface of the central region is also etched to remove the pad oxide layer on the surface of the central region; The upper surface of the oxide layer grown on the surface of the shallow trench and the channel region is flush with the upper surface of the isolation region.

9. The manufacturing method according to claim 8, wherein: Forming a gate stack on the surface of the channel region, and forming a control gate at a position opposite to the floating gate structure on the surface of the isolation region, comprising: forming a gate conductor layer covering the gate dielectric layer and the region of the isolation region opposite to the gate dielectric layer; forming a second mask layer on the gate conductor layer, wherein the second mask layer has second opening areas on both sides of the gate dielectric layer; The gate conductor layer is etched through the second opening region to form the gate stack including the floating gate structure located on the surface of the gate dielectric layer and the control gate on the surface of the isolation region.

10. The manufacturing method according to claim 9, further comprising: Growing an oxide film layer included in the inter-gate dielectric layer on the formed sidewalls of the floating gate structure and the control gate, and a gap exists between the oxide film layer grown on the sidewall of the floating gate structure and the oxide film layer grown on the sidewall of the control gate; The gap is filled with nitride to form a nitride film layer included in the inter-gate dielectric layer.

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