File operation device and method for embedded system

Abstract

The present invention belongs to the field of embedded system file operation, and discloses a file operation device and method for an embedded system. The device includes a processor, a general memory, a lock, a secure backup memory, a power supply, a clock and an interface circuit, wherein the lock opens and closes the secure backup memory based on a random number comparison. When the file in the general memory passes the verification, the file operation is performed according to the general process, otherwise the lock is opened by a random number comparison method generated and saved in advance, the secure backup memory is enabled, the backup file in the general memory is used to restore the file in the general memory, and then the lock is set to close the secure backup memory. The present invention discloses a specific method and steps for file operation of an embedded system, and the file operation monitors the operation status throughout the operation, and outputs and records error log information when an error occurs. The present invention can ensure that the file operation is safe and reliable, and improve the stability and reliability of the system.

Description

Technical Field

[0001] The invention belongs to the field of embedded system file operation, and relates to a file operation device and method for an embedded system. Background Art

[0002] An embedded system is a special computer system that is application-centric, based on modern computer technology, and flexibly configures software and hardware modules according to user needs. Its basic hardware structure usually includes a processor, memory, external devices, I / O interface, power supply, and clock system. Embedded operating systems involve the operation and use of some read-only files, which usually include fixed program code, configuration data, and other important fixed information. In order to prevent such read-only files from being damaged or tampered with due to interference, the files need to be verified when used. Common verification methods include checksum, cyclic redundancy check, hash function, etc. If the verification is wrong, the file needs to be corrected or restored to ensure safe and reliable file operation. Summary of the invention

[0003] The present invention provides a file operation device and method for an embedded system, which can effectively solve the problem of file damage or tampering in file operation of an existing embedded operating system, can reliably and safely restore file content when an error occurs in the file, protect the file in the secure backup memory through a locker, ensure that the backed-up source file is safe and reliable during recovery, thereby improving the security and reliability of file operation of the embedded system as a whole.

[0004] The design block diagram of the embedded operating system file operation device proposed by the present invention is shown in the attached figure. Figure 1 As shown. It includes a processor, a lock, a secure backup memory, a general memory, a power supply, a clock system and an interface circuit, etc. In particular, it includes a specially designed independent lock module, which outputs a control signal according to the instruction sent by the processor through the bus, and is connected to the enable signal of the secure backup memory, and enables / disables the secure backup memory through the high and low level states of the signal, thereby realizing the function of read and write operation protection.

[0005] The lock opening and closing control is achieved through two random numbers generated by the processor, which improves the confidentiality and security of the operation and enhances the anti-tampering capability.

[0006] The two random numbers are generated by software after the processor is powered on. The two random numbers remain unchanged during the power-on period of the embedded system. They are regenerated after the power is turned off and then powered on again. Among them, random number 1 is used to open the lock, and random number 2 is used to close the lock.

[0007] Furthermore, the 1# random number is used to control the control signal output by the lock to be at a low level, and the 2# random number is used to control the control signal output by the lock to be at a high level.

[0008] The locker is an independent module, which is realized by programmable devices CPLD, FPGA, and can also be realized by ARM, microcontroller programming.

[0009] Based on the file operation device of the above embedded system, a safe and reliable operation method is provided which can restore damaged or tampered files. The specific steps are as follows:

[0010] S1: After the embedded operating system is powered on, two random numbers are generated, 1# random number and 2# random number. 1# random number is used to control the control signal output by the lock to be low level, and 2# random number is used to control the control signal output by the lock to be high level. 1# random number and 2# random number are written into the lock's opening flag register and closing flag register respectively by the processor. The lock's error register is initialized to 0. Enter S2.

[0011] S2: The processor performs file operations, reads files in the general memory, and verifies the integrity of the files. If the verification passes, the file is considered intact, and the error register of the locker is cleared after the file operation. If the verification fails, the error register is first updated, the error count value therein is increased by one, and then the error count value is checked to see if it reaches the threshold value. If it reaches the threshold value, the file operation error overload information is recorded and the process exits. If it does not reach the threshold value, the file that failed the verification is deleted, and a new empty file with the same name is created. Then, the process enters S3.

[0012] S3: The processor writes random number 1# into the lock's opening control register and enters S4;

[0013] S4: The locker sends the values ​​of the opening control register and the opening flag register to the comparator for comparison. If they are the same, the safety backup memory is controlled to be opened, otherwise it is closed; the locker updates the switch status register to open or close; enter S5;

[0014] S5: The processor checks the switch status register of the lock. If it is in the closed state, it records the error message of the opening failure and exits; if it is in the open state, it reads the backup file in the safe backup memory and copies its content to the file of the same name in the general memory; then enters S6;

[0015] S6: The processor writes the 2# random number into the lock's closing control register and enters S7;

[0016] S7: The locker sends the values ​​of the shutdown control register and the shutdown flag register to the comparator for comparison. If they are the same, the safety backup memory is closed, otherwise it is opened; the locker updates the switch status register to close or open; enter S8;

[0017] S8: The processor checks the switch status register of the lock, and exits if it is closed; if it is open, it records the closing failure error message and then exits. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a design block diagram of the embedded system file operation device of the present invention.

[0020] Figure 2 It is a step diagram of the embedded system file operation method of the present invention.

[0021] Figure 3 It is a design block diagram of the lock of the present invention realized by a programmable device. Implementation

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention described and given in the drawings here can be arranged and designed in other different orders or configurations.

[0023] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Embodiment 1:

[0025] The following is a detailed description of the embodiment 1 of the present invention in conjunction with the accompanying drawings. Figure 1 .

[0026] The lock is implemented using programmable logic devices such as CPLD and FPGA. The lock consists of six registers, two comparators, a selector and an address decoder. The design block diagram is shown in the attached figure. Figure 3 shown.

[0027] The input signal of the lock is the bus signal of the processor, including: control bus, address bus and data bus, which are connected to the corresponding buses of the processor respectively. The output control signal is connected to the enable signal EN of the safety backup memory. Since the EN signal is usually low effective, all output low levels turn on the safety backup memory; output high levels turn off the safety backup memory.

[0028] The six registers are: enable flag register, disable flag register, enable control register, disable control register, switch status register and error register.

[0029] The 1# random number generated when the processor is powered on is written into the enable flag register, and the 2# random number is written into the disable flag register as a basis for comparison and judgment of enable and disable.

[0030] When the file in the general register fails the integrity check and needs to be restored, the processor writes the 1# random number generated at startup into the start control register. The locker sends the values ​​of the start control register and the start status register to comparator 1. If the two are equal, the output of comparator 1 is a low-level signal. The decoder decodes the start control register address and controls the two-way selector to select the signal of comparator 1 as the output control signal.

[0031] When the processor file is restored and the security backup memory needs to be closed, the 2# random number is written into the close control register. The locker sends the values ​​of the close control register and the close standard register to comparator 2. If the two are equal, the output of comparator 2 is a high-level signal. The decoder decodes the close control register address and controls the two-way selector to select the signal of comparator 2 as the output control signal.

[0032] The input signals of the two-way selector are the output signals of comparator 1 and comparator 2. The output of comparator 1 is selected by turning on the control register address, and the output of comparator 2 is selected by turning off the control register address.

[0033] The switch status register of the lock stores the status of the output control signal. It is used by the processor to determine the status of the lock. If it is inconsistent with the actual operation, the corresponding error information is recorded in the error log.

[0034] The error register of the locker records the number of failed file recovery attempts. If the number exceeds a set threshold, the error information is recorded in the error log. In this embodiment, the threshold is set to 3.

[0035] Further, the detailed steps of the embedded system file operation method of the present invention refer to the attached Figure 2 accomplish.

[0036] Embodiment 2:

[0037] Based on Example 1, Example 2 is provided. The difference between Example 2 and Example 1 is that the locker is implemented by a single-chip microcomputer or an ARM processor. The clock signal, read-write control signal, data bus, and address bus of the single-chip microcomputer or ARM are connected to the corresponding signals of the processor.

[0038] Six general registers of ARM or single-chip microcomputer are selected as the start flag register, the close flag register, the start control register, the close control register, the switch status register and the error register.

[0039] Select the general purpose input and output GPIO of ARM or microcontroller as the output control signal.

[0040] Comparator 1 and Comparator 2 are implemented by software programming.

[0041] The two-way selector is implemented through software programming.

Claims

1. A file operation device for an embedded system, characterized in that: The device comprises a processor, a general memory, a lock, a secure backup memory, a power supply, a clock and an interface circuit; when an error occurs in a file in the general memory or it is tampered with, verification identification and recovery are performed, the secure backup memory is opened by a control signal output by the lock, and a file with the same name in the general memory is restored by a backup file in the secure backup memory, and after the file restoration is completed, the secure backup memory is closed by a control signal output by the lock; The lock is an independent component, and its function is to control the opening or closing of the safety backup memory by outputting a control signal; the lock is implemented by a CPLD or FPGA programmable device, including a register group containing six registers, an address decoder, a comparator and a two-way selector; the register group includes an opening flag register, an opening control register, a closing flag register, a closing control register, a switch status register and an error register.

2. The device according to claim 1, characterized in that The lock is implemented by programming a single-chip microcomputer or an ARM microprocessor, and uses the general registers of the single-chip microcomputer or the ARM microprocessor as an opening flag register, an opening control register, a closing flag register, a closing control register, a switch status register and an error register; and uses the general input and output ports of the single-chip microcomputer or the ARM microprocessor to output control signals to open or close the security backup memory.

3. The device according to claim 1 or 2, characterized in that The enable signal of the safety backup memory is connected to the control signal output by the locker.

4. The device according to claim 1 or 2, characterized in that: The control signal output by the lock is set according to the values ​​in the open flag register, the open control register, the close flag register, and the close control register: when the processor writes the open control register, the written value is the same as the open flag register, and an open signal is output, otherwise the current state is maintained; when the processor writes the close control register, if the written value is the same as the close flag register, a close signal is output, otherwise the current state is maintained.

5. The device according to claim 1 or 2, characterized in that: The values ​​of the four registers, namely, the enable flag register, the enable control register, the disable flag register and the disable control register, are two random numbers generated by the processor when it is powered on. The 1# random number is used to control the control signal output by the lock to be low level, and the 2# random number is used to control the control signal output by the lock to be high level.

6. A file operation method for an embedded system, the method using the device according to claim 1 or 2 to implement the file operation of the embedded system, characterized in that: The following steps are involved: S1: After the embedded operating system is powered on, two random numbers are generated, 1# random number and 2# random number. 1# random number is used to control the control signal output by the lock to be low level, and 2# random number is used to control the control signal output by the lock to be high level. 1# random number and 2# random number are written into the lock's opening flag register and closing flag register respectively by the processor. The lock's error register is initialized to 0. Enter S2. S2: The processor performs file operations, reads files in the general memory, and verifies the integrity of the files. If the verification passes, the file is considered intact. After the file operation, the error register of the locker is cleared. If the check fails, the error register is updated first, the error count value therein is increased by one, and then the error count value is checked to see if it reaches the threshold value. If it reaches the threshold value, the file operation error overload information is recorded and the program exits; if it does not reach the threshold value, the file that failed the check is deleted and a new empty file with the same name is created; Enter S3; S3: The processor writes random number 1# into the lock's opening control register and enters S4; S4: The locker sends the values ​​of the opening control register and the opening flag register to the comparator for comparison. If they are the same, the safety backup memory is controlled to be opened, otherwise it is closed; the locker updates the switch status register to open or close; and enters S5; S5: The processor checks the switch status register of the lock. If it is in the closed state, the processor records the error message of the opening failure and exits. If it is in the open state, the processor reads the backup file in the secure backup memory and copies its content to the file of the same name in the general memory. Enter S6; S6: The processor writes the 2# random number into the lock's closing control register and enters S7; S7: The locker sends the values ​​of the closing register and the closing flag register to the comparator for comparison. If they are the same, the safety backup memory is closed, otherwise it is opened; the locker updates the switch status register to close or open; enter S8; S8: The processor checks the switch status register of the lock, and exits if it is closed; if it is open, it records the closing failure error message and then exits.

Images