Synchronous control method, device, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a synchronization control method, device, electronic device and readable storage medium, the method comprising: controlling the design to be tested to execute the test program, and determining the number of execution instructions of the design to be tested; when the design to be tested meets the first trigger condition of the instruction submission event, driving the reference model to execute the same number of instructions according to the number of execution instructions of the design to be tested; when the design to be tested meets the second trigger condition of the synchronization event, interrupting the operation of the design to be tested and obtaining the first state information of the design to be tested; updating the second state information of the reference model according to the first state information, so as to synchronize the state of the design to be tested with the reference model. The embodiment of the present invention decouples the driving logic of the design to be tested and the reference model by dividing the instruction submission event and the synchronization event, thereby improving the operation speed of the verification system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a synchronization control method, device, electronic equipment and readable storage medium. Background Art

[0002] For frameworks that run processors on FPGAs and need to compare them with software reference models, a method is needed to synchronously control the processors on the FPGA and the software reference models. Traditional processor verification DUT and REF are synchronized at the cycle level. The DUT and REF drivers have a sequential dependency and are not easy to decouple, resulting in a slower verification system. Summary of the invention

[0003] The embodiments of the present invention provide a synchronous control method, device, electronic device and readable storage medium, which can solve the problem in the related art that the driving logic of the design to be tested and the reference model are dependent, resulting in the slow operation of the verification system.

[0004] In order to solve the above problem, an embodiment of the present invention discloses a synchronization control method, which is applied to a verification system, wherein the verification system includes a hardware end and a software end, wherein the hardware end includes a design to be tested, and the software end includes a reference model of the design to be tested; the method includes:

[0005] Controlling the design to be tested to execute the test program and determining the number of execution instructions of the design to be tested;

[0006] When the design to be tested meets the first trigger condition of the instruction submission event, driving the reference model to execute the same number of instructions according to the number of execution instructions of the design to be tested;

[0007] When the design to be tested meets the second trigger condition of the synchronization event, interrupting the operation of the design to be tested and acquiring first state information of the design to be tested;

[0008] The second state information of the reference model is updated according to the first state information to synchronize the states of the design to be tested and the reference model.

[0009] Optionally, the second trigger condition of the synchronization event includes at least one of the following:

[0010] An abnormal event occurs in the design to be tested;

[0011] An external interrupt event occurs in the design under test;

[0012] A self-trap event occurs in the design under test;

[0013] The design under test executes atomic instructions;

[0014] The design under test accesses external devices on the hardware side.

[0015] Optionally, the hardware end further includes a control module; the output end of the first clock domain of the control module is connected to the input end of the gated clock, and the output end of the gated clock is connected to the input end of the second clock domain of the design to be tested;

[0016] The interrupting the operation of the design under test includes:

[0017] The control module turns off the gated clock to suspend the clock of the second clock domain.

[0018] Optionally, the instruction submission event includes an instruction comparison event, and the first trigger condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

[0019] Optionally, the method further comprises:

[0020] Writing first execution information of the design to be tested into a first queue;

[0021] Writing second execution information of the reference model into a second queue;

[0022] After detecting that data is written to both the first queue and the second queue, reading the first execution information recorded in the first queue and the second execution information recorded in the second queue;

[0023] comparing the first execution information with the second execution information;

[0024] In the case that the first execution information does not match the second execution information, it is determined that an operation error occurs in the design to be tested, and the operation of the design to be tested and the reference model is interrupted.

[0025] Optionally, the instruction submission event includes a register comparison event, and the first trigger condition includes: the number of instructions executed by the design under test since the last register comparison event occurred is greater than or equal to a second threshold.

[0026] Optionally, the hardware end further includes a register data module; and the method further includes:

[0027] Writing the first value of each register in the design to be tested into the register data module;

[0028] Writing the second value of each register in the reference model into the register data module;

[0029] When the design under test meets the first trigger condition of the register comparison event, the operation of the design under test is interrupted until the first value and the second value are all written into the register data module, and then the operation of the design under test is resumed to compare the first value and the second value.

[0030] On the other hand, an embodiment of the present invention discloses a synchronization control device, which is applied to a verification system, wherein the verification system includes a hardware end and a software end, wherein the hardware end includes a design to be tested, and the software end includes a reference model of the design to be tested; the device includes:

[0031] A first control module, used for controlling the design to be tested to execute the test program and determining the number of execution instructions of the design to be tested;

[0032] A second control module is used to drive the reference model to execute the same number of instructions according to the number of executed instructions of the design under test when the design under test meets the first trigger condition of the instruction submission event;

[0033] An interrupt module, configured to interrupt the operation of the design to be tested and obtain first status information of the design to be tested when the design to be tested meets a second trigger condition of a synchronization event;

[0034] A synchronization module is used to update the second state information of the reference model according to the first state information, so as to synchronize the state of the design to be tested with the reference model.

[0035] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned synchronization control method.

[0036] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned synchronization control method.

[0037] The embodiments of the present invention include the following advantages:

[0038] The embodiment of the present invention provides a synchronous control method, which abstracts the behavior of the design under test into events, and performs synchronous control on the design under test and the reference model according to the events: when the first trigger condition of the instruction submission event is met, the reference model is driven to execute the same number of instructions according to the number of execution instructions of the design under test, so as to synchronize the execution information of the reference model with the design under test; when the second trigger condition of the synchronization event is met, the operation of the design under test is interrupted, and the second state information of the reference model is synchronized according to the first state information of the design under test, so as to synchronize the state of the design under test with the reference model. The embodiment of the present invention decouples the driving logic of the design under test and the reference model by dividing the instruction submission event and the synchronization event, thereby improving the operation speed of the verification system. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0040] Figure 1 is a flowchart of steps of an embodiment of a synchronization control method of the present invention;

[0041] Figure 2 is a structural block diagram of an embodiment of a synchronous control device of the present invention;

[0042] Figure 3 It is a structural block diagram of an electronic device for synchronous control provided by an example of the present invention. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0045] Method Embodiment

[0046] Reference Figure 1 , shows a flowchart of a synchronous control method embodiment of the present invention, the method is applied to a verification system, the verification system includes a hardware end and a software end, the hardware end includes a design to be tested, and the software end includes a reference model of the design to be tested; the method may specifically include the following steps:

[0047] Step 101, controlling the design to be tested to execute the test program, and determining the number of execution instructions of the design to be tested;

[0048] Step 102: when the design to be tested meets the first trigger condition of the instruction submission event, drive the reference model to execute the same number of instructions according to the number of execution instructions of the design to be tested;

[0049] Step 103: When the design to be tested meets the second trigger condition of the synchronization event, interrupt the operation of the design to be tested and obtain the first state information of the design to be tested;

[0050] Step 104: Update the second state information of the reference model according to the first state information to synchronize the states of the design under test and the reference model.

[0051] The verification method provided in the embodiment of the present invention can be applied to a verification system, wherein the verification system includes a hardware end and a software end, and the hardware end and the software end are used to perform collaborative verification on a design under test (DUT). The hardware end includes the DUT, and the software end includes a reference model of the DUT.

[0052] Exemplarily, the hardware end in the present invention may be a programmable logic chip (Field Programmable Gate Array, FPGA), and the design to be tested is deployed in a programmable logic (Programmable Logic, PL) area of ​​the FPGA chip.

[0053] It should be noted that FPGA is a reconfigurable integrated circuit chip with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs to adapt to different applications and functions. FPGAs are composed of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks are usually composed of look-up tables (LUTs), registers, and other logic elements, which can perform various logic functions. Programmable interconnect resources are used to connect logic blocks to form the required circuit structure. With FPGAs, design engineers can use hardware description languages ​​to describe the required circuit functions and convert them into bitstreams compatible with FPGA chips through programming tools. The bitstream contains information for programming and configuring the internal logic and interconnection resources of the FPGA. One of the main advantages of FPGAs is its programmability and flexibility. It allows design engineers to implement customized functions and algorithms at the hardware level without the need for traditional custom integrated circuit design and manufacturing processes. This makes FPGAs play an important role in prototype development and rapid design iteration.

[0054] The Design Under Test (DUT) refers to the circuit design or implementation to be tested in prototype verification. Exemplarily, the design under test can be a register transfer level (RTL) circuit or other hardware design. It should be noted that the RTL circuit is a common hardware description level circuit. The RTL circuit describes the behavior and structure of the digital circuit and is represented using the abstract hierarchy of the register transfer level. The RTL circuit description is usually written in a hardware description language (HDL), such as VHDL (VHSIC Hardware Description Language), Verilog HDL, and System Verilog HDL. Designers can use the RTL level description to define and implement the required digital circuit functions, and then use the synthesis tool to convert the RTL level description into a physical implementation in a field-programmable gate array (FPGA).

[0055] The reference model is used to implement the same function as the design under test. During the verification of the design under test, the data generated when the reference model is called can be considered correct and used as reference data for comparison with the data generated by the design under test. It is understandable that different reference models are generated for different designs under test. As an example, before the design under test is subjected to high-level synthesis, a source design model of the design under test can be generated based on the design code of the design under test in C / C++ language. The source design model has the same algorithm function as the design under test and can be used as a reference model of the design under test.

[0056] Software and hardware need to communicate through a defined interaction structure, and the decoupling of software and hardware is achieved through interfaces. For example, for a CPU, the interface between software and hardware is the instruction set architecture ISA. The processor under the ISA is hardware, and the various programs, data sets, files, etc. above the instruction set are software.

[0057] The software end in the embodiment of the present invention refers to a program on an instruction set. The software end can be installed in a personal computer (PC) or in other electronic devices with an operating system that can run software. The electronic devices may include but are not limited to: smart terminals, computers, personal digital assistants (PDAs), tablet computers, etc.

[0058] The hardware and software ends communicate through data interfaces, such as the high-speed serial computer expansion bus standard Peripheral Component Interconnect Express (PCIE) interface, General Purpose Input Output (GPIO), and so on.

[0059] In the embodiment of the present invention, the behavior of the design under test can be abstracted as events, and the design under test and the reference model can be synchronized based on the events, thereby decoupling the design under test and the reference model.

[0060] Exemplarily, taking a processor with multiple out-of-order operations as an example, the processor behavior can be abstracted into: instruction comparison events (instruction execution result comparison events), register comparison events, comparison error events, exception events, external interrupt events, self-trap events, atomic instruction events, and peripheral access events. Among them, the instruction comparison event refers to the comparison of the instruction execution results of the design under test and the reference model. The register comparison event refers to the comparison of the values ​​of each register in the design under test and the reference model. The comparison error event includes at least one of the comparison error of the instruction execution result of the design under test and the reference model and the comparison error of the register value. The exception event refers to an abnormal event that occurs during the operation of the design under test, and the exception event will interrupt the normal execution process of the instruction. In the field of chip design, the exception events in the design under test can generally include hardware execution exceptions or software faults. The exception received by the processor after executing an instruction will trigger the processor to execute a special exception handling process. The external interrupt event refers to the interruption of the design under test caused by the input signal outside the design under test. For example, the external interrupt event of the design under test can include that when the design under test fails to run, the interrupt module in the hardware end sends an interrupt signal to the design under test, causing the design under test to be interrupted. After the processor receives an interrupt signal from external hardware, it needs to respond to the input interrupt. A trap event is a pre-arranged exception event, just like a pre-set "trap". When the processor executes a trap instruction, it will automatically perform corresponding processing according to different trap types, and then return to the next instruction of the trap instruction (if the trap instruction is a transfer instruction, it returns to the transfer target instruction). Atomic instruction events refer to the processor locking the accessed memory space to prevent other hardware from accessing it, ensuring that the processor can access data synchronously with multiple threads when running the program. Access peripheral events refer to the design under test accessing external devices. The external devices refer to devices mounted on the FPGA chip that are neither on the PL side nor on the PS side, such as external storage devices such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR).

[0061] In an embodiment of the present invention, the design to be tested and the reference model execute the same test program. When the design to be tested meets the first trigger condition of the instruction submission event, the reference model is driven to execute the same number of instructions according to the number of execution instructions of the design to be tested. Exemplarily, during the operation of the design to be tested, if the first trigger condition is met, a data packet is generated according to the first execution information of the design to be tested, and the data packet contains the number of execution instructions of the design to be tested. The hardware end sends the data packet to the software end. Based on the number of execution instructions in the data packet, the software end drives the reference model to execute the same number of instructions.

[0062] Furthermore, the software end can update the second execution information of the reference model into the data packet and send the updated data packet to the hardware end. The hardware end parses the updated data packet of the software end to obtain the second execution information of the reference model. Then, the first execution information of the design to be tested is compared with the second execution information of the reference model. If the first execution information does not match the second execution information, it can be determined that the design to be tested has an error in operation.

[0063] It can be understood that the test programs executed by the design to be tested and the reference model are the same, so the order of instructions executed by the two is the same. When the design to be tested and the reference model execute the same number of instructions each time, it can be ensured that the first execution information of the design to be tested and the second execution information of the reference model are synchronized, thereby achieving synchronous control of the design to be tested and the reference model, avoiding inaccurate verification results due to the lack of synchronization between the first execution information and the second execution information, and ensuring the accuracy of the verification results.

[0064] In addition, if the design under test meets the second trigger condition of the synchronization event, the operation of the design under test can be interrupted, the first state information of the design under test can be obtained, and the second state information of the reference model can be updated based on the first state information of the design under test to keep the state of the design under test and the reference model synchronized.

[0065] Optionally, the second trigger condition of the synchronization event includes at least one of the following:

[0066] An abnormal event occurs in the design to be tested;

[0067] An external interrupt event occurs in the design under test;

[0068] A self-trap event occurs in the design under test;

[0069] The design under test executes atomic instructions;

[0070] The design under test accesses external devices on the hardware side.

[0071] As an example, when the hardware side detects that the design to be tested encounters an event that requires synchronization (such as interruption, exception, self-trap, access to peripherals, atomic instruction events, etc.), an interrupt signal is sent to the design to be tested and enters a synchronization processing state. At this time, the relevant state of the design to be tested needs to be sent to the software side, and the corresponding synchronization function of the software side is started. Exemplarily, the hardware side also includes a control module and a transmission module. The control module detects the synchronization event and outputs the corresponding synchronization event signal to the transmission module, and also outputs the number of instructions to be executed. The transmission module reads the corresponding synchronization information according to the synchronization event signal and forms a data packet, sets the corresponding synchronization information bit, and then sends the data packet to the software side. After receiving the data packet, the software side parses it, first drives the reference model to execute the instruction according to the number of instructions to be executed and writes the result into the data packet, and then the software side extracts the synchronization information in the data packet and passes it into the synchronization processing function, and updates the relevant state in the reference model. After the processing is completed, the end state of the data packet is set, and the data packet is sent to the parsing module of the hardware side through the transmission module. The parsing module parses the data packet, generates a synchronization event end signal, and sends the signal to the control module, and writes the instruction execution result in the data packet into the FIFO queue corresponding to the reference model. After receiving the synchronization event end signal, the control module ends the interrupt signal, resumes the operation of the design under test, and the synchronization event ends.

[0072] Optionally, the hardware end further includes a control module; the output end of the first clock domain of the control module is connected to the input end of the gated clock, and the output end of the gated clock is connected to the input end of the second clock domain of the design to be tested. The interrupting the operation of the design to be tested includes:

[0073] The control module turns off the gated clock to suspend the clock of the second clock domain.

[0074] In the embodiment of the present invention, the control module may suspend the clock in the clock domain of the design under test by gating the clock.

[0075] It should be noted that when the clock is gated, the input clock can be output according to the clock enable condition. When the processor clock is no longer updated, the internal state of the processor remains unchanged, realizing the pause function. The gated clock enable comes from the external module input. For example, when a synchronization event is triggered, or the FIFO storing processor information such as PC is almost full, the operation of the processor will be paused.

[0076] The hardware modules whose clocks are suspended need to be considered as separate clock domains. In other words, when the clock of the design under test is suspended, the second clock domain of the design under test is a separate clock domain, and the communication between the hardware in this clock domain and the outside world needs to be processed across clock domains.

[0077] Exemplarily, for bus signals, since it is a bidirectional communication, the AXI-InterConnect IP is used for connection. Since the paused clock does not trigger an update, the AXI-InterConnect module can save the access status on the bus.

[0078] For unidirectional line type signals, only the signals when the clock of the design under test is not paused are sampled, and the signal input when it is paused is ignored.

[0079] In an embodiment of the present invention, the control module can use the original clock domain of the design under test and control the gated clock to control the running state of the design under test. For the AXI bus originally used by the design under test to access peripherals, AXI-InterConnect is added to handle synchronization issues. For the connection between the design under test and the control module, the control module will only detect data when the design under test is not paused. When the control module sends a communication to an external module, AXI_interConnect is used to process the output request, and an asynchronous FIFO is used to store the data returned by the external module.

[0080] Optionally, the instruction submission event includes an instruction comparison event, and the first trigger condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

[0081] Optionally, the method further comprises:

[0082] Step S11, writing the first execution information of the design to be tested into the first queue;

[0083] Step S12, writing the second execution information of the reference model into the second queue;

[0084] Step S13: after detecting that both the first queue and the second queue have data written, reading the first execution information recorded in the first queue and the second execution information recorded in the second queue;

[0085] Step S14: comparing the first execution information with the second execution information;

[0086] Step S15: When the first execution information does not match the second execution information, it is determined that an operation error occurs in the design to be tested, and the operation of the design to be tested and the reference model is interrupted.

[0087] In an embodiment of the present invention, a queue can be configured for the design to be tested and the reference model on the hardware side, respectively, for writing execution information. Specifically, the first execution information of the design to be tested is written into the first queue, and the second execution information of the reference model is written into the second queue. After detecting that both the first queue and the second queue have data written, the execution information recorded in the two queues is read and compared. If the first execution information does not match the second execution information, it can be determined that the design to be tested has an error in operation.

[0088] The contents of the first execution information and the second execution information can be determined according to the data that needs to be verified in the design to be tested. For example, the first execution information and the second execution information can include the values ​​of all general purpose registers (GPR), the values ​​of control and status registers (CSR), the values ​​of program counters (PC), the results of instruction execution, etc. In practical applications, the specific contents of the first execution information and the second execution information can be specified according to the actual situation and specific verification requirements. Taking the design to be tested as a RISC-V processor as an example, when making comparisons, 32 GPR registers, 18 CSR registers, and PC values ​​can be compared.

[0089] The first execution information of the design to be tested is compared with the second execution information of the reference model. If the first execution information matches the second execution information, for example, the first execution information is the same as the second execution information, or the value of the parameter in the first execution information falls within the value range of the corresponding parameter in the second execution information, etc., it can be considered that there is no error in the design to be tested. At this time, the design to be tested can be controlled to continue executing the next instruction.

[0090] If the first execution information does not match the second execution information, for example, the first execution information is different from the second execution information, or the value of the parameter in the first execution information does not fall within the value range of the corresponding parameter in the second execution information, etc., it can be considered that the design under test has an error. In this case, a snapshot can be taken of the entire hardware end, the status information of the hardware end can be saved, and the saved data can be sent to the software end, which displays the information so that the verification engineer can perform on-site error checking based on the saved status information.

[0091] In a possible application scenario of the present invention, snapshot information on the hardware side may be imported into simulation software on the software side, and the simulation software may be used to perform fine-grained debugging on the design to be tested.

[0092] Optionally, the instruction submission event includes a register comparison event, and the first trigger condition includes: the number of instructions executed by the design under test since the last register comparison event occurred is greater than or equal to a second threshold.

[0093] Optionally, the hardware end further includes a register data module; and the method further includes:

[0094] Writing the first value of each register in the design to be tested into the register data module;

[0095] Writing the second value of each register in the reference model into the register data module;

[0096] When the design under test meets the first trigger condition of the register comparison event, the operation of the design under test is interrupted until the first value and the second value are all written into the register data module, and then the operation of the design under test is resumed to compare the first value and the second value.

[0097] In an embodiment of the present invention, a register data module, such as a Diff_Tilefor Reg data module, may be allocated in the hardware end. When the triggering condition of the register comparison event is met, the first value of each register in the design to be tested and the second value of each register in the reference model are written into the register data module for comparison.

[0098] Optionally, the method further comprises:

[0099] When it is detected that the number of instructions executed by the design under test since the last register comparison event occurs is greater than or equal to a second threshold, the operation of the design under test is interrupted until the first value and the second value are all written into the register data module, and then the operation of the design under test is resumed.

[0100] In an embodiment of the present invention, when the triggering condition of the register comparison event is met, the operation of the design under test can be interrupted first. After the first value of the register in the design under test and the second value of the register in the reference model are written into the register data module, the operation of the design under test can be resumed to avoid the design under test continuing to execute instructions to update the value of the register, causing the register state of the design under test to be out of sync with the register state of the reference model.

[0101] In summary, the embodiment of the present invention provides a synchronous control method, which abstracts the behavior of the design under test into events, and performs synchronous control on the design under test and the reference model according to the events: when the first trigger condition of the instruction submission event is met, the reference model is driven to execute the same number of instructions according to the number of execution instructions of the design under test, so as to synchronize the execution information of the reference model with the design under test; when the second trigger condition of the synchronization event is met, the operation of the design under test is interrupted, and the second state information of the reference model is synchronized according to the first state information of the design under test, so as to synchronize the state of the design under test with the reference model. The embodiment of the present invention decouples the driving logic of the design under test and the reference model by dividing the instruction submission event and the synchronization event, thereby improving the operation speed of the verification system.

[0102] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0103] Device Embodiment

[0104] Reference Figure 2 , shows a structural block diagram of a synchronous control device of the present invention, which is applied to a verification system, wherein the verification system includes a hardware end and a software end, wherein the hardware end includes a design to be tested, and the software end includes a reference model of the design to be tested; the device may specifically include:

[0105] The first control module 201 is used to control the design under test to execute the test program and determine the number of execution instructions of the design under test;

[0106] A second control module 202 is used to drive the reference model to execute the same number of instructions according to the number of executed instructions of the design under test when the design under test meets the first trigger condition of the instruction submission event;

[0107] An interrupt module 203 is used to interrupt the operation of the design under test and obtain first state information of the design under test when the design under test meets the second trigger condition of the synchronization event;

[0108] The synchronization module 204 is used to update the second state information of the reference model according to the first state information, so as to synchronize the state of the design under test with the reference model.

[0109] Optionally, the second trigger condition of the synchronization event includes at least one of the following:

[0110] An abnormal event occurs in the design to be tested;

[0111] An external interrupt event occurs in the design under test;

[0112] A self-trap event occurs in the design under test;

[0113] The design under test executes atomic instructions;

[0114] The design under test accesses external devices on the hardware side.

[0115] Optionally, the hardware end further includes a control module; the output end of the first clock domain of the control module is connected to the input end of the gated clock, and the output end of the gated clock is connected to the input end of the second clock domain of the design to be tested;

[0116] The interrupt module comprises:

[0117] The clock control submodule is used for the control module to turn off the gated clock to suspend the clock of the second clock domain.

[0118] Optionally, the instruction submission event includes an instruction comparison event, and the first trigger condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

[0119] Optionally, the device further comprises:

[0120] A first writing module, used for writing the first execution information of the design to be tested into a first queue;

[0121] A second writing module, used for writing second execution information of the reference model into a second queue;

[0122] A reading module, configured to read the first execution information recorded in the first queue and the second execution information recorded in the second queue after detecting that data is written to both the first queue and the second queue;

[0123] A first comparison module, configured to compare the first execution information with the second execution information;

[0124] The determination module is used to determine that the design to be tested has an operation error when the first execution information does not match the second execution information, and interrupt the operation of the design to be tested and the reference model.

[0125] Optionally, the instruction submission event includes a register comparison event, and the first trigger condition includes: the number of instructions executed by the design under test since the last register comparison event occurred is greater than or equal to a second threshold.

[0126] Optionally, the hardware end further includes a register data module; the device further includes:

[0127] A third writing module, used for writing the first value of each register in the design to be tested into the register data module;

[0128] A fourth writing module, used for writing the second value of each register in the reference model into the register data module;

[0129] The second comparison module is used to interrupt the operation of the design under test when the design under test meets the first trigger condition of the register comparison event, and resume the operation of the design under test and compare the first value with the second value after the first value and the second value are all written into the register data module.

[0130] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0131] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0132] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0133] Reference Figure 3 , is a structural block diagram of an electronic device for synchronous control provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the synchronization control method of the aforementioned embodiment.

[0134] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0135] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0136] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0137] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is enabled to execute Figure 1 The synchronous control method shown.

[0138] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0139] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0140] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0141] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0142] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0143] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0144] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0145] The above is a detailed introduction to a synchronous control method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A synchronous control method, characterized in that: Applied to a verification system, the verification system includes a hardware end and a software end, the hardware end includes a design to be tested, and the software end includes a reference model of the design to be tested; the method includes: Controlling the design to be tested to execute a test program and determining the number of execution instructions of the design to be tested; When the design to be tested meets the first trigger condition of the instruction submission event, driving the reference model to execute the same number of instructions according to the number of execution instructions of the design to be tested; When the design to be tested meets the second trigger condition of the synchronization event, interrupting the operation of the design to be tested and acquiring the first state information of the design to be tested; updating the second state information of the reference model according to the first state information to synchronize the states of the design to be tested and the reference model; Wherein, the design to be tested and the reference model execute the same test procedure; When the design to be tested meets the first trigger condition of the instruction submission event, driving the reference model to execute the same number of instructions according to the number of execution instructions of the design to be tested includes: When the design to be tested meets the first trigger condition of the instruction submission event, the hardware end generates a data packet according to the first execution information of the design to be tested, and sends the data packet to the software end; the data packet includes the number of execution instructions of the design to be tested; The software end drives the reference model to execute the same number of instructions based on the number of execution instructions in the data packet.

2. The method according to claim 1, characterized in that The second trigger condition of the synchronization event includes at least one of the following: An abnormal event occurs in the design to be tested; An external interrupt event occurs in the design under test; A self-trap event occurs in the design under test; The design under test executes atomic instructions; The design under test accesses external devices on the hardware side.

3. The method according to claim 1, characterized in that The hardware end also includes a control module; the output end of the first clock domain of the control module is connected to the input end of the gated clock, and the output end of the gated clock is connected to the input end of the second clock domain of the design to be tested; The interrupting the operation of the design to be tested includes: The control module turns off the gated clock to suspend the clock of the second clock domain.

4. The method according to claim 1, characterized in that The instruction submission event includes an instruction comparison event, and the first trigger condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

5. The method according to claim 4, characterized in that The method further comprises: Writing first execution information of the design to be tested into a first queue; Writing second execution information of the reference model into a second queue; After detecting that data is written to both the first queue and the second queue, reading the first execution information recorded in the first queue and the second execution information recorded in the second queue; comparing the first execution information with the second execution information; In the case that the first execution information does not match the second execution information, it is determined that an operation error occurs in the design to be tested, and the operation of the design to be tested and the reference model is interrupted.

6. The method according to claim 1, characterized in that The instruction submission event includes a register comparison event, and the first trigger condition includes: the number of instructions executed by the design under test since the last register comparison event occurred is greater than or equal to a second threshold.

7. The method according to claim 6, characterized in that The hardware end also includes a register data module; the method also includes: Writing the first value of each register in the design to be tested into the register data module; Writing the second value of each register in the reference model into the register data module; When the design under test meets the first trigger condition of the register comparison event, the operation of the design under test is interrupted until the first value and the second value are all written into the register data module, and then the operation of the design under test is resumed to compare the first value and the second value.

8. A synchronous control device, characterized in that: Applied to a verification system, the verification system includes a hardware end and a software end, the hardware end includes a design to be tested, and the software end includes a reference model of the design to be tested; the device includes: A first control module, used for controlling the design to be tested to execute a test program and determining the number of execution instructions of the design to be tested; A second control module is used to drive the reference model to execute the same number of instructions according to the number of executed instructions of the design under test when the design under test meets the first trigger condition of the instruction submission event; An interrupt module, configured to interrupt the operation of the design to be tested and obtain first status information of the design to be tested when the design to be tested meets a second trigger condition of a synchronization event; A synchronization module, configured to update the second state information of the reference model according to the first state information, so as to synchronize the state of the design to be tested with the reference model; Wherein, the design to be tested and the reference model execute the same test procedure; A second control module, comprising a data packet generating unit arranged at the hardware end and a driving unit arranged at the software end; The data packet generating unit is used to generate a data packet according to the first execution information of the design to be tested, and send the data packet to the software end when the design to be tested meets the first trigger condition of the instruction submission event; the data packet includes the number of execution instructions of the design to be tested; The driving unit is used to drive the reference model to execute the same number of instructions based on the number of execution instructions in the data packet.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the synchronization control method as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the synchronization control method as claimed in any one of claims 1 to 7.

Images