Chip layout grid fast subdivision method, device, equipment and medium

Abstract

The embodiments of the present application provide a method, device, equipment and medium for rapid grid segmentation of a chip layout, the method comprising: obtaining a chip layout to be segmented; parsing the chip layout, obtaining multiple layout elements to be segmented, and calculating the minimum feature tree corresponding to the layout elements; the layout elements at least include pads, vias, copper plating shapes and connections; sorting multiple layout elements in a preset order to generate a layout element queue; sequentially querying in the layout element queue whether each layout element corresponds to a feature tree, and if not, performing rapid node segmentation on the feature tree of each layout element according to the minimum feature tree to obtain a multi-branch tree data structure corresponding to the layout element; the rapid node segmentation includes any one of virtual rule node segmentation, high-precision rule node segmentation and AI rapid automatic segmentation; and completing rapid grid segmentation of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

Description

Technical Field

[0001] The present invention belongs to the technical field of finite element analysis, and in particular relates to a method, device, equipment and medium for fast meshing of a chip layout. Background Art

[0002] In the field of integrated circuit (IC) design and manufacturing, the design and analysis and verification of chip layout is a crucial link. With the increasing complexity of chip functions and the improvement of integration, it is particularly important to accurately simulate and emulate the physical fields inside the chip (such as temperature field, stress field, electromagnetic field, etc.) through finite element technology. These simulation processes are inseparable from high-quality mesh generation, which directly affects the accuracy and computational efficiency of the simulation results. Meshing technology, especially three-dimensional mesh generation, can more realistically reflect the complex structure inside the chip and improve the accuracy of the simulation.

[0003] In the existing finite element simulation technology, mesh generation methods are mainly divided into two categories: two-dimensional mesh generation and three-dimensional mesh generation. Although two-dimensional mesh generation has a fast calculation speed, its accuracy is limited and it is difficult to meet the needs of high-precision simulation. Three-dimensional mesh generation is divided into structured meshes and unstructured meshes. Structured meshes are more efficient when processing regular geometric shapes, but when facing objects with complex shapes, mesh construction is time-consuming and difficult to ensure accuracy. Unstructured meshes have stronger geometric adaptability and can easily perform local encryption and adaptive adjustment, but the calculation efficiency is relatively low and the calculation equations are complex.

[0004] At present, 3D mesh generation technology has been applied to chip layout design, but it generally faces the problem of balancing accuracy and efficiency. Structured mesh methods such as sweeping method and mapping method are efficient in processing simple geometric shapes, but difficult to process complex structures. Unstructured mesh methods such as Delaunay triangulation and frontier advancing method can better adapt to complex geometric shapes, but the computational cost is high and it is difficult to achieve efficient parallel processing. Summary of the invention

[0005] The present application provides a method, device, equipment and medium for rapid grid division of chip layout, aiming to solve the problem that three-dimensional grid division technology has been applied to chip layout design to a certain extent, but generally faces the problem of balancing accuracy and efficiency. Structured grid methods such as sweeping method and mapping method are more efficient when processing simple geometric shapes, but have difficulty in processing complex structures. Unstructured grid methods such as Delaunay triangulation and frontier advancement method, although they can better adapt to complex geometric shapes, have high computational costs and are difficult to achieve efficient parallel processing.

[0006] In a first aspect, an embodiment of the present application provides a method for fast gridding of a chip layout, comprising:

[0007] Obtaining the chip layout to be segmented;

[0008] Analyze the chip layout, obtain multiple layout elements to be segmented, and calculate the minimum feature tree corresponding to the layout elements; the layout elements at least include pads, vias, copper shapes and connections;

[0009] Sorting multiple layout elements according to a preset order to generate a layout element queue; the preset order includes any one of a heat conduction direction, a current direction, a stress direction and a layout direction;

[0010] In the layout element queue, query in sequence whether each layout element corresponds to a feature tree; if not, perform fast node partitioning on the feature tree of each layout element according to the minimum feature tree to obtain a multi-branch tree data structure corresponding to the layout element; the multi-branch tree data structure includes a root node corresponding to each of the layout elements; fast node partitioning includes any one of virtual rule node partitioning, high-precision rule node partitioning and AI fast automatic partitioning;

[0011] The chip layout is quickly meshed according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

[0012] In some embodiments, before sorting multiple layout elements in a preset order to generate a layout element queue, it also includes: establishing a parallel processing queue, the parallel processing queue includes a stack element queue and a layout element queue; and running the stack element queue and the layout element queue at the same time to complete the rapid grid division of the chip layout.

[0013] In some embodiments, if the fast node decomposition is virtual regular node decomposition, the feature tree of each layout element is fast node decomposition according to the minimum feature tree, including: establishing an element multi-branch tree corresponding to the layout element; the element multi-branch tree includes at least any one of an element octree and an element quadtree; judging whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element; if not, recursively performing the element multi-branch tree to obtain the unit node that satisfies the minimum feature tree corresponding to the layout element and the unit node that triggers the recursive partial threshold; determining the unit node that triggers the recursive partial threshold as a virtual unit node; decomposing the unit node that satisfies the minimum feature tree; forming a multi-branch tree data structure according to the unit center coordinates of the unit nodes completed by each layout element decomposition, the unit nodes that satisfy the minimum feature tree, and the virtual unit nodes; the multi-branch tree data structure includes at least any one of the quadtree data structure and the octree data structure.

[0014] Exemplarily, before determining whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element, it also includes: determining whether the element multi-branch tree needs to be simplified; if the element multi-branch tree needs to be simplified, polygonally simplifying the element multi-branch tree.

[0015] Exemplarily, before completing the rapid grid partitioning of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element, it also includes: obtaining element feature information of each layout element; determining similar element groups among multiple layout elements according to the element feature information, each similar element group includes multiple layout elements; and storing the partitioning results corresponding to each layout element in the similar element group into the feature tree data area.

[0016] In some embodiments, if the fast node partitioning is AI fast automatic partitioning, the feature tree of each layout element is quickly node partitioned according to the minimum feature tree, including: extracting features from multiple layout elements to be partitioned, and obtaining feature information corresponding to each layout element; the feature information at least includes vertex coordinates and materials; forming a hash value based on the feature information and synchronously querying the feature tree data area; synchronously querying the feature tree data area and each layout element according to the hash value to complete the generation of the automatic partitioning model to be trained; completing the grid pre-partitioning of multiple layout elements through the automatic partitioning model to be optimized, and outputting the pre-partitioned grid; scoring the pre-partitioned grid, and completing the training of the automatic partitioning model according to the scoring results corresponding to the scoring, which is used to quickly node partition the feature tree of each layout element; wherein the scoring results include at least one or more of the regular node number score, the grid density adaptability score, the node number score in the area where the physical phenomenon changes drastically, and the grid generation efficiency score.

[0017] In some embodiments, after completing the rapid grid division of the chip layout according to the subtree information corresponding to the multi-tree data structure, it also includes: generating a calculation expression for each node corresponding to the multi-tree data structure; calculating the parameter value of the corresponding node according to the calculation expression; the parameter value includes at least one or more of resistance, stress, thermal resistance and impedance.

[0018] In a second aspect, an embodiment of the present application provides a device for fast grid subdivision of a chip layout, comprising:

[0019] A layout acquisition unit, which acquires the chip layout to be segmented;

[0020] An element acquisition unit, used to parse the chip layout, acquire multiple layout elements to be segmented, and calculate the minimum feature tree corresponding to the layout elements; the layout elements at least include pads, vias, copper shapes and connections;

[0021] An element sorting unit, used to sort a plurality of layout elements in a preset order to generate a layout element queue; the preset order includes any one of a heat conduction direction, a current direction, a stress direction and a layout direction;

[0022] A fast partitioning unit is used to sequentially query whether each layout element in the layout element queue corresponds to a feature tree, and if not, to perform fast node partitioning on the feature tree of each layout element according to the minimum feature tree to obtain a multi-branch tree data structure corresponding to the layout element; the multi-branch tree data structure includes a root node corresponding to each layout element; the fast node partitioning includes any one of virtual rule node partitioning, high-precision rule node partitioning and AI fast automatic partitioning;

[0023] The subdivision completion unit is used to complete the rapid grid subdivision of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

[0024] In a third aspect, the present application further provides a computer device, including:

[0025] Memory and processor;

[0026] The memory is used to store computer programs;

[0027] The processor is used to execute the computer program and implement the steps of the chip layout grid fast subdivision method as described in the first aspect above when executing the computer program.

[0028] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the steps of the chip layout grid rapid segmentation method as described in the first aspect above.

[0029] The present application discloses a method, device, computer equipment and storage medium for fast meshing of chip layout. Obtain a chip layout file that needs to be meshed from a design library or design tool. Parse the chip layout and identify some key layout elements. These elements include pads, vias, copper shapes and connections. Calculate the minimum spanning tree (MST) of each layout element for efficient subsequent meshing. Sort multiple layout elements in a preset order. The sorting can be based on any one of the heat conduction direction, current direction, stress direction and layout direction. Generate a sorted layout element queue for subsequent meshing. In the sorted layout element queue, query each layout element in turn whether it already has a feature tree. If so, perform fast node meshing on the feature tree of each layout element according to the minimum feature tree. Multiple methods are provided for fast node meshing, virtual rule node meshing: fast but low-precision meshing using predefined rules. High-precision rule node meshing: high-precision node meshing in combination with actual design requirements. AI fast automatic segmentation: Use artificial intelligence algorithms to automatically segment according to historical design data and current design requirements. After each segmentation is completed, a multi-tree data structure containing subtree information is generated. According to the subtree information in the multi-tree data structure, the grid of the chip layout is quickly segmented. The provided method not only finds a balance between efficiency and accuracy, but also adapts to complex chip layout design requirements, improving parallel processing capabilities and design automation levels.

[0030] The proposed method can efficiently complete meshing in complex geometric shapes through pre-sorting and fast feature tree segmentation methods. A variety of segmentation strategies are used to balance different requirements while retaining accuracy. Whether it is simple or complex layout elements, different segmentation methods are used to adapt to various geometric shapes and improve applicability. The introduction of sorting and multi-branch tree data structures provides a better foundation for parallel processing. Distributed processing can be performed while ensuring the consistency of segmentation results.

[0031] At the same time, the provided method also has the following beneficial effects:

[0032] 1. Use the octree data structure: The octree data structure and construction method can achieve efficient subdivision of the chip layout. The octree structure can naturally reflect the hierarchy and directionality of the three-dimensional space, making it easier to judge the logical relationship of the chip layout. In the same layout, it is easier to achieve structured grids than traditional triangulation, which not only achieves higher accuracy for numerical calculations, but also avoids large-scale matrix operations.

[0033] 2. Introducing virtual nodes and feature nodes: By introducing virtual regular nodes, also called structured unit nodes and feature nodes, the problem of computational conversion between unstructured grids and structured grids is solved, the complexity of subdivision is simplified, and the computational efficiency is improved. Compared with traditional simplified vertex subdivision, it has higher parallel computing capabilities and higher accuracy.

[0034] 3. By using user feature tree extraction and permanently retaining the feature tree mode, the AI ​​automatic segmentation mode maintains a higher level of advancement and expansion innovation. The segmentation speed and memory have unparalleled advantages in the feature tree mode.

[0035] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 This is a schematic flow chart of the steps of a method for rapid grid partitioning of a chip layout provided by an embodiment of the present application;

[0038] Figure 2 This is a schematic flow chart of the subtree division structure provided by an embodiment of the present application;

[0039] Figure 3 is a top view of a topological structure of a chip provided in one embodiment of the present application;

[0040] Figure 4 It is a top view of a single pad element and a routing element of a topological structure of a chip provided by an embodiment of the present application;

[0041] Figure 5 It is a single pad element division topology structure provided by an embodiment of the present application;

[0042] Figure 6 It is a single routing element division topology structure provided by an embodiment of the present application;

[0043] Figure 7 It is a structural schematic diagram of a chip layout grid fast subdivision device provided in an embodiment of the present application;

[0044] Figure 8 It is a schematic block diagram of the structure of a computer device provided in one embodiment of the present application.

[0045] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0048] It should be understood that, in order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art can understand that the words "first", "second", etc. do not limit the quantity and execution order, and the words "first", "second", etc. do not necessarily limit the difference.

[0049] It should be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0050] It should also be understood that the term “and / or” used in the specification and appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0051] To facilitate understanding of the content of this application, some of the specific terms that appear in the embodiments of this application are explained:

[0052] 1. Octree partitioning, such as Figure 2 As shown, by dividing an area into 8 cells, that is, eight tree nodes, the area that does not meet the conditions can be recursively divided until it meets the conditions.

[0053] 2. Feature tree: a regular node tree, such as vias. Although vias of the same radius and material may exist in different places on different layers, the path from a node to the via is the same. For example, routing may have the same width, thickness, angle, length, shape, and material, but the starting point and end point are different.

[0054] 3. General feature tree: The structure of the feature tree that can be obtained by angle and offset coordinates after merging multiple feature trees.

[0055] 4. Elements of chip layout: including Pad, Wirebond, Via, Lead, Shap (including conductive polygons, quadrilaterals, circles, ellipses and other graphics, including hollowed-out polygons).

[0056] 5. Index storage: Linear indexing maps the nodes of the octree to a one-dimensional array. The position of each node in the array is determined by the position of its parent node and the order of the node in its parent node's child nodes. This indexing method usually requires a clear rule to calculate the corresponding index value from the three-dimensional coordinates, or to infer the three-dimensional coordinates from the index value. Since each layer is stacked evenly (except for via elements), the bottom node units of the octree of other elements can be calculated based on the upper node units. The actual design of index compression only has quadtrees. Figure 2 As shown, the octree nodes are stored in the storage space in the order of normal vectors: 0 upper left corner, 1 upper right corner, 2 lower left corner, 3 lower right corner, 4 bottom upper left corner, 5 bottom upper right corner, 6 bottom lower left corner, 7 bottom lower right corner, as shown in Figure 2 First, perform octree decomposition on the blue part (0-7 can represent the direction and can also be used as a serial number as above, then perform octree decomposition on the blue 3, and the 0-7 after decomposition can still represent the direction and serial number, and the same is true for the yellow part).

[0057] 6. Virtual regular nodes: Irregular units will be generated when processing complex graphic units. The octree virtual regular nodes composed of regular units and function pointer mapping can be used to quickly calculate the actual resistance value, impedance value, unit thermal stress, thermal resistance value according to the pointer expression during calculation. It can also quickly merge nodes and retrieve the actual irregular unit information of nodes according to the expression.

[0058] 7. AI fast and automatic segmentation is based on machine learning space, which is mounted on external memory for permanent storage. The data comes from feature tree storage for each chip layout, and each element can quickly find the feature tree based on the layout element features (vertices, radius, length, width, material, etc.). Since the probability of identical unit elements is greatly increased, the feature tree extraction of the learning library is of great significance. It can solve the segmentation problems of large-scale identical elements and the merging of tree nodes, and can optimize the feature tree according to the segmentation scoring system at each segmentation to improve the accuracy of element segmentation or element set segmentation.

[0059] 8. Minimum partition equal unit: From the perspective of matrix, it is the partition threshold. This threshold is related to the length, width and height of the layout element. According to the relevant description of the octree, it is also called the minimum feature tree.

[0060] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0061] The reason for meshing chips is mainly related to numerical calculations such as finite element analysis (FEM), and its application in chip design, simulation and optimization. Currently, meshing has the following disadvantages:

[0062] 2D meshing:

[0063] a. The accuracy is not enough, and the errors in heat conduction, thermal stress, electromagnetic, and electrothermal coupling calculations are large, but the structure is simple and the calculation speed is fast.

[0064] 3D meshing:

[0065] b. Structured grid, used to process objects with complex shapes. The grid construction is time-consuming, but for numerical calculations, the calculation is simple and the speed is fast.

[0066] c. Unstructured grid: Unstructured grid has strong adaptability to complex geometric models and can be easily adaptively adjusted and locally encrypted. However, it may be less efficient for numerical calculations and the calculation equations are more complicated.

[0067] This application adopts three-dimensional mesh partitioning technology and utilizes the data structure and construction method of multi-branch trees (such as octrees) to improve the accuracy and flexibility of chip layout partitioning, and is more applicable to high-precision simulation verification of multiple physical fields. At the same time, the introduction of virtual regular nodes (unstructured) and feature nodes solves the calculation conversion of unstructured grids and structured grids, and simplifies the complexity of partitioning. Since the partitioning is to reconstruct the feature tree after unitization, it is merged into the octree root node. The method provided by this application not only processes units of different chip layouts in parallel, but also translates and calculates the feature tree of the unit, which improves the speed and saves partitioning resources.

[0068] To solve the above problems, please refer to Figure 1 , Figure 1 The schematic flow chart of the chip layout grid fast segmentation method provided by an embodiment of the present application is as follows. The chip layout grid fast segmentation method can be implemented by a computer device, and the computer device can be deployed on a single server or a server cluster. It can also be deployed on a handheld terminal, a laptop computer, a wearable device or a robot, etc.

[0069] To solve the above problems, please refer to Figure 1 Specifically, Figure 1 As shown, the provided chip layout grid fast subdivision method includes steps S101 to S105. The details are as follows:

[0070] Step S101. Obtain the chip layout to be segmented.

[0071] Specifically, this step is mainly an input stage, which requires obtaining the chip layout data to be segmented from a design warehouse or design tool. These data usually include the chip's geometry, material information, and manufacturing constraints. This provides basic data for subsequent segmentation steps, ensuring that all operations in the segmentation process are based on the actual chip design layout data, ensuring the accuracy and effectiveness of subsequent processing.

[0072] Step S102: Analyze the chip layout, obtain multiple layout elements to be segmented, and calculate the minimum feature tree corresponding to the layout elements; the layout elements at least include pads, vias, copper shapes and connections.

[0073] Specifically, in this step, the obtained chip layout is parsed to extract the layout elements to be segmented (such as pads, vias, copper shapes and connections). Next, the minimum feature tree of each layout element is calculated to describe the geometric characteristics and relationships of the elements. This decomposes the complex layout into smaller, processable units to facilitate subsequent sorting and segmentation operations. By constructing a minimum feature tree, the geometric and topological features of the layout elements can be effectively captured, providing an accurate basis for subsequent segmentation.

[0074] Step S103. Sort multiple layout elements according to a preset order to generate a layout element queue; the preset order includes any one of heat conduction direction, current direction, stress direction and layout direction.

[0075] Specifically, by sorting the extracted layout elements according to preset rules (such as heat conduction direction, current direction, stress direction, and layout direction, etc.), a sequential layout element queue is formed. Sorting helps to optimize the order of segmentation, making the segmentation process more coherent and improving the overall processing efficiency. Different sorting rules can be optimized for different design requirements (for example, improving heat conduction efficiency or reducing the risk of stress concentration).

[0076] Step S104. Query in sequence in the layout element queue whether each layout element has a corresponding feature tree. If not, perform fast node partitioning on the feature tree of each layout element according to the minimum feature tree to obtain the multi-branch tree data structure corresponding to the layout element; the multi-branch tree data structure includes the root node corresponding to each layout element; fast node partitioning includes any one of virtual rule node partitioning, high-precision rule node partitioning and AI fast automatic partitioning.

[0077] Specifically, by querying the feature tree of each layout element, if the feature tree exists, directly extract the feature tree and enter step S105. If the feature tree does not exist, fast node segmentation is performed according to the minimum feature tree to form a multi-branch tree data structure. The specific method can be virtual rule node segmentation, high-precision rule node segmentation, or AI fast automatic segmentation. Fast node segmentation can significantly reduce the amount of calculation and improve segmentation efficiency. The use of a multi-branch tree data structure can effectively organize and manage the segmented data, thereby improving the efficiency and accuracy of data processing. Different segmentation methods can be selected according to specific needs to further optimize performance.

[0078] Step S105: Complete the rapid grid division of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

[0079] Specifically, by utilizing the multi-tree data structure of each layout element, the entire chip layout is meshed according to its subtree information. The use of multi-tree structures (such as octrees) can better handle complex geometric shapes, improve the precision and accuracy of meshing, and maintain efficient computing performance. The final result is efficient and accurate meshing, which provides a reliable foundation for subsequent simulation, manufacturing, and optimization.

[0080] In summary, the provided method solves the problem of low efficiency and insufficient accuracy of traditional meshing when dealing with complex geometric shapes through the use of parsing, sorting, fast node partitioning and multi-branch tree structure. It can significantly improve the partitioning efficiency while maintaining high accuracy.

[0081] In some embodiments, before sorting multiple layout elements in a preset order to generate a layout element queue, it also includes: establishing a parallel processing queue, the parallel processing queue includes a stack element queue and a layout element queue; and running the stack element queue and the layout element queue at the same time to complete the rapid grid division of the chip layout.

[0082] Before sorting multiple layout elements in a preset order and generating a layout element queue, a parallel processing queue is also established. The parallel processing queue includes a stacking element queue and a layout element queue; the stacking element queue and the layout element queue are run simultaneously to complete the rapid meshing of the chip layout. By introducing a parallel processing queue, multiple tasks can be processed simultaneously, thereby improving the overall efficiency of meshing. This method is particularly suitable for large-scale chip design, and uses parallel computing resources to significantly shorten processing time.

[0083] In some embodiments, if the fast node decomposition is virtual regular node decomposition, the feature tree of each layout element is fast node decomposition according to the minimum feature tree, including: establishing an element multi-branch tree corresponding to the layout element; the element multi-branch tree includes at least any one of an element octree and an element quadtree; judging whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element; if not, recursively performing the element multi-branch tree to obtain the unit node that satisfies the minimum feature tree corresponding to the layout element and the unit node that triggers the recursive partial threshold; determining the unit node that triggers the recursive partial threshold as a virtual unit node; decomposing the unit node that satisfies the minimum feature tree; forming a multi-branch tree data structure according to the unit center coordinates of the unit nodes completed by each layout element decomposition, the unit nodes that satisfy the minimum feature tree, and the virtual unit nodes; the multi-branch tree data structure includes at least any one of the quadtree data structure and the octree data structure.

[0084] If the fast node decomposition is virtual regular node decomposition, the feature tree of each layout element is fast node decomposition according to the minimum feature tree, and the provided embodiment includes the following steps: establish an element multi-branch tree corresponding to the layout element; the element multi-branch tree includes at least one of the element octree and the element quadtree. Determine whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element; if not, recursively operate to obtain the unit node that satisfies the minimum feature tree and the virtual unit node that triggers the recursive part threshold. The unit node that satisfies the minimum feature tree is decomposed. According to the decomposition result, a multi-branch tree data structure is formed; the multi-branch tree data structure includes at least one of the quadtree data structure and the octree data structure. By introducing virtual regular node decomposition and multi-branch tree structure, the decomposition process is made more efficient and accurate. It can effectively handle complex geometric shapes and improve the accuracy and consistency of decomposition.

[0085] Exemplarily, before determining whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element, it also includes: determining whether the element multi-branch tree needs to be simplified; if the element multi-branch tree needs to be simplified, polygonally simplifying the element multi-branch tree.

[0086] The provided method further includes determining whether the element multitree needs to be simplified before determining whether the unit node corresponding to the element multitree satisfies the minimum feature tree corresponding to the layout element; if necessary, polygon simplification is performed on the element multitree. Polygon simplification can reduce the amount of calculation, improve the processing speed, and maintain the geometric accuracy after segmentation. The balance between segmentation efficiency and accuracy is ensured before simplification, which is an effective means to improve overall efficiency.

[0087] Exemplarily, before completing the rapid grid partitioning of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element, it also includes: obtaining element feature information of each layout element; determining similar element groups among multiple layout elements according to the element feature information, each similar element group includes multiple layout elements; and storing the partitioning results corresponding to each layout element in the similar element group into the feature tree data area.

[0088] The provided method further includes obtaining element feature information of each layout element before completing the fast grid segmentation of the chip layout according to the subtree information corresponding to the multi-branch tree data structure. Based on the feature information, similar element groups are determined in multiple layout elements, each of which includes multiple layout elements; and the segmentation results corresponding to each layout element in the similar element group are stored in the feature tree data area. By analyzing and utilizing the commonalities between similar elements, repeated calculations are reduced and the segmentation efficiency is further improved. This method is particularly suitable for situations where there are a large number of similar structures in the layout.

[0089] In some embodiments, if the fast node partitioning is AI fast automatic partitioning, the feature tree of each layout element is quickly node partitioned according to the minimum feature tree, including: extracting features from multiple layout elements to be partitioned, and obtaining feature information corresponding to each layout element; the feature information at least includes vertex coordinates and materials; forming a hash value based on the feature information and synchronously querying the feature tree data area; synchronously querying the feature tree data area and each layout element according to the hash value to complete the generation of the automatic partitioning model to be trained; completing the grid pre-partitioning of multiple layout elements through the automatic partitioning model to be optimized, and outputting the pre-partitioned grid; scoring the pre-partitioned grid, and completing the training of the automatic partitioning model according to the scoring results corresponding to the scoring, which is used to quickly node partition the feature tree of each layout element; wherein the scoring results include at least one or more of the regular node number score, the grid density adaptability score, the node number score in the area where the physical phenomenon changes drastically, and the grid generation efficiency score.

[0090] If the fast node partitioning method provided is AI fast automatic partitioning, it includes the following steps: extract features from multiple layout elements to be partitioned, and obtain feature information (such as vertex coordinates and materials) of each element. A hash value is formed based on the feature information, which is used to synchronously query the feature tree data area. An automatic partitioning model to be trained is generated based on the query results and the element feature information. The model is used to pre-mesh the elements and output the pre-meshed mesh. The pre-meshed mesh is scored, and the automatic partitioning model is trained according to the scoring results to improve the partitioning effect. The scoring indicators include the number of regular nodes, the adaptability of the mesh density, the number of nodes in the area where the physical phenomenon changes dramatically, and the mesh generation efficiency. By using AI technology for automatic partitioning, the partitioning speed and quality are improved. At the same time, by continuously training the model, the partitioning results are gradually optimized to adapt to different design requirements.

[0091] In some embodiments, after completing the rapid grid division of the chip layout according to the subtree information corresponding to the multi-tree data structure, it also includes: generating a calculation expression for each node corresponding to the multi-tree data structure; calculating the parameter value of the corresponding node according to the calculation expression; the parameter value includes at least one or more of resistance, stress, thermal resistance and impedance.

[0092] After completing the fast meshing of the chip layout according to the subtree information corresponding to the multi-tree data structure, it also includes generating a calculation expression for each node; calculating the parameter value of the corresponding node according to the calculation expression, and these parameter values ​​include at least one or more of resistance, stress, thermal resistance and impedance. Furthermore, by providing the physical parameter calculation function required for actual engineering applications, the meshing results can not only meet the geometric requirements, but also be used for further engineering simulation and optimization, providing strong support for engineering design.

[0093] In order to reflect the specific application scenarios of the embodiments of the present application, the provided method is now described through a complete embodiment:

[0094] Step 0: Read the chip layout file.

[0095] Step 1: Select the layout elements to be split and classify the elements, including various types of layout elements such as pads, vias, copper shapes, routing, etc.

[0096] Step 2: Calculate the minimum feature tree of the layout elements to be segmented. The following is the method for calculating the minimum feature tree:

[0097] The minimum value of the width W, height H, and length L of each element.

[0098] Wmin=MIN(number1width, [number2]width, ...);

[0099] Hmin=MIN(number1height, [number2]height, ...);

[0100] Lmin=MIN(number1 length, [number2] length, ...);

[0101] Matrix_Min_i unit = Wmin > Lmin? H / 2*L / 2*L / 2 hexahedron: H / 2*W / 2*W / 2 hexahedron (the above expression means that if Wmin > Lmin holds, then Matrix_Min_i unit = H / 2*L / 2*L / 2 hexahedron; otherwise, if not, then Matrix_Min_i unit = H / 2*W / 2*W / 2 hexahedron).

[0102] Often, each stacked structure of the chip has a uniform height, that is, H is uniform. The Matrix_Min_i unit can be enlarged or reduced in width and length by integer multiples according to the computing resources. The so-called integer multiples are related to the regular structure unit in the following step 6. For example, a cylinder with a layer height of 1 nanometer is directly obtained, and the Matrix_Min_i unit hexahedron (W=0.5, L=0.5, H=0.25) is obtained. The so-called integer multiple refinement of the unit hexahedron is equivalent to dividing all parameters by integer multiples n, and the height direction remains unchanged. For example, the 2-fold refined unit hexahedron (W=0.25, L=0.25, H=0.25) is essential for the extraction of the Matrix_Min_i unit, because granularity control is crucial to the feasibility and optimization of the subsequent power network octree partitioning. The threshold of uniform partitioning is a prerequisite. Because the extraction of Matrix_Min_i is similar to setting the resolution reasonably during 3D modeling, the depth of the octree is reduced according to this threshold, and the complex graphics of the chip layout are reasonably divided, such as the narrow edges brought by circles, nano-sized wires, etc. Complex polygons can be simplified to obtain equally divided L hexahedrons. No detailed description is given here. The provided method preferentially selects the so-called virtual regular nodes.

[0103] Step 3: Establish a parallel processing queue. The parallel queue includes two methods: parallel processing by stacked elements or by layout elements. Since parallel processing depends on CPU computing resources, it is scheduled here according to the actual application scenario (parallel technology generally refers to multi-threading and multi-process. Data synchronization and mutual exclusion use the multi-process and multi-thread communication technology commonly used in computers. Since the technology is relatively mature, it will not be described in detail here). The traditional method of segmentation is to perform Boolean operations on the large layout and then perform segmentation by layer or after the overall Boolean operation. However, if the computing resources allow, the method provided preferably directly segments by layer according to the layout element type, that is, first segment, and then perform Boolean operations when merging octree nodes. The advantage of this method is that it can maximize the use of computing units according to different layout unit types and perform flexible parallel segmentation, and more efficiently extract feature trees and merge octree nodes. Utilizing this advantage can reduce the number of segmentations and the amount of merge calculations after segmentation, and at the same time can extract better feature trees to match, solve, optimize, surface segmentation and other complex layout units.

[0104] Step 4: Sort the layout elements to be segmented into a segmentation queue in a fixed direction (the direction can be the heat conduction direction, current direction, stress direction, or the top, bottom, left, or right of the layout).

[0105] Step 5: Query the feature tree for the selected layout element (due to parallelism, the query requires task synchronization, which is often called computer lock. It is actually a mutual exclusion mechanism and will not be explained in detail). If the feature tree exists, directly extract the feature tree and proceed to step 6. If the feature tree does not exist, proceed to the next step.

[0106] Step 6: Perform octree partitioning. There are three partitioning methods, namely virtual rule node partitioning, high-precision rule node partitioning, and AI fast automatic partitioning. The specific applications of the three partitioning methods are now explained.

[0107] 1. The steps for high-precision regular node segmentation are as follows:

[0108] a. Create an element octree with the root node being the element name + id.

[0109] b. Start octree partitioning, and recursively check whether the layout elements and unit nodes meet the minimum feature tree. If so, stop partitioning the element and go to step c; if not, perform recursive octree partitioning and execute step b again; if the number of recursions is less than a certain set partitioning threshold, the minimum feature tree is reduced by a multiple; similarly, if the number of recursions is greater than a certain set partitioning threshold, the minimum feature tree is enlarged by a multiple.

[0110] c. The final result of each element decomposition object is the grid unit formed by the decomposition. The center coordinates of the unit after decomposition in each direction are stored in sequence, and are stored in the octree nodes in sequence according to a certain direction to form an octree of the unit decomposition.

[0111] d. Since each element often has similar features, such as the same via radius, the same material, but different names and coordinates, this type of element can be marked as a feature tree after the first segmentation. Store it in the feature tree data area (where there is a computer resource mutex parallel scheduling).

[0112] e. Octree decomposes the calculation elements and generates calculation expressions and values ​​for each node, such as resistance, stress, thermal resistance, impedance, etc.

[0113] f. Set the root node to the element name + id, and finally map it to the child node of the N-ary tree. The split result is permanently stored in the external memory, and is provided for parallel threads or processes to perform secondary splitting (there is computer resource mutex parallel scheduling).

[0114] g. Use the optimal octree depth search depth and recursive steps as well as manual result calibration to calibrate the level of the element's segmentation results. At the same time, the core algorithm measurement indicators include structured grids, the number of segmentation times and the number of grids, and update the feature tree data area (where there is a computer resource mutex parallel scheduling).

[0115] 2. The steps of virtual rule node segmentation are as follows:

[0116] a. Establish an element octree, with the root node being the element name + id + V, and determine whether simplification is required. If simplification is required, perform polygon simplification and then enter the next link b, otherwise directly enter the next link b. Graphical simplification, here it is preferred to generate fitting regular nodes after simplification. This method is based on the minimum regular feature tree calculated by the minimum feature tree when identifying complex graphics. It can flexibly increase the accuracy by multiples to process and identify complex graphics. If the subdivision cannot converge to the minimum regular feature tree and reaches the number of subdivision recursions, the provided method will simplify identification and processing. This method can be identified based on the subdivision results, or it can be judged and processed by vertex intersection and connection relationship before subdivision. This simplification method is different from traditional simplification. The traditional simplified graphics are judged by the vertex coordinates of the graphics and the vertices are simplified and modified and a simplified new vertex set is generated. The difference is that the same octree regular nodes are constructed, which is conducive to linear calculations to minimize the error during simulation. The real vertices of this simplification method are not simplified, and the information of the original vertices can be obtained through the pointer formula.

[0117] b. Start octree partitioning to see if the partitioned unit node satisfies the minimum feature tree. If so, stop partitioning the unit node, mark the node name as the regular node id, and go to step c. If not, perform recursive octree partitioning and execute step b again. If the number of recursions is less than a certain threshold of partition times, the minimum feature tree is reduced by a multiple. If the recursive partitioning threshold is triggered, mark the unit node as a virtual unit node, stop partitioning the unit node, and go to step c.

[0118] c. The final result of each element decomposition object is the grid unit formed by the decomposition. The center coordinates of the unit after decomposition in each direction are stored in sequence, and are stored in the octree nodes in sequence according to a certain direction to form an octree of unit decomposition containing virtual regular nodes.

[0119] d. Since each element often has similar features, such as the same via radius, the same material, but different names and coordinates, this type of element can be marked as a feature tree after the first segmentation. Store it in the feature tree data area (where there is a computer resource mutex parallel scheduling).

[0120] e. Since the octree is divided into calculation elements, calculation expressions and values ​​are generated for each node, such as resistance, stress, thermal resistance, impedance, etc.

[0121] f. The root node is the element name + id + V, and is finally mapped to the child node of the N-ary tree. The split result is permanently stored in the external memory, and parallel threads or processes are provided for secondary splitting (there is a computer resource mutex parallel scheduling).

[0122] g. Use the optimal octree depth search depth and recursive steps as well as manual result calibration to calibrate the level of the element's segmentation results. At the same time, the core algorithm measurement indicators include structured grids, the number of segmentation times and the number of grids, and update the feature tree data area (where there is a computer resource mutex parallel scheduling).

[0123] 3. AI quick automatic segmentation steps are as follows:

[0124] a. Extract features of the entire element to be segmented (including the general feature tree formed by the combination of elements in the direction). The so-called feature refers to the vertex coordinates, material, etc. of the element to be segmented. The feature information is used to form a hash value key to synchronously query the feature tree data area.

[0125] b. If all the elements to be segmented match the feature tree (where there is a computer resource mutex parallel scheduling), directly extract the feature tree and update it to the child node of the N-ary tree, otherwise enter the above two segmentation processes or enter step c.

[0126] c. Entering feature library training, data-driven finite element analysis has become a new trend. The essence of AI fast and automatic segmentation is to rely on more feature trees to directly extract the segmentation model. Feature library training not only extracts feature libraries in unit segmentation, but also extracts features from the root nodes of the n-ary tree. Since AI fast and automatic segmentation relies on one-to-one feature tree extraction, how to enrich the feature library here relies on machine learning to automatically model and input various common design elements of different layouts. It is also part of this method of AI fast and automatic segmentation. Use machine learning to automatically build models, and use high-precision rule node segmentation methods to supplement feature libraries. Unlike traditional methods, the feature library provided by the method is based on unit element segmentation, so the extraction of feature trees to feature libraries has relatively simpler processing steps and is more efficient in solving complex layout model problems. Figure 2 The dissection steps are specifically reflected.

[0127] d. The feature library trains each feature tree and starts the grid partitioning scoring system. The scoring system is automatically calibrated based on the uniformity of the grid size, that is, the number of regular nodes of the octree nodes as the main dimension. It also includes the adaptability of the grid density, that is, the number of nodes in the octree, the number of nodes in the area where a physical phenomenon changes dramatically, and the grid generation efficiency, that is, the time and performance consumption from octree training to generation.

[0128] e. Query the feature tree record for the element and update the optimal feature tree for the segmentation unit based on the score.

[0129] Step 7: Store the subtree information of the octree data structure in the segmentation result into external memory, obtain the latest N-ary tree, and enter the multi-physics field calculation engine call or three-dimensional rendering call.

[0130] Figure 3 This is the topology of the BGA layer of a chip layout. The red area represents the power network and the green area represents the ground network. Figures 4 to 6 The figure shows an octree decomposition method for the device layer power network, where the device layer thickness is uniformly H.

[0131] 0. Query the feature tree to see whether the element to be segmented has a feature tree.

[0132] S1. By dividing a pad element into an octree as follows Figure 5 , forming a subtree labeled Tree1. Figure 5 a, b, c, d, a', b', c' and d' correspond to the child nodes of Tree1 respectively).

[0133] S2. By dividing a routing element into an octree as follows Figure 6 , forming a subtree labeled Tree2. Figure 6where e, f, g, h, i, j, k, l, e', f', g', h', i', j', k', and l' correspond to the child nodes of Tree2 respectively).

[0134] S3. Merge Tree1 and Tree2 into Tree3. Merging here means using the boundary method to determine whether the two feature tree bounding boxes (Axis-Aligned Bounding Box, AABB) intersect, and then merge the overlapping nodes to form a new tree Tree3. Figure 4 The octree structure is formed ( Figure 4 a, b, c, d, e, f, g, h, i, j, k, and l are the child nodes of the formed Tree3 respectively).

[0135] S4. Extract feature trees into sets, Tree1, Tree2, Tree3, store them in a low-speed storage area (not limited to json tree files, xml tree files, ini tree files in the disk, for indexed storage), and keep the root node in the N-ary tree.

[0136] Special note: Tree1, Tree2, and Tree3 may have multiple locations in the layout. Some feature trees only intersect in different directions. The intersecting tree nodes can be determined by offset direction and offset, saving the time of merging Tree1 and Tree2 again and judging nodes. Therefore, as long as two feature tree IDs and a merge function pointer information are stored in the subtree root node of Tree3, a pan-feature tree with direction is finally formed. Function pointer information (including search, thermal resistance, resistance, stress, coordinates, impedance, direction and other linear equations or values).

[0137] S5. Check whether the elements of the power network of this layer have been segmented. If not, return to step 0. If the segmentation is completed, stop segmenting this layer and proceed to the next layer segmentation. Here, the information of the marked layer is mapped to the depth field of the root node information of the N-ary tree.

[0138] Then the above steps have the following technical improvements:

[0139] 1. Three ways to use octree recursive subdivision to divide the layout.

[0140] 2: By using the high-precision partitioning and restoration method of octree virtual regular nodes and nodes with equations, the accuracy problem and calculation responsibility problem caused by partitioning of discrete units can be solved.

[0141] 3: Through parallel processing of layout units, recursive decomposition of octree hexahedrons, and the method of merging octrees by octree node coordinate collision, a parallel method of forming an N-ary tree structured grid is proposed.

[0142] 4: A method of combining three types of subdivision to achieve high efficiency and avoid repeated subdivision.

[0143] The provided method has the following beneficial effects:

[0144] 1. Use the octree data structure: The octree data structure and construction method can achieve efficient subdivision of the chip layout. The octree structure can naturally reflect the hierarchy and directionality of the three-dimensional space, making it easier to judge the logical relationship of the chip layout. In the same layout, it is easier to achieve structured grids than traditional triangulation, which not only achieves higher accuracy for numerical calculations, but also avoids large-scale matrix operations.

[0145] 2. Introducing virtual nodes and feature nodes: By introducing virtual regular nodes, also called structured unit nodes and feature nodes, the problem of computational conversion between unstructured grids and structured grids is solved, the complexity of subdivision is simplified, and the computational efficiency is improved. Compared with traditional simplified vertex subdivision, it has higher parallel computing capabilities and higher accuracy.

[0146] 3. By using user feature tree extraction and permanently retaining the feature tree mode, the AI ​​automatic segmentation mode maintains a higher level of advancement and expansion innovation. The segmentation speed and memory have unparalleled advantages in the feature tree mode.

[0147] See also Figure 7 As shown, Figure 7 1 is a schematic diagram of the structure of the chip layout grid fast segmentation device 200 provided in an embodiment of the present application. The chip layout grid fast segmentation device 200 is used to execute the steps of the chip layout grid fast segmentation method shown in the above embodiments. The chip layout grid fast segmentation device 200 can be a single server or a server cluster, or the chip layout grid fast segmentation device 200 can be a terminal, which can be a handheld terminal, a laptop computer, a wearable device or a robot, etc.

[0148] like Figure 7 As shown, the chip layout grid fast subdivision device 200 includes:

[0149] A layout acquisition unit 201 acquires a chip layout to be segmented;

[0150] An element acquisition unit 202 is used to parse the chip layout, acquire multiple layout elements to be segmented, and calculate the minimum feature tree corresponding to the layout elements; the layout elements at least include pads, vias, copper shapes and connections;

[0151] An element sorting unit 203, used to sort multiple layout elements according to a preset order to generate a layout element queue; the preset order includes any one of a heat conduction direction, a current direction, a stress direction and a layout direction;

[0152] A fast partitioning unit 204 is used to sequentially query whether each layout element in the layout element queue corresponds to a feature tree. If not, the feature tree of each layout element is quickly partitioned according to the minimum feature tree to obtain a multi-branch tree data structure corresponding to the layout element; the multi-branch tree data structure includes a root node corresponding to each layout element; the fast node partitioning includes any one of virtual rule node partitioning, high-precision rule node partitioning and AI fast automatic partitioning;

[0153] The subdivision completing unit 205 is used to complete the fast grid subdivision of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

[0154] In some embodiments, a parallel establishment unit is used to establish a parallel processing queue, and the parallel processing queue includes a stack element queue and a layout element queue; the stack element queue and the layout element queue are run simultaneously to complete the rapid grid division of the chip layout.

[0155] In some embodiments, if the fast node decomposition is a virtual regular node decomposition, the fast decomposition unit 204 is also used to: establish an element multi-branch tree corresponding to the layout element; the element multi-branch tree includes at least any one of the element octree and the element quadtree; determine whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element; if not, recursively perform the element multi-branch tree to obtain the unit node that satisfies the minimum feature tree corresponding to the layout element and the unit node that triggers the recursive part threshold; determine the unit node that triggers the recursive part threshold as a virtual unit node; decompose the unit node that satisfies the minimum feature tree; form a multi-branch tree data structure according to the unit center coordinates of each unit node completed by the decomposition of the layout element, the unit node that satisfies the minimum feature tree, and the virtual unit node; the multi-branch tree data structure includes at least any one of the quadtree data structure and the octree data structure.

[0156] Exemplarily, before determining whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element, the fast segmentation unit 204 is also used to: determine whether the element multi-branch tree needs to be simplified; if the element multi-branch tree needs to be simplified, perform polygon simplification on the element multi-branch tree.

[0157] Exemplarily, before completing the rapid grid partitioning of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element, it also includes: an information acquisition unit, used to obtain element feature information of each layout element; determining similar element groups among multiple layout elements according to the element feature information, each similar element group includes multiple layout elements; and storing the partitioning results corresponding to each layout element in the similar element group into the feature tree data area.

[0158] In some embodiments, if the fast node partitioning is AI fast automatic partitioning, the fast partitioning unit 204 is also used to: perform feature extraction on multiple layout elements to be partitioned, and obtain feature information corresponding to each layout element; the feature information at least includes vertex coordinates and materials; form a hash value based on the feature information and synchronously query the feature tree data area; synchronously query the feature tree data area and each layout element based on the hash value to complete the generation of the automatic partitioning model to be trained; complete the grid pre-partitioning of multiple layout elements through the automatic partitioning model to be optimized, and output the pre-partitioned grid; score the pre-partitioned grid, and complete the training of the automatic partitioning model according to the scoring results corresponding to the scoring, which is used to perform fast node partitioning on the feature tree of each layout element; wherein the scoring results at least include one or more of the regular node number score, the grid density adaptability score, the node number score in the area where the physical phenomenon changes drastically, and the grid generation efficiency score.

[0159] In some embodiments, after completing the rapid grid division of the chip layout according to the subtree information corresponding to the multi-tree data structure, it also includes: an expression acquisition unit, used to generate a calculation expression for each node corresponding to the multi-tree data structure; calculate the parameter value of the corresponding node according to the calculation expression; the parameter value includes at least one or more of resistance, stress, thermal resistance and impedance.

[0160] It should be noted that technical personnel in the relevant field can clearly understand that, for the convenience and simplicity of description, the specific working processes of the chip layout grid rapid subdivision device and each module described above can refer to the corresponding processes in the chip layout grid rapid subdivision method embodiments described in the above embodiments, and will not be repeated here.

[0161] The above-mentioned chip layout grid fast subdivision method can be implemented in the form of a computer program. The computer program can be used in Figure 7 Run on the device shown.

[0162] See also Figure 8 , Figure 8 1 is a schematic block diagram of the structure of a computer device provided in an embodiment of the present application. The computer device includes a processor, a memory and a network interface connected via a device bus, wherein the memory may include a storage medium and an internal memory.

[0163] The storage medium can store an operating device and a computer program. The computer program includes program instructions, and when the program instructions are executed, the processor can execute any one of the chip layout grid fast subdivision methods.

[0164] The processor is used to provide computing and control capabilities and support the operation of the entire computer equipment.

[0165] The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium. When the computer program is executed by the processor, the processor can execute any chip layout grid fast subdivision method.

[0166] The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present application, and does not constitute a limitation on the terminal to which the scheme of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0167] It should be understood that the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0168] In one embodiment, the processor is used to run a computer program stored in the memory to implement the following steps:

[0169] Obtaining the chip layout to be segmented;

[0170] Analyze the chip layout, obtain multiple layout elements to be segmented, and calculate the minimum feature tree corresponding to the layout elements; the layout elements at least include pads, vias, copper shapes and connections;

[0171] Sorting multiple layout elements according to a preset order to generate a layout element queue; the preset order includes any one of a heat conduction direction, a current direction, a stress direction and a layout direction;

[0172] In the layout element queue, query in sequence whether each layout element has a corresponding feature tree. If not, perform fast node partitioning on the feature tree of each layout element according to the minimum feature tree to obtain a multi-branch tree data structure corresponding to the layout element; the multi-branch tree data structure includes a root node corresponding to each layout element; fast node partitioning includes any one of virtual rule node partitioning, high-precision rule node partitioning and AI fast automatic partitioning;

[0173] The chip layout is quickly meshed according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

[0174] In some embodiments, before sorting multiple layout elements in a preset order to generate a layout element queue, it also includes: establishing a parallel processing queue, the parallel processing queue includes a stack element queue and a layout element queue; and running the stack element queue and the layout element queue at the same time to complete the rapid grid division of the chip layout.

[0175] In some embodiments, if the fast node decomposition is virtual regular node decomposition, the feature tree of each layout element is fast node decomposition according to the minimum feature tree, including: establishing an element multi-branch tree corresponding to the layout element; the element multi-branch tree includes at least any one of an element octree and an element quadtree; judging whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element; if not, recursively performing the element multi-branch tree to obtain the unit node that satisfies the minimum feature tree corresponding to the layout element and the unit node that triggers the recursive partial threshold; determining the unit node that triggers the recursive partial threshold as a virtual unit node; decomposing the unit node that satisfies the minimum feature tree; forming a multi-branch tree data structure according to the unit center coordinates of the unit nodes completed by each layout element decomposition, the unit nodes that satisfy the minimum feature tree, and the virtual unit nodes; the multi-branch tree data structure includes at least any one of the quadtree data structure and the octree data structure.

[0176] Exemplarily, before determining whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element, it also includes: determining whether the element multi-branch tree needs to be simplified; if the element multi-branch tree needs to be simplified, polygonally simplifying the element multi-branch tree.

[0177] Exemplarily, before completing the rapid grid partitioning of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element, it also includes: obtaining element feature information of each layout element; determining similar element groups among multiple layout elements according to the element feature information, each similar element group includes multiple layout elements; and storing the partitioning results corresponding to each layout element in the similar element group into the feature tree data area.

[0178] In some embodiments, if the fast node partitioning is AI fast automatic partitioning, the feature tree of each layout element is quickly node partitioned according to the minimum feature tree, including: extracting features from multiple layout elements to be partitioned, and obtaining feature information corresponding to each layout element; the feature information at least includes vertex coordinates and materials; forming a hash value based on the feature information and synchronously querying the feature tree data area; synchronously querying the feature tree data area and each layout element according to the hash value to complete the generation of the automatic partitioning model to be trained; completing the grid pre-partitioning of multiple layout elements through the automatic partitioning model to be optimized, and outputting the pre-partitioned grid; scoring the pre-partitioned grid, and completing the training of the automatic partitioning model according to the scoring results corresponding to the scoring, which is used to quickly node partition the feature tree of each layout element; wherein the scoring results include at least one or more of the regular node number score, the grid density adaptability score, the node number score in the area where the physical phenomenon changes drastically, and the grid generation efficiency score.

[0179] In some embodiments, after completing the rapid grid division of the chip layout according to the subtree information corresponding to the multi-tree data structure, it also includes: generating a calculation expression for each node corresponding to the multi-tree data structure; calculating the parameter value of the corresponding node according to the calculation expression; the parameter value includes at least one or more of resistance, stress, thermal resistance and impedance.

[0180] A computer-readable storage medium is also provided in an embodiment of the present application, wherein the computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and the processor executes the program instructions to implement the steps of the chip layout grid rapid segmentation method provided in the above-mentioned embodiments of the present application.

[0181] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (SmartMedia Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc., equipped on the computer device.

[0182] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for rapid grid generation of a chip layout, characterized in that: include: Obtaining the chip layout to be segmented; Parsing the chip layout, obtaining a plurality of layout elements to be segmented, and calculating a minimum feature tree corresponding to the layout elements; The layout elements at least include pads, vias, copper shapes and connections; Sorting a plurality of layout elements in a preset order to generate a layout element queue; the preset order includes any one of a heat conduction direction, a current direction, a stress direction and a layout direction; In the layout element queue, query in sequence whether each layout element corresponds to a feature tree; if not, perform fast node partitioning on each layout element according to the minimum feature tree to generate a multi-branch tree data structure corresponding to the layout element; the multi-branch tree data structure includes a root node corresponding to each layout element; the fast node partitioning includes any one of virtual rule node partitioning, high-precision rule node partitioning and AI fast automatic partitioning; The fast grid division of the chip layout is completed according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

2. The method according to claim 1, characterized in that Before sorting the plurality of layout elements in a preset order to generate a layout element queue, the method further includes: A parallel processing queue is established, wherein the parallel processing queue includes a stack element queue and a layout element queue; and the stack element queue and the layout element queue are simultaneously run to complete the rapid meshing of the chip layout.

3. The method according to claim 1, characterized in that If the fast node decomposition is the virtual regular node decomposition, the fast node decomposition of each layout element according to the minimum feature tree includes: Establishing an element multitree corresponding to the layout element; the element multitree at least includes any one of an element octree and an element quadtree; Determine whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element; If not, recursively perform the element multi-branch tree to obtain the unit node that satisfies the minimum feature tree corresponding to the layout element and the unit node that triggers the recursive partial threshold; Determine the unit node that triggers the recursive partial threshold as a virtual unit node; Splitting the unit nodes satisfying the minimum feature tree; The multi-tree data structure is formed according to the unit nodes after each decomposition of the layout elements, the unit nodes satisfying the minimum feature tree and the unit center coordinates of the virtual unit nodes; the multi-tree data structure includes at least any one of a quadtree data structure and an octree data structure.

4. The method according to claim 3, characterized in that Before judging whether the unit node corresponding to the element multi-branch tree satisfies the minimum feature tree corresponding to the layout element, the method further includes: Determine whether the element multitree needs to be simplified; If the element multitree needs to be simplified, polygon simplification is performed on the element multitree.

5. The method according to claim 3, characterized in that: Before completing the fast meshing of the chip layout according to the subtree information corresponding to the multi-tree data structure corresponding to each layout element, the method further includes: Obtain element feature information of each layout element; Determine a similar element group among the plurality of layout elements according to the element characteristic information, each of the similar element groups including a plurality of layout elements; The segmentation result corresponding to each of the layout elements in the similar element group is stored in the feature tree data area.

6. The method according to claim 1, characterized in that If the fast node partitioning is the AI ​​fast automatic partitioning, the fast node partitioning of each layout element according to the minimum feature tree includes: Performing feature extraction on the plurality of layout elements to be segmented, and obtaining feature information corresponding to each of the layout elements; the feature information at least includes vertex coordinates and materials; Forming a hash value based on the feature information and synchronously querying the feature tree data area; Synchronously querying the feature tree data area and each of the layout elements according to the hash value to complete the generation of the automatic segmentation model to be trained; Complete mesh pre-division of the plurality of layout elements by using the automatic division model to be optimized, and output the pre-divided mesh; The pre-divided grid is scored, and the automatic partitioning model is trained according to the scoring result corresponding to the scoring, so as to perform fast node partitioning on the feature tree of each layout element; wherein the scoring result includes at least one or more of a regular node quantity score, a grid density adaptability score, a node quantity score in areas where physical phenomena change dramatically, and a grid generation efficiency score.

7. The method according to claim 1, characterized in that After completing the fast grid division of the chip layout according to the subtree information corresponding to the multi-tree data structure, the method further includes: Generate a calculation expression for each node corresponding to the multi-tree data structure; The parameter value of the corresponding node is calculated according to the calculation expression; the parameter value includes at least one or more of resistance, stress, thermal resistance and impedance.

8. A device for rapid grid subdivision of a chip layout, characterized in that: include: A layout acquisition unit, which acquires the chip layout to be segmented; An element acquisition unit, used to parse the chip layout, acquire multiple layout elements to be segmented, and calculate the minimum feature tree corresponding to the layout elements; The layout elements at least include pads, vias, copper shapes and connections; An element sorting unit, used to sort a plurality of layout elements in a preset order to generate a layout element queue; the preset order includes any one of a heat conduction direction, a current direction, a stress direction and a layout direction; A fast partitioning unit, used for sequentially querying whether each layout element in the layout element queue corresponds to a feature tree, and if not, performing fast node partitioning on each layout element according to the minimum feature tree to obtain a multi-branch tree data structure corresponding to the layout element; the multi-branch tree data structure includes a root node corresponding to each of the layout elements; the fast node partitioning includes any one of virtual rule node partitioning, high-precision rule node partitioning and AI fast automatic partitioning; A subdivision completion unit is used to complete the rapid grid subdivision of the chip layout according to the subtree information corresponding to the multi-branch tree data structure corresponding to each layout element.

9. A computer device, characterized in that: The computer device includes a memory and a processor; The memory is used to store computer programs; The processor is configured to execute the computer program and implement the steps of the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, enables the processor to implement the steps of the method according to any one of claims 1 to 7.

Images