Semiconductor structure and method for forming the same
By designing a semiconductor structure including drift region, body region, gate structure, source region and drain region, and using resistors to form multiple conduction channels, the problem of insufficient anti-ESD capability in ESD protection is solved, and a higher maintenance voltage and ESD discharge capacity is achieved.
Patent Information
- Application Number
- CN202411457328.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2044-10-18
AI Technical Summary
In integrated circuit manufacturing process, when LDMOS is an ESD protection device, its anti-ESD capability is insufficient, which affects the reliability of the chip.
A semiconductor structure is designed, including a substrate, a drift region, a body region, a gate structure, a source region and a drain region, and is electrically connected to the gate structure and a source region through a resistor to form a multi-conducting channel to improve the maintenance voltage and ESD discharge capacity.
By increasing the maintenance voltage, the ESD discharge capacity is enhanced, and the chip's anti-ESD capability and reliability are improved.
Smart Images
Figure CN118969850B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present specification relate to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same. Background Art
[0002] With the improvement of integrated circuit manufacturing technology, the minimum line width has dropped to the nanometer level. While improving chip performance, the chip's ability to resist ESD strikes has also been greatly reduced. When ESD occurs, it will affect the reliability of the chip. Therefore, the contradiction between the development of integrated circuit manufacturing technology and the chip's ESD capability has become one of the issues that integrated circuit designers must consider.
[0003] As a type of power device, LDMOS (Lateral Double-diffused MOS) has high driving voltage and good switching characteristics. It is used as an ESD protection device in various chips.
[0004] However, there are still some problems when using LDMOS as a protection device. Summary of the invention
[0005] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can increase the sustaining voltage of the semiconductor structure and enhance the ESD protection capability.
[0006] An embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate having an epitaxial layer with a first type of doping; a drift region with a first type of doping, located in the epitaxial layer; a body region with a second type of doping, located in the epitaxial layer and adjacent to the drift region; a first gate structure, located on the substrate and spanning the body region and the drift region; a second gate structure, located on the substrate of the body region; a first source region with the first type of doping, located in the body region, and the first source region is located between the first gate structure and the second gate structure; a second source region with the first type of doping, located in the body region, and the second source region is located on a side of the second gate structure away from the first source region; a drain region with the first type of doping, located in the drift region; and a resistor, the resistor being electrically connected to the first gate structure, the second gate structure, and the first source region or the second source region, respectively.
[0007] Optionally, the doping concentration of the first source region is greater than the doping concentration of the second source region.
[0008] Optionally, a thickness of a gate oxide layer of the second gate structure is less than or equal to a thickness of a gate oxide layer of the first gate structure.
[0009] Optionally, a first end of the resistor is electrically connected to the first gate structure, the second gate structure and the first source region respectively; a second end of the resistor is electrically connected to the second source region and is grounded.
[0010] Optionally, a first end of the resistor is electrically connected to the first gate structure, the second gate structure and the second source region respectively; a second end of the resistor is electrically connected to the first source region and is grounded.
[0011] Optionally, the semiconductor structure further comprises:
[0012] A body contact region having the second type doping, wherein the body contact region is located in a body region of the second source region on a side away from the second gate structure;
[0013] The resistor is also electrically connected to the body contact region.
[0014] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein an epitaxial layer having a first type of doping is formed in the substrate; forming a drift region having the first type of doping and a body region having a second type of doping in the epitaxial layer, wherein the drift region and the body region are adjacent to each other; forming a first gate structure spanning the body region and the drift region on the substrate; forming a second gate structure on the substrate of the body region; forming a first source region having the first type of doping and a second source region having the first type of doping in the body region, wherein the first source region is located between the first gate structure and the second gate structure, and the second source region is located on a side of the second gate structure away from the first source region; forming a drain region having the first type of doping in the drift region; and forming a resistor, wherein the resistor is electrically connected to the first gate structure, the second gate structure, and the first source region or the second source region, respectively.
[0015] Optionally, the doping concentration of the first source region is greater than the doping concentration of the second source region.
[0016] Optionally, a thickness of a gate oxide layer of the second gate structure is less than or equal to a thickness of a gate oxide layer of the first gate structure.
[0017] Optionally, when the thickness of the gate oxide layer of the second gate structure is equal to the thickness of the gate oxide layer of the first gate structure, the first gate structure and the second gate structure are formed in the same process step.
[0018] Optionally, a first end of the resistor is electrically connected to the first gate structure, the second gate structure and the first source region respectively; a second end of the resistor is electrically connected to the second source region and is grounded.
[0019] Optionally, a first end of the resistor is electrically connected to the first gate structure, the second gate structure and the second source region respectively; a second end of the resistor is electrically connected to the first source region and is grounded.
[0020] Optionally, the method for forming a semiconductor structure further includes:
[0021] forming a body contact region having a second doping in the body region, wherein the body contact region is located on a side of the second source region away from the second gate structure;
[0022] The resistor is also electrically connected to the body contact region.
[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0024] In the semiconductor structure provided by the embodiment of the present invention, the drift region, the first source region and the second source region are all first-type doped, the body region is second-type doped, the resistor is electrically connected to the first gate structure and the second gate structure, and the end of the resistor connected to the first gate structure is also electrically connected to the first source region or the second source region, so that the drain region is affected by ESD. Since the drift region is adjacent to the body region, and the first source region and the second source region are located in the body region, the first source region or the second source region, the drift region and the body region electrically connected to the first gate structure and the resistor form a second conduction channel, while the first source region or the second source region, the drift region and the body region not electrically connected to the first gate structure and the resistor form a first conduction channel. In this way, the current generated in the first conduction channel can be amplified and fed back to the first gate structure and the second gate structure through the resistor, thereby increasing the maintenance voltage on the second conduction channel, so that the second conductive channel can better discharge ESD and enhance ESD protection capability.
[0025] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the drift region, the first source region, and the second source region formed in the substrate are all first-type doped, the body region is second-type doped, the resistor is electrically connected to the first gate structure and the second gate structure, and the end of the resistor connected to the first gate structure is also electrically connected to the first source region or the second source region, so that the drain region is affected by ESD. Since the drift region is adjacent to the body region, and the first source region and the second source region are located in the body region, the first source region or the second source region, the drift region, and the body region electrically connected to the first gate structure and the resistor form a first conduction channel, while the first source region or the second source region, the drift region, and the body region not electrically connected to the first gate structure and the resistor form a first conduction channel. In this way, the current generated in the first conduction channel can be amplified and fed back to the first gate structure and the second gate structure through the resistor, thereby increasing the maintenance voltage on the second conduction channel, so that the second conductive channel can better discharge ESD and enhance ESD protection capability. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;
[0027] Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;
[0028] Figures 3 to 7 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention;
[0029] Figure 8 yes Figure 7 A schematic diagram of a circuit equivalent structure of the semiconductor structure of the present invention shown;
[0030] Fig. 9 It is a structural schematic diagram of a second embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0031] As can be seen from the background art, there are still some problems when using LDMOS as a protection device. The reasons for the poor performance are now analyzed in combination with a semiconductor structure.
[0032] See also Figure 1 A schematic diagram of a semiconductor structure shown in FIG. Figure 1 As shown, the semiconductor structure includes: a substrate 10; an epitaxial layer 12 with a first type of doping; a drift region 14 with a first type of doping, located in the epitaxial layer 12; a body region 16 with a second type of doping, located in the epitaxial layer 12 and adjacent to the drift region 14; a gate structure 18, located on the substrate 10 and spanning the body region 16 and the drift region 14; a drain region 20 with a first type of doping, located in the drift region 14; and a source region 22 with a first type of doping, located in the body region 16.
[0033] At present, when the drain region 20 is affected by ESD, a conductive channel can be formed through the drift region 14, the body region 16 and the source region 22, so that the generated current can flow to the gate structure 18, and the path between the gate structure 18 and the drain region 20 is opened, so that the ESD can be discharged to the ground.
[0034] In actual applications, when the drain region 20 is affected by ESD, the holding voltage of the semiconductor device is low, a latch-up effect is likely to occur, and the ESD cannot be discharged.
[0035] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure. In the formation method provided by the embodiment of the present invention, the drift region, the first source region, and the second source region formed in the substrate are all first-type doped, the body region is second-type doped, the resistor is electrically connected to the first gate structure and the second gate structure, and the end of the resistor connected to the first gate structure is also electrically connected to the first source region or the second source region, so that the drain region is affected by ESD. Since the drift region is adjacent to the body region, and the first source region and the second source region are located in the body region, the first source region or the second source region, the drift region, and the body region electrically connected to the first gate structure and the resistor form a first conduction channel, while the first source region or the second source region, the drift region, and the body region not electrically connected to the first gate structure and the resistor form a first conduction channel. In this way, the current generated in the first conduction channel can be amplified and fed back to the first gate structure and the second gate structure through the resistor, thereby increasing the holding voltage on the second conduction channel, so that the second conductive channel can better discharge ESD and enhance ESD protection capability.
[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention is described below with reference to the accompanying drawings.
[0037] Figure 2 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.
[0038] See also Figure 2 In this embodiment, the semiconductor structure includes: a substrate 100, the substrate 100 having an epitaxial layer 102 with a first type of doping; a drift region 104 with a first type of doping, located in the epitaxial layer 102; a body region 106 with a second type of doping, located in the epitaxial layer 102 and adjacent to the drift region 104; a first gate structure 112, located on the substrate 100 and spanning the body region 106 and the drift region 104; a second gate structure 118, located on the substrate 100 in the body region 106; a first source region 118 having a first type of doping 120, located in the body region 106, and the first source region 120 is located between the first gate structure 112 and the second gate structure 118; the second source region 122 with the first type doping is located in the body region 106, and the second source region 122 is located on the side of the second gate structure 118 away from the first source region 120; the drain region 124 with the first type doping is located in the drift region 104; the resistor R, the resistor R is electrically connected to the first gate structure 112, the second gate structure 118, and the first source region 120 respectively.
[0039] The substrate 100 is used to provide a process platform for subsequently forming a semiconductor structure. Specifically, the formed semiconductor structure is LDMOS.
[0040] In this embodiment, the formed LDMOS is a planar transistor as an example, and the substrate 100 is a planar substrate. In other embodiments, when the formed LDMOS is a fin field effect transistor, the substrate includes a substrate and separate fins on the substrate.
[0041] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0042] The epitaxial layer 102 is used as a path for carrier migration when the LDMOS device is working. When the LDMOS device is working, the electric field distribution on the epitaxial layer 102 is controlled by changing the doping distribution and thickness of the epitaxial layer 102 .
[0043] In this embodiment, the first type doping may be N type doping, and the doping ions may include at least one of P ions, As ions or Sb ions.
[0044] In other embodiments, the first type doping may be P type doping, and the doping ions may include at least one of B ions, Ga ions, or In ions.
[0045] The presence of the drift region 104 is beneficial to improving the breakdown voltage between the subsequently formed source region (first source region 120) and the drain region 124, and reducing the parasitic capacitance between (the first source region 120) and the drain region 124, and the drift region 104 can be used to withstand a larger bias voltage, thereby improving the breakdown voltage of the LDMOS device.
[0046] In this embodiment, the drift region 104 has first-type doping ions. Specifically, when the LDMOS device is an N-type transistor, the doping ions in the drift region 104 are N-type ions, such as P ions, As ions, or Sb ions; when the LDMOS device is a P-type transistor, the doping ions in the drift region 104 are P-type ions, such as B ions, Ga ions, or In ions.
[0047] The body region 106 serves as a lateral diffusion region to form a channel with a concentration gradient. Specifically, the portion of the body region 106 covered by the first gate structure 112 and the second gate structure 118 serves as an effective channel region.
[0048] In this embodiment, the body region 106 has second type doping ions which are different from the doping type of the drift region 104 .
[0049] Specifically, the doping type of the body region 106 is P-type doping, and the doping ions used in the P-type doping are B, Ga or In.
[0050] In this embodiment, the body region 106 and the drift region 104 are adjacent to each other and have different doping types, so that when ESD is generated at the drain end, a conductive channel can be formed through the body region 106 and the drift region 104 .
[0051] When the device is working, the first gate structure 112 is used to control the opening and closing of the conductive channel, and the first gate structure 112 spans the interface surface between the body region 106 and the drift region 104 , so that the drift region 104 can withstand a larger divided voltage.
[0052] It should be noted that when the semiconductor structure in this solution is used for ESD protection, the first gate structure 112 does not work. This is because the turn-on voltage applied to the first gate structure 112 is generally less than the threshold voltage, so that the channel inside the semiconductor will not be turned on, and thus no breakdown phenomenon will occur.
[0053] In this embodiment, the first gate structure 112 includes a first gate oxide layer 108 and a first gate layer 110 located above the first gate oxide layer 108, wherein the first gate oxide layer 108 is used to electrically isolate the LDMOS channel and the first gate structure 112; the first gate layer 110 is used to electrically connect to an external circuit.
[0054] The material of the first gate oxide layer 108 is silicon oxide. In other embodiments, the material of the first gate oxide layer may also be silicon oxynitride.
[0055] The material of the first gate layer 110 is a dielectric material, such as polysilicon.
[0056] When the device is in operation, the second gate structure 118 is used to control the opening and closing of the conductive channel.
[0057] The working state of the second gate structure 118 may refer to the description of the first gate structure 112 .
[0058] In this embodiment, the second gate structure 118 includes a second gate oxide layer 114 and a second gate layer 116 located above the second gate oxide layer 114, wherein the second gate oxide layer 114 is used to electrically isolate the LDMOS channel and the second gate structure 118; the second gate layer 116 is used to electrically connect to an external circuit.
[0059] The material of the second gate oxide layer 114 is silicon oxide. In other embodiments, the material of the first gate oxide layer may also be silicon oxynitride.
[0060] The material of the second gate layer 116 is a dielectric material, such as polysilicon.
[0061] In the present embodiment, the thickness of the gate oxide layer 114 of the second gate structure 118 is less than the thickness of the gate oxide layer 108 of the first gate structure 112. This is because the first source region 120 and the second source region 122 are both located in the body region 106, and the distance between the first source region 120 and the second source region 122 is short, so it is easy to perform inversion treatment on the area between the first source region 120 and the second source region 122, so that the gate oxide layer 114 of the second gate structure 118 can have a smaller thickness and can reduce the volume of the semiconductor structure.
[0062] In some other embodiments, the thickness of the gate oxide layer of the second gate structure may be equal to the thickness of the gate oxide layer of the first gate structure.
[0063] The first source region 120 and the second source region 122 are used as the source of the semiconductor structure. When the device is working, the first source region 120 and the second source region 122 are used to provide a carrier source.
[0064] In this embodiment, the first source region 120 and the second source region 122 are located in the body region 106, and the first source region 120 and the second source region 122 have the same doping type as the body region 106 and the same doping type as the drift region 104. In this way, when ESD is generated in the drain region 124, a second conductive channel is formed between the first source region 120, the body region 106 and the drift region 104, and a first conductive channel is formed between the second source region 120, the body region 106 and the drift region 104. Through the coordination between the first conductive channel, the second conductive channel, and the resistor R, the semiconductor structure can quickly discharge ESD.
[0065] The ion doping type of the first source region 120 and the second source region 122 is N type.
[0066] In this embodiment, the doping concentration of the first source region 120 is greater than the doping concentration of the second source region 122. In this way, when the drain region 124 is affected by ESD, the first conduction channel formed by the second source region 122, the drift region 104 and the body region 106 can be quickly turned on, so that a higher maintenance voltage can be quickly established in the second conduction channel, so that the second conductive channel can better discharge ESD and improve the ESD protection capability.
[0067] In some other embodiments, the doping concentration of the first source region 120 is the same as the doping concentration of the second source region 122 , or the doping concentration of the first source region 120 is less than the doping concentration of the second source region 122 , and the embodiments of the present invention do not impose any limitation on this.
[0068] The drain region 124 is used as a drain of the semiconductor structure. When the device is working, the drain region 224 is used to provide a carrier source.
[0069] In this embodiment, the ion doping type of the drain region 124 is N-type, and the doping ion concentration in the drain region 124 is greater than the doping ion concentration in the drift region 104, so that the drift region 104 is a high-resistance region, so that the drift region 104 can be used to withstand a larger voltage divider to increase the breakdown voltage of the semiconductor structure.
[0070] In this embodiment, the semiconductor structure may further include: a body contact region 126 having a second doping agent, wherein the body contact region 126 is located in the body region 106 on a side of the second source region 122 away from the second gate structure 118 .
[0071] The body contact region 126 is used as a signal connector of the body region 106 , thereby realizing electrical connection between the body region 106 and an external circuit or other interconnection structures.
[0072] In this embodiment, the doping type of the body contact region 126 is the same as the doping type of the body region 106 , both of which are P-type ions.
[0073] In this embodiment, the sidewall of the body contact region 126 does not contact the sidewall of the source region 122 .
[0074] By setting the resistor R, when ESD is generated on the drain region 124, a part of the current can be transmitted to the resistor R, so that after amplification and feedback by the resistor R, a higher driving voltage can be generated on the first gate structure 112 and the second gate structure 118, thereby improving the driving capabilities of the first gate structure 112 and the second gate structure 118, so as to speed up the discharge path between the drain region 124 and the ground, thereby improving the ESD discharge speed.
[0075] More specifically, the first end of the resistor R is electrically connected to the first gate structure 112, the second gate structure 118 and the first source region 120, respectively, and the second end of the resistor R is electrically connected to the second source region 122 and is grounded, so that when ESD is generated on the drain region 124, the drift region 104, the body region 106 and the second source region 122 can form a first conductive channel L1, so that a part of the current can be fed back and amplified to the first gate structure 112 and the second gate structure 118 through the resistor R, so that the second conductive channel L2 formed by the drift region 104, the body region 106 and the first source region 120 can be turned on, so that the ESD flowing through the drain region 124 can be discharged to the ground through the second conductive channel L2.
[0076] In this embodiment, when a body contact region 126 is formed in the body region 106, the body contact region 126 is generally used as a substrate, and the potential of the body contact region 126 needs to be 0. Therefore, the body contact region 126 is electrically connected to the second end of the resistor R and grounded, thereby ensuring that the potential of the body contact region 126 is 0.
[0077] In short, compared to Figure 1The semiconductor structure shown in the figure can improve the ESD discharge speed by adding a second gate structure 118, a second source region 122 located on the side of the second gate structure 118 away from the first source region 120, and a resistor R electrically connected to the second gate structure 118 and the first gate structure 112.
[0078] The present invention also provides a schematic diagram of the structure of a second embodiment of the semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiment are not repeated here. The difference between this embodiment and the previous embodiment is that the first end of the resistor is electrically connected to the first gate structure, the second gate structure and the second source region respectively, and the second end of the resistor is electrically connected to the first source and grounded.
[0079] Figures 3 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0080] See also Figure 3 , providing a substrate 200 , in which an epitaxial layer 202 having a first type of doping is formed.
[0081] The substrate 200 is used to provide a process platform for subsequently forming a semiconductor structure. Specifically, the formed semiconductor structure is LDMOS.
[0082] In this embodiment, the formed LDMOS is a planar transistor as an example, and the substrate 200 is a planar substrate. In other embodiments, when the formed LDMOS is a fin field effect transistor, the substrate includes a substrate and separate fins on the substrate.
[0083] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.
[0084] The epitaxial layer 202 is used as a path for carrier migration when the LDMOS device is working. When the LDMOS device is working, the electric field distribution on the epitaxial layer 202 is controlled by changing the doping distribution and thickness of the epitaxial layer 202 .
[0085] In this embodiment, an epitaxial layer 202 is formed on a substrate 200 by epitaxial growth. During the epitaxial growth process, the epitaxial layer 202 having the first type of doping is obtained by in-situ doping with the first type of ions.
[0086] In this embodiment, the first type doping may be N type doping, and the doping ions may include at least one of P ions, As ions or Sb ions.
[0087] In other embodiments, the first type doping may be P type doping, and the doping ions may include at least one of B ions, Ga ions, or In ions.
[0088] See also Figure 4 A drift region 204 with a first type of doping and a body region 206 with a second type of doping are formed in the epitaxial layer 202 , and the drift region 204 and the body region 206 are adjacent to each other.
[0089] The presence of the drift region 204 is beneficial to improving the breakdown voltage between the source region and the drain region formed subsequently and reducing the parasitic capacitance between the source region and the drain region. The drift region 204 can be used to withstand a larger bias voltage, thereby improving the breakdown voltage of the LDMOS device.
[0090] In this embodiment, the drift region 204 has first type doping ions.
[0091] Specifically, when the LDMOS device is an N-type transistor, the doped ions in the drift region 204 are N-type ions, such as P ions, As ions or Sb ions; when the LDMOS device is a P-type transistor, the doped ions in the drift region 204 are P-type ions, such as B ions, Ga ions or In ions.
[0092] The body region 206 serves as a lateral diffusion region to form a channel with a concentration gradient. Specifically, the portion of the body region 206 covered by the first gate structure and the second gate structure serves as an effective channel region.
[0093] In this embodiment, the body region 206 has second type doping ions which are different from the doping type of the drift region 204 .
[0094] Specifically, the doping type of the body region 206 is P-type doping, and the doping ions used in the P-type doping are B, Ga or In.
[0095] In this embodiment, the body region 206 and the drift region 204 are adjacent to each other and have different doping types, so that when ESD is generated at the drain end, a conductive channel can be formed through the body region 206 and the drift region 204 .
[0096] See also Figure 5 , a first gate structure 212 is formed on the substrate 200 and spans the body region 206 and the drift region 204 .
[0097] When the device is working, the first gate structure 212 is used to control the opening and closing of the conductive channel, and the first gate structure 212 spans the interface surface between the body region 206 and the drift region 204 , so that the drift region 204 can withstand a larger divided voltage.
[0098] It should be noted that when the semiconductor structure in this solution is used for ESD protection, the first gate structure 212 does not work. This is because the turn-on voltage applied to the first gate structure 212 is generally less than the threshold voltage, so that the channel inside the semiconductor will not be turned on, and thus no breakdown phenomenon will occur.
[0099] See next Figure 5 , a second gate structure 218 is formed on the substrate 200 in the body region 206 .
[0100] When the device is in operation, the second gate structure 218 is used to control the opening and closing of the conductive channel.
[0101] The working state of the second gate structure 218 may refer to the description of the first gate structure 212 .
[0102] In the present embodiment, the thickness of the gate oxide layer 214 of the second gate structure 218 is less than the thickness of the gate oxide layer 208 of the first gate structure 212. This is because the first source region 220 and the second source region 222 are both located in the body region 206, and the distance between the first source region 220 and the second source region 222 is short, so it is easy to perform inversion treatment on the area between the first source region 220 and the second source region 222, so that the gate oxide layer 214 of the second gate structure 218 can have a smaller thickness and can reduce the volume of the semiconductor structure.
[0103] In this embodiment, the thickness of the gate oxide layer 214 of the second gate structure 218 is smaller than the thickness of the gate oxide layer 208 of the first gate structure 212 , and the second gate structure 218 and the first gate structure 212 are formed in different steps.
[0104] For example, a first initial gate oxide layer (not labeled in the figure) and a first initial main material layer (not labeled in the figure) are sequentially formed on the substrate 200 .
[0105] A patterned first mask layer (not shown) is formed, and the first initial main material layer and the first initial gate oxide layer are etched using the first mask layer as a mask to obtain a first gate structure 212 .
[0106] In this embodiment, the first initial gate oxide layer is formed by performing oxidation treatment on the surface of the substrate 200, which can improve the formation quality and density of the first initial gate oxide layer.
[0107] In a specific embodiment, the process of forming the first initial gate oxide layer by oxidation treatment may be an in-situ water vapor generation oxidation process.
[0108] In this embodiment, the material of the first initial gate oxide layer is silicon oxide. In other embodiments, the material of the first initial gate oxide layer may also be silicon oxynitride.
[0109] In this embodiment, a deposition process (such as a chemical vapor deposition process) is used to form a first initial main material layer above the first initial gate oxide layer.
[0110] In this embodiment, the material of the first initial main material layer is a dielectric material, such as polysilicon.
[0111] In this embodiment, by performing a graphical process, the remaining first initial gate oxide layer serves as the first gate oxide layer 208 for electrically isolating the LDMOS channel and the first gate structure 212; the remaining first initial main material layer serves as the first gate layer 210, and the first gate layer 210 is used to be electrically connected to an external circuit.
[0112] It is understandable that after forming the first gate structure 212, a step of removing the first mask layer is further performed. For example, by dry etching, the sidewall morphology quality of the first gate structure 212 can be improved while removing the first mask layer.
[0113] Next, according to the formation method of the first gate structure 212 , a second gate structure 218 is formed on the substrate on the body region 206 . The second gate structure 218 includes a second gate oxide layer 214 and a second gate layer 216 located above the second gate oxide layer 214 .
[0114] It should be noted that, in this embodiment, the second gate structure is formed after the first gate structure is formed. In other embodiments, the first gate structure may be formed after the second gate structure is formed.
[0115] In some other embodiments, the thickness of the gate oxide layer of the second gate structure may be equal to the thickness of the gate oxide layer of the first gate structure, so that the first gate structure and the second gate structure may be formed in the same process step.
[0116] By forming the first gate structure and the second gate structure in the same process step, it is helpful to simplify the process steps for forming the second gate structure without affecting the electrical properties of the first gate structure, so that the first gate structure can normally control the opening and closing of the conductive channel, thereby improving the reliability of the semiconductor structure.
[0117] See also Figure 6 A first source region 220 with first-type doping and a second source region 222 with first-type doping are formed in the body region 206, the first source region 220 is located between the first gate structure 212 and the second gate structure 218, and the second source region 222 is located on a side of the second gate structure 218 away from the first source region 220. The first source region 220 and the second source region 222 are used as the source of the semiconductor structure, and when the device is working, the first source region 220 and the second source region 222 are used to provide a carrier source.
[0118] In this embodiment, the first source region 220 and the second source region 222 are located in the body region 206, and the first source region 220 and the second source region 222 have the same doping type as the body region 206 and the same doping type as the drift region 204. In this way, when ESD is generated in the drain region, a second conductive channel is formed between the first source region 220, the body region 206 and the drift region 204, and a first conductive channel is formed between the second source region 222, the body region 206 and the drift region 204. Through the coordination between the first conductive channel, the second conductive channel, and the subsequently formed resistors, the semiconductor structure can quickly discharge ESD.
[0119] In this embodiment, an ion implantation process is used to form the first source region 220 and the second source region 222 , and the ion doping type is N-type.
[0120] It should be noted that the first source region 220 and the second source region 222 may be formed in the same ion implantation process, or may be formed in different process steps, and the present invention is not limited thereto.
[0121] In this embodiment, the doping concentration of the first source region 220 is greater than the doping concentration of the second source region 222. In this way, when the drain region 224 is affected by ESD, the first conduction channel formed by the second source region 222, the drift region 204 and the body region 206 can be quickly turned on, so that a higher maintenance voltage can be quickly established in the second conduction channel, so that the second conductive channel can better discharge ESD and improve the ESD protection capability.
[0122] In some other embodiments, the doping concentration of the first source region 220 is the same as the doping concentration of the second source region 222 , or the doping concentration of the first source region 220 is less than the doping concentration of the second source region 222 , and the embodiments of the present invention do not impose any limitation on this.
[0123] See next Figure 6 , a drain region 224 having a first type of doping is formed in the drift region 204 .
[0124] The drain region 224 is used as a drain of the semiconductor structure. When the device is working, the drain region 224 is used to provide a carrier source.
[0125] In this embodiment, an ion implantation process is used to form the drain region 224, and the ion doping type is N-type.
[0126] In this embodiment, the drift region 204 is a high resistance region, and the doping ion concentration in the drift region 204 is small and much smaller than the doping ion concentration in the drain region 224 , so that the drift region 204 is used to withstand a larger partial pressure to increase the breakdown voltage of the semiconductor structure.
[0127] In this embodiment, the first source region 220, the second source region 222 and the drain region 224 are formed in the same step.
[0128] Specifically, the process includes: forming a graphic layer (not shown) on the substrate 200, the graphic layer covering the first gate structure 212 and the second gate structure 218, and exposing a partial area of the substrate 200 on the side of the first gate structure 212 away from the second gate structure 218, and also exposing a partial area of the substrate 200 on both sides of the second gate structure 218; using the graphic layer as a mask, performing a doping treatment on the substrate 200 to form a first source region 220, a second source region 222 and a drain region 224; and finally removing the graphic layer.
[0129] In some other embodiments, the first source region 220 , the second source region 222 , and the drain region 224 may also be formed in different steps.
[0130] In this embodiment, the formation method may further include: forming a body contact region 226 having a second doping agent in the body region 206 , wherein the body contact region 226 is located at a side of the second source region 222 away from the second gate structure 218 .
[0131] The body contact region 226 is used as a signal connector of the body region 206 , thereby realizing electrical connection between the body region 206 and an external circuit or other interconnection structures.
[0132] In this embodiment, the doping type of the body contact region 226 is the same as the doping type of the body region 206 , both of which are P-type ions.
[0133] In this embodiment, the sidewall of the body contact region 226 does not contact the sidewall of the source region 222 .
[0134] See also Figure 7 , forming a resistor R, which is electrically connected to the first gate structure 212, the second gate structure 218, and the first source region 220 respectively.
[0135] By setting the resistor R, when ESD is generated on the drain region 224, part of the current can be transmitted to the resistor R, so that after amplification and feedback by the resistor R, a higher maintenance voltage can be generated on the second conductive channel, so that the second conductive channel can better discharge ESD and improve the ESD protection capability.
[0136] More specifically, the first end of the resistor R is electrically connected to the first gate structure 212, the second gate structure 218 and the first source region 220, respectively, and the second end of the resistor R is electrically connected to the second source region 222 and is grounded. Therefore, when ESD is generated on the drain region 224, the drift region 204, the body region 206 and the second source region 222 can form a first conductive channel L1, so that a part of the current can be fed back and amplified through the resistor R to the second conductive channel L2 formed by the drift region 204, the body region 206 and the first source region 220, so that the second conductive channel L2 has a higher maintenance voltage, avoiding the latch effect, so that the ESD can be better discharged to the ground.
[0137] In other words, if Figure 8 shown Figure 7 The circuit equivalent structure diagram in is as follows: Figure 8 As shown, the first end of the resistor R is electrically connected to the collector of the first transistor NM1 (the first transistor NM1 can be formed by the drift region 204, the body region 206 and the second source region 222) and the emitter of the second transistor NM2 (the second transistor NM2 can be formed by the drift region 204, the body region 206 and the first source region 220), respectively, and the second end of the resistor R is electrically connected to the emitter of the first transistor NM1 and is grounded.
[0138] The base of the first transistor NM1 is electrically connected to the base of the second transistor NM1 and the drain region 224 respectively, and is connected to the drain region 224 through the parasitic resistance R well Ground.
[0139] The collector of the second transistor NM2 is connected to the parasitic resistor R of the drift region 204. Drift Electrically connected to the drain region 224 .
[0140] When an ESD surge occurs in the drain region Drain, the potential of the drift region 204 and the body region 206 increases. When the potential increases to a certain value, an avalanche breakdown occurs at the contact between the drift region 204 and the body region 206. The reverse bias current generated thereby flows through the parasitic resistor R well , so that the first transistor NM1 and the second transistor NM2 operate, so that the ESD is released to the ground through the first transistor NM1 and the second transistor NM2.
[0141] At this time, the holding voltage of the semiconductor structure is determined by the reverse bias voltage of the collector junction of the first transistor NM1 and the parasitic resistor R well The voltage drop across the semiconductor structure can increase the holding voltage and prevent the latch-up effect from occurring in the semiconductor structure.
[0142] At the same time, when the ESD surge is applied to the second transistor NM2, a portion of the forward current flows through the resistor R to reach the terminal A, and the potential of the terminal A increases, so that a higher potential difference is exhibited between the first source region 220 and the drain region 224 of the second transistor NM2, and the holding voltage can also be increased, so that the ESD can be better released to the ground.
[0143] In this embodiment, when a body contact region 226 is formed in the body region 206, the body contact region 226 is generally used as a substrate, and the potential of the body contact region 226 needs to be 0. Therefore, the body contact region 226 is electrically connected to the second end of the resistor R and grounded, thereby ensuring that the potential of the body contact region 226 is 0.
[0144] In short, compared to Figure 1 The semiconductor structure shown in the figure can improve the ESD discharge speed by adding a second gate structure 218, a second source region 222 located on the side of the second gate structure 218 away from the first source region 220, and a resistor R electrically connected to the second gate structure 218 and the first gate structure 212.
[0145] Fig. 9 It is a structural schematic diagram of a second embodiment of a method for forming a semiconductor structure of the present invention.
[0146] The differences between this embodiment and the above embodiment are as follows: the first end of the resistor R is electrically connected to the first gate structure 212, the second gate structure 218 and the second source region 222 respectively, and the second end of the resistor R is electrically connected to the first source region 220 and grounded.
[0147] It should be noted that the semiconductor structure described in this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.
[0148] Although the present specification is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: A substrate having an epitaxial layer doped with a first type of doping; a drift region having a first type of doping, located in the epitaxial layer; a body region having a second type of doping, located in the epitaxial layer and adjacent to the drift region; A first gate structure, located on the substrate and spanning the body region and the drift region; a second gate structure, located on the substrate of the body region; a first source region having the first type of doping, located in the body region, and the first source region is located between the first gate structure and the second gate structure; a second source region having the first type of doping, located in the body region, and the second source region is located on a side of the second gate structure away from the first source region; a drain region having the first type of doping, located in the drift region; A body contact region having the second type doping, wherein the body contact region is located in a body region of the second source region on a side away from the second gate structure; A resistor, wherein the first end of the resistor is electrically connected to the first gate structure, the second gate structure and the first source region respectively, and the second end of the resistor is electrically connected to the second source region and the body contact region respectively, and is grounded; or, the first end of the resistor is electrically connected to the first gate structure, the second gate structure and the second source region respectively, and the second end of the resistor is electrically connected to the first source region and the body contact region respectively, and is grounded.
2. The semiconductor structure according to claim 1, characterized in that: The doping concentration of the first source region is greater than the doping concentration of the second source region.
3. The semiconductor structure according to claim 1, characterized in that: The thickness of the gate oxide layer of the second gate structure is less than or equal to the thickness of the gate oxide layer of the first gate structure.
4. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, in which an epitaxial layer having a first type of doping is formed; forming a drift region having the first type of doping and a body region having the second type of doping in the epitaxial layer, wherein the drift region and the body region are adjacent to each other; forming a first gate structure on the substrate that spans the body region and the drift region; forming a second gate structure on the substrate of the body region; forming a first source region having the first type of doping and a second source region having the first type of doping in the body region, wherein the first source region is located between the first gate structure and the second gate structure, and the second source region is located on a side of the second gate structure away from the first source region; forming a drain region having the first type of doping in the drift region; forming a body contact region having a second doping in the body region, wherein the body contact region is located on a side of the second source region away from the second gate structure; A resistor is formed, wherein a first end of the resistor is electrically connected to the first gate structure, the second gate structure and the first source region, respectively, and a second end of the resistor is electrically connected to the second source region and the body contact region, respectively, and is grounded; or, a first end of the resistor is electrically connected to the first gate structure, the second gate structure and the second source region, respectively, and a second end of the resistor is electrically connected to the first source region and the body contact region, respectively, and is grounded.
5. The method for forming a semiconductor structure according to claim 4, characterized in that: The doping concentration of the first source region is greater than the doping concentration of the second source region.
6. The method for forming a semiconductor structure according to claim 4, characterized in that: The thickness of the gate oxide layer of the second gate structure is less than or equal to the thickness of the gate oxide layer of the first gate structure.
7. The method for forming a semiconductor structure according to claim 6, wherein: When the thickness of the gate oxide layer of the second gate structure is equal to the thickness of the gate oxide layer of the first gate structure, the first gate structure and the second gate structure are formed in the same process step.
Citation Information
Patent Citations
Power MOSFET with integrated gate resistor and diode-connected MOSFET
CN103782386A