A logic latch circuit with fixed output level when powered on

Abstract

The present invention relates to the field of logic latch chips, and in particular to a logic latch circuit with a fixed output level upon power-on, comprising an input module, a latch module and an output drive module; the latch module comprises a MOS transistor P0, a MOS transistor P1, a MOS transistor P2, a MOS transistor N0, a MOS transistor N1 and a MOS transistor N2; since the driving capability of the MOS transistor N2 is stronger than that of the MOS transistor P2, at the moment of power-on, a Din voltage is clamped at a low level by the MOS transistor N2; since the driving capabilities of the MOS transistors P1 and P0 are stronger than those of the MOS transistors N1 and N0, a #imgabs0# signal is clamped at a high level by the MOS transistors P1 and P0, and finally Q0 is fixed at a low level at the moment of power-on, thereby avoiding an indeterminate state, thereby avoiding a situation where an external device is mistakenly triggered to start by a logic latch chip when an MCU is not initialized, resulting in system abnormality.

Description

Technical Field

[0001] The invention relates to the field of logic latch chips, and in particular to a logic latch circuit which outputs a fixed level when powered on. Background Art

[0002] A logic latch chip is an electronic component with two stable states (usually 0 and 1). Once its state is determined, it can maintain the state by itself until the latch level changes. This feature makes logic latch chips widely used in digital circuits to store and transmit 1-bit binary data. In complex electronic systems, logic latch chips play the role of a bridge. They connect different circuit parts to ensure that data can be accurately transmitted from one place to another. Whether it is the registers and caches inside the computer, or the data transmission units in the communication system, they are inseparable from the contribution of logic latch chips. With the continuous advancement of technology, logic latch chips are also evolving. They have become more efficient, energy-saving, and smaller in size to meet the high performance and space requirements of modern electronic equipment.

[0003] However, if the input of the existing logic latch chip with input enable is not enabled at the moment of power-on, the internal latch signal is in an unstable state (high H or low L) and the output state is also unstable. When used with an MCU, the MCU output is connected to the input of the logic latch chip, and the logic latch chip controls the external device. Because the MCU requires initialization time, if the MCU output fails to enable the input of the logic latch chip during the initialization stage, the output state of the logic latch chip is determined by the internal latch signal and the output is unstable, that is, when the MCU is not initialized, the external device may be mistakenly triggered and started by the logic latch chip. Summary of the invention

[0004] The purpose of the present invention is to provide a logic latch circuit with a fixed output level when powered on, aiming to improve the existing logic latch chip with input enable. If the input is not enabled at the moment of power-on, the internal latch signal is in an unstable state (high H or low L) and the output state is also unstable.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A logic latch circuit with a fixed output level when powered on, characterized in that it comprises an input module, a latch module and an output drive module;

[0007] The latch module includes MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor N0, MOS transistor N1 and MOS transistor N2;

[0008] The input module outputs an enable signal to the output drive module, the input module outputs a latch control signal to the gates of the MOS transistor P1 and the MOS transistor N1, and the input module outputs a data input signal to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2, and the gate of the MOS transistor N2;

[0009] The source of the MOS transistor P0, the source of the MOS transistor P2 and the power input terminal of the output driving module are electrically connected to the external power supply VDD;

[0010] The drain of the MOS transistor P0 is electrically connected to the source of the MOS transistor P1, the gate of the MOS transistor P0 is electrically connected to the gate of the MOS transistor N0, the drain of the MOS transistor P2 and the drain of the MOS transistor N2, and serves as an output end to output a Din signal to an output drive module;

[0011] The source of the MOS transistor N1 is electrically connected to the drain of the MOS transistor N0, and the source of the MOS transistor N0 and the source of the MOS transistor N2 are both grounded;

[0012] And the following conditions are met:

[0013] The driving capability of the MOS tube N2 is greater than the driving capability of the MOS tube P2;

[0014] The driving capability of the MOS transistors P1 and P0 is greater than the driving capability of the MOS transistors N1 and N0;

[0015] The driving capability of the MOS transistor N2 is greater than the driving capabilities of the MOS transistors P1 and P0.

[0016] Furthermore, the following conditions are met:

[0017]

[0018] Among them, (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) P2 is the width-to-length ratio of MOS tube P2; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

[0019] Furthermore, the following conditions are met:

[0020]

[0021] Among them, (W / L)N0 is the width-to-length ratio of MOS tube N0; (W / L) P0 is the width-to-length ratio of MOS tube P0; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

[0022] Furthermore, the following conditions are met:

[0023]

[0024] Among them, (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) P0 is the width-to-length ratio of MOS tube P0; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

[0025] Furthermore, the latch module further includes a MOS transistor P4 and a MOS transistor N6;

[0026] The drain, source and substrate of the MOS transistor P4 are all electrically connected to the external power supply VDD, and the gate of the MOS transistor P4 is electrically connected to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2 and the gate of the MOS transistor N2;

[0027] The drain, source and substrate of the MOS transistor N6 are all grounded, and the gate of the MOS transistor N6 is electrically connected to the gate of the MOS transistor P0, the gate of the MOS transistor N0, the drain of the MOS transistor P2 and the drain of the MOS transistor N2.

[0028] Further, the output driving module includes an inverter 203, an inverter 204, an inverter 205, a NAND gate 400, a NOR gate 500, a transmission gate 301, a MOS transistor P3, a MOS transistor N3, a MOS transistor N4, a MOS transistor N5, and a resistor R0 and a resistor R1;

[0029] The source of the MOS tube P3 is electrically connected to the external power supply VDD;

[0030] The gate of the MOS transistor P0 is electrically connected to the input end of the inverter 203, the output end of the inverter 203 is electrically connected to the input end of the inverter 204 and the input end of the transmission gate 301, and the output end of the inverter 204 is electrically connected to the first input end of the NOR gate 500 and the first input end of the NAND gate 400;

[0031] The input module outputs an enable signal to the input end of the inverter 205, the second input end of the NOR gate 500, the PMOS control end of the transmission gate 301 and the gate of the MOS tube N5; the output end of the inverter 205 is electrically connected to the NMOS control end of the transmission gate 301 and the second input end of the NAND gate 400; the output end of the transmission gate 301 is electrically connected to the drain of the MOS tube N5 and the gate of the MOS tube N4;

[0032] The output end of the NAND gate 400 is electrically connected to the gate of the MOS transistor P3, the drain of the MOS transistor P3 is electrically connected to one end of the resistor R0 and one end of the resistor R1, and outputs the Q signal as an output end; the output end of the NOR gate 500 is electrically connected to the gate of the MOS transistor N3, the drain of the MOS transistor N3 is electrically connected to the other end of the resistor R0; the drain of the MOS transistor N4 is electrically connected to the other end of the resistor R1;

[0033] The source of the MOS transistor N3 , the source of the MOS transistor N4 and the source of the MOS transistor N5 are all grounded.

[0034] Furthermore, the output driving module further includes an inverter 206;

[0035] The output end of the inverter 203 is electrically connected to the input end of the inverter 206 , and the output end of the inverter 206 is electrically connected to the input end of the inverter 204 and the input end of the transmission gate 301 .

[0036] Further, the input module includes a Schmitt trigger 100, a Schmitt trigger 101, a Schmitt trigger 102, an inverter 200, an inverter 201, an inverter 202 and a transmission gate 300;

[0037] The input end of the Schmitt trigger 100 is electrically connected to the outside as an enable end, the output end of the Schmitt trigger 100 is electrically connected to the input end of the inverter 200, and the output end of the inverter 200 outputs an enable signal to the output drive module;

[0038] The input end of the Schmitt trigger 101 is electrically connected to the outside as a latch control end, the output end of the Schmitt trigger 101 is electrically connected to the input end of the inverter 201 and the input end of the inverter 202, the output end of the inverter 201 is electrically connected to the NMOS control end of the transmission gate 300 and the gate of the MOS transistor P1; the output end of the inverter 202 is electrically connected to the PMOS control end of the transmission gate 300 and the gate of the MOS transistor N1;

[0039] The input end of the Schmitt trigger 102 is electrically connected to the outside as a data input end, the output end of the Schmitt trigger 102 is electrically connected to the input end of the transmission gate 300, and the output end of the transmission gate 300 is electrically connected to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2, and the gate of the MOS transistor N2.

[0040] Further, the MOS tube P0, MOS tube P1, MOS tube P2, MOS tube P3 and MOS tube P4 are all SLOW PMOS tubes; the MOS tube N0, MOS tube N1, MOS tube N2, MOS tube N3, MOS tube N4, MOS tube N5 and MOS tube N6 are all FAST NMOS tubes.

[0041] After adopting the above technical solution, the present invention has the following advantages compared with the background technology:

[0042] Since the driving capability of MOS tube N2 is stronger than that of P2, at the moment of power-on, the Din voltage is clamped at a low level by MOS tube N2; since the driving capabilities of MOS tubes P1 and MOS tubes P0 are stronger than those of MOS tubes N1 and MOS tubes N0, The signal is clamped at a high level by MOS tubes P1 and P0, which ultimately fixes Q0 at a low level at the moment of power-on to avoid an unstable state, thereby preventing the external device from being mistakenly triggered and started by the logic latch chip when the MCU is not initialized, causing system abnormalities. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A first circuit diagram of the logic latch circuit with a fixed power-on output level according to the present invention;

[0044] Figure 2 A second circuit diagram of the logic latch circuit with a fixed power-on output level according to the present invention;

[0045] Figure 3 The output Q simulation result of the first circuit diagram of the logic latch circuit with a fixed level of output when powered on according to the present invention;

[0046] Figure 4The output Q simulation result of the second circuit diagram of the logic latch circuit with a fixed power-on output level according to the present invention;

[0047] Figure 5 A third circuit diagram of the logic latch circuit with a fixed power-on output level according to the present invention;

[0048] Figure 6 The present invention is a schematic circuit diagram of a multi-channel logic latch chip with input enable and output enable control terminals of the logic latch circuit with a fixed power-on output level.

[0049] Description of reference numerals:

[0050] 1000, input module; 1001, latch module; 1002, output drive module. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0052] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0053] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0054] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Example

[0055] Please refer to Figure 1-6 As shown, this embodiment provides a logic latch circuit with a fixed output level when powered on, including an input module 1000, a latch module 1001 and an output driver module 1002. Figure 1 As shown, specifically, the latch module 1001 includes a MOS transistor P0, a MOS transistor P1, a MOS transistor P2, a MOS transistor N0, a MOS transistor N1 and a MOS transistor N2.

[0056] The input module 1000 outputs an enable signal to the output driver module 1002, the input module 1000 outputs a latch control signal to the gates of the MOS transistor P1 and the MOS transistor N1, and the input module 1000 outputs a data input signal to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2, and the gate of the MOS transistor N2. The source of the MOS transistor P0, the source of the MOS transistor P2, and the power input terminal of the output driver module 1002 are electrically connected to the external power supply VDD. The drain of the MOS transistor P0 is electrically connected to the source of the MOS transistor P1, the gate of the MOS transistor P0 is electrically connected to the gate of the MOS transistor N0, the drain of the MOS transistor P2, and the drain of the MOS transistor N2, and outputs the Din signal to the output driver module 1002 as an output terminal. The source of the MOS transistor N1 is electrically connected to the drain of the MOS transistor N0, and the source of the MOS transistor N0 and the source of the MOS transistor N2 are both grounded.

[0057] Specifically, the input module 1000 includes a Schmitt trigger 100, a Schmitt trigger 101, a Schmitt trigger 102, an inverter 200, an inverter 201, an inverter 202 and a transmission gate 300;

[0058] The input terminal of the Schmitt trigger 100 is electrically connected to the outside as an enable terminal, the output terminal of the Schmitt trigger 100 is electrically connected to the input terminal of the inverter 200 , and the output terminal of the inverter 200 outputs an enable signal to the output driving module 1002 .

[0059] The input end of the Schmitt trigger 101 is electrically connected to the outside as a latch control end, the output end of the Schmitt trigger 101 is electrically connected to the input end of the inverter 201 and the input end of the inverter 202, the output end of the inverter 201 is electrically connected to the NMOS control end of the transmission gate 300 and the gate of the MOS tube P1; the output end of the inverter 202 is electrically connected to the PMOS control end of the transmission gate 300 and the gate of the MOS tube N1.

[0060] The input end of the Schmitt trigger 102 is electrically connected to the outside as a data input end, the output end of the Schmitt trigger 102 is electrically connected to the input end of the transmission gate 300, and the output end of the transmission gate 300 is electrically connected to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2, and the gate of the MOS transistor N2.

[0061] Specifically, the output driving module 1002 includes an inverter 203, an inverter 204, an inverter 205, a NAND gate 400, a NOR gate 500, a transmission gate 301, a MOS transistor P3, a MOS transistor N3, a MOS transistor N4, a MOS transistor N5, and resistors R0 and R1.

[0062] The source of the MOS transistor P3 is electrically connected to the external power supply VDD. The gate of the MOS transistor P0 is electrically connected to the input end of the inverter 203, the output end of the inverter 203 is electrically connected to the input end of the inverter 204 and the input end of the transmission gate 301, and the output end of the inverter 204 is electrically connected to the first input end of the NOR gate 500 and the first input end of the NAND gate 400.

[0063] The input module 1000 outputs an enable signal to the input end of the inverter 205, the second input end of the NOR gate 500, the PMOS control end of the transmission gate 301, and the gate of the MOS tube N5; that is, the output end of the inverter 200 is electrically connected to the input end of the inverter 205, the second input end of the NOR gate 500, the PMOS control end of the transmission gate 301, and the gate of the MOS tube N5. The output end of the inverter 205 is electrically connected to the NMOS control end of the transmission gate 301 and the second input end of the NAND gate 400; the output end of the transmission gate 301 is electrically connected to the drain of the MOS tube N5 and the gate of the MOS tube N4.

[0064] The output end of the NAND gate 400 is electrically connected to the gate of the MOS transistor P3, the drain of the MOS transistor P3 is electrically connected to one end of the resistor R0 and one end of the resistor R1, and outputs the Q signal as the output end; the output end of the NOR gate 500 is electrically connected to the gate of the MOS transistor N3, the drain of the MOS transistor N3 is electrically connected to the other end of the resistor R0; the drain of the MOS transistor N4 is electrically connected to the other end of the resistor R1. The source of the MOS transistor N3, the source of the MOS transistor N4 and the source of the MOS transistor N5 are all grounded.

[0065] Please refer to Figure 6 As shown in Table 1 below, Figure 6 This is a circuit diagram of a multi-channel logic latch chip with input enable and output enable control terminals.

[0066] Table 1:

[0067]

[0068] Among them, Table 1 is the truth table of the logic latch chip with input enable and output enable control terminals.

[0069] From Table 1, we can see that when When both LE and LE are low (L), the output remains in the previous state Q0 and does not change with the input signal D.

[0070] Please refer to the attached Figure 1 When VDD is high and LE is low, the transmission gate 300 is closed, and the D signal cannot enter the latch module 1001. At this time, the input and output of the two-stage inverter composed of MOS tube P0, MOS tube P1, MOS tube P2, MOS tube N0, MOS tube N1 and MOS tube N2 are connected head to tail, and the latch module 1001 latches Din and Signal;

[0071] when When the Din signal is at a low level, the Din signal controls the on / off of the MOS tube P3 through the inverter 203, the inverter 204 and the NAND gate 400, and the Din controls the on / off of the MOS tube N3 through the inverter 203, the inverter 204 and the NOR gate 500; when the Din signal is at a high level, the MOS tube P3 is turned on and the MOS tube N3 is turned off, and the output Q is at a high level; when the Din signal is at a low level, the MOS tube P3 is turned off and the MOS tube N3 is turned on, and the output Q is at a low level, that is, the output Q is in the same direction as the Din signal (Q=Din);

[0072] when When it is high level, The MOS tube P3 is turned off through the Schmitt trigger 100, the inverter 200, the reverse 205 and the NAND gate 400; The MOS tube N3 is turned off through the Schmitt trigger 100, the inverter 200, and the NOR gate 500; The transmission gate 301 is closed through the Schmitt trigger 100 and the inverter 200. When the MOS tube N5 is turned on, the MOS tube N4 is turned off; since the MOS tube P3, the MOS tube N3 and the MOS tube N4 are all turned off, the output Q is in a high impedance state;

[0073] when When switching from high level to low level, The MOS tube N5 is turned off through the Schmitt trigger 100 and the inverter 200. If the Din signal is at a low level, the Din signal controls the MOS tube N4 to be turned on through the inverter 203 and the transmission gate 301, so that the output Q is quickly pulled down to a low level.

[0074] However, at the moment of VDD power-on, if and LE are both low level, Din signal and The signal cannot be determined to be high or low, that is, it is in an uncertain state (Din may be high or low, but It may be a low level or a high level), then Q is also in an indeterminate state (Q0 is an indeterminate state).

[0075] Furthermore, the following conditions are met:

[0076] The driving capability of MOS tube N2 is greater than that of MOS tube P2;

[0077] The driving capability of MOS tube P1 and MOS tube P0 is greater than the driving capability of MOS tube N1 and MOS tube N0;

[0078] The driving capability of the MOS tube N2 is greater than that of the MOS tube P1 and the MOS tube P0, wherein the driving capability is proportional to the drain current of the MOS tube, that is, the larger the drain current of the MOS tube, the stronger the driving capability.

[0079] Control MOS tube P0, MOS tube P1, MOS tube P2, MOS tube N0, MOS tube N1 and MOS tube N2 to meet the above conditions.

[0080] Among them, MOS tube N2 and MOS tube P2 form an inverter. Assume that Din signal and The signal level is V DD / 2,V SG.P2 is the source-gate voltage of MOS tube P2, V GS.N2 is the gate-source voltage of MOS tube N2, which is equal to V DD / 2, at this time,

[0081] The saturation region drain current of MOS tube P2 is:

[0082] ;

[0083] The saturation drain current of MOS tube N2 is:

[0084] ;

[0085] Since the driving capability of MOS tube N2 is greater than that of MOS tube P2, I N2 >I P2 ,Right now

[0086] ;

[0087] Then the following conditions are satisfied:

[0088] ;

[0089] Among them, (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) P2 is the width-to-length ratio of MOS tube P2; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; VDD is the input voltage.

[0090] Since the driving capability of MOS tubes P1 and P0 is greater than that of MOS tubes N1 and N0, let (W / L) N1 = (W / L) P1 , MOS tube P1 and MOS tube N1 are both in the on state and work in the deep linear region, ignoring the influence of MOS tube N1 and MOS tube P1, where (W / L) N1 is the width-to-length ratio of MOS tube N1; (W / L) P1 is the width-to-length ratio of the MOS tube P1. Then the saturation region drain current of the MOS tube P0 is:

[0091] ;

[0092] The saturation drain current of MOS tube N0 is:

[0093] ;

[0094] Since the driving capability of MOS tubes P1 and P0 is greater than that of MOS tubes N1 and N0, I P0 >I N0 ,Right now

[0095] ;

[0096] Then the following conditions are satisfied:

[0097] ;

[0098] Among them, (W / L) N0 is the width-to-length ratio of MOS tube N0; (W / L) P0 is the width-to-length ratio of MOS tube P0; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

[0099] Since the driving capability of MOS tube N2 is greater than that of MOS tube P1 and MOS tube P0, assuming that MOS tube P1 is in the on state and works in the deep linear region, the influence of MOS tube P1 is ignored. Then the following conditional formula is satisfied:

[0100] ;

[0101] Among them, (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L)P0 is the width-to-length ratio of MOS tube P0; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

[0102] According to different processes, the PMOS hole mobility μ p and NMOS electron mobility μ n , under the conditions of equal PMOS source gate voltage (VSG) and NMOS gate source voltage (VGS). Since the driving capability of MOS tube N2 is stronger than that of P2, at the moment of power-on, the Din voltage is clamped at a low level by MOS tube N2; since the driving capability of MOS tube P1 and MOS tube P0 is stronger than that of MOS tube N1 and MOS tube N0, The signal is clamped at a high level by MOS tubes P1 and P0, which ultimately fixes Q0 at a low level at the moment of power-on to avoid an unstable state, thereby preventing the external device from being mistakenly triggered and started by the logic latch chip when the MCU is not initialized, causing system abnormalities.

[0103] Please refer to the attached Figure 2 Furthermore, the latch module also includes a MOS tube P4 and a MOS tube N6.

[0104] The drain, source and substrate of the MOS transistor P4 are electrically connected to the external power supply VDD, and the gate of the MOS transistor P4 is electrically connected to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2 and the gate of the MOS transistor N2.

[0105] The drain, source and substrate of MOS transistor N6 are all grounded, and the gate of MOS transistor N6 is electrically connected to the gate of MOS transistor P0, the gate of MOS transistor N0, the drain of MOS transistor P2 and the drain of MOS transistor N2. MOS transistor P4 and MOS transistor N6 act as capacitors, and similarly, capacitor CAP can be used directly.

[0106] At the moment when VDD is powered on, the voltage difference between the source, drain and gate of MOS tube P4 (as MOS capacitor) does not change suddenly. The signal will be pulled to VDD instantly; at the same time, since the voltage difference between the source, drain and gate of MOS tube N6 (as MOS capacitor) does not change suddenly, the Din signal voltage will remain at a low level. At this time, the input and output of the two-stage inverter composed of MOS tube P0, MOS tube P1, MOS tube P2, MOS tube N0, MOS tube N1 and MOS tube N2 are connected head to tail, and the latch module 1001 latches the Din signal and Signal, that is The signal is high and the Din signal is low; It is at a low level, so Q=Din remains at a low level (that is, Q0 remains at a low level) to avoid an unstable state, thereby avoiding the situation where the external device is mistakenly triggered to start by the logic latch chip when the MCU is not initialized, causing system abnormalities.

[0107] Please refer to the attached Figure 3 and attached Figure 4 , including Figure 3 For attachment Figure 1 Schematic diagram of simulation results of output Q when the circuit does not limit the driving capability of the MOS tube; Figure 4 For attachment Figure 2 The simulation structure diagram of the circuit output Q. Figure 3 and attached Figure 4 The simulation conditions are -40℃, 25℃, 85℃, 1.65V, 3.6V, rising edge 10ns, TT, FS, SF, SS, FF coners. TT, FS, SF, SS, FF coners are different process corners. Specifically, F stands for FAST, S stands for SLOW, and T stands for TYPICAL.

[0108] By the attached Figure 3 It can be seen that the basic circuit has an abnormality in the SF corner, and Q outputs a high level. Figure 4 It can be seen that adding MOS tube P4 and MOS tube N6 makes all corners output Q=L, which solves the problem of unstable output.

[0109] Please refer to the attached Figure 5 The output driving module further includes an inverter 206; the output end of the inverter 203 is electrically connected to the input end of the inverter 206, and the output end of the inverter 206 is electrically connected to the input end of the inverter 204 and the input end of the transmission gate 301.

[0110] If Q0 needs to output a high level at the power-on moment, a first-stage inverter 206 is inserted between the output end of the inverter 203 and the input end of the inverter 204 and the input end of the transmission gate 301, so that Q0 outputs a high level at the power-on moment.

[0111] In this embodiment, MOS transistors P0, P1, P2, P3 and P4 are all SLOW PMOS transistors; MOS transistors N0, N1, N2, N3, N4, N5 and N6 are all FAST NMOS transistors.

[0112] In the process of semiconductor manufacturing, the process corners of conventional NMOS and PMOS are selected according to TYPICAL mode. By adjusting the driving capabilities of NMOS and PMOS, NMOS devices are specifically selected to be processed according to FAST mode, that is, MOS tubes N0, MOS tubes N1, MOS tubes N2, MOS tubes N3, MOS tubes N4, MOS tubes N5 and MOS tubes N6 are all processed according to FAST mode; PMOS is processed according to SLOW mode, that is, MOS tubes P0, MOS tubes P1, MOS tubes P2, MOS tubes P3 and MOS tubes P4 are all processed according to SLOW mode. The thresholds of MOS tubes N0, MOS tubes N1 and MOS tubes N2 are reduced, and the driving capabilities are stronger. At the same time, the thresholds of MOS tubes P2, MOS tubes P1 and MOS tubes P0 are increased, and the driving capabilities are weakened, and the output Q0 is further fixed at a low level at the moment of power-on to avoid the occurrence of unstable states.

[0113] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A logic latch circuit with a fixed output level when powered on, characterized in that: It includes an input module, a latch module and an output drive module; The latch module includes MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor N0, MOS transistor N1 and MOS transistor N2; The input module outputs an enable signal to the output drive module, the input module outputs a latch control signal to the gates of the MOS transistor P1 and the MOS transistor N1, and the input module outputs a data input signal to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2, and the gate of the MOS transistor N2; The source of the MOS transistor P0, the source of the MOS transistor P2 and the power input terminal of the output driving module are electrically connected to the external power supply VDD; The drain of the MOS transistor P0 is electrically connected to the source of the MOS transistor P1, the gate of the MOS transistor P0 is electrically connected to the gate of the MOS transistor N0, the drain of the MOS transistor P2 and the drain of the MOS transistor N2, and serves as an output end to output a Din signal to an output drive module; The source of the MOS transistor N1 is electrically connected to the drain of the MOS transistor N0, and the source of the MOS transistor N0 and the source of the MOS transistor N2 are both grounded; And the following conditions are met: The driving capability of the MOS tube N2 is greater than the driving capability of the MOS tube P2; The driving capability of the MOS transistors P1 and P0 is greater than the driving capability of the MOS transistors N1 and N0; The driving capability of the MOS tube N2 is greater than the driving capabilities of the MOS tube P1 and the MOS tube P0; The output driving module includes an inverter 203, an inverter 204, an inverter 205, a NAND gate 400, a NOR gate 500, a transmission gate 301, a MOS transistor P3, a MOS transistor N3, a MOS transistor N4, a MOS transistor N5, and a resistor R0 and a resistor R1; The source of the MOS tube P3 is electrically connected to the external power supply VDD; The gate of the MOS transistor P0 is electrically connected to the input end of the inverter 203, the output end of the inverter 203 is electrically connected to the input end of the inverter 204 and the input end of the transmission gate 301, and the output end of the inverter 204 is electrically connected to the first input end of the NOR gate 500 and the first input end of the NAND gate 400; The input module outputs an enable signal to the input end of the inverter 205, the second input end of the NOR gate 500, the PMOS control end of the transmission gate 301 and the gate of the MOS tube N5; the output end of the inverter 205 is electrically connected to the NMOS control end of the transmission gate 301 and the second input end of the NAND gate 400; the output end of the transmission gate 301 is electrically connected to the drain of the MOS tube N5 and the gate of the MOS tube N4; The output end of the NAND gate 400 is electrically connected to the gate of the MOS transistor P3, the drain of the MOS transistor P3 is electrically connected to one end of the resistor R0 and one end of the resistor R1, and outputs the Q signal as an output end; the output end of the NOR gate 500 is electrically connected to the gate of the MOS transistor N3, the drain of the MOS transistor N3 is electrically connected to the other end of the resistor R0; the drain of the MOS transistor N4 is electrically connected to the other end of the resistor R1; The source of the MOS transistor N3 , the source of the MOS transistor N4 and the source of the MOS transistor N5 are all grounded.

2. The logic latch circuit with a fixed power-on output level according to claim 1, characterized in that: The following conditions are met: Among them, (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) P2 is the width-to-length ratio of MOS tube P2; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

3. The logic latch circuit with a fixed output level upon power-on according to claim 1, characterized in that: The following conditions are met: Among them, (W / L) N0 is the width-to-length ratio of MOS tube N0; (W / L) P0 is the width-to-length ratio of MOS tube P0; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

4. The logic latch circuit with a fixed output level upon power-on according to claim 1, characterized in that: The following conditions are met: Among them, (W / L) N2 is the width-to-length ratio of MOS tube N2; (W / L) P0 is the width-to-length ratio of MOS tube P0; μ p is the hole mobility of the PMOS tube; μ n is the electron mobility of the NMOS tube; V thp is the threshold voltage of the PMOS tube; V thn is the threshold voltage of the NMOS tube; V DD is the input voltage.

5. The logic latch circuit with a fixed output level upon power-on according to claim 1, characterized in that: The latch module also includes a MOS transistor P4 and a MOS transistor N6; The drain, source and substrate of the MOS transistor P4 are all electrically connected to the external power supply VDD, and the gate of the MOS transistor P4 is electrically connected to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2 and the gate of the MOS transistor N2; The drain, source and substrate of the MOS transistor N6 are all grounded, and the gate of the MOS transistor N6 is electrically connected to the gate of the MOS transistor P0, the gate of the MOS transistor N0, the drain of the MOS transistor P2 and the drain of the MOS transistor N2.

6. The logic latch circuit with a fixed output level upon power-on according to claim 1, characterized in that: The output driving module further includes an inverter 206; The output end of the inverter 203 is electrically connected to the input end of the inverter 206 , and the output end of the inverter 206 is electrically connected to the input end of the inverter 204 and the input end of the transmission gate 301 .

7. The logic latch circuit with a fixed output level upon power-on according to claim 1, characterized in that: The input module includes a Schmitt trigger 100, a Schmitt trigger 101, a Schmitt trigger 102, an inverter 200, an inverter 201, an inverter 202 and a transmission gate 300; The input end of the Schmitt trigger 100 is electrically connected to the outside as an enable end, the output end of the Schmitt trigger 100 is electrically connected to the input end of the inverter 200, and the output end of the inverter 200 outputs an enable signal to the output drive module; The input end of the Schmitt trigger 101 is electrically connected to the outside as a latch control end, the output end of the Schmitt trigger 101 is electrically connected to the input end of the inverter 201 and the input end of the inverter 202, the output end of the inverter 201 is electrically connected to the NMOS control end of the transmission gate 300 and the gate of the MOS transistor P1; the output end of the inverter 202 is electrically connected to the PMOS control end of the transmission gate 300 and the gate of the MOS transistor N1; The input end of the Schmitt trigger 102 is electrically connected to the outside as a data input end, the output end of the Schmitt trigger 102 is electrically connected to the input end of the transmission gate 300, and the output end of the transmission gate 300 is electrically connected to the drain of the MOS transistor P1, the drain of the MOS transistor N1, the gate of the MOS transistor P2, and the gate of the MOS transistor N2.

8. The logic latch circuit with a fixed output level upon power-on according to claim 1, characterized in that: The MOS tubes P0, P1, P2, P3 and P4 are all SLOW PMOS tubes; the MOS tubes N0, N1, N2, N3, N4, N5 and N6 are all FAST NMOS tubes.

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