A Sigma-Delta modulator with adjustable range

Abstract

The present invention relates to the field of Sigma-Delta modulators, and in particular to a range-adjustable Sigma-Delta modulator, comprising a 2byte-EEPROM module, three 5bit-DAC modules, a signal sampling and feedback module, an integral amplifier module, a two-phase non-overlapping and chopping clock module, and a quantization module; the output end of the 2byte-EEPROM module is electrically connected to the input end of the 5bit-DAC module, and the output ends of the three 5bit-DAC modules respectively output voltages V A , voltage V B and voltage V C To the input end of the signal sampling and feedback module, the signal is written through an external digital module to control the internal 5-bit DAC module, so that the range of the modulator can be changed as needed. There is no need to replace the hardware when the signal amplitude changes, which meets the measurement requirements of signals with different amplitudes and helps reduce costs.

Description

Technical Field

[0001] The invention relates to the field of Sigma-Delta modulators, in particular to a range-adjustable Sigma-Delta modulator. Background Art

[0002] The analog-to-digital converter in the sensor interface circuit is a key component to ensure the accuracy of the system. It is mainly divided into Nyquist type and Sigma-Delta type. Among them, the Sigma-Delta modulator is an advanced analog-to-digital converter design that cleverly combines oversampling technology and noise shaping strategies to achieve a perfect combination of high precision and low power consumption. This modulator continuously compares the difference between the input analog signal and the internal feedback signal, accumulates these differences using an integrator, and then converts the accumulated results into digital form through a simple 1-bit quantizer. In this process, the noise generated by quantization is cleverly shaped to a high frequency band, so that most of the noise can be easily filtered out by a low-pass filter, thereby significantly improving the accuracy of the conversion. Due to its unique advantages, the Sigma-Delta modulator has been widely used in many fields such as audio, sensor data processing, and wireless communications. It not only provides high-fidelity signal conversion, but also has strong anti-interference capabilities to ensure stable operation in various complex environments.

[0003] However, when used in low-frequency sensor interface circuits and the signal amplitude needs to be changed, the Sigma-Delta modulator usually needs to be replaced according to different signal amplitudes. The Sigma-Delta modulator has poor adaptability and high cost. Summary of the invention

[0004] The purpose of the present invention is to provide a range-adjustable Sigma-Delta modulator, which aims to improve the problem that when it is used in a low-frequency sensor interface circuit and the signal amplitude needs to be changed, the Sigma-Delta modulator usually needs to be replaced according to different signal amplitudes, and the Sigma-Delta modulator has poor adaptability and high cost.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A range-adjustable Sigma-Delta modulator includes a 2byte-EEPROM module, three 5bit-DAC modules, a signal sampling and feedback module, an integral amplifier module, a two-phase non-overlapping and chopping clock module, and a quantization module;

[0007] The input end of the 2byte-EEPROM module is electrically connected to the external digital module, the output end of the 2byte-EEPROM module is electrically connected to the input end of the 5bit-DAC module, and the output ends of the three 5bit-DAC modules respectively output voltages V A , voltage V B and voltage V C to the input end of the signal sampling and feedback module, the output end of the signal sampling and feedback module is electrically connected to the input end of the integral amplifier module, and the output end of the integral amplifier module is electrically connected to the input end of the quantization module,

[0008] The external clock signal is input to the input end of the two-phase non-overlapping and chopping clock module, and the two-phase non-overlapping and chopping clock module outputs non-overlapping S1 clock signals and S2 clock signals to the signal sampling and feedback module, and outputs CLK chop Chopping the switching clock signal and Chop the switching clock signal to the integrating amplifier block.

[0009] Furthermore, the 2-byte-EEPROM module includes two word lines SG<0:1> and eight bit lines BL<0:7>. The storage capacity of the 2-byte-EEPROM module is 16 bits, wherein each bit is connected by a MOS tube N S And MOS tube N FG The MOS tube N S For the gate tube N S , the MOS tube N FG For storage tube N FG .

[0010] Further, the 2byte-EEPROM module further includes a data reading unit, and the data reading unit includes MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor N1, MOS transistor N2, MOS transistor N3, MOS transistor N4 and MOS transistor N5;

[0011] The source of the MOS tube P1, the source of the MOS tube P2, the source of the MOS tube P3, the source of the MOS tube N S The gate and the source of the MOS tube N5 are electrically connected to the external power supply VDD1;

[0012] The MOS tube N S The drain of the MOS tube is electrically connected to the BL port, the drain of the MOS tube N2, the gate of the MOS tube P2 and the gate of the MOS tube N3; the MOS tube N S The source of MOS tube N FG The drain of the MOS tube N is electrically connected; FGThe gate of the MOS tube N5 is electrically connected to the drain of the MOS tube N5. FG The source of the MOS transistor P1 is electrically connected to the drain of the MOS transistor P1 and the drain of the MOS transistor N1; the gate of the MOS transistor P1 is electrically connected to the RST port, the gate of the MOS transistor N1 and the gate of the MOS transistor N2;

[0013] The drain of the MOS transistor P2 is electrically connected to the drain of the MOS transistor N3, the gate of the MOS transistor P3 and the gate of the MOS transistor N4; the drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N4 and serves as an output terminal to output V out ;

[0014] The source of the MOS transistor N1 , the source of the MOS transistor N2 , the source of the MOS transistor N3 and the source of the MOS transistor N4 are all grounded.

[0015] Further, the 5-bit-DAC module includes port D0, port D1, port D2, port D3, port D4, MOS tube P4, MOS tube P5, MOS tube P6, MOS tube P7, MOS tube P8, MOS tube P9, MOS tube N6, MOS tube N7, MOS tube N8, MOS tube N9, MOS tube N10 and resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10;

[0016] The source of the MOS transistor P4, the source of the MOS transistor P5, the source of the MOS transistor P6, the source of the MOS transistor P7, the source of the MOS transistor P8 and the source of the MOS transistor P9 are all electrically connected to the external power supply VDD1;

[0017] The drain of the MOS transistor P4 is electrically connected to one end of the resistor R1; the port D0 is electrically connected to the gate of the MOS transistor P5 and the gate of the MOS transistor N6; the drain of the MOS transistor P5 is electrically connected to the drain of the MOS transistor N6 and one end of the resistor R2; the other end of the resistor R2 is electrically connected to the other end of the resistor R1 and one end of the resistor R7;

[0018] The port D1 is electrically connected to the gate of the MOS transistor P6 and the gate of the MOS transistor N7, the drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor N7 and one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the other end of the resistor R7 and one end of the resistor R8;

[0019] The port D2 is electrically connected to the gate of the MOS transistor P7 and the gate of the MOS transistor N8, the drain of the MOS transistor P7 is electrically connected to the drain of the MOS transistor N8 and one end of the resistor R4, and the other end of the resistor R4 is electrically connected to the other end of the resistor R8 and one end of the resistor R9;

[0020] The port D3 is electrically connected to the gate of the MOS transistor P8 and the gate of the MOS transistor N9, the drain of the MOS transistor P8 is electrically connected to the drain of the MOS transistor N9 and one end of the resistor R5, and the other end of the resistor R5 is electrically connected to the other end of the resistor R9 and one end of the resistor R10;

[0021] The port D4 is electrically connected to the gate of the MOS transistor P9 and the gate of the MOS transistor N10, the drain of the MOS transistor P9 is electrically connected to the drain of the MOS transistor N10 and one end of the resistor R6, the other end of the resistor R6 is electrically connected to the other end of the resistor R10, and is electrically connected to the input end of the signal sampling and feedback module as an output end;

[0022] Port D0, port D1, port D2, port D3 and port D4 of the three 5-bit-DAC modules are electrically connected to the first to fifteenth output terminals of the 2-byte-EEPROM module respectively; the gate of the MOS tube P4, the source of the MOS tube N6, the source of the MOS tube N7, the source of the MOS tube N8, the source of the MOS tube N9 and the source of the MOS tube N10 are all grounded.

[0023] Furthermore, the signal sampling and feedback module includes V IN Port, Clock Switch 1S1, Clock Switch 2S1, Clock Switch 3S1, Clock Switch 4S1, Clock Switch 5S1, Clock Switch 6S1, Clock Switch 7S1, Clock Switch 8S1, Clock Switch 1S2, Clock Switch 2S2, Clock Switch 3S2, Clock Switch 4S2, Switch 1V out S2, switch 2V out S2, switch 1 S2, switch 2 S2 and sampling capacitor 1C S1 , sampling capacitor 2C S1 , sampling capacitor 1C S2 , sampling capacitor 2C S2 ;

[0024] The 5-bit-DAC module outputs a voltage V A to one end of the clock switch 2S2, one end of the clock switch 3S1 and one end of the clock switch 3S2; the 5-bit-DAC module outputs a voltage V B To one end of the clock switch 1S2 and one end of the clock switch 4S2; the 5-bit-DAC module outputs a voltage V C to one end of the clock switch 4S1, one end of the clock switch 5S1, one end of the clock switch 6S1, one end of the clock switch 7S1 and one end of the clock switch 8S1; the V INThe port is electrically connected to one end of the clock switch 2S1;

[0025] One end of the clock switch 1S1 is connected to the other end of the clock switch 1S2 and the sampling capacitor 1C S2 One end of the sampling capacitor is electrically connected to S2 The other end of the switch 1 One end of S2, switch 1V out One end of S2 is electrically connected to the other end of the clock switch 5S1, and the other end of the clock switch 1S1 is grounded;

[0026] The other end of the clock switch 2S1 is connected to the other end of the clock switch 2S2 and the sampling capacitor 1C S1 One end of the sampling capacitor is electrically connected to S1 The other end of the switch 2 One end of S2, switch 1V out The other end of S2 is electrically connected to the other end of the clock switch 7S1 and is electrically connected to the first input end of the integrating amplifier module as a first output end;

[0027] The other end of the clock switch 3S1 and the other end of the clock switch 3S2 are connected to the sampling capacitor 2C S1 One end of the sampling capacitor is electrically connected to S1 The other end of the switch 1 The other end of S2, switch 2V out One end of S2 is electrically connected to the other end of the clock switch 8S1 and is electrically connected to the second input end of the integrating amplifier module as a second output end;

[0028] The other end of the clock switch 4S1 and the other end of the clock switch 4S2 are connected to the sampling capacitor 2C S2 One end of the sampling capacitor is electrically connected to S2 The other end of the switch 2 The other end of S2, switch 2V out The other end of S2 is electrically connected to the other end of the clock switch 6S1.

[0029] Furthermore, the integrating amplifier module includes a first chopper switch, a rail-to-rail fully differential folded common source and common gate amplifier U3, a second chopper switch and an integrating capacitor 1C I 、Integral capacitor 2C I ;

[0030] The first input terminal and the second input terminal of the first chopper switch are electrically connected to the first output terminal and the second output terminal of the signal sampling and feedback module, respectively; the first output terminal and the second output terminal of the first chopper switch are electrically connected to the same-direction input terminal and the reverse input terminal of the rail-to-rail fully differential folded common-source amplifier U3, respectively; the same-direction output terminal and the reverse output terminal of the rail-to-rail fully differential folded common-source amplifier U3 are electrically connected to the first input terminal and the second input terminal of the second chopper switch, respectively; the first output terminal and the second output terminal of the second chopper switch are electrically connected to the first input terminal and the second input terminal of the quantization module, respectively;

[0031] The integrating capacitor 1C I The integral capacitor 2C is electrically connected between the first input terminal of the first chopper switch and the first output terminal of the second chopper switch; I The first chopper is electrically connected between the second input terminal of the first chopper switch and the second output terminal of the second chopper switch.

[0032] Further, the rail-to-rail fully differential folded cascode amplifier U3 includes a bias unit, a constant-transduction rail-to-rail folded cascode input unit and a Class-AB output unit;

[0033] The same-direction input terminal and the inverting input terminal of the constant-span rail-to-rail folded common-source common-gate input unit are electrically connected to the first output terminal and the second output terminal of the first chopper switch, respectively; the output terminal of the constant-span rail-to-rail folded common-source common-gate input unit is electrically connected to the input terminal of the Class-AB output unit; and the same-direction output terminal and the inverting output terminal of the Class-AB output unit are electrically connected to the first input terminal and the second input terminal of the second chopper switch, respectively;

[0034] The bias unit is electrically connected to an external bias module, and the external bias module outputs a bias current I bias1 To the bias unit, the bias unit outputs a first bias voltage V B1 , the fourth bias voltage V B4 , the sixth bias voltage V B6 and the eighth bias voltage V B8 To the Class-AB output unit; the bias unit outputs a second bias voltage V B2 , the third bias voltage V B3 , the fifth bias voltage V B5 and the sixth bias voltage V B6 To constant-span rail-to-rail folded cascode input cell.

[0035] Further, the signal sampling and feedback module includes a common mode feedback unit, and the common mode feedback unit includes a clock switch 9S1, a clock switch 10S1, a clock switch 11S1, a clock switch 12S1, a clock switch 13S1, a clock switch 5S2, a clock switch 6S2, a clock switch 7S2, a clock switch 8S2 and capacitors C1, C2, C3 and C4;

[0036] One end of the clock switch 9S1 and one end of the clock switch 12S1 are both electrically connected to the external power supply VDD1;

[0037] The other end of the clock switch 9S1 is electrically connected to one end of the capacitor C4 and one end of the clock switch 5S2, the other end of the clock switch 5S2 is electrically connected to one end of the clock switch 6S2 and the reverse output end of the Class-AB output unit, and the other end of the clock switch 6S2 is electrically connected to one end of the clock switch 11S1 and one end of the capacitor C1;

[0038] The other end of the clock switch 12S1 is electrically connected to one end of the capacitor C3 and one end of the clock switch 7S2, the other end of the clock switch 7S2 is electrically connected to one end of the clock switch 8S2 and the same-direction output end of the Class-AB output unit, and the other end of the clock switch 8S2 is electrically connected to one end of the clock switch 13S1 and one end of the capacitor C2;

[0039] The other end of the capacitor C4 is electrically connected to the other end of the capacitor C3, the other end of the capacitor C1, the other end of the capacitor C2 and one end of the clock switch 10S1, and is electrically connected to the feedback input end of the Class-AB output unit as a feedback output end. The bias unit outputs a sixth bias voltage V B6 To the other end of the clock switch 10S1;

[0040] The other end of the clock switch 11S1 and the other end of the clock switch 13S1 are both grounded.

[0041] Further, the quantization module includes a rail-to-rail current mirror comparator U4, a D flip-flop and a NAND gate logic unit;

[0042] The first output terminal and the second output terminal of the integrating amplifier module are electrically connected to the same-direction input terminal and the reverse input terminal of the rail-to-rail current mirror comparator U4, respectively. The output terminal of the rail-to-rail current mirror comparator U4 is electrically connected to the input terminal of the D flip-flop. The first output terminal and the second output terminal of the D flip-flop output V out and To the first input terminal and the second input terminal of the NAND gate logic unit; the NAND gate logic unit outputs V out S2 and S2 signal.

[0043] Further, the rail-to-rail current mirror comparator U4 includes MOS transistor P50, MOS transistor P51, MOS transistor P52, MOS transistor P53, MOS transistor P54, MOS transistor P55, MOS transistor P56, MOS transistor P57, MOS transistor P58, MOS transistor P59, MOS transistor P60, MOS transistor P61, MOS transistor N50, MOS transistor N51, MOS transistor N52, MOS transistor N53, MOS transistor N54, MOS transistor N55, MOS transistor N56, MOS transistor N57, MOS transistor N58, MOS transistor N59, MOS transistor N60, MOS transistor N61 and MOS transistor N62;

[0044] The source of the MOS transistor P50, the source of the MOS transistor P51, the source of the MOS transistor P52, the source of the MOS transistor P53, the source of the MOS transistor P54, the source of the MOS transistor P55, the source of the MOS transistor P58, the source of the MOS transistor P59 and the source of the MOS transistor N61 are all electrically connected to the external power supply VDD1;

[0045] The gate and drain of the MOS transistor P50 are electrically connected to the drain of the MOS transistor N51 and the gate of the MOS transistor P59, providing a bias voltage V for the gate of the MOS transistor P59. BPO The drain of the MOS tube P59 is electrically connected to the source of the MOS tube P60 and the source of the MOS tube P61; the drain of the MOS tube P60 is electrically connected to the gate of the MOS tube N55 and the gate and drain of the MOS tube N56;

[0046] External bias module output bias current I bias0 To the drain and gate of MOS tube N50, the gate of MOS tube N51 and the gate of MOS tube N54, providing a bias voltage V for the gate of MOS tube N54 BNO ;

[0047] The gate of the MOS transistor P51 is electrically connected to the gate and drain of the MOS transistor P52 and the drain of the MOS transistor N52; the drain of the MOS transistor P51 is electrically connected to the drain of the MOS transistor P61, the gate and drain of the MOS transistor N57 and the gate of the MOS transistor N58;

[0048] The gate of the MOS tube N52 is electrically connected to the gate of the MOS tube P60, and is electrically connected to the first output end of the integration amplifier module as a non-inverting input end; the source of the MOS tube N52 is electrically connected to the drain of the MOS tube N54 and the source of the MOS tube N53; the gate of the MOS tube N53 is electrically connected to the gate of the MOS tube P61, and is electrically connected to the second output end of the integration amplifier module as a reverse input end, and the drain of the MOS tube N53 is electrically connected to the gate and drain of the MOS tube P53, the gate of the MOS tube P54, and the drain of the MOS tube N55;

[0049] The drain of the MOS transistor P54 is electrically connected to the drain of the MOS transistor N58, the gate of the MOS transistor P55, the gate of the MOS transistor P56, the gate of the MOS transistor N59 and the gate of the MOS transistor N60; the drain of the MOS transistor P55 is electrically connected to the source of the MOS transistor P56 and the source of the MOS transistor P57; the drain of the MOS transistor P56 is electrically connected to the gate of the MOS transistor P57, the drain of the MOS transistor N59, the gate of the MOS transistor P58, the gate of the MOS transistor N61 and the gate of the MOS transistor N62; the source of the MOS transistor N59 is electrically connected to the drain of the MOS transistor N60 and the drain of the MOS transistor N61; the drain of the MOS transistor P58 is electrically connected to the drain of the MOS transistor N62, and is electrically connected to the input end of the D flip-flop as an output end;

[0050] The source of the MOS tube N50, the source of the MOS tube N51, the source of the MOS tube N54, the source of the MOS tube N55, the source of the MOS tube N56, the source of the MOS tube N57, the source of the MOS tube N58, the source of the MOS tube N60, the source of the MOS tube N62 and the drain of the MOS tube P57 are all grounded.

[0051] After adopting the above technical solution, the present invention has the following advantages compared with the background technology:

[0052] The external digital module writes 16-bit data into the 2-byte-EEPROM module. The three 5-bit-DAC modules read the V stored in the 2-byte-EEPROM module. out The digital value in <14:0>, where V out <15> Leave it unconnected. And convert it to V A 、V B and V C Three voltage values, V B =1 / 2V C, the common-mode voltage of the signal sampling and feedback module and the integral amplifier module. The signal sampling and feedback module and the integral amplifier module form a fully differential switched capacitor integrator, which is conducive to suppressing common-mode noise and noise on the power line and ground line. The input charge sampled by the signal sampling and feedback module and the integral amplifier module is converted to the integral capacitor through the integral amplifier module. The voltage values ​​on the integral capacitors at the positive and negative ends are compared through the quantization module, and the quantization output 0 and 1 are sent to the D flip-flop of the quantization module. After the NAND gate logic unit of the quantization module, the positive and negative reference voltage values ​​at the positive and negative ends are controlled. By controlling the signal writing through the external digital module and controlling the internal 5-bit-DAC module, the range of the modulator can be changed as needed. When the signal amplitude changes, there is no need to replace the hardware, which meets the measurement requirements of signals with different amplitudes and helps to reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a general schematic diagram of the adjustable range Sigma-Delta modulator of the present invention;

[0054] Figure 2 A schematic diagram of a 2byte-EEPROM module storage array of the adjustable range Sigma-Delta modulator of the present invention;

[0055] Figure 3 A circuit diagram of a data reading unit of the range-adjustable Sigma-Delta modulator of the present invention;

[0056] Figure 4 It is a circuit diagram of a 5-bit-DAC module of the range-adjustable Sigma-Delta modulator of the present invention;

[0057] Figure 5 This is a simulated waveform diagram of the output voltage of the 5-bit-DAC module of the range-adjustable Sigma-Delta modulator of the present invention;

[0058] Figure 6 A circuit diagram of a bias unit of a rail-to-rail fully differential folded common-source common-gate amplifier U3 of the range-adjustable Sigma-Delta modulator of the present invention;

[0059] Figure 7 It is a partial circuit diagram of the rail-to-rail fully differential folded common source and common gate amplifier U3 of the adjustable range Sigma-Delta modulator of the present invention;

[0060] Figure 8 A circuit diagram of a common-mode feedback unit of the range-adjustable Sigma-Delta modulator of the present invention;

[0061] Fig. 9A circuit diagram of a rail-to-rail current mirror comparator U4 of the range-adjustable Sigma-Delta modulator of the present invention;

[0062] Fig.10 It is a circuit diagram of a two-phase non-overlapping and chopping clock module of the range-adjustable Sigma-Delta modulator of the present invention;

[0063] Fig.11 It is a two-phase non-overlapping clock and chopping signal waveform diagram of the adjustable range Sigma-Delta modulator of the present invention;

[0064] Fig.12 This is a schematic diagram of the chopping principle of the adjustable range Sigma-Delta modulator of the present invention;

[0065] Fig.13 This is a simulation diagram comparing the range changes of the adjustable-range Sigma-Delta modulator described in the present invention.

[0066] Description of reference numerals:

[0067] 1. 2byte-EEPROM module; 2. 5bit-DAC module; 3. Signal sampling and feedback module; 4. Integral amplifier module; 5. Quantization module; 51. NAND gate logic unit; 6. Two-phase non-overlapping and chopping clock module; 7. Bias unit; 8. Constant cross rail-to-rail folded common source and common gate input unit; 9. Class-AB output unit. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0069] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0070] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0071] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Example

[0072] Please refer to Figure 1-13 As shown, this embodiment provides a range-adjustable Sigma-Delta modulator, including a 2byte-EEPROM module 1, three 5bit-DAC modules 2, a signal sampling and feedback module 3, an integral amplifier module 4, a two-phase non-overlapping and chopping clock module 6 and a quantization module 5.

[0073] The input end of the 2byte-EEPROM module 1 is electrically connected to the external digital module, the output end of the 2byte-EEPROM module 1 is electrically connected to the input end of the 5bit-DAC module 2, and the output ends of the three 5bit-DAC modules 2 output voltages V A , voltage V B and voltage V C The output end of the signal sampling and feedback module 3 is electrically connected to the input end of the integral amplifier module 4, and the output end of the integral amplifier module 4 is electrically connected to the input end of the quantization module 5. The external clock signal is input to the input end of the two-phase non-overlapping and chopping clock module, and the two-phase non-overlapping and chopping clock module outputs non-overlapping S1 clock signals and S2 clock signals to the signal sampling and feedback module 3, and outputs CLK chop and The chopped switching clock signal is sent to the integrating amplifier module 4.

[0074] The external digital module writes 16-bit data into the 2-byte-EEPROM module 1. The three 5-bit-DAC modules 2 read the V stored in the 2-byte-EEPROM module 1. out The digital value in <14:0>, where V out <15> Leave it unconnected. And convert it to V A 、V B and V C Three voltage values, V B =1 / 2V C, the common-mode voltage of the signal sampling and feedback module 3 and the integral amplifier module 4. The signal sampling and feedback module 3 and the integral amplifier module 4 form a fully differential switched capacitor integrator, which is conducive to suppressing common-mode noise and noise on the power line and ground line. The input charge sampled by the signal sampling and feedback module 3 and the integral amplifier module 4 is converted to the integral capacitor through the integral amplifier module 4. Then the voltage values ​​on the integral capacitors at the positive and negative ends are compared through the quantization module 5, and the quantization output 0 and 1 are sent to the D trigger of the quantization module 5. After the NAND gate logic unit of the quantization module 5, the positive and negative reference voltage values ​​at the positive and negative ends are controlled. By controlling the signal writing through the external digital module and controlling the internal 5bit-DAC module 2, the range of the modulator can be changed as needed. When the signal amplitude changes, there is no need to replace the hardware, which meets the measurement requirements of signals with different amplitudes and helps to reduce costs.

[0075] Please refer to the attached Figure 2 Specifically, the 2-byte-EEPROM module 1 includes two word lines SG<0:1> and eight bit lines BL<0:7>. The storage capacity of the 2-byte-EEPROM module 1 is 16 bits, where each bit is connected by a MOS tube N S And MOS tube N FG Composition, MOS tube N S For the gate tube N S , MOS tube N FG For storage tube N FG By inputting different potentials to the bit line, word line and control gate, the 2byte-EEPROM module 1 is erased and written to complete the "0" or "1" function. When in use, 16-bit data is written into the storage array of the 2byte-EEPROM module 1 through an external digital module.

[0076] Please refer to the attached Figure 3 The 2-byte-EEPROM module 1 also includes a data reading unit, which includes MOS transistors P1, P2, P3, N1, N2, N3, N4 and N5. MOS transistor N5 is a voltage-resistant transistor, which plays a buffering role for the control gate CG and protects the storage transistor N FG The source of MOS tube P1, the source of MOS tube P2, the source of MOS tube P3, and the source of MOS tube N S The gate and the source of the MOS tube N5 are electrically connected to the external power supply VDD1.

[0077] MOS tube N SThe drain of MOS tube N2 is electrically connected to the BL port, the drain of MOS tube P2, the gate of MOS tube P2 and the gate of MOS tube N3, wherein the BL port is electrically connected to the external digital circuit, and the erasing and writing of the unit data in the 2byte-EEPROM module 1 is controlled by the external digital circuit, wherein the BL port is attached Figure 2 BL0<0:7> port and BL1<0:7> port. When erasing data, the BL port is grounded, when writing data 0, the BL port is suspended, when writing data 1, the BL port is connected to the high voltage VPP, and when reading, the BL port is suspended. MOS tube N S The source of MOS tube N FG The drain of MOS tube N is electrically connected. FG The gate of the MOS tube is electrically connected to the drain of the MOS tube N5. FG The source of the MOS transistor P1 is electrically connected to the drain of the MOS transistor P1 and the drain of the MOS transistor N1. The gate of the MOS transistor P1 is electrically connected to the RST port, the gate of the MOS transistor N1 and the gate of the MOS transistor N2.

[0078] The drain of MOS transistor P2 is electrically connected to the drain of MOS transistor N3, the gate of MOS transistor P3 and the gate of MOS transistor N4; the drain of MOS transistor P3 is electrically connected to the drain of MOS transistor N4 and serves as an output terminal to output V out .

[0079] The source of MOS tube N1, the source of MOS tube N2, the source of MOS tube N3 and the source of MOS tube N4 are all grounded. In this embodiment, the data reading unit is a voltage-sensitive sensitive amplifier, RST is a reset terminal, when resetting, the RST port is suspended, the SG terminal and the source terminal of MOS tube N5 are connected to a high level, and the point potential of CG is VDD1-V THN5 When the storage tube N FG When '1' is written, its threshold voltage is negative, then the MOS tube N S And MOS tube N FG On, V BL The potential is VDD1-V THNS , V BL >VDD1 / 2, then the output V out is '1'. Where V THN5 and V THNS are the threshold voltages of MOS transistor N5 and MOS transistor NS respectively. For better data readability, the L value of MOS transistor P2 can be increased to reduce the voltage flip point of the subsequent inverter, that is, to increase the channel length of MOS transistor P2. FG When writing '0', its threshold voltage is positive and higher than VDD1-V THN5 , storage tube N FG No conduction, V BL is 0, the output Vout is '0'.

[0080] Please refer to the attached Figure 4 Specifically, the 5-bit-DAC module 2 includes port D0, port D1, port D2, port D3, port D4, MOS tube P4, MOS tube P5, MOS tube P6, MOS tube P7, MOS tube P8, MOS tube P9, MOS tube N6, MOS tube N7, MOS tube N8, MOS tube N9, MOS tube N10 and resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10.

[0081] The source of the MOS transistor P4 , the source of the MOS transistor P5 , the source of the MOS transistor P6 , the source of the MOS transistor P7 , the source of the MOS transistor P8 and the source of the MOS transistor P9 are all electrically connected to the external power source VDD1 .

[0082] The drain of the MOS transistor P4 is electrically connected to one end of the resistor R1; the port D0 is electrically connected to the gate of the MOS transistor P5 and the gate of the MOS transistor N6; the drain of the MOS transistor P5 is electrically connected to the drain of the MOS transistor N6 and one end of the resistor R2; the other end of the resistor R2 is electrically connected to the other end of the resistor R1 and one end of the resistor R7.

[0083] Port D1 is electrically connected to the gate of MOS transistor P6 and the gate of MOS transistor N7. The drain of MOS transistor P6 is electrically connected to the drain of MOS transistor N7 and one end of resistor R3. The other end of resistor R3 is electrically connected to the other end of resistor R7 and one end of resistor R8.

[0084] Port D2 is electrically connected to the gate of MOS transistor P7 and the gate of MOS transistor N8, the drain of MOS transistor P7 is electrically connected to the drain of MOS transistor N8 and one end of resistor R4, and the other end of resistor R4 is electrically connected to the other end of resistor R8 and one end of resistor R9.

[0085] Port D3 is electrically connected to the gate of MOS transistor P8 and the gate of MOS transistor N9, the drain of MOS transistor P8 is electrically connected to the drain of MOS transistor N9 and one end of resistor R5, and the other end of resistor R5 is electrically connected to the other end of resistor R9 and one end of resistor R10.

[0086] Port D4 is electrically connected to the gate of MOS transistor P9 and the gate of MOS transistor N10, the drain of MOS transistor P9 is electrically connected to the drain of MOS transistor N10 and one end of resistor R6, the other end of resistor R6 is electrically connected to the other end of resistor R10, and is electrically connected to the input end of signal sampling and feedback module 3 as an output end.

[0087] Ports D0, D1, D2, D3 and D4 of the three 5-bit-DAC modules 2 are electrically connected to the first to fifteenth output terminals of the 2-byte-EEPROM module 1 respectively; the gate of the MOS transistor P4, the source of the MOS transistor N6, the source of the MOS transistor N7, the source of the MOS transistor N8, the source of the MOS transistor N9 and the source of the MOS transistor N10 are all grounded. In this embodiment, the resistance value of the resistor R1-resistor R6 is 2R, and the resistance value of the resistor R7-resistor R8 is R.

[0088] The output voltage of 5bit-DAC module 2 is

[0089] ;

[0090] Please refer to the attached Figure 5 , attached Figure 5 This is the output voltage simulation waveform of the 5-bit-DAC module 2. The 5-bit-DAC module 2 can output 32 voltage values.

[0091] Please refer to the attached Figure 1 Specifically, the signal sampling and feedback module 3 includes V IN Port, Clock Switch 1S1, Clock Switch 2S1, Clock Switch 3S1, Clock Switch 4S1, Clock Switch 5S1, Clock Switch 6S1, Clock Switch 7S1, Clock Switch 8S1, Clock Switch 1S2, Clock Switch 2S2, Clock Switch 3S2, Clock Switch 4S2, Switch 1V out S2, switch 2V out S2, switch 1 S2, switch 2 S2 and sampling capacitor 1C S1 , sampling capacitor 2C S1 , sampling capacitor 1C S2 , sampling capacitor 2C S2 ; The two-phase non-overlapping and chopping clock module outputs the S1 clock signal to control the on and off of the clock switch 1S1, the clock switch 2S1, the clock switch 3S1, the clock switch 4S1, the clock switch 5S1, the clock switch 6S1, the clock switch 7S1 and the clock switch 8S1; the two-phase non-overlapping and chopping clock module outputs the S2 clock signal to control the on and off of the clock switch 1S2, the clock switch 2S2, the clock switch 3S2 and the clock switch 4S2; the quantization module 5 outputs V out S2 signal and ·S2 signal control switch 1V out S2, switch 2V out S2, switch 1 S2 and switch 2 In this embodiment, the clock switch 1S1, the clock switch 2S1, the clock switch 3S1, the clock switch 4S1, the clock switch 5S1, the clock switch 6S1, the clock switch 7S1, the clock switch 8S1, the clock switch 1S2, the clock switch 2S2, the clock switch 3S2, the clock switch 4S2, the switch 1V out ·S2 and switch 2V out ·S2 is a transmission gate.

[0092] 5bit-DAC module 2 output voltage V A To one end of the clock switch 2S2, one end of the clock switch 3S1 and one end of the clock switch 3S2; 5bit-DAC module 2 outputs voltage V B To one end of the clock switch 1S2 and one end of the clock switch 4S2; 5-bit-DAC module 2 output voltage V C To one end of the clock switch 4S1, one end of the clock switch 5S1, one end of the clock switch 6S1, one end of the clock switch 7S1 and one end of the clock switch 8S1; V IN The port is electrically connected to one end of the clock switch 2S1, V IN The port is connected to the external input analog signal to be measured.

[0093] One end of the clock switch 1S1 is connected to the other end of the clock switch 1S2 and the sampling capacitor 1C S2 One end of the sampling capacitor is electrically connected to S2 The other end of the switch 1 One end of S2, switch 1V out One end of S2 is electrically connected to the other end of the clock switch 5S1, and the other end of the clock switch 1S1 is grounded.

[0094] The other end of the clock switch 2S1 is connected to the other end of the clock switch 2S2 and the sampling capacitor 1C S1 One end of the sampling capacitor is electrically connected to S1 The other end of the switch 2 One end of S2, switch 1V out The other end of S2 is electrically connected to the other end of the clock switch 7S1 , and is electrically connected to the first input end of the integrating amplifier module 4 as a first output end.

[0095] The other end of the clock switch 3S1 and the other end of the clock switch 3S2 are connected to the sampling capacitor 2C S1 One end is electrically connected to the sampling capacitor 2C S1 The other end of the switch 1 The other end of S2, switch 2V outOne end of S2 is electrically connected to the other end of the clock switch 8S1 , and is electrically connected to the second input end of the integrating amplifier module 4 as a second output end.

[0096] The other end of the clock switch 4S1 and the other end of the clock switch 4S2 are connected to the sampling capacitor 2C S2 One end is electrically connected to the sampling capacitor 2C S2 The other end of the switch 2 The other end of S2, switch 2V out The other end of S2 is electrically connected to the other end of the clock switch 6S1.

[0097] Please refer to the attached Figure 1 Specifically, the integrating amplifier module 4 includes a first chopper switch, a rail-to-rail fully differential folded common source and common gate amplifier U3, a second chopper switch and an integrating capacitor 1C I 、Integral capacitor 2C I .

[0098] The first input terminal and the second input terminal of the first chopper switch are electrically connected to the first output terminal and the second output terminal of the signal sampling and feedback module 3, respectively, that is, the sampling capacitor 1C S1 The other end and the sampling capacitor 2C S1 The other end is electrically connected to the first input and the second input of the first chopper switch respectively. The first output and the second output of the first chopper switch are electrically connected to the same-direction input and the reverse input of the rail-to-rail fully differential folded common-source amplifier U3 respectively, the same-direction output and the reverse output of the rail-to-rail fully differential folded common-source amplifier U3 are electrically connected to the first input and the second input of the second chopper switch respectively, and the first output and the second output of the second chopper switch are electrically connected to the first input and the second input of the quantization module 5 respectively. Two-phase non-overlapping and chopping clock module output CLK chop Chopping the switching clock signal and The chopping switch clock signal is sent to the clock input terminals of the first chopping switch and the second chopping switch.

[0099] Integral capacitor 1C I Electrically connected between the first input terminal of the first chopper switch and the first output terminal of the second chopper switch; an integral capacitor 2C I The first chopper is electrically connected between the second input terminal of the first chopper switch and the second output terminal of the second chopper switch.

[0100] Sampling capacitor 1C S1 , sampling capacitor 2C S1 , sampling capacitor 1C S2 , sampling capacitor 2C S2, clock switch 1S1, clock switch 2S1, clock switch 3S1, clock switch 4S1, clock switch 5S1, clock switch 6S1, clock switch 7S1, clock switch 8S1, clock switch 1S2, clock switch 2S2, clock switch 3S2, clock switch 4S2, the first chopper switch, the rail-to-rail fully differential folded common source amplifier U3 and the second chopper switch form an integrator to convert the sampled input charge to the integration capacitor 1C I 、Integral capacitor 2C I On, and through the integrating capacitor 1C I 、Integral capacitor 2C I The data is transmitted to the first input terminal and the second input terminal of the quantization module 5 for quantization output.

[0101] Please refer to the attached Fig.12 , attached Fig.12 This is a schematic diagram of the chopping principle. The input signal is modulated to a high frequency without flicker noise through a square wave modulation signal. After amplification, the input signal is restored through square wave demodulation of the same frequency, effectively reducing the influence of low-frequency noise and DC offset input of the rail-to-rail fully differential folded common source and common gate amplifier U3. In this embodiment, the chopping frequency of the first chopping switch and the second chopping switch is less than half of the sampling frequency to ensure that the circuit is completely established. In this embodiment, the chopping frequency of the first chopping switch and the second chopping switch should be greater than the frequency of the input signal to ensure the noise filtering effect.

[0102] Assume the chopping signal is cosw c t, the DC signal generated at the input end is A d , the offset and noise signal is A n , input signal x(t)=A i cosw i t.

[0103] The signal after the first stage chopping modulation:

[0104] ;

[0105] The signal after the second stage chopping modulation:

[0106] ;

[0107] The above formula shows that the offset and noise signal A n After passing through two chopper switches, it is modulated to a frequency of w c The high frequency of the amplifier is reduced, thereby reducing the low frequency noise and DC offset at the input of the op amp.

[0108] Please refer to the attached Figure 6 and Figure 7 ,in, Figure 6 and Figure 7Specifically, the rail-to-rail fully differential folded cascode amplifier U3 includes a bias unit 7, a constant-span rail-to-rail folded cascode input unit 8, and a Class-AB output unit 9.

[0109] The same-direction input terminal and the inverting input terminal of the constant-span rail-to-rail folded common-source and common-gate input unit 8 are electrically connected to the first output terminal and the second output terminal of the first chopper switch, respectively, the output terminal of the constant-span rail-to-rail folded common-source and common-gate input unit 8 is electrically connected to the input terminal of the Class-AB output unit 9, and the same-direction output terminal and the inverting output terminal of the Class-AB output unit 9 are electrically connected to the first input terminal and the second input terminal of the second chopper switch, respectively.

[0110] The bias unit 7 is electrically connected to the external bias module, and the external bias module outputs a bias current I bias1 To the bias unit 7, the bias unit 7 outputs a first bias voltage V B1 , the fourth bias voltage V B4 , the sixth bias voltage V B6 and the eighth bias voltage V B8 To Class-AB output unit 9; bias unit 7 outputs a second bias voltage V B2 , the third bias voltage V B3 , the fifth bias voltage V B5 and the sixth bias voltage V B6 To the constant-span rail-to-rail folded common-source common-gate input unit 8.

[0111] Specifically, the bias unit 7 includes MOS transistors P10, P11, P12, P13, P14, P15, N11, N12, N13, N14, N15, N16, N17, N18 and N19.

[0112] The source of the MOS transistor P10 , the source of the MOS transistor P11 , the source of the MOS transistor P13 , and the source of the MOS transistor P14 are all electrically connected to the external power source VDD1 .

[0113] The gate and drain of the MOS transistor P10 are electrically connected to the gate of the MOS transistor P11 and the drain of the MOS transistor N13, and outputs a second bias voltage V B2 To the constant cross rail-to-rail folded common source and common gate input unit 8. The external bias module outputs the bias current I bias1 To the drain and gate of the MOS tube N11, the gate of the MOS tube N13, the gate of the MOS tube N16 and the gate of the MOS tube N18, and output the first bias voltage V B1To Class-AB output unit 9. The source of MOS transistor N11 is electrically connected to the drain, gate, gate of MOS transistor N12, gate of MOS transistor N14, gate of MOS transistor N17 and gate of MOS transistor N19, and outputs the sixth bias voltage V B6 To the constant cross rail-to-rail folded common source and common gate input unit 8. The source of the MOS transistor N13 is electrically connected to the drain of the MOS transistor N14.

[0114] The drain of the MOS transistor P11 is electrically connected to the source of the MOS transistor P12, the gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P13 and the drain of the MOS transistor N16, and outputs a fifth bias voltage V B5 To the constant cross rail-to-rail folded common source and common gate input unit 8, the source of MOS transistor N16 is electrically connected to the drain of MOS transistor N17. The drain of MOS transistor P12 is electrically connected to the gate and drain of MOS transistor N15, and outputs the third bias voltage V B3 To the constant-span rail-to-rail folded common-source common-gate input unit 8.

[0115] The gate and drain of the MOS transistor P14 are electrically connected to the source of the MOS transistor P15, and output a fourth bias voltage V B4 To Class-AB output unit 9. The gate and drain of MOS transistor P15 are electrically connected to the drain of MOS transistor N18, and outputs the eighth bias voltage V B8 To the Class-AB output unit 9, the source of the MOS transistor N18 is electrically connected to the drain of the MOS transistor N19.

[0116] The source of the MOS transistor N12, the source of the MOS transistor N1, the source of the MOS transistor N15, the source of the MOS transistor N17 and the source of the MOS transistor N19 are all grounded.

[0117] Specifically, the constant cross rail-to-rail folded common source and common gate input unit 8 includes MOS tube P16, MOS tube P17, MOS tube P18, MOS tube P19, MOS tube P20, MOS tube P21, MOS tube P22, MOS tube P23, MOS tube P24, MOS tube P25, MOS tube P26, MOS tube P27, MOS tube P28, MOS tube P29, MOS tube P30, MOS tube P31, MOS tube P39, MOS tube P40, MOS tube N20, MOS tube N21, MOS tube N22, MOS tube N23, MOS tube N24, MOS tube N25, MOS tube N26, MOS tube N27, MOS tube N28, MOS tube N29, MOS tube N30 and MOS tube N31.

[0118] The Class-AB output unit 9 includes MOS transistor P16, MOS transistor P32, MOS transistor P33, MOS transistor P34, MOS transistor P35, MOS transistor P36, MOS transistor P37, MOS transistor P38, MOS transistor P41, MOS transistor P42, MOS transistor N32, MOS transistor N33, MOS transistor N34, MOS transistor N37, MOS transistor N38, MOS transistor N39, MOS transistor N40, MOS transistor N41, MOS transistor N42 and capacitors C5, C6, C7 and C8.

[0119] The source of MOS tube P16, the source of MOS tube P17, the source of MOS tube P18, the source of MOS tube P22, the source of MOS tube P23, the source of MOS tube P24, the source of MOS tube P25, the source of MOS tube P26, the source of MOS tube P27, the source of MOS tube P28, the source of MOS tube P29, the source of MOS tube P32, the source of MOS tube P34, the source of MOS tube P35, the source of MOS tube P36, the source of MOS tube P39, the source of MOS tube P40 and the source of MOS tube P42 are all electrically connected to the external power supply VDD1.

[0120] The gate of MOS transistor P16 is electrically connected to the gate and drain of MOS transistor P17, the drain of MOS transistor N20 and the gate of MOS transistor P40. The drain of MOS transistor P16 is electrically connected to the gate and drain of MOS transistor P24, the gate of MOS transistor P39 and the drain of MOS transistor N24.

[0121] The bias unit 7 outputs a second bias voltage V B2 To the gate of the MOS tube P18, that is, the gate and drain of the MOS tube P10 are electrically connected to the gate of the MOS tube P18; the drain of the MOS tube P18 is electrically connected to the source of the MOS tube P19, and the bias unit 7 outputs the fifth bias voltage V B5 To the gate of MOS transistor P19, that is, the drain of MOS transistor P11 is electrically connected to the gate of MOS transistor P19, and the drain of MOS transistor P19 is electrically connected to the source of MOS transistor P20 and the source of MOS transistor P21. The gate of MOS transistor P20 is electrically connected to the gate of MOS transistor N25, and is electrically connected to the second output end of the first chopper switch as a reverse input end; the gate of MOS transistor P21 is electrically connected to the gate of MOS transistor N24, and is electrically connected to the first output end of the first chopper switch as a non-inverting input end. The drain of MOS transistor P20 is electrically connected to the gate of MOS transistor N20 and the gate and drain of MOS transistor N21. The drain of MOS transistor P21 is electrically connected to the gate of MOS transistor N23 and the gate and drain of MOS transistor N22.

[0122] The gate and drain of MOS transistor P22 are electrically connected to the drain of MOS transistor N23, the gate of MOS transistor P23 and the gate of MOS transistor P27. The drain of MOS transistor P23 is electrically connected to the drain of MOS transistor N25, the drain and gate of MOS transistor P25 and the gate of MOS transistor P26. The source of MOS transistor N25 is electrically connected to the source of MOS transistor N24 and the drain of MOS transistor N26. The bias unit 7 outputs a third bias voltage V B3 To the gate of MOS transistor N26, that is, the drain of MOS transistor P12 is electrically connected to the gate of MOS transistor N26, and the source of MOS transistor N26 is electrically connected to the drain of MOS transistor N27. The bias unit 7 outputs the sixth bias voltage V B6 To the gate of the MOS transistor N27, that is, the source of the MOS transistor N11 is electrically connected to the gate of the MOS transistor N27.

[0123] The drain of MOS transistor P26 is electrically connected to the drain of MOS transistor P27, the source of MOS transistor N30 and the drain of MOS transistor N31. The drain of MOS transistor P39 is electrically connected to the drain of MOS transistor P40, the source of MOS transistor N28 and the drain of MOS transistor N29. The bias unit 7 outputs a third bias voltage V B3 The bias unit 7 outputs the sixth bias voltage V B6 The gate of MOS transistor N29 and the gate of MOS transistor N31, that is, the source of MOS transistor N11 is electrically connected to the gate of MOS transistor N29 and the gate of MOS transistor N31. The drain of MOS transistor N28 is electrically connected to the drain of MOS transistor P33 and the source of MOS transistor N33; the drain of MOS transistor N30 is electrically connected to the drain of MOS transistor P41 and the source of MOS transistor N34.

[0124] The gate of MOS transistor P28 is electrically connected to the gate of MOS transistor P29, the gate and drain of MOS transistor P32, and the drain of MOS transistor N32; the drain of MOS transistor P28 is electrically connected to the source of MOS transistor P30, and the drain of MOS transistor P29 is electrically connected to the source of MOS transistor P31. The bias unit 7 outputs a fifth bias voltage V B5The gate of MOS transistor P30 and the gate of MOS transistor P31, that is, the drain of MOS transistor P11 is electrically connected to the gate of MOS transistor P30 and the gate of MOS transistor P31. The drain of MOS transistor P30 is electrically connected to the source of MOS transistor P33 and the drain of MOS transistor N33; the drain of MOS transistor P31 is electrically connected to the source of MOS transistor P41 and the drain of MOS transistor N34. The gate of MOS transistor P33 is electrically connected to the gate of MOS transistor P41, the gate and drain of MOS transistor P37, and the drain of MOS transistor N38. The gate of MOS transistor N33 is electrically connected to the gate of MOS transistor N34, the gate and drain of MOS transistor 40, and the drain of MOS transistor P38.

[0125] The bias unit 7 outputs a first bias voltage V B1 To the gate of the MOS tube N38, that is, the drain and gate of the MOS tube N11 are electrically connected to the gate of the MOS tube N38; the source of the MOS tube N38 is electrically connected to the drain of the MOS tube N39, and the bias unit 7 outputs the sixth bias voltage V B6 The gate of the MOS transistor N39, that is, the source of the MOS transistor N11 is electrically connected to the gate of the MOS transistor N39. The source of the MOS transistor N40 is electrically connected to the drain and gate of the MOS transistor N41.

[0126] Common mode feedback unit output V CMFB voltage to the gate of MOS tube N32, that is, the seventh bias voltage V B7 By the common mode feedback voltage V CMFB The current mirror formed by the MOS transistor P32 is input to the gate of the MOS transistor P28 and the gate of the MOS transistor P29. The gate and drain of the MOS transistor P34 are electrically connected to the source of the MOS transistor P37. The bias unit 7 outputs a fourth bias voltage V B4 To the gate of the MOS transistor P35, that is, the gate and drain of the MOS transistor P14 are electrically connected to the gate of the MOS transistor P35; the drain of the MOS transistor P35 is electrically connected to the source of the MOS transistor P38, and the bias unit 7 outputs the eighth bias voltage V B8 To the gate of the MOS transistor P38, that is, the gate and drain of the MOS transistor P15 are electrically connected to the gate of the MOS transistor P38.

[0127] The gate of MOS transistor P36 is electrically connected to one end of capacitor C5, the source of MOS transistor P33 and the drain of MOS transistor N33. The other end of capacitor C5 is electrically connected to the drain of MOS transistor P36, one end of capacitor C6 and the drain of MOS transistor N37, and is electrically connected to the second input end of the second chopper switch as a reverse output end. The gate of MOS transistor N37 is electrically connected to the other end of capacitor C6, the drain of MOS transistor P33 and the source of MOS transistor N33. The gate of MOS transistor P42 is electrically connected to one end of capacitor C7, the source of MOS transistor P41 and the drain of MOS transistor N34. The other end of capacitor C7 is electrically connected to the drain of MOS transistor P42, one end of capacitor C8 and the drain of MOS transistor N42, and is electrically connected to the first input end of the second chopper switch as a non-inverting output end; the gate of MOS transistor N42 is electrically connected to the other end of capacitor C8, the drain of MOS transistor P41 and the source of MOS transistor N34.

[0128] The source of the MOS tube N20, the source of the MOS tube N21, the source of the MOS tube N22, the source of the MOS tube N23, the source of the MOS tube N27, the source of the MOS tube N29, the source of the MOS tube N31, the source of the MOS tube N32, the source of the MOS tube N37, the source of the MOS tube N39, the source of the MOS tube N41 and the source of the MOS tube N42 are all grounded.

[0129] The rail-to-rail fully differential folded cascode amplifier U3 effectively avoids the limitation that the common-mode input range of traditional op amps cannot reach the full swing. The input stage of the rail-to-rail fully differential folded cascode amplifier U3 adopts both NMOS and PMOS differential pair structures to form a maximum current selection circuit to achieve constant input transconductance, ensuring that the op amp can maintain a stable operating state when the common-mode input voltage changes over the entire power supply voltage range. The output stage of the rail-to-rail fully differential folded cascode amplifier U3 adopts a class AB output stage with a translinear ring structure, which effectively improves the output swing of the op amp. The rail-to-rail fully differential folded cascode amplifier U3 achieves a rail-to-rail common-mode input range, breaking through the previous stage V C The common-mode voltage range is limited so that V C The voltage value can be close to the power supply voltage. , so increase V C It can effectively expand the measuring range of the modulator.

[0130] Assume that the relationship between the non-inverting input terminal and the reverse input terminal is V in+ >V in- , we can get:

[0131] ;

[0132] ;

[0133] ;

[0134] ;

[0135] Among them, V id is the small signal differential input voltage, I nr and I np is the tail current of the differential pair of NMOS and PMOS tubes, ɡ mp andɡ mn They are the transconductance of the differential pair of NMOS and PMOS tubes respectively.

[0136] From the circuit we can see

[0137] ;

[0138] ;

[0139] ;

[0140] Among them, I o is the output current of the input stage;

[0141] When only the PMOS tube differential pair is working and the NMOS tube differential pair is turned off, we can get:

[0142] I nr pr =I rmax , mn < mp，max = m，max ;

[0143] I o = m，max ·V id ;

[0144] When only the NMOS tube differential pair is working and the PMOS tube differential pair is turned off, we can get:

[0145] I pr nr =I rmax , mp < mn，max = m，max ;

[0146] I o = m，max ·V id ;

[0147] When both the PMOS tube and the NMOS tube are turned on, we can get:

[0148] I pr ​​=I nr =I rmax , mp，max = mn，max = m，max ;

[0149] I o = m，max ·V id ;

[0150] Among them, m，max is the maximum transconductance of the complementary differential pair, I rmax is the maximum value of tail current, ɡ mn，max andɡ mp，max They are the maximum transconductance of the differential pair of NPMOS and PMOS tubes respectively. The maximum current selection circuit can select the maximum value of the PMOS differential input pair tube current, which can keep the input stage transconductance constant. .

[0151] Please refer to the attached Figure 8 Specifically, the common-mode feedback unit includes a clock switch 9S1, a clock switch 10S1, a clock switch 11S1, a clock switch 12S1, a clock switch 13S1, a clock switch 5S2, a clock switch 6S2, a clock switch 7S2, a clock switch 8S2 and capacitors C1, C2, C3 and C4; the two-phase non-overlapping and chopping clock module outputs an S1 clock signal to control the on and off of the clock switches 9S1, 10S1, 11S1, 12S1 and 13S1; the two-phase non-overlapping and chopping clock module outputs an S2 clock signal to control the on and off of the clock switches 5S2, 6S2, 7S2 and 8S2. In this embodiment, the clock switches 9S1, 10S1, 11S1, 12S1, 13S1, 5S2, 6S2, 7S2 and 8S2 are transmission gates.

[0152] One end of the clock switch 9S1 and one end of the clock switch 12S1 are both electrically connected to the external power source VDD1.

[0153] The other end of the clock switch 9S1 is electrically connected to one end of the capacitor C4 and one end of the clock switch 5S2, and the other end of the clock switch 5S2 is electrically connected to one end of the clock switch 6S2 and the reverse output end of the Class-AB output unit 9, that is, the other end of the capacitor C5 is electrically connected to the other end of the clock switch 5S2. The other end of the clock switch 6S2 is electrically connected to one end of the clock switch 11S1 and one end of the capacitor C1.

[0154] The other end of the clock switch 12S1 is electrically connected to one end of the capacitor C3 and one end of the clock switch 7S2, and the other end of the clock switch 7S2 is electrically connected to one end of the clock switch 8S2 and the same-direction output end of the Class-AB output unit 9, that is, the other end of the capacitor C7 is electrically connected to the other end of the clock switch 7S2. The other end of the clock switch 8S2 is electrically connected to one end of the clock switch 13S1 and one end of the capacitor C2.

[0155] The other end of capacitor C4 is electrically connected to the other end of capacitor C3, the other end of capacitor C1, the other end of capacitor C2 and one end of clock switch 10S1, and is electrically connected to the feedback input end of Class-AB output unit 9 as a feedback output end, that is, the other end of capacitor C4 is electrically connected to the gate of MOS tube N32. Bias unit 7 outputs sixth bias voltage V B6 To the other end of the clock switch 10S1. The other end of the clock switch 11S1 and the other end of the clock switch 13S1 are both grounded.

[0156] Capacitors C1, C2, C3, and C4 are feedback capacitors, and their capacitances are equal, all C. Then, at the S1 and S2 clock phases, the total charge on the feedback capacitors is:

[0157]

[0158]

[0159] According to the law of charge conservation, we can get

[0160]

[0161] From the formula, we can see that the feedback voltage V CMFB By outputting the common mode voltage V OCM With common mode voltage V CM The difference between the sixth bias voltage V B6 When V OCM When the disturbance increases, V CMFB Synchronously rises and pulls down the voltage V B7 , the current I flowing through MOS tube P4 and MOS tube P5 DP4 ,I DP5 The gate voltage V of MOS tube P36 rises. OPG1 And the gate voltage V of MOS tube P42 OPG2 increases, thereby lowering V OCM Complete negative feedback and finally stabilize the output common mode voltage V OCM .

[0162] Please refer to the attached Figure 1Specifically, the quantization module 5 includes a rail-to-rail current mirror comparator U4, a D flip-flop, and a NAND gate logic unit. The first output terminal and the second output terminal of the integrating amplifier module 4 are respectively electrically connected to the same-direction input terminal and the reverse input terminal of the rail-to-rail current mirror comparator U4, the output terminal of the rail-to-rail current mirror comparator U4 is electrically connected to the input terminal of the D flip-flop, and the first output terminal and the second output terminal of the D flip-flop respectively output V out and To the first input terminal and the second input terminal of the NAND gate logic unit; the NAND gate logic unit outputs V out S2 and S2 signal.

[0163] Please refer to the attached Fig. 9 Specifically, the rail-to-rail current mirror comparator U4 includes MOS tube P50, MOS tube P51, MOS tube P52, MOS tube P53, MOS tube P54, MOS tube P55, MOS tube P56, MOS tube P57, MOS tube P58, MOS tube P59, MOS tube P60, MOS tube P61, MOS tube N50, MOS tube N51, MOS tube N52, MOS tube N53, MOS tube N54, MOS tube N55, MOS tube N56, MOS tube N57, MOS tube N58, MOS tube N59, MOS tube N60, MOS tube N61 and MOS tube N62.

[0164] The source of MOS transistor P50, the source of MOS transistor P51, the source of MOS transistor P52, the source of MOS transistor P53, the source of MOS transistor P54, the source of MOS transistor P55, the source of MOS transistor P58, the source of MOS transistor P59 and the source of MOS transistor N61 are all electrically connected to the external power supply VDD1.

[0165] The gate and drain of MOS transistor P50 are electrically connected to the drain of MOS transistor N51 and the gate of MOS transistor P59, providing a bias voltage V for the gate of MOS transistor P59. BPO The drain of the MOS transistor P59 is electrically connected to the source of the MOS transistor P60 and the source of the MOS transistor P61. The drain of the MOS transistor P60 is electrically connected to the gate of the MOS transistor N55 and the gate and drain of the MOS transistor N56.

[0166] External bias module output bias current I bias0 To the drain and gate of MOS tube N50, the gate of MOS tube N51 and the gate of MOS tube N54, providing a bias voltage V for the gate of MOS tube N54 BNO .

[0167] The gate of MOS transistor P51 is electrically connected to the gate and drain of MOS transistor P52 and the drain of MOS transistor N52; the drain of MOS transistor P51 is electrically connected to the drain of MOS transistor P61, the gate and drain of MOS transistor N57 and the gate of MOS transistor N58.

[0168] The gate of MOS transistor N52 is electrically connected to the gate of MOS transistor P60, and is electrically connected to the first output end of the integration amplifier module 4 as a non-inverting input end, that is, the gate of MOS transistor N52 is electrically connected to the first output end of the second chopper switch. The source of MOS transistor N52 is electrically connected to the drain of MOS transistor N54 and the source of MOS transistor N53; the gate of MOS transistor N53 is electrically connected to the gate of MOS transistor P61, and is electrically connected to the second output end of the integration amplifier module 4 as a reverse input end, that is, the gate of MOS transistor N53 is electrically connected to the second output end of the second chopper switch. The drain of MOS transistor N53 is electrically connected to the gate and drain of MOS transistor P53, the gate of MOS transistor P54, and the drain of MOS transistor N55.

[0169] The drain of MOS transistor P54 is electrically connected to the drain of MOS transistor N58, the gate of MOS transistor P55, the gate of MOS transistor P56, the gate of MOS transistor N59 and the gate of MOS transistor N60; the drain of MOS transistor P55 is electrically connected to the source of MOS transistor P56 and the source of MOS transistor P57; the drain of MOS transistor P56 is electrically connected to the gate of MOS transistor P57, the drain of MOS transistor N59, the gate of MOS transistor P58, the gate of MOS transistor N61 and the gate of MOS transistor N62; the source of MOS transistor N59 is electrically connected to the drain of MOS transistor N60 and the drain of MOS transistor N61; the drain of MOS transistor P58 is electrically connected to the drain of MOS transistor N62, and is electrically connected to the input end of the D trigger as an output end.

[0170] The source of the MOS transistor N50, the source of the MOS transistor N51, the source of the MOS transistor N54, the source of the MOS transistor N55, the source of the MOS transistor N56, the source of the MOS transistor N57, the source of the MOS transistor N58, the source of the MOS transistor N60, the source of the MOS transistor N62 and the drain of the MOS transistor P57 are all grounded.

[0171] The rail-to-rail current mirror comparator U4 adopts a rail-to-rail input stage, which can effectively improve the common-mode input range and ensure the normal operation of the quantization module 5.

[0172] Please refer to the attached Figure 1 Specifically, the NAND gate logic unit includes a NAND gate U1, a NAND gate U2, an inverter D1 and an inverter D2.

[0173] The first output terminal and the second output terminal of the D flip-flop output Vout and To the first input terminal of the NAND gate U1 and the second input terminal of the NAND gate U2, the two-phase non-overlapping and chopping clock module outputs the S2 clock signal to the second input terminal of the NAND gate U1 and the first input terminal of the NAND gate U2. The output terminal of the NAND gate U1 and the output terminal of the NAND gate U2 are electrically connected to the input terminal of the inverter D1 and the input terminal of the inverter D2 respectively, and the output terminal of the inverter D1 and the output terminal of the inverter D2 respectively output V out S2 and S2 signal.

[0174] Please refer to the attached Fig.10 , CLK signal is an externally given clock signal, which generates non-overlapping S1 and S2 two-phase clocks through the path delay and logic operation of the gate circuit chain. The two-phase non-overlapping clocks can avoid the channel charge injection effect from introducing errors into the switched capacitor circuit. The non-overlapping time is related to the delay time difference, and the specific delay time is determined by the length of the inverter chain.

[0175] CLK chop It is a chopped switching clock signal that divides CLK by 16.

[0176] Please refer to the attached Fig.11 , attached Fig.11 The waveform diagram of the two-phase non-overlapping clock and chopping signal is shown in Figure 2. The modulator output voltage V out There is the following relationship,

[0177] When V out =1:

[0178] ;

[0179] ;

[0180] In a single cycle, the difference Δ between the change in the positive terminal and the change in the negative terminal of the rail-to-rail current mirror comparator U4 is:

[0181] ;

[0182] Among them, V inp The modulation input V in , V inn Constant V A ,but:

[0183] ;

[0184] Similarly, when V out =0:

[0185] ;

[0186] ;

[0187] ;

[0188] When V out =1, it is necessary to satisfy Δ Vout=1 <0, when V out =0, it is necessary to satisfy Δ Vout=1 >0,V out To flip, then:

[0189] ;

[0190] ;

[0191] Right now,

[0192] ;

[0193] Therefore, V in The measuring range is , the range size is , it can be seen that the range is affected by V A 、V C And the sampling capacitor 1C S1 , sampling capacitor 2C S1 , sampling capacitor 1C S2 , sampling capacitor 2C S2 When the capacitance value is fixed, by controlling V A With V C The voltage value can be adjusted to achieve the range adjustment.

[0194] In this embodiment, the sampling capacitor 1C S1 , sampling capacitor 2C S1 The capacitance value is the same as the integral capacitance 1C I 、Integral capacitor 2C I The capacitance value is equal to the sampling capacitor 1C S2 , sampling capacitor 2C S2 Twice. B The voltage value is V C Half of the voltage value, which uses a sampling capacitor 1C S2 , sampling capacitor 2C S2 Generate positive and negative reference voltage .

[0195] Write the stored data into 2byte-EEPROM module 1, and then use 5bit-DAC module 2 to read the desired V A With V CVoltage value. The 2byte-EEPROM module 1 has the feature of being repeatedly erasable and writable, so that the range can be adjusted.

[0196] From the above, we can see that the difference between the positive and negative output terminals is:

[0197] ;

[0198] After Z transformation, we can get

[0199] ;

[0200] Its transfer function is

[0201] ;

[0202] The results are consistent with the discrete domain linear model of the first-order Sigma-Delta modulator.

[0203] Please refer to the attached Fig.13 , attached Fig.13 The following is a simulation diagram comparing the range changes under six storage values.

[0204] Table 1: Theoretical correspondence between the measurement range and the storage value of 2byte-EEPROM module 1

[0205]

[0206] Table 1 lists the theoretical corresponding values ​​of some measuring ranges and the storage values ​​of 2byte-EEPROM module 1, and verifies them. Fig.13 In the table, the ranges of the six storage values ​​listed in the table are compared. The input is a triangle wave signal from 0 to VDD, the modulator outputs a low potential represented by '0', and the output VDD is represented by '1'. The simulation results show that when it is higher than the range, the proportion of the modulator outputting '1' increases, and the output is '1' when the input signal exceeds the range. When it is lower than the range, the proportion of the modulator outputting 0 increases, and the output is '0' when the input signal is lower than the range. The density of '1' in the code stream corresponds to the amplitude of the input signal, and the simulation results are basically consistent with the theoretical values. This shows that the range and range size of the adjustable range Sigma-Delta modulator described in this embodiment can be adjusted by the storage value of the 2byte-EEPROM module 1.

[0207] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A range-adjustable Sigma-Delta modulator, characterized in that: It includes 2byte-EEPROM module, three 5bit-DAC modules, signal sampling and feedback module, integral amplifier module, two-phase non-overlapping and chopping clock module and quantization module; The input end of the 2byte-EEPROM module is electrically connected to the external digital module, the output end of the 2byte-EEPROM module is electrically connected to the input end of the 5bit-DAC module, and the output ends of the three 5bit-DAC modules respectively output voltages V A , voltage V B and voltage V C to the input end of the signal sampling and feedback module, the output end of the signal sampling and feedback module is electrically connected to the input end of the integral amplifier module, and the output end of the integral amplifier module is electrically connected to the input end of the quantization module, The external clock signal is input to the input end of the two-phase non-overlapping and chopping clock module, and the two-phase non-overlapping and chopping clock module outputs non-overlapping S1 clock signals and S2 clock signals to the signal sampling and feedback module, and outputs CLK chop Chopping the switching clock signal and chopping the switching clock signal to the integrating amplifier module; The 2-byte-EEPROM module includes two word lines SG<0:1> and eight bit lines BL<0:7>. The storage capacity of the 2-byte-EEPROM module is 16 bits, wherein each bit is connected by a MOS tube N S And MOS tube N FG The MOS tube N S For the gate tube N S , the MOS tube N FG For storage tube N FG ; The 2byte-EEPROM module further includes a data reading unit, and the data reading unit includes a MOS transistor P1, a MOS transistor P2, a MOS transistor P3, a MOS transistor N1, a MOS transistor N2, a MOS transistor N3, a MOS transistor N4 and a MOS transistor N5; The source of the MOS tube P1, the source of the MOS tube P2, the source of the MOS tube P3, the source of the MOS tube N S The gate and the source of the MOS tube N5 are electrically connected to the external power supply VDD1; The MOS tube N S The drain of the MOS tube is electrically connected to the BL port, the drain of the MOS tube N2, the gate of the MOS tube P2 and the gate of the MOS tube N3; the MOS tube N S The source of MOS tube N FG The drain of the MOS tube N is electrically connected; FG The gate of the MOS tube N5 is electrically connected to the drain of the MOS tube N5. FG The source of the MOS transistor P1 is electrically connected to the drain of the MOS transistor P1 and the drain of the MOS transistor N1; the gate of the MOS transistor P1 is electrically connected to the RST port, the gate of the MOS transistor N1 and the gate of the MOS transistor N2; The drain of the MOS transistor P2 is electrically connected to the drain of the MOS transistor N3, the gate of the MOS transistor P3 and the gate of the MOS transistor N4; the drain of the MOS transistor P3 is electrically connected to the drain of the MOS transistor N4 and serves as an output terminal to output V out ; The source of the MOS tube N1, the source of the MOS tube N2, the source of the MOS tube N3 and the source of the MOS tube N4 are all grounded; The 5-bit-DAC module includes port D0, port D1, port D2, port D3, port D4, MOS tube P4, MOS tube P5, MOS tube P6, MOS tube P7, MOS tube P8, MOS tube P9, MOS tube N6, MOS tube N7, MOS tube N8, MOS tube N9, MOS tube N10 and resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10; The source of the MOS transistor P4, the source of the MOS transistor P5, the source of the MOS transistor P6, the source of the MOS transistor P7, the source of the MOS transistor P8 and the source of the MOS transistor P9 are all electrically connected to the external power supply VDD1; The drain of the MOS transistor P4 is electrically connected to one end of the resistor R1; the port D0 is electrically connected to the gate of the MOS transistor P5 and the gate of the MOS transistor N6; the drain of the MOS transistor P5 is electrically connected to the drain of the MOS transistor N6 and one end of the resistor R2; the other end of the resistor R2 is electrically connected to the other end of the resistor R1 and one end of the resistor R7; The port D1 is electrically connected to the gate of the MOS transistor P6 and the gate of the MOS transistor N7, the drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor N7 and one end of the resistor R3, and the other end of the resistor R3 is electrically connected to the other end of the resistor R7 and one end of the resistor R8; The port D2 is electrically connected to the gate of the MOS transistor P7 and the gate of the MOS transistor N8, the drain of the MOS transistor P7 is electrically connected to the drain of the MOS transistor N8 and one end of the resistor R4, and the other end of the resistor R4 is electrically connected to the other end of the resistor R8 and one end of the resistor R9; The port D3 is electrically connected to the gate of the MOS transistor P8 and the gate of the MOS transistor N9, the drain of the MOS transistor P8 is electrically connected to the drain of the MOS transistor N9 and one end of the resistor R5, and the other end of the resistor R5 is electrically connected to the other end of the resistor R9 and one end of the resistor R10; The port D4 is electrically connected to the gate of the MOS transistor P9 and the gate of the MOS transistor N10, the drain of the MOS transistor P9 is electrically connected to the drain of the MOS transistor N10 and one end of the resistor R6, the other end of the resistor R6 is electrically connected to the other end of the resistor R10, and is electrically connected to the input end of the signal sampling and feedback module as an output end; Port D0, port D1, port D2, port D3 and port D4 of the three 5-bit-DAC modules are electrically connected to the first to fifteenth output terminals of the 2-byte-EEPROM module respectively; the gate of the MOS tube P4, the source of the MOS tube N6, the source of the MOS tube N7, the source of the MOS tube N8, the source of the MOS tube N9 and the source of the MOS tube N10 are all grounded.

2. The adjustable range Sigma-Delta modulator according to claim 1, characterized in that: The signal sampling and feedback module includes V IN Port, Clock Switch 1S1, Clock Switch 2S1, Clock Switch 3S1, Clock Switch 4S1, Clock Switch 5S1, Clock Switch 6S1, Clock Switch 7S1, Clock Switch 8S1, Clock Switch 1S2, Clock Switch 2S2, Clock Switch 3S2, Clock Switch 4S2, Switch 1V out S2, switch 2V out S2, switch 1 S2, switch 2 S2 and sampling capacitor 1C S1 , sampling capacitor 2C S1 , sampling capacitor 1C S2 , sampling capacitor 2C S2 ; The 5-bit-DAC module outputs a voltage V A to one end of the clock switch 2S2, one end of the clock switch 3S1 and one end of the clock switch 3S2; the 5-bit-DAC module outputs a voltage V B To one end of the clock switch 1S2 and one end of the clock switch 4S2; the 5-bit-DAC module outputs a voltage V C to one end of the clock switch 4S1, one end of the clock switch 5S1, one end of the clock switch 6S1, one end of the clock switch 7S1 and one end of the clock switch 8S1; the V IN The port is electrically connected to one end of the clock switch 2S1; One end of the clock switch 1S1 is connected to the other end of the clock switch 1S2 and the sampling capacitor 1C S2 One end of the sampling capacitor is electrically connected to S2 The other end of the switch 1 One end of S2, switch 1V out One end of S2 is electrically connected to the other end of the clock switch 5S1, and the other end of the clock switch 1S1 is grounded; The other end of the clock switch 2S1 is connected to the other end of the clock switch 2S2 and the sampling capacitor 1C S1 One end of the sampling capacitor is electrically connected to S1 The other end of the switch 2 One end of S2, switch 1V out The other end of S2 is electrically connected to the other end of the clock switch 7S1 and is electrically connected to the first input end of the integrating amplifier module as a first output end; The other end of the clock switch 3S1 and the other end of the clock switch 3S2 are connected to the sampling capacitor 2C S1 One end of the sampling capacitor is electrically connected to S1 The other end of the switch 1 The other end of S2, switch 2V out One end of S2 is electrically connected to the other end of the clock switch 8S1 and is electrically connected to the second input end of the integrating amplifier module as a second output end; The other end of the clock switch 4S1 and the other end of the clock switch 4S2 are connected to the sampling capacitor 2C S2 One end of the sampling capacitor is electrically connected to S2 The other end of the switch 2 The other end of S2, switch 2V out The other end of S2 is electrically connected to the other end of the clock switch 6S1.

3. The adjustable range Sigma-Delta modulator according to claim 1, characterized in that: The integrating amplifier module includes a first chopper switch, a rail-to-rail fully differential folded common source and common gate amplifier U3, a second chopper switch and an integrating capacitor 1C I 、Integral capacitor 2C I ; The first input terminal and the second input terminal of the first chopper switch are electrically connected to the first output terminal and the second output terminal of the signal sampling and feedback module, respectively; the first output terminal and the second output terminal of the first chopper switch are electrically connected to the same-direction input terminal and the reverse input terminal of the rail-to-rail fully differential folded common-source amplifier U3, respectively; the same-direction output terminal and the reverse output terminal of the rail-to-rail fully differential folded common-source amplifier U3 are electrically connected to the first input terminal and the second input terminal of the second chopper switch, respectively; the first output terminal and the second output terminal of the second chopper switch are electrically connected to the first input terminal and the second input terminal of the quantization module, respectively; The integrating capacitor 1C I The integral capacitor 2C is electrically connected between the first input terminal of the first chopper switch and the first output terminal of the second chopper switch; I The first chopper is electrically connected between the second input terminal of the first chopper switch and the second output terminal of the second chopper switch.

4. The adjustable range Sigma-Delta modulator according to claim 3, characterized in that: The rail-to-rail fully differential folded cascode amplifier U3 includes a bias unit, a constant-transduction rail-to-rail folded cascode input unit and a Class-AB output unit; The same-direction input terminal and the inverting input terminal of the constant-span rail-to-rail folded common-source common-gate input unit are electrically connected to the first output terminal and the second output terminal of the first chopper switch, respectively; the output terminal of the constant-span rail-to-rail folded common-source common-gate input unit is electrically connected to the input terminal of the Class-AB output unit; and the same-direction output terminal and the inverting output terminal of the Class-AB output unit are electrically connected to the first input terminal and the second input terminal of the second chopper switch, respectively; The bias unit is electrically connected to an external bias module, and the external bias module outputs a bias current I bias1 To the bias unit, the bias unit outputs a first bias voltage V B1 , the fourth bias voltage V B4 , the sixth bias voltage V B6 and the eighth bias voltage V B8 To the Class-AB output unit; the bias unit outputs a second bias voltage V B2 , the third bias voltage V B3 , the fifth bias voltage V B5 and the sixth bias voltage V B6 To constant-span rail-to-rail folded cascode input cell.

5. The adjustable range Sigma-Delta modulator according to claim 4, characterized in that: The signal sampling and feedback module includes a common mode feedback unit, and the common mode feedback unit includes a clock switch 9S1, a clock switch 10S1, a clock switch 11S1, a clock switch 12S1, a clock switch 13S1, a clock switch 5S2, a clock switch 6S2, a clock switch 7S2, a clock switch 8S2 and capacitors C1, C2, C3 and C4; One end of the clock switch 9S1 and one end of the clock switch 12S1 are both electrically connected to the external power supply VDD1; The other end of the clock switch 9S1 is electrically connected to one end of the capacitor C4 and one end of the clock switch 5S2, the other end of the clock switch 5S2 is electrically connected to one end of the clock switch 6S2 and the reverse output end of the Class-AB output unit, and the other end of the clock switch 6S2 is electrically connected to one end of the clock switch 11S1 and one end of the capacitor C1; The other end of the clock switch 12S1 is electrically connected to one end of the capacitor C3 and one end of the clock switch 7S2, the other end of the clock switch 7S2 is electrically connected to one end of the clock switch 8S2 and the same-direction output end of the Class-AB output unit, and the other end of the clock switch 8S2 is electrically connected to one end of the clock switch 13S1 and one end of the capacitor C2; The other end of the capacitor C4 is electrically connected to the other end of the capacitor C3, the other end of the capacitor C1, the other end of the capacitor C2 and one end of the clock switch 10S1, and is electrically connected to the feedback input end of the Class-AB output unit as a feedback output end. The bias unit outputs a sixth bias voltage V B6 To the other end of the clock switch 10S1; The other end of the clock switch 11S1 and the other end of the clock switch 13S1 are both grounded.

6. The adjustable range Sigma-Delta modulator according to claim 1, characterized in that: The quantization module includes a rail-to-rail current mirror comparator U4, a D flip-flop and a NAND gate logic unit; The first output terminal and the second output terminal of the integrating amplifier module are electrically connected to the same-direction input terminal and the reverse input terminal of the rail-to-rail current mirror comparator U4, respectively. The output terminal of the rail-to-rail current mirror comparator U4 is electrically connected to the input terminal of the D flip-flop. The first output terminal and the second output terminal of the D flip-flop output V out and To the first input terminal and the second input terminal of the NAND gate logic unit; the NAND gate logic unit outputs V out S2 and S2 signal.

7. The adjustable range Sigma-Delta modulator according to claim 6, characterized in that: The rail-to-rail current mirror comparator U4 includes MOS transistors P50, P51, P52, P53, P54, P55, P56, P57, P58, P59, P60, P61, N50, N51, N52, N53, N54, N55, N56, N57, N58, N59, N60, N61 and N62. The source of the MOS transistor P50, the source of the MOS transistor P51, the source of the MOS transistor P52, the source of the MOS transistor P53, the source of the MOS transistor P54, the source of the MOS transistor P55, the source of the MOS transistor P58, the source of the MOS transistor P59 and the source of the MOS transistor N61 are all electrically connected to the external power supply VDD1; The gate and drain of the MOS transistor P50 are electrically connected to the drain of the MOS transistor N51 and the gate of the MOS transistor P59, providing a bias voltage V for the gate of the MOS transistor P59. BPO The drain of the MOS tube P59 is electrically connected to the source of the MOS tube P60 and the source of the MOS tube P61; the drain of the MOS tube P60 is electrically connected to the gate of the MOS tube N55 and the gate and drain of the MOS tube N56; External bias module output bias current I bias0 To the drain and gate of MOS tube N50, the gate of MOS tube N51 and the gate of MOS tube N54, providing a bias voltage V for the gate of MOS tube N54 BNO ; The gate of the MOS transistor P51 is electrically connected to the gate and drain of the MOS transistor P52 and the drain of the MOS transistor N52; the drain of the MOS transistor P51 is electrically connected to the drain of the MOS transistor P61, the gate and drain of the MOS transistor N57 and the gate of the MOS transistor N58; The gate of the MOS tube N52 is electrically connected to the gate of the MOS tube P60, and is electrically connected to the first output end of the integration amplifier module as a non-inverting input end; the source of the MOS tube N52 is electrically connected to the drain of the MOS tube N54 and the source of the MOS tube N53; the gate of the MOS tube N53 is electrically connected to the gate of the MOS tube P61, and is electrically connected to the second output end of the integration amplifier module as a reverse input end, and the drain of the MOS tube N53 is electrically connected to the gate and drain of the MOS tube P53, the gate of the MOS tube P54, and the drain of the MOS tube N55; The drain of the MOS transistor P54 is electrically connected to the drain of the MOS transistor N58, the gate of the MOS transistor P55, the gate of the MOS transistor P56, the gate of the MOS transistor N59 and the gate of the MOS transistor N60; the drain of the MOS transistor P55 is electrically connected to the source of the MOS transistor P56 and the source of the MOS transistor P57; the drain of the MOS transistor P56 is electrically connected to the gate of the MOS transistor P57, the drain of the MOS transistor N59, the gate of the MOS transistor P58, the gate of the MOS transistor N61 and the gate of the MOS transistor N62; the source of the MOS transistor N59 is electrically connected to the drain of the MOS transistor N60 and the drain of the MOS transistor N61; the drain of the MOS transistor P58 is electrically connected to the drain of the MOS transistor N62, and is electrically connected to the input end of the D flip-flop as an output end; The source of the MOS transistor N50, the source of the MOS transistor N51, the source of the MOS transistor N54, the source of the MOS transistor N55, the source of the MOS transistor N56, the source of the MOS transistor N57, the source of the MOS transistor N58, the source of the MOS transistor N60, the source of the MOS transistor N62 and the drain of the MOS transistor P57 are all grounded.

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