Three-dimensional memory and method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a manufacturing method thereof. The manufacturing method of the three-dimensional memory comprises the following steps: forming a base, the base comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer; forming a storage hole in the first dielectric layer that at least exposes the side wall of the first contact structure; forming a storage structure that at least continuously covers the inner wall of the storage hole, the side wall of the first contact structure, and the top surface of the first contact structure; forming a conductive filling layer that fills the storage hole and covers the surface of the storage structure; using a chemical mechanical polishing process to remove part of the conductive filling layer and part of the storage structure, and the top surface of the remaining conductive filling layer, the top surface of the remaining storage structure, and the top surface of the first contact structure are flush; forming a first lead-out structure electrically connected to the conductive filling layer. The present invention increases the area of ​​the storage structure and avoids leakage between storage structures in the same layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a manufacturing method thereof. Background Art

[0002] Phase change memory or ferroelectric memory (FeRAM) and other memories are devices that integrate memory cells (Cells) in the back end of line (BEOL), which are structures in which the memory cells are inserted between two adjacent metal layers. The memory cell is generally composed of an upper and lower electrode layer and a ferroelectric memory layer in the middle. The storage performance of the ferroelectric memory is proportional to the effective area of ​​the ferroelectric memory layer and the electrode layer in the memory cell. The traditional two-dimensional structure memory is composed of a vertically stacked upper electrode layer, a lower electrode layer, and a ferroelectric material layer or a phase change material layer located between the upper electrode layer and the lower electrode layer. However, as the size of the memory continues to shrink, the effective area of ​​the storage structure in the traditional two-dimensional structure memory continues to shrink, thereby limiting the further improvement of the memory performance. Moreover, after the traditional two-dimensional memory forms the storage structure, when a lead-out structure electrically connected to the storage structure is formed above the storage structure, it is easy to cause damage to the storage structure, thereby affecting the performance of the memory.

[0003] Therefore, how to increase the effective area of ​​the storage structure while reducing the damage to the storage structure when forming the lead-out structure, thereby improving the performance and manufacturing yield of the memory, is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a three-dimensional memory and a manufacturing method thereof, which are used to increase the effective area of ​​the memory structure while reducing the damage to the memory structure when forming a lead-out structure, thereby improving the performance and manufacturing yield of the memory.

[0005] According to some embodiments, the present invention provides a method for manufacturing a three-dimensional memory, comprising the following steps:

[0006] forming a substrate, the substrate comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer;

[0007] forming a storage hole in the first dielectric layer to expose at least a side wall of the first contact structure;

[0008] forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, and the storage structure is in electrical contact with the first contact structure;

[0009] forming a conductive filling layer that fills the storage hole and covers the surface of the storage structure, wherein the conductive filling layer is electrically connected to the storage structure;

[0010] Using a chemical mechanical polishing process to remove part of the conductive filling layer and part of the storage structure, so that the top surface of the remaining conductive filling layer, the top surface of the remaining storage structure and the top surface of the first contact structure are flush;

[0011] A first lead-out structure is formed which is located above the substrate and is electrically connected to the conductive filling layer.

[0012] In some embodiments, the specific steps of forming the substrate include:

[0013] Providing a substrate, wherein the substrate includes an active region, and the substrate includes a top surface and a bottom surface that are relatively distributed;

[0014] forming a first dielectric layer on the top surface of the substrate;

[0015] The first contact structure is formed along a first direction penetrating the first dielectric layer and electrically connected to the active region in the substrate, wherein the first direction intersects perpendicularly with the top surface of the substrate.

[0016] In some embodiments, the active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along a second direction, wherein the second direction is parallel to the top surface of the substrate; the first contact structure is electrically connected to the drain region, and the substrate further includes a second contact structure that penetrates the first dielectric layer and is electrically connected to the source region; the specific steps of forming a storage hole in the first dielectric layer that exposes at least a sidewall of the first contact structure include:

[0017] forming a second dielectric layer covering the first dielectric layer, the first contact structure and the second contact structure;

[0018] The second dielectric layer and the first dielectric layer are etched to form the storage hole penetrating the second dielectric layer and extending into the first dielectric layer.

[0019] In some embodiments, the specific step of forming a storage hole in the first dielectric layer to expose at least a sidewall of the first contact structure includes:

[0020] The first dielectric layer and the second dielectric layer are etched to form the storage holes distributed around the periphery of the first contact structure and exposing the sidewalls of the first contact structure.

[0021] In some embodiments, the specific steps of forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure, and the top surface of the first contact structure include:

[0022] forming a lower electrode layer that continuously covers the inner wall of the storage hole, the side wall of the first contact structure, the top surface of the first contact structure, and the top surface of the second dielectric layer;

[0023] forming a storage layer covering the lower electrode layer;

[0024] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

[0025] In some embodiments, the specific steps of removing part of the conductive filling layer and part of the storage structure by using a chemical mechanical polishing process include:

[0026] A chemical mechanical polishing process is used to remove part of the conductive filling layer, part of the storage structure and the entire second dielectric layer above the first dielectric layer, so that the top surface of the remaining conductive filling layer, the top surface of the remaining storage structure, the top surface of the first contact structure and the top surface of the first dielectric layer are flush, and the second contact structure is exposed.

[0027] In some embodiments, the specific steps of forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer include:

[0028] forming a third dielectric layer covering the substrate;

[0029] forming two first sub-lead-out holes penetrating the third dielectric layer and exposing the conductive filling layer located on opposite sides of the first contact structure along the second direction one by one;

[0030] A first sub-lead-out structure is formed to fill each of the first sub-lead-out holes respectively, and two first sub-lead-out structures together constitute the first lead-out structure.

[0031] In some embodiments, after forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer, the following steps are further included:

[0032] A first conductive connection pad electrically connecting the two first sub-lead-out structures is formed above the third dielectric layer.

[0033] In some embodiments, the specific step of forming a storage hole in the first dielectric layer to expose at least a sidewall of the first contact structure includes:

[0034] The first dielectric layer and the second dielectric layer are etched to form the storage hole which is located only on one side of the first contact structure along the second direction and exposes the sidewall of the first contact structure.

[0035] In some embodiments, the substrate includes at least two first contact structures adjacent to each other along the second direction; the specific steps of forming a storage hole in the first dielectric layer to expose at least the sidewalls of the first contact structure include:

[0036] The first dielectric layer and the second dielectric layer are etched to form the storage hole located between two adjacent first contact structures and exposing the side walls of the two adjacent first contact structures.

[0037] According to some other embodiments, the present invention also provides a three-dimensional memory, including:

[0038] A base, comprising a substrate, a first dielectric layer located above the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, wherein the substrate comprises a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly;

[0039] A storage hole, located in the first dielectric layer, wherein the storage hole at least exposes a side wall of the first contact structure;

[0040] a storage structure, continuously covering an inner wall of the storage hole and a side wall of the first contact structure, and the storage structure is in electrical contact with the first contact structure;

[0041] A conductive filling layer, which fills the storage hole and covers the surface of the storage structure, the conductive filling layer is electrically connected to the storage structure, and the top surface of the conductive filling layer, the top surface of the storage structure and the top surface of the first contact structure are flush;

[0042] The first lead-out structure is located above the substrate and is electrically connected to the conductive filling layer.

[0043] In some embodiments, the storage holes are distributed around the periphery of the first contact structure and expose sidewalls of the first contact structure.

[0044] In some embodiments, the storage hole is located only at one side of the first contact structure along a second direction and exposes a sidewall of the first contact structure, and the second direction is parallel to a top surface of the substrate.

[0045] In some embodiments, the substrate includes at least two adjacent first contact structures along the second direction, and the storage hole is located between the two adjacent first contact structures and exposes side walls of the two adjacent first contact structures.

[0046] In some embodiments, the first lead-out structure includes two first sub-lead-out structures arranged along a second direction, and the two first sub-lead-out structures are electrically connected to the conductive filling layer located on opposite sides of the first contact structure along the second direction, and the second direction is parallel to the top surface of the substrate.

[0047] The three-dimensional memory and its manufacturing method provided by the present invention, the substrate has a first contact structure penetrating the first dielectric layer, and a storage hole is formed in the first dielectric layer to expose at least the side wall of the first contact structure, and a storage structure is formed to continuously cover at least the inner wall of the storage hole and the side wall of the first contact structure, thereby forming a memory with a three-dimensional structure, which not only increases the area of ​​the storage structure and improves the performance and manufacturing yield of the memory, but also reduces the number of other dielectric layers deposited above the first dielectric layer, thereby helping to further reduce the size of the three-dimensional memory and improve the integration of the three-dimensional memory. At the same time, part of the conductive filling layer and part of the storage structure are removed by a chemical mechanical polishing process, so that the electrical connection between adjacent storage structures can be fully disconnected to avoid leakage between storage structures in the same layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a flow chart of a method for manufacturing a three-dimensional memory in a specific embodiment of the present invention;

[0049] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;

[0050] Figure 3 is a schematic diagram of a structure after a storage hole is formed in a specific embodiment of the present invention;

[0051] Figure 4 is a schematic diagram of a structure after a storage structure and a conductive filling layer are formed in a specific embodiment of the present invention;

[0052] Figure 5 It is a structural schematic diagram after a part of the conductive filling layer and a part of the storage structure are removed by a chemical mechanical polishing process in a specific embodiment of the present invention;

[0053] Figure 6 is a schematic diagram of a structure after forming a third dielectric layer in a specific embodiment of the present invention;

[0054] Figure 7 is a schematic diagram of a structure after the first lead-out hole is formed in a specific embodiment of the present invention;

[0055] Figure 8 is a structural schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention;

[0056] Fig. 9 is a schematic diagram of a structure after a first conductive connection pad is formed in a specific embodiment of the present invention;

[0057] Fig.10 is a schematic diagram of the structure of another three-dimensional memory manufactured in a specific embodiment of the present invention;

[0058] Fig.11 It is a schematic diagram of the structure of another three-dimensional memory manufactured in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0059] The specific implementation of the three-dimensional memory and the manufacturing method thereof provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0060] This specific embodiment provides a method for manufacturing a three-dimensional memory. Figure 1 FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the three-dimensional memory comprises the following steps:

[0061] Step S11, forming a base, wherein the base includes a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer;

[0062] Step S12, forming a storage hole in the first dielectric layer to expose at least a side wall of the first contact structure;

[0063] Step S13, forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, and the storage structure is in electrical contact with the first contact structure;

[0064] Step S14, forming a conductive filling layer that fills the storage holes and covers the surface of the storage structure, wherein the conductive filling layer is electrically connected to the storage structure;

[0065] Step S15, removing part of the conductive filling layer and part of the storage structure by a chemical mechanical polishing process, so that the top surface of the remaining conductive filling layer, the top surface of the remaining storage structure and the top surface of the first contact structure are flush;

[0066] Step S16, forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer.

[0067] Figure 2 Schematic diagram of a structure of a substrate in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the substrate include:

[0068] Providing a substrate 20, wherein the substrate includes an active region, and the substrate 20 includes a top surface and a bottom surface that are relatively distributed;

[0069] forming a first dielectric layer 21 on the top surface of the substrate 20;

[0070] The first contact structure 25 is formed along a first direction D1 that penetrates the first dielectric layer 21 and is electrically connected to the active region in the substrate 20. The first direction D1 intersects the top surface of the substrate 20 perpendicularly. Figure 2 shown.

[0071] Figure 3 : is a schematic diagram of a structure after forming a storage hole in a specific embodiment of the present invention. In some embodiments, the active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along a second direction D2, and the second direction D2 is parallel to the top surface of the substrate 20; the first contact structure 25 is electrically connected to the drain region, and the substrate further includes a second contact structure 26 that penetrates the first dielectric layer 21 and is electrically connected to the source region; the specific steps of forming a storage hole 31 in the first dielectric layer 21 to expose at least the sidewall of the first contact structure 25 include:

[0072] forming a second dielectric layer 30 covering the first dielectric layer 21, the first contact structure 25 and the second contact structure 26;

[0073] The second dielectric layer 30 and the first dielectric layer 21 are etched to form the storage hole 31 penetrating the second dielectric layer 30 and extending into the first dielectric layer 21 .

[0074] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 20 as a silicon substrate as an example. The substrate 20 includes at least a plurality of active regions spaced apart along the second direction D2. The active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along the second direction D2. The base also includes a gate structure located on the substrate 20, the gate structure including a gate dielectric layer 22 located above the channel region, a gate conductive layer 23 covering the surface of the gate dielectric layer 22, and an isolation sidewall 24 covering the sidewalls of the gate dielectric layer 22 and the sidewalls of the gate conductive layer 23, as shown in FIG. Figure 2As shown. The first dielectric layer 21 covers the top surface of the substrate 20 and the gate structure. The material of the first dielectric layer 21 can be an oxide material, such as silicon dioxide. In one example, the first contact structure 25 penetrates the first dielectric layer 21 along the first direction D1 and is electrically connected to the drain region, and the second contact structure 26 penetrates the first dielectric layer 21 along the first direction D1 and is electrically connected to the source region. The first contact structure 25 and the second contact structure 26 can be formed by the following method: after forming the first dielectric layer 21 covering the top surface of the substrate 20 and the gate structure, the first dielectric layer 21 is etched to form a first contact hole that penetrates the first dielectric layer 21 along the first direction D1 and exposes the drain region, and at the same time, a second contact hole that penetrates the first dielectric layer 21 along the first direction D1 and exposes the source region is formed; then, a material such as metal tungsten is filled in the first contact hole and the second contact hole to form the first contact structure 25 that is electrically connected to the drain region in the first contact hole, and at the same time, the second contact structure 26 that is electrically connected to the source region is formed in the second contact hole. Before etching the first dielectric layer 21 to form the storage hole 31, an insulating material such as silicon oxynitride is deposited on the first dielectric layer 21 to form the second dielectric layer 30 covering the first dielectric layer 21, the first contact structure 25 and the second contact structure 26. The second dielectric layer 30 is used as a protective layer to avoid damage to the second contact structure 26 and the gate structure during etching the storage hole 31.

[0075] After forming the second dielectric layer 30, the second dielectric layer 30 and the first dielectric layer 21 are etched downward from the second dielectric layer 30, so as to form the storage hole 31 penetrating the second dielectric layer 30 and extending into the first dielectric layer 21, and the storage hole 31 does not penetrate the first dielectric layer 21 along the first direction D1. Figure 3 In the process of etching the first dielectric layer 21, the depth of the storage hole 31 along the first direction D1 can be adjusted by controlling the etching time, thereby avoiding damage to the device structure such as the gate structure in the first dielectric layer 21 and the substrate 20, and meeting the storage performance requirements of the three-dimensional memory.

[0076] In this specific embodiment, by forming the storage hole 31 in the first dielectric layer 21 that at least exposes the side wall of the first contact structure 25, on the one hand, the area for subsequently forming the storage structure is increased, thereby increasing the area of ​​the storage structure and improving the electrical performance of the memory; on the other hand, since the storage hole 31 is directly formed in the first dielectric layer 21, the subsequently formed storage structure is located in the first dielectric layer 21, not only a three-dimensional structured memory (i.e., the three-dimensional memory) is formed, but also the thickness of the memory is greatly reduced, which helps to further reduce the size of the memory and further improve the storage density.

[0077] In some embodiments, the specific steps of forming the storage hole 31 in the first dielectric layer 21 to expose at least the sidewall of the first contact structure 25 include:

[0078] The first dielectric layer 21 and the second dielectric layer 30 are etched to form the storage holes 31 which are distributed around the periphery of the first contact structure 25 and expose the sidewalls of the first contact structure 25. Figure 3 shown.

[0079] Specifically, by distributing the storage holes 31 around the periphery of the first contact structure 25, for example, distributing the storage holes 31 symmetrically about the first contact structure 25, on the one hand, the inner wall area of ​​the storage holes 31 can be further increased, thereby further increasing the area of ​​the storage structure subsequently formed, so as to further improve the storage performance of the three-dimensional storage structure; on the other hand, the contact area between the storage structure subsequently formed and the first contact structure 25 can also be increased, thereby further reducing the contact resistance between the storage structure and the first contact structure 25, thereby further improving the electrical performance of the three-dimensional storage.

[0080] Figure 4 FIG. 1 is a schematic diagram of a structure after forming a storage structure and a conductive filling layer in a specific embodiment of the present invention. Figure 4 As shown, the specific steps of forming the storage structure 40 that continuously covers at least the inner wall of the storage hole 31, the side wall of the first contact structure 25 and the top surface of the first contact structure 25 include:

[0081] forming a lower electrode layer that continuously covers the inner wall of the storage hole 31, the side wall of the first contact structure 25, the top surface of the first contact structure 25, and the top surface of the second dielectric layer 30;

[0082] forming a storage layer covering the lower electrode layer;

[0083] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure 40 .

[0084] For example, if Figure 4 As shown, after forming the storage hole 31, TiN or other materials are deposited on the substrate to form the lower electrode layer that continuously covers the inner wall of the storage hole 31 (including the side wall and bottom surface of the storage hole 31), the side wall of the first contact structure 25, the top surface of the first contact structure 25 and the top surface of the second dielectric layer 30. Phase change material or ferroelectric material is deposited on the substrate to form a storage layer that continuously covers the lower electrode layer. TiN or other materials are deposited on the substrate again to form an upper electrode layer that continuously covers the storage layer. The lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure 40. Since the surface used to form the storage structure 40 includes not only the inner wall of the storage hole 31 but also the side wall of the first contact structure 25, the surface area of ​​the storage structure 40 formed in the storage hole 31 is increased, thereby improving the storage performance of the three-dimensional memory and helping to further reduce the size of the three-dimensional memory. Next, a conductive material such as metal tungsten is deposited on the substrate to form the conductive filling layer 41 that fills the storage hole 31 and continuously covers the surface of the upper electrode layer. The conductive filling layer 41 can not only lead out the signal of the upper electrode layer, increase the process window when the first lead-out structure is subsequently formed, and simplify the formation process of the first lead-out structure, but also avoid damage to the storage structure 40 when the first lead-out hole is formed by an etching process, thereby ensuring the stability of the performance of the storage structure 40.

[0085] Figure 5 1 is a schematic diagram of a structure after a part of the conductive filling layer and a part of the storage structure are removed by a chemical mechanical polishing process in a specific embodiment of the present invention. In some embodiments, the specific steps of removing part of the conductive filling layer and part of the storage structure by a chemical mechanical polishing process include:

[0086] A chemical mechanical polishing process is used to remove a portion of the conductive filling layer 41, a portion of the storage structure 40 and the entire second dielectric layer 30 above the first dielectric layer 21, and the top surface of the remaining conductive filling layer 41, the top surface of the remaining storage structure 40, the top surface of the first contact structure 25 and the top surface of the first dielectric layer 21 are flush, and the second contact structure 26 is exposed, as shown in FIG. Figure 5 shown.

[0087] This specific embodiment adopts a chemical mechanical polishing process to remove part of the conductive filling layer 41, part of the storage structure 40 and all of the second dielectric layer 30 above the first dielectric layer 21, so as to fully disconnect the connection between the adjacent storage structures in the same layer and avoid leakage between the adjacent storage structures. In addition, this specific embodiment adopts a chemical mechanical polishing method to remove part of the conductive filling layer 41, part of the storage structure 40 and all of the second dielectric layer 30 above the first dielectric layer 21, and there is no need to use a mask in the process of disconnecting the connection between adjacent storage structures, thereby reducing the manufacturing cost of the three-dimensional memory.

[0088] In one example, a chemical mechanical polishing process can be used to remove part of the conductive filling layer 41, part of the storage structure 40 and the entire second dielectric layer 30 above the first dielectric layer 21, so that the top surface of the remaining conductive filling layer 41, the top surface of the remaining storage structure 40, the top surface of the first contact structure 25 and the top surface of the first dielectric layer 21 are flush, thereby further improving the manufacturing efficiency of the three-dimensional memory.

[0089] In another example, a portion of the conductive filling layer 41, a portion of the storage structure 40, and the entire second dielectric layer 30 above the first dielectric layer 21 may be removed by multiple chemical mechanical polishing processes, so as to facilitate the control of the polishing end point and avoid damage to the storage structure 40 in the storage hole 31, the conductive filling layer 41 in the storage hole 31, and the first contact structure 25 and the second contact structure 26. For example, the storage layer is first used as a polishing stop layer, and the conductive filling layer 41 and the upper electrode layer above the top surface of the first dielectric layer 21 and above the storage hole 31 are removed by a first chemical mechanical polishing process; then, the storage layer and the lower electrode layer above the top surface of the first dielectric layer 21 and above the storage hole 31 may be removed by a second chemical mechanical polishing process by controlling the polishing time, and the second dielectric layer 30 is removed, so as to form a structure as shown in FIG. Figure 5 The structure shown.

[0090] Figure 6 is a schematic diagram of a structure after forming a third dielectric layer in a specific embodiment of the present invention, Figure 7 is a schematic diagram of a structure after the first lead-out hole is formed in a specific embodiment of the present invention, Figure 8 4 is a schematic diagram of a structure after forming the first lead-out structure in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the first lead-out structure located above the substrate and electrically connected to the conductive filling layer 41 include:

[0091] forming a third dielectric layer covering the substrate;

[0092] forming two first sub-leading holes 70 penetrating the third dielectric layer and exposing the conductive filling layer 41 located at two opposite sides of the first contact structure 25 along the second direction D2;

[0093] A first sub-lead-out structure 80 is formed to fill each of the first sub-lead-out holes 70 , and two first sub-lead-out structures 80 together constitute the first lead-out structure.

[0094] For example, a material such as silicon nitride is deposited on the substrate to form a first sub-isolation layer 60 covering the top surface of the first dielectric layer 21, the top surface of the second contact structure 26, the top surface of the remaining conductive filling layer 41, and the top surface of the remaining storage structure 40. A material such as oxide (such as silicon dioxide) is deposited on the first sub-isolation layer 60 to form a second sub-isolation layer 61, and the first sub-isolation layer 60 and the second sub-isolation layer 61 are used together as the third dielectric layer. Then, a mask layer 62 is formed on the second sub-isolation layer 61, such as Figure 6 The mask layer 62 and the third dielectric layer are etched to simultaneously form two first sub-lead holes 70 exposing the conductive filling layer 41 located on opposite sides of the first contact structure 25 along the second direction and a second lead hole 71 exposing the second contact structure 26, as shown in FIG. Figure 7 As shown, the two first sub-lead-out holes 70 together constitute the first lead-out hole. A conductive material such as metal tungsten is deposited on the substrate to form a first sub-lead-out structure 80 that fills the first sub-lead-out hole 70 and a second lead-out structure 81 that fills the second lead-out hole 71. The two first sub-lead-out structures 80 together constitute the first lead-out structure.

[0095] In this specific embodiment, a portion of the conductive filling layer 41, a portion of the storage structure 40 and the entire second dielectric layer 30 above the first dielectric layer 21 are removed by a chemical mechanical polishing process, so that the top surface of the remaining conductive filling layer 41, the top surface of the remaining storage structure 40, the top surface of the first contact structure 25 and the top surface of the first dielectric layer 21 are flush, thereby making the top surface of the conductive filling layer 41 flush with the top surface of the second contact structure 26, and subsequently the first lead-out hole and the second lead-out hole 71 of the same depth can be formed simultaneously by a one-step etching process, which not only reduces the depth of the second lead-out hole 71 and avoids a deep hole etching process, but also improves the manufacturing efficiency and manufacturing yield of the three-dimensional memory.

[0096] Fig. 94 is a schematic diagram of a structure after forming the first conductive connection pad in a specific embodiment of the present invention. In some embodiments, after forming the first lead-out structure located above the substrate and electrically connected to the conductive filling layer 41, the following steps are also included:

[0097] A first conductive connection pad 90 is formed on the third dielectric layer to electrically connect the two first sub-lead structures 80. Fig. 9 shown.

[0098] Specifically, a metal material is deposited on the top surface of the third dielectric layer, and a first conductive connection pad 90 electrically connecting the two first sub-lead-out structures 80 and a second conductive connection pad 91 electrically connecting the second lead-out structure 81 are formed at the same time. The two first sub-lead-out structures 80 are simultaneously connected through the first conductive connection pad 90, so that two mutually parallel storage structures can be formed in one storage unit, which not only increases the storage capacity of the three-dimensional memory, but also further improves the stability of the performance of the three-dimensional memory.

[0099] In other embodiments, two independent first conductive connection pads 90 may be formed above the third dielectric layer, and the two first conductive connection pads 90 are electrically connected to the two first sub-lead structures 80 in a one-to-one correspondence to further expand the function of the three-dimensional memory.

[0100] Fig.10 is a schematic diagram of the structure of another three-dimensional memory manufactured in a specific embodiment of the present invention. In other embodiments, such as Fig.10 As shown, the specific steps of forming the storage hole 31 in the first dielectric layer 21 to expose at least the sidewall of the first contact structure 25 include:

[0101] The first dielectric layer 21 and the second dielectric layer 30 are etched to form the storage hole 31 which is located only on one side of the first contact structure 25 along the second direction D2 and exposes the sidewall of the first contact structure 25 .

[0102] For example, by forming the storage hole 31 only on one side of the first contact structure 25, the storage structure 40 formed in the storage hole 31 and electrically connected to the first contact structure 25 and the conductive filling layer 41 filled in the storage hole 31 are only located on one side of the first contact structure 25 along the second direction D2 (such as Fig.10 As shown in FIG. 1 ), even if the size of the three-dimensional memory is continuously reduced and the interval between adjacent storage units in the three-dimensional memory is continuously reduced, the area of ​​the storage structure 40 can be increased. In one example, in one storage unit ( Fig.10, two storage units sharing the second contact structure 26 are shown in the figure), the storage structure is located on the side of the first contact structure 25 facing the second contact structure 26, thereby further increasing the distance between the two adjacent storage structures 40 and reducing the parasitic capacitance effect between the adjacent storage structures 40. In one example, in the same storage unit, the first lead-out structure 100 is electrically connected to the first conductive connection pad 90, the second lead-out structure 81 is electrically connected to the second conductive connection pad 91, and the first conductive connection pad 90 and the second conductive connection pad 91 are independent of each other. In another example, in the same storage unit, the first lead-out structure 100 and the second lead-out structure 81 are both electrically connected to the third conductive connection pad to expand the function of the three-dimensional memory.

[0103] Fig.11 FIG. 1 is a schematic diagram of another three-dimensional memory structure manufactured in a specific embodiment of the present invention. In some other embodiments, Fig.11 As shown, the substrate includes at least two first contact structures 25 adjacent to each other along the second direction D2; the specific steps of forming a storage hole 31 in the first dielectric layer 21 to expose at least the sidewall of the first contact structure 25 include:

[0104] The first dielectric layer 21 and the second dielectric layer 30 are etched to form the storage hole 31 located between two adjacent first contact structures 25 and exposing the side walls of the two adjacent first contact structures 25 .

[0105] For example, the substrate at least includes a plurality of memory cells arranged along the second direction D2, each of the memory cells includes an active region located in the substrate, the gate structure located above the substrate, the first dielectric layer 21 covering the substrate and the gate structure, and the first contact structure 25 and the second contact structure 26 located in the first dielectric layer 21, and the first contact structures 25 in two adjacent memory cells are also adjacent along the second direction D2. By forming the storage hole 31 between two adjacent first contact structures 25 and exposing the sidewalls of the two adjacent first contact structures 25, the two adjacent memory cells share the same storage structure 40 (see Fig.11 ), which not only helps to further increase the area of ​​the storage structure 40, but also can more fully utilize the space in the three-dimensional memory and expand the function of the three-dimensional memory.

[0106] This specific embodiment also provides a three-dimensional memory. The three-dimensional memory provided in this specific embodiment can be used as follows Figure 1-Figure 11The three-dimensional memory is formed by the manufacturing method shown in FIG. 1 , and the structure of the three-dimensional memory provided in this specific embodiment can be referred to in FIG. Fig. 9 , Fig.10 and Fig.11 .like Figure 1-Figure 11 As shown, the three-dimensional memory comprises:

[0107] A base, comprising a substrate 20, a first dielectric layer 21 located above the substrate 20, and a first contact structure 25 penetrating the first dielectric layer 21 along a first direction D1, wherein the substrate 20 comprises a top surface and a bottom surface that are relatively distributed, and the first direction D1 intersects the top surface of the substrate 20 vertically;

[0108] A storage hole 31, located in the first dielectric layer 21, wherein the storage hole 31 at least exposes a side wall of the first contact structure 25;

[0109] A storage structure 40 continuously covers the inner wall of the storage hole 31 and the side wall of the first contact structure 25, and the storage structure 40 is in contact and electrically connected with the first contact structure 25;

[0110] A conductive filling layer 41, which fills the storage hole 31 and covers the surface of the storage structure 40, the conductive filling layer 41 is electrically connected to the storage structure 40, and the top surface of the conductive filling layer 41, the top surface of the storage structure 40 and the top surface of the first contact structure 25 are flush;

[0111] The first lead-out structure is located above the substrate and is electrically connected to the conductive filling layer 41 .

[0112] In this specific embodiment, by forming the storage hole 31 in the first dielectric layer 21 to expose at least the side wall of the first contact structure 25, on the one hand, the area of ​​the storage structure 40 is increased, and the electrical performance of the memory is improved; on the other hand, since the storage hole 31 is directly formed in the first dielectric layer 21, the storage structure 40 is located in the first dielectric layer 21, not only a three-dimensional memory (i.e., the three-dimensional memory) is formed, but also the thickness of the memory is greatly reduced, which is conducive to further reducing the size of the memory and further improving the storage density. In this specific embodiment, a chemical mechanical polishing process is used to remove part of the conductive filling layer 41, part of the storage structure 40 and all of the second dielectric layer 30 above the first dielectric layer 21, so that the conductive filling layer 41 is electrically connected to the storage structure 40, and the top surface of the conductive filling layer 41, the top surface of the storage structure 40 and the top surface of the first contact structure 25 are flush, so that the connection between the adjacent storage structures in the same layer can be fully disconnected to avoid leakage between the adjacent storage structures. In addition, this specific embodiment uses chemical mechanical polishing to remove part of the conductive filling layer 41 above the first dielectric layer 21, part of the storage structure 40 and the entire second dielectric layer 30, without the need to use a mask in the process of disconnecting the connection between adjacent storage structures, thereby reducing the manufacturing cost of the three-dimensional memory.

[0113] In some embodiments, Figure 3 and Fig. 9 As shown, the storage holes 31 are distributed around the periphery of the first contact structure 25 and expose the sidewalls of the first contact structure 25. With the above structure, on the one hand, the inner wall area of ​​the storage hole 31 can be further increased, thereby further increasing the area of ​​the storage structure formed subsequently, so as to further improve the storage performance of the three-dimensional storage structure; on the other hand, the contact area between the storage structure formed subsequently and the first contact structure 25 can be increased, thereby further reducing the contact resistance between the storage structure and the first contact structure 25, thereby further improving the electrical performance of the three-dimensional memory.

[0114] In other embodiments, Fig.10 As shown, the storage hole 31 is located only on one side of the first contact structure 25 along the second direction D2 and exposes the side wall of the first contact structure 25, and the second direction D2 is parallel to the top surface of the substrate 20, so that even if the size of the three-dimensional memory continues to shrink and the interval between adjacent storage units in the three-dimensional memory continues to shrink, the area of ​​the storage structure 40 can be increased.

[0115] In some other embodiments, Fig.11As shown, the substrate includes at least two first contact structures 25 adjacent to each other along the second direction D2, and the storage hole 31 is located between the two adjacent first contact structures 25 and exposes the sidewalls of the two adjacent first contact structures 25, so that the two adjacent storage units share the same storage structure 40 (see Fig.11 ), which not only helps to further increase the area of ​​the storage structure 40, but also can more fully utilize the space in the three-dimensional memory and expand the function of the three-dimensional memory.

[0116] In some embodiments, Fig. 9 As shown, the first lead-out structure includes two first sub-lead-out structures 80 arranged along the second direction D2, and the two first sub-lead-out structures 80 are electrically connected to the conductive filling layer 41 located on opposite sides of the first contact structure 25 along the second direction D2, and the second direction D2 is parallel to the top surface of the substrate 20.

[0117] The three-dimensional memory and its manufacturing method provided in this specific embodiment, the substrate has a first contact structure that penetrates the first dielectric layer, and a storage hole that at least exposes the side wall of the first contact structure is formed in the first dielectric layer, and a storage structure that at least continuously covers the inner wall of the storage hole and the side wall of the first contact structure is formed, thereby forming a memory with a three-dimensional structure, which not only increases the area of ​​the storage structure and improves the performance and manufacturing yield of the memory, but also reduces the number of other dielectric layers deposited above the first dielectric layer, thereby helping to further reduce the size of the three-dimensional memory and improve the integration of the three-dimensional memory. At the same time, part of the conductive filling layer and part of the storage structure are removed through a chemical mechanical polishing process, so that the electrical connection between adjacent storage structures can be fully disconnected to avoid leakage between storage structures in the same layer.

[0118] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that: The steps include: forming a substrate, the substrate comprising a substrate, a first dielectric layer located on the substrate, and a first contact structure penetrating the first dielectric layer; forming a storage hole in the first dielectric layer to expose at least a side wall of the first contact structure; forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure and the top surface of the first contact structure, and the storage structure is in electrical contact with the first contact structure; forming a conductive filling layer that fills the storage hole and covers the surface of the storage structure, wherein the conductive filling layer is electrically connected to the storage structure; Using a chemical mechanical polishing process to remove part of the conductive filling layer and part of the storage structure, so that the top surface of the remaining conductive filling layer, the top surface of the remaining storage structure and the top surface of the first contact structure are flush; A first lead-out structure is formed which is located above the substrate and is electrically connected to the conductive filling layer.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that: The specific steps of forming the substrate include: Providing a substrate, wherein the substrate includes an active region, and the substrate includes a top surface and a bottom surface that are relatively distributed; forming a first dielectric layer on the top surface of the substrate; The first contact structure is formed along a first direction penetrating the first dielectric layer and electrically connected to the active region in the substrate, wherein the first direction intersects perpendicularly with the top surface of the substrate.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that: The active region includes a channel region and a source region and a drain region located on opposite sides of the channel region along a second direction, wherein the second direction is parallel to the top surface of the substrate; the first contact structure is electrically connected to the drain region, and the substrate further includes a second contact structure that penetrates the first dielectric layer and is electrically connected to the source region; The specific steps of forming a storage hole in the first dielectric layer to expose at least the sidewall of the first contact structure include: forming a second dielectric layer covering the first dielectric layer, the first contact structure and the second contact structure; The second dielectric layer and the first dielectric layer are etched to form the storage hole penetrating the second dielectric layer and extending into the first dielectric layer.

4. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that: The specific steps of forming a storage hole in the first dielectric layer to expose at least the sidewall of the first contact structure include: The first dielectric layer and the second dielectric layer are etched to form the storage holes distributed around the periphery of the first contact structure and exposing the sidewalls of the first contact structure.

5. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that: The specific steps of forming a storage structure that continuously covers at least the inner wall of the storage hole, the side wall of the first contact structure, and the top surface of the first contact structure include: forming a lower electrode layer that continuously covers the inner wall of the storage hole, the side wall of the first contact structure, the top surface of the first contact structure, and the top surface of the second dielectric layer; forming a storage layer covering the lower electrode layer; An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

6. The method for manufacturing a three-dimensional memory according to claim 5, characterized in that: The specific steps of removing part of the conductive filling layer and part of the storage structure by using a chemical mechanical polishing process include: A chemical mechanical polishing process is used to remove part of the conductive filling layer, part of the storage structure and the entire second dielectric layer above the first dielectric layer, so that the top surface of the remaining conductive filling layer, the top surface of the remaining storage structure, the top surface of the first contact structure and the top surface of the first dielectric layer are flush, and the second contact structure is exposed.

7. The method for manufacturing a three-dimensional memory according to claim 6, characterized in that: The specific steps of forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer include: forming a third dielectric layer covering the substrate; forming two first sub-lead-out holes penetrating the third dielectric layer and exposing the conductive filling layer located on opposite sides of the first contact structure along the second direction one by one; A first sub-lead-out structure is formed to fill each of the first sub-lead-out holes respectively, and two first sub-lead-out structures together constitute the first lead-out structure.

8. The method for manufacturing a three-dimensional memory according to claim 7, characterized in that: After forming a first lead-out structure located above the substrate and electrically connected to the conductive filling layer, the following steps are also included: A first conductive connection pad electrically connecting the two first sub-lead-out structures is formed above the third dielectric layer.

9. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that: The specific steps of forming a storage hole in the first dielectric layer to expose at least the sidewall of the first contact structure include: The first dielectric layer and the second dielectric layer are etched to form the storage hole which is located only on one side of the first contact structure along the second direction and exposes the sidewall of the first contact structure.

10. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that: The substrate comprises at least two first contact structures adjacent to each other along the second direction; The specific steps of forming a storage hole in the first dielectric layer to expose at least the sidewall of the first contact structure include: The first dielectric layer and the second dielectric layer are etched to form the storage hole located between two adjacent first contact structures and exposing the side walls of the two adjacent first contact structures.

11. A three-dimensional memory, characterized in that: include: A base, comprising a substrate, a first dielectric layer located above the substrate, and a first contact structure penetrating the first dielectric layer along a first direction, wherein the substrate comprises a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the substrate perpendicularly; A storage hole, located in the first dielectric layer, wherein the storage hole at least exposes a side wall of the first contact structure; a storage structure, continuously covering an inner wall of the storage hole and a side wall of the first contact structure, and the storage structure is in electrical contact with the first contact structure; A conductive filling layer, which fills the storage hole and covers the surface of the storage structure, the conductive filling layer is electrically connected to the storage structure, and the top surface of the conductive filling layer, the top surface of the storage structure and the top surface of the first contact structure are flush; The first lead-out structure is located above the substrate and is electrically connected to the conductive filling layer.

12. The three-dimensional memory according to claim 11, characterized in that: The storage holes are distributed around the outer circumference of the first contact structure and expose the sidewalls of the first contact structure.

13. The three-dimensional memory according to claim 11, characterized in that: The storage hole is located only at one side of the first contact structure along a second direction and exposes a sidewall of the first contact structure. The second direction is parallel to a top surface of the substrate.

14. The three-dimensional memory according to claim 13, characterized in that: The substrate includes at least two adjacent first contact structures along the second direction, and the storage hole is located between the two adjacent first contact structures and exposes side walls of the two adjacent first contact structures.

15. The three-dimensional memory according to claim 12, characterized in that: The first lead-out structure includes two first sub-lead-out structures arranged along a second direction, the two first sub-lead-out structures are electrically connected to the conductive filling layer located on opposite sides of the first contact structure along the second direction, and the second direction is parallel to the top surface of the substrate.

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