Training method and device for directed graph neural network model based on graph pattern

Abstract

The present application relates to a training method and device for a directed graph neural network model based on a graph pattern. The method includes: obtaining non-AND graph data and physical data labels corresponding to the non-AND graph data; the non-AND graph data includes a two-input AND gate logic network and a one-input NOT gate logic network; constructing a graph pattern according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network; according to the graph pattern, identifying pattern features and pattern distribution from the non-AND graph data to obtain graph pattern data; constructing a directed graph neural network model to be trained according to the structural features of the non-AND graph and the functional features of the non-AND graph; training the directed graph neural network model to be trained according to the non-AND graph data, physical data labels and graph pattern data to obtain a trained directed graph neural network model. The use of this method can be beneficial to troubleshooting and subsequent improvements.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to a training method and device for a directed graph neural network model based on a graph pattern. Background Art

[0002] In electronic design automation, the process of logic synthesis includes logic conversion, logic optimization and process mapping. Logic conversion is to convert other forms of logic expressions into logic expressions that are easy to process. Logic optimization is to convert logic expressions into "optimal implementations" and comprehensively consider the best parameters such as complexity, area, and delay. In order to obtain these indicators and parameters, process mapping can convert gate circuits into standard cell netlists of specified processes. Through physical design analysis, parameters such as delay and area based on the cell library can be obtained. The goal of logic synthesis is not only functional correctness, but also optimization in many aspects such as area, power consumption and speed.

[0003] In traditional technology, the feature extraction process of the NAND graph is an undisclosed formula in existing commercial tools. The process is generally a given NAND graph, and the tool can automatically generate its area, delay and other feature data, and its process flow is unknown. Since the optimization process in existing tools is an undisclosed technical content, the NAND graph optimization process using existing tools has the problems of technical opacity and unpredictable feature extraction effects. In addition, it is impossible to obtain data in the middle of the NAND graph optimization sequence, and the specific algorithms and steps of the feature extraction process are unknown. If a problem occurs, it is difficult for engineers to locate the specific cause, which is not conducive to troubleshooting and subsequent improvements. Summary of the invention

[0004] Based on this, it is necessary to provide a training method, device, computer equipment, computer-readable storage medium and computer program product for a directed graph neural network model based on a graph pattern, which can be conducive to troubleshooting and subsequent improvement in order to solve the above technical problems.

[0005] In a first aspect, the present application provides a method for training a directed graph neural network model based on a graph pattern. The method comprises:

[0006] Acquire non-AND graph data and physical data labels corresponding to the non-AND graph data; the non-AND graph data includes a two-input AND gate logic network and a one-input NOT gate logic network;

[0007] Constructing a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network;

[0008] According to the graph pattern, pattern features and pattern distribution are identified from the AND-NON graph data to obtain graph pattern data;

[0009] According to the structural features of the non-AND graph and the functional features of the non-AND graph, a directed graph neural network model to be trained is constructed; the structural features of the non-AND graph and the functional features of the non-AND graph are obtained by extracting features from the non-AND graph data and the physical data labels;

[0010] The directed graph neural network model to be trained is trained according to the NAND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model.

[0011] In a second aspect, the present application also provides a training device for a directed graph neural network model based on a graph pattern. The device comprises:

[0012] A data acquisition module, used to acquire AND-not graph data and physical data labels corresponding to the AND-not graph data; the AND-not graph data includes a two-input AND gate logic network and a one-input NOT gate logic network;

[0013] A data definition module, used to construct a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network;

[0014] A data processing module, used for identifying pattern features and pattern distribution from the AND / OR graph data according to the graph pattern, to obtain graph pattern data;

[0015] A model building module, used to build a directed graph neural network model to be trained according to the structural features of the non-AND graph and the functional features of the non-AND graph; the structural features of the non-AND graph and the functional features of the non-AND graph are obtained by extracting features from the non-AND graph data and the physical data labels;

[0016] The model training module is used to train the directed graph neural network model to be trained according to the non-AND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model.

[0017] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0018] Acquire non-AND graph data and physical data labels corresponding to the non-AND graph data; the non-AND graph data includes a two-input AND gate logic network and a one-input NOT gate logic network;

[0019] Constructing a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network;

[0020] According to the graph pattern, pattern features and pattern distribution are identified from the AND-NON graph data to obtain graph pattern data;

[0021] According to the structural features of the non-AND graph and the functional features of the non-AND graph, a directed graph neural network model to be trained is constructed; the structural features of the non-AND graph and the functional features of the non-AND graph are obtained by extracting features from the non-AND graph data and the physical data labels;

[0022] The directed graph neural network model to be trained is trained according to the NAND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model.

[0023] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0024] Acquire non-AND graph data and physical data labels corresponding to the non-AND graph data; the non-AND graph data includes a two-input AND gate logic network and a one-input NOT gate logic network;

[0025] Constructing a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network;

[0026] According to the graph pattern, pattern features and pattern distribution are identified from the AND-NON graph data to obtain graph pattern data;

[0027] According to the structural features of the non-AND graph and the functional features of the non-AND graph, a directed graph neural network model to be trained is constructed; the structural features of the non-AND graph and the functional features of the non-AND graph are obtained by extracting features from the non-AND graph data and the physical data labels;

[0028] The directed graph neural network model to be trained is trained according to the NAND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model.

[0029] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0030] Acquire non-AND graph data and physical data labels corresponding to the non-AND graph data; the non-AND graph data includes a two-input AND gate logic network and a one-input NOT gate logic network;

[0031] Constructing a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network;

[0032] According to the graph pattern, pattern features and pattern distribution are identified from the AND-NON graph data to obtain graph pattern data;

[0033] According to the structural features of the non-AND graph and the functional features of the non-AND graph, a directed graph neural network model to be trained is constructed; the structural features of the non-AND graph and the functional features of the non-AND graph are obtained by extracting features from the non-AND graph data and the physical data labels;

[0034] The directed graph neural network model to be trained is trained according to the NAND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model.

[0035] The above-mentioned training method, device, computer equipment, storage medium and computer program product of a directed graph neural network model based on a graph pattern, by introducing the physical label information of the AND-NORMAL graph data and combining the structural characteristics of the two-input AND gate logic network and the one-input NOT gate logic network, constructs a graph pattern and extracts pattern features and pattern distribution from it, so that the complex logical relationship of the circuit structure can be accurately modeled. Through these characteristics and distribution information, a directed graph neural network model based on a graph pattern is constructed and targeted training is carried out. This method not only enhances the model's ability to characterize the physical characteristics of the circuit, but also improves the comprehensiveness and accuracy of feature extraction, so that in the subsequent circuit optimization and analysis process, it can better handle large-scale and complex circuit design problems, which is conducive to troubleshooting and subsequent improvements, and overcomes the limitations of traditional methods in insufficient feature extraction and model opacity, thereby significantly improving the overall performance and optimization effect of circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a diagram of an application environment of a training method for a directed graph neural network model based on a graph pattern in one embodiment;

[0037] FIG2 is a flow chart of a method for training a directed graph neural network model based on a graph pattern in one embodiment;

[0038] FIG3 is a schematic flow chart of a method for obtaining a trained directed graph neural network model in one embodiment;

[0039] FIG4 is a schematic flow chart of a method for obtaining a trained directed graph neural network model in another embodiment;

[0040] FIG5 is a schematic flow chart of a method for obtaining a trained directed graph neural network model in another embodiment;

[0041] FIG6 is a schematic diagram of a flow chart of a method for constructing a directed graph neural network model to be trained in one embodiment;

[0042] FIG7 is a schematic diagram of a flow chart of a method for constructing a directed graph neural network model to be trained in another embodiment;

[0043] FIG8 is a schematic diagram of a flow chart of a method for obtaining map model data in one embodiment;

[0044] FIG9 is a conceptual diagram of non-graphic data and physical data labels in one embodiment;

[0045] FIG10 is a schematic diagram of a setting of a drawing mode in one embodiment;

[0046] FIG11 is a schematic diagram of a structure setting of a directed graph neural network model to be trained in one embodiment;

[0047] FIG12 is a schematic diagram of a training process of a directed graph neural network model to be trained in one embodiment;

[0048] FIG13 is a structural block diagram of a training device for a directed graph neural network model based on a graph pattern in one embodiment;

[0049] FIG. 14 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] A training method for a directed graph neural network model based on a graph pattern provided in an embodiment of the present application can be applied in an application environment as shown in FIG1 . In which, the terminal 102 communicates with the server 104 via a network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on a cloud or other network server. The server 104 obtains the AND-NON graph data and the physical data labels corresponding to the AND-NON graph data through the terminal 102; the AND-NON graph data includes a two-input AND gate logic network and a one-input NOT gate logic network; a graph pattern is constructed according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network; according to the graph pattern, the pattern features and pattern distribution are identified from the AND-NON graph data to obtain the graph pattern data; according to the structure features of the AND-NON graph and the functional features of the AND-NON graph, a directed graph neural network model to be trained is constructed; the structure features of the AND-NON graph and the functional features of the AND-NON graph are obtained by feature extraction of the AND-NON graph data and the physical data labels; according to the AND-NON graph data, the physical data labels and the graph pattern data, the directed graph neural network model to be trained is trained to obtain a trained directed graph neural network model. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptops, tablet computers, etc. The server 104 can be implemented by an independent server or a server cluster composed of multiple servers.

[0052] In one embodiment, as shown in FIG2 , a training method for a directed graph neural network model based on a graph pattern is provided, and the method is applied to the server in FIG1 as an example for explanation, and includes the following steps:

[0053] Step 202, obtaining non-graph data and physical data labels corresponding to the non-graph data.

[0054] The NAND graph data may be graph structure data used to represent a logic circuit, wherein nodes represent two-input AND gates and one-input Inverter gates, and edges represent the transmission relationship of logic signals between these nodes.

[0055] Among them, physical data labels can refer to key physical properties related to logic circuits or non-graph data, which usually include indicators such as area, delay, power consumption, etc. They are used to quantitatively describe the performance of the circuit in actual hardware implementation.

[0056] Specifically, a set of NAND graph data containing a two-input AND gate logic network and a one-input NOT gate logic network is obtained, and then the physical data label is attached to each NAND graph data, including key indicators such as area, delay, and power consumption. The data is standardized or normalized using data preprocessing technology to ensure the consistency of model input and data availability. Finally, the preprocessed NAND graph data and physical data labels are obtained as the input of the subsequent graph neural network model. The basic concept and structural diagram of the NAND graph (AIG) shown in Figure 9, where the NAND graph is a logic network composed of two-input AND gates and one-input NOT gates. The nodes in the graph represent logic gates: AND gates are used to implement the logical AND operation of two inputs, and NOT gates are used for inversion operations. The edges represent the transmission path of the logic signal, connecting different logic gates to realize the function of the circuit. Figure 9 shows how to decompose a complex logic expression into a combination of basic AND gates and NOT gates, thereby forming a graph model, which is convenient for analysis and optimization in the process of circuit design automation (EDA) and logic synthesis optimization.

[0057] Step 204, constructing a graph model based on the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network.

[0058] Among them, the structural characteristic information can be the topological structure and connection relationship of the two-input AND gate and NOT gate logic network in the NOT diagram. This information includes node type, connection method between nodes, input-output relationship, and combination mode of logic gates, etc. These characteristic information can reflect the internal logical layout and organization of the circuit.

[0059] Among them, graph patterns refer to smaller subgraphs that appear frequently in a graph and are represented as the basic patterns of the graph. Graph patterns can reveal some general laws in the graph, showing the significance of one or some structures in the graph, and can predict hidden relationships that have not yet been discovered in the graph through the distribution law of graph patterns. For example, graph patterns can be specific subgraph structures or patterns that appear repeatedly in graph data structures. These patterns capture the common connection relationships between nodes and edges in the graph. In a non-AND graph, graph patterns are usually subgraph structures that exist in large numbers in the non-AND graph, which are usually selected manually or automatically generated by algorithms. For example, Figure 9 shows all logical structures that can be represented by all two-input structures, which is an example of a graph pattern and is used to represent common logical units or combinations in circuits.

[0060] Specifically, the structural characteristics of the two-input AND gate logic network and the one-input NOT gate logic network are analyzed, such as their connection methods and common combinations in the circuit. Based on these structural characteristics, common subgraph structures or patterns are defined and extracted, such as the series combination of AND gates and NAND gates, the parallel structure of multi-input AND gates, etc. As shown in Figure 10, the typical structure of the combination of two-input AND gates and NOT gates in the NAND graph is illustrated, and these structures are abstracted into standardized graph patterns. These graph patterns not only represent the common logical combinations in circuits, such as the series or parallel structure of AND gates and NOT gates, but are also used to identify and extract key features in the NAND graph. Figure 10 uses intuitive diagrams to illustrate how to extract patterns from complex NAND graphs for subsequent feature analysis and optimization processes, helping the model to better understand the logical relationship of the circuit.

[0061] Step 206, according to the graph pattern, identify the pattern features and pattern distribution from the non-graph data to obtain the graph pattern data.

[0062] Among them, pattern features can be the key attributes and structural features of specific graph patterns identified in graph data, which include the type and number of nodes, the connection relationship of edges, the shape of the graph, and physical properties related to the pattern (such as area, delay, power consumption, etc.).

[0063] The pattern distribution can be the frequency and location distribution of a specific graph pattern in the entire graph data. It describes the distribution range, concentration, and number of occurrences of a specific pattern in different parts of the graph.

[0064] Among them, graph pattern data can refer to a set of information about a specific graph pattern extracted and recorded in the graph structure. These data include pattern features (such as node type, connection relationship, physical properties) and pattern distribution (the frequency and position of the pattern in the graph).

[0065] Specifically, predefined graph patterns are extracted from the AND-NO graph data, and relevant substructures in the AND-NO graph are identified by matching these patterns. Then, the features of each graph pattern are calculated, such as the number of nodes, the connection relationship of the edges, and the physical properties related to the pattern (such as area, delay, etc.). At the same time, the distribution frequency of these graph patterns in the entire AND-NO graph is counted, and the number and location of their occurrences are recorded. Finally, these features and distribution information are summarized to form complete graph pattern data.

[0066] Step 208, constructing a directed graph neural network model to be trained according to the structural features of the non-AND graph and the functional features of the non-AND graph.

[0067] The structural features of the AIG may refer to physical properties related to circuit performance described by the topological structure and connection relationship in the AIG, such as the area, delay, power consumption and other characteristics of the circuit.

[0068] Among them, the functional characteristics of the NAND graph may refer to the functions represented by the circuit in the NAND graph (AIG), such as gcd (greatest common divisor), sqrt (square root), adder (adder) and other functions.

[0069] The directed graph neural network model to be trained can be a neural network model that has not been trained yet, and its structure is specially designed to process directed graph data, such as an AND-independent graph (AIG). The input layer of the model accepts the structural and functional features of the graph, and gradually extracts and learns the complex relationships between nodes and edges in the graph through multi-layer neural networks (such as graph attention layers and recurrent unit layers).

[0070] Specifically, the properties of the non-graph are extracted from the non-graph data, where the properties of the non-graph include at least structural features (such as node type, connection relationship, topology, circuit area, delay, power consumption, etc.) and functional features (gcd (greatest common divisor), sqrt (square root), adder (adder), etc.), and feature processing and normalization are performed in combination with physical data labels. Then, based on these extracted features, the input layer of the directed graph neural network model is designed to receive these feature data, and the deep structure of the model is constructed through the graph neural network layer (such as the graph attention layer and the gated recurrent unit layer), so that it can capture and learn the complex relationships and functional attributes in the graph. Finally, the output layer is designed by generating the representation vector of the non-graph through the multi-layer perceptron output layer to obtain the directed graph neural network model to be trained. The input of the directed graph neural network model to be trained is the non-graph network, and the output is the representation feature of the non-graph in the feature space, so that the representation feature can characterize the physics, structure and function of the non-graph to a certain extent under the action of the activation function. As shown in Figure 11, it is one example of a directed graph neural network model to be trained, which consists of 4 layers of attention graph perceptron layers, 4 layers of gated recurrent units, and multiple multi-layer perceptrons for outputting results. At the same time, Figure 11 shows the data processing and transmission process in the directed graph neural network model to be trained. However, for the directed graph neural network model to be trained, different numbers of attention graph perceptron layers, gated recurrent units, and multi-layer perceptrons can be selected. Figure 11 further shows the overall architecture of the directed graph neural network model built based on the structural features and functional features of the NAND graph. Figure 11 describes in detail that starting from the input layer, the node features and edge features of the NAND graph are accepted, and after being processed by multi-layer attention graph perceptrons (Graph Attention Layers) and gated recurrent units (GRU Layers), the complex structural relationships and functional characteristics in the graph are gradually extracted and learned. Finally, the representation feature vector of the NAND graph is generated through the multi-layer perceptron (MLP) output layer. This model architecture combines structural and functional features to enable the neural network to more accurately simulate and predict the physical properties of the circuit, providing efficient support for subsequent optimization and design.

[0071] Step 210, training the directed graph neural network model to be trained according to the non-graph data, physical data labels and graph pattern data to obtain a trained directed graph neural network model.

[0072] The trained directed graph neural network model may be a neural network model obtained after a training process, and the model is specialized in processing directed graph data, such as an AND-not graph (AIG). During the training process, the model parameters have been optimized based on the input AND-not graph structural features, functional features, graph pattern data, and corresponding physical data labels.

[0073] Specifically, the non-graph data, physical data labels and graph pattern data are used as the input vectors of the directed graph neural network model to be trained, and the randomly initialized orthogonal vector is used as the initial value. The number of network iterations is set to 1000, the learning rate is set to 0.001, and the Adam optimizer is used to combine the representation features and physical features to form a mixed loss function (as shown in Figure 12); the predicted value is calculated by forward propagation, and the loss function is used to measure the gap between the predicted value and the actual label. Then, the optimization algorithm (such as Adam) is applied to adjust the model parameters through back propagation, gradually reduce the value of the loss function, and obtain the pre-trained directed graph neural network model through multiple iterative training. The test data is further input into the pre-trained directed graph neural network model for testing, and the predicted non-graph physical parameter features are compared with the actual parameter features. According to the comparison results, the network model is reversely optimized to obtain the trained directed graph neural network model.

[0074] In the above-mentioned training method of a directed graph neural network model based on graph patterns, by introducing the physical label information of the AND-NORMAL graph data and combining the structural characteristics of the two-input AND gate logic network and the one-input NOT gate logic network, a graph pattern is constructed and pattern features and pattern distribution are extracted from it, so that the complex logical relationship of the circuit structure can be accurately modeled. Through these features and distribution information, a directed graph neural network model based on graph patterns is constructed and targeted training is carried out. This method not only enhances the model's ability to characterize the physical characteristics of the circuit, but also improves the comprehensiveness and accuracy of feature extraction, so that in the subsequent circuit optimization and analysis process, it can better handle large-scale and complex circuit design problems, which is conducive to troubleshooting and subsequent improvements, and overcomes the limitations of traditional methods in insufficient feature extraction and model opacity, thereby significantly improving the overall performance and optimization effect of circuit design.

[0075] In one embodiment, as shown in FIG3 , the directed graph neural network model to be trained is trained according to the non-graph data, the physical data label, and the graph pattern data to obtain a trained directed graph neural network model, including:

[0076] Step 302: Initialize the orthogonal vectors of the directed graph neural network model to be trained using the graph pattern features, and set the number of network iterations and the learning rate of the directed graph neural network model to be trained.

[0077] Among them, orthogonal vectors can be a set of vectors in the vector space whose inner product between each other is zero, indicating that these vectors are perpendicular and independent of each other in space. In neural networks, using orthogonal vectors for weight initialization can ensure that the weight matrices of each layer have no correlation in the initial state, avoid information redundancy and collinearity problems, thereby helping to accelerate the convergence of the training process and improve the training efficiency and performance of the model.

[0078] The number of network iterations may be the total number of times the entire training data set is used to update model parameters during the neural network training process.

[0079] The learning rate is the step size of the model parameter update at each iteration during the neural network training process. It determines the speed at which the model adjusts weights and biases during the back propagation process. A learning rate that is too high may cause the model to miss the optimal solution or the training to be unstable, while a learning rate that is too low may slow down the training process or even cause it to fall into a local minimum.

[0080] Specifically, by using graph pattern features to generate random matrices and orthogonalizing them (such as QR decomposition), a set of orthogonal vectors are obtained to initialize the weights of the neural network model to ensure the stability and convergence speed of the training. Then, the number of iterations of the network (such as 1000 times) and the learning rate (such as 0.001) are specified, where the number of iterations determines the number of times the model optimizes the parameters during the training process, and the learning rate controls the amplitude of the parameter adjustment in each iteration.

[0081] Step 304, performing multimodal training on the set directed graph neural network model to be trained according to the non-graph data, physical data labels and graph pattern data to obtain a trained directed graph neural network model.

[0082] Specifically, the structural features of non-graph data, physical data labels, and graph mode data are integrated into multimodal inputs to ensure that each data type can be fully utilized in the model. Then, these multimodal input data are input into the set directed graph neural network model, and the contribution of each data modality to the model output is calculated through forward propagation. In the back propagation, the model will adjust parameters based on the comprehensive loss function (combining the errors of all modalities). Through multiple iterative training, the model is gradually optimized, and finally a trained directed graph neural network model that can effectively integrate multiple data types is obtained.

[0083] In this embodiment, by initializing the orthogonal vectors of the directed graph neural network model to be trained, and reasonably setting the number of network iterations and the learning rate, it is ensured that the model is trained from the optimized starting point, thereby improving the stability and efficiency of the training. The model is multimodally trained in combination with non-graph data, physical data labels, and graph pattern data, so that the model can integrate the characteristics of multiple data sources and comprehensively learn and capture the complex relationship between circuit structure and function. Ultimately, this training method not only improves the prediction accuracy and generalization ability of the model, but also significantly enhances the practicality and reliability of the model in actual circuit design and optimization.

[0084] In one embodiment, as shown in FIG4 , multimodal training is performed on the set directed graph neural network model to be trained according to the non-graph data, the physical data label, and the graph pattern data to obtain a trained directed graph neural network model, including:

[0085] Step 402, based on the initial value of the orthogonal vector, the number of network iterations and the learning rate, the directed graph neural network model to be trained is trained using non-graph data, physical data labels and graph pattern data until the loss value of the mixed loss function of the directed graph neural network model to be trained is the minimum, thereby obtaining a pre-trained directed graph neural network model.

[0086] Among them, the hybrid loss function can be a loss function that combines multiple error metrics during the model training process to comprehensively evaluate the prediction error of the model. It usually combines different types of losses (such as the error of the representation feature and the error of the physical feature) with certain weights, thereby optimizing multiple objectives simultaneously during the training process.

[0087] Among them, the pre-trained directed graph neural network model can be a directed graph neural network model that has undergone preliminary training. The model has been trained through a specific data set (such as non-graph data, physical data labels, and graph pattern data), and its parameters have been optimized, so that the model has certain feature extraction and prediction capabilities. The pre-trained model can be used as a basic model, on which further fine-tuning or specific task training is performed to accelerate the convergence process and improve the performance of the final model.

[0088] Specifically, the weights of the model are initialized with orthogonal vectors, and the appropriate number of network iterations and learning rate are set. Then, the non-graph data, physical data labels, and graph pattern data are used as multimodal inputs to perform forward propagation to calculate the output of the model, and the gap between the output and the actual label is measured by the hybrid loss function. The hybrid loss function combines the differences between representational features and physical features in the feature space to comprehensively evaluate the prediction effect of the model. The model parameters are adjusted through the back-propagation algorithm to gradually reduce the loss value. This process continues within the specified number of iterations until the loss value of the hybrid loss function reaches the minimum, and finally the optimized pre-trained directed graph neural network model is obtained.

[0089] Step 404: Use the test data set to test the pre-trained directed graph neural network model, and reversely optimize the pre-trained directed graph neural network model according to the test results to obtain a trained directed graph neural network model.

[0090] The test data set may be a data set used to further optimize the model performance after the model is initially trained.

[0091] Specifically, the test data set is input into the pre-trained directed graph neural network model, and the pre-trained directed graph neural network model performs forward propagation to calculate the prediction results of the model to obtain the test results of the network model. Then, the test results of the network model are statistically calculated to obtain the non-graph physical parameter characteristics, and further compared with the actual parameter characteristics. According to the comparison results, the network model is reversely optimized, that is, the weights and biases of the model are adjusted to optimize the model parameters. This process is repeated to gradually reduce the error, and finally an optimized and better-performing trained directed graph neural network model is obtained.

[0092] In this embodiment, by initializing based on orthogonal vectors, reasonably setting the number of network iterations and learning rates, and using non-graph data, physical data labels, and graph pattern data for training, the model can effectively learn and capture the complex relationship between circuit structure and functional characteristics. By minimizing the loss value of the hybrid loss function, the model is ensured to achieve optimal performance in multiple dimensions. Subsequently, the prediction accuracy and generalization ability of the model are further improved by testing and reverse optimization using a test data set. Ultimately, this training and optimization process not only enables the model to perform well on the training set, but also ensures its robustness and practicality on unseen data, providing strong support for actual circuit design and optimization.

[0093] In one embodiment, as shown in FIG5 , the pre-trained directed graph neural network model is tested using a test data set, and the pre-trained directed graph neural network model is reversely optimized according to the test results to obtain a trained directed graph neural network model, including:

[0094] Step 502, input the test AND non-graph data into the pre-trained directed graph neural network model to obtain the test AND non-graph physical parameter characteristics.

[0095] Among them, the physical parameter characteristics of the test NAND graph can be the physical properties of the NAND graph output by the model prediction after the NAND graph data for testing is input into the pre-trained directed graph neural network model, and these properties include key indicators in circuit design.

[0096] Specifically, the NAND graph data (including node features and edge features) for testing are organized into an input format acceptable to the model. Then, these input data are passed to the pre-trained directed graph neural network model for forward propagation calculation. The model will process the input NAND graph data according to the learned weights and parameters, and output the corresponding test NAND graph physical parameter features, key indicators in circuit design, such as circuit design, structural features, functional features, area, delay, power consumption, etc.

[0097] Step 504 , compare the test and non-graphic physical parameter characteristics with the actual parameter characteristics corresponding to the test and non-graphic data to obtain parameter characteristic difference information.

[0098] Among them, the actual parameter characteristics can be physical properties measured or calculated in real hardware or design environment with non-graph data, including key performance indicators such as circuit design, structural characteristics, functional characteristics, area, delay, power consumption, etc.

[0099] The parameter characteristic difference information may be difference data obtained after comparing the physical parameter characteristics predicted by the model with the actual parameter characteristics. Such information quantifies the deviation between the model prediction and the actual situation.

[0100] Specifically, the test and non-graph physical parameter features predicted by the model are matched one by one with the actual physical parameter features recorded in the test data set, and the difference between each pair of corresponding parameters is calculated, for example, by calculating the absolute error or relative error to quantify the deviation between the predicted result and the actual value. Finally, these difference data are summarized as parameter feature difference information.

[0101] Step 506, optimizing the model parameters of the pre-trained directed graph neural network model according to the parameter feature difference information to obtain a trained directed graph neural network model.

[0102] Specifically, the error between the model prediction result and the actual value is calculated using the parameter feature difference information, and these errors are fed back to each layer of the model through the back propagation algorithm to adjust the model's weights and bias parameters. This optimization process gradually reduces the difference information and the overall error of the model through multiple iterations until the model parameters reach the optimal state. The final optimized model is a trained directed graph neural network model with higher prediction accuracy and generalization ability.

[0103] In this embodiment, by inputting the test non-graph data into the pre-trained directed graph neural network model, the predicted physical parameter characteristics are obtained, and these prediction results are compared with the actual parameter characteristics, so that the prediction error of the model can be quantified and parameter characteristic difference information can be generated. The model parameters are optimized based on this difference information to further adjust and improve the accuracy of the model. Ultimately, this iterative optimization process significantly improves the prediction accuracy and reliability of the model in practical applications, so that the model can more accurately reflect the real physical performance of the circuit, thereby providing more effective support for circuit design and optimization.

[0104] In one embodiment, as shown in FIG6 , a directed graph neural network model to be trained is constructed according to the structural features of the non-AND graph and the functional features of the non-AND graph, including:

[0105] Step 602, extract features from the NAND graph data and physical data labels to obtain NAND graph structural features and NAND graph functional features.

[0106] Specifically, the structural features of non-graph attributes are extracted from non-graph data, such as node type, connection relationship, topology, circuit area, delay, power consumption, etc.; the functional features of non-graph attributes are extracted from physical data labels, such as gcd (greatest common divisor), sqrt (square root), adder (adder), etc., which reflect the actual performance of the circuit. By combining these structural and functional features, a complete feature vector is formed.

[0107] Step 604, determining graph perception machine layer parameters, cyclic unit parameters and output layer parameters according to the NAND graph structural characteristics and NAND graph functional characteristics.

[0108] Among them, the graph perception machine layer parameters, recurrent unit parameters, and output layer parameters can be configuration parameters of different hierarchical structures in the graph neural network. The graph perception machine layer parameters include node feature dimensions, attention mechanism weights, etc., which are used to capture the complex relationship between nodes and edges in the graph. Recurrent unit parameters (such as the hidden layer size and time step of LSTM or GRU) are used to handle the sequence dependency and dynamic changes of graph data. The output layer parameters involve the selection of output dimensions and activation functions, which determine how the model generates the final prediction results, such as the physical properties of the circuit.

[0109] Specifically, the graph structure features are analyzed and the parameter configuration of the graph perception machine layer is determined, such as node feature dimensions, attention mechanism weights, etc., to accurately capture the relationship between nodes. Then, based on functional characteristics (such as area, delay, etc.), the parameters of the recurrent unit, such as hidden layer size and time step, are configured to handle the sequence dependencies in the graph data. Finally, according to the output requirements of the overall model, the parameters of the output layer, including output dimension and activation function, are set so that the model can effectively predict and characterize the physical properties of the circuit.

[0110] Step 606, constructing a directed graph neural network model to be trained according to the graph perception machine layer parameters, the recurrent unit parameters and the output layer parameters.

[0111] Specifically, the input layer and graph perception module of the graph neural network are set using the determined graph perception machine layer parameters to ensure that the features of nodes and edges can be effectively captured and processed. Next, the recurrent unit parameters are configured and a recurrent layer (such as GRU or LSTM) is added to handle the sequence dependencies in the graph data. Finally, the output layer is designed based on the output layer parameters, and the output dimension and activation function are set so that the model can accurately produce prediction results. These hierarchical structures are combined together to form a complete directed graph neural network model to be trained.

[0112] In this embodiment, by extracting features from the non-graph data and physical data labels, the structural features and functional features of the non-graph are accurately obtained, so that the model can better understand the logic and performance of the circuit. Based on these features, the parameters of the graph perception machine layer, the loop unit, and the output layer are reasonably determined to ensure that the model structure can fully capture the complex relationships and dynamic changes in the graph. Ultimately, the constructed directed graph neural network model to be trained has stronger expressive power and adaptability, laying a solid foundation for subsequent training and optimization, and improving the overall performance and application value of the model.

[0113] In one embodiment, as shown in FIG7 , a directed graph neural network model to be trained is constructed according to graph perception machine layer parameters, recurrent unit parameters, and output layer parameters, including:

[0114] Step 702, determining the correlation between the attention mechanism calculation nodes according to the graph perception machine layer parameters.

[0115] Specifically, according to the set graph perception machine layer parameters, the feature dimension and weight matrix of each node are defined, and the attention mechanism is applied to generate attention coefficients by calculating the similarity or correlation between nodes (usually using the dot product or weighted sum of node features), and these coefficients are normalized (such as using the softmax function) to ensure that their sum is 1, indicating the importance of the node to its neighbors. Finally, these normalized attention coefficients will be used to weight the sum of the features of neighboring nodes, thereby dynamically updating the representation of each node and obtaining the correlation between nodes in the graph.

[0116] Step 704, determining data flow information of the gated cycle unit according to the cycle unit parameters.

[0117] Among them, data flow information can be how input data is transmitted and processed between network layers and time steps in a neural network, especially in a recurrent neural network (such as GRU or LSTM). It includes the transmission path of data in the network, the activation function passed, and the control of information retention or forgetting by the gating mechanism (such as update gate, reset gate). Data flow information determines how the model processes and memorizes information at different time steps or sequence positions.

[0118] Specifically, the dimensions of the input and hidden states of the gated recurrent unit (such as GRU or LSTM) are configured according to the set recurrent unit parameters (such as hidden layer size and time step). Then, based on these parameters, the weight matrix and bias vector of the internal gating mechanisms such as update gate and reset gate are defined. Then, these gating mechanisms are used to control the flow of data within the unit, determine which information to retain, update or forget, so as to process the dependencies of sequence data and obtain data flow information.

[0119] Step 706, determining each fully connected layer and each nonlinear activation function in the output layer of the multilayer perceptron according to the output layer parameters.

[0120] Specifically, the structure of the multi-layer perceptron (MLP) is set according to the output layer parameters, and the input and output dimensions of each layer are determined, so as to configure the weight matrix and bias vector of each fully connected layer. Then, according to the parameter requirements, a suitable nonlinear activation function (such as ReLU, Sigmoid or Tanh) is selected after each fully connected layer to introduce nonlinear characteristics so that the model can better fit complex functional relationships. Finally, these fully connected layers and activation functions are combined into a complete output layer structure.

[0121] Step 708, constructing a directed graph neural network model to be trained according to the correlations, data flow information, fully connected layers and nonlinear activation functions.

[0122] Specifically, the attention mechanism is used to determine the correlation between nodes and applied to the graph perception machine layer to update the node feature representation. Then, by configuring the parameters of the gated recurrent unit, the data flow information is managed to ensure that the dependencies and dynamic changes of the sequence data are effectively processed. Then, the multi-layer perceptron output layer is constructed, and the outputs of the graph perception machine layer and the recurrent unit layer are connected according to the parameter settings of the fully connected layer and the nonlinear activation function to form a complete model architecture. Finally, these components are integrated to build a directed graph neural network model with graph structure processing capabilities.

[0123] In this embodiment, by determining the attention mechanism according to the parameters of the graph perception machine layer and accurately calculating the correlation between nodes, the model can effectively capture the complex relationship between nodes in the graph. The data flow information of the gated recurrent unit is optimized using the recurrent unit parameters to ensure that the model maintains the integrity and fluidity of information when processing sequence dependencies. By reasonably setting the output layer parameters, the fully connected layer and nonlinear activation function in the multi-layer perceptron are determined to enhance the nonlinear expression ability of the model. Finally, the directed graph neural network model to be trained constructed by integrating these key elements has powerful feature learning and prediction capabilities, provides a highly optimized architectural foundation for subsequent training, and improves the overall performance and application effect of the model. In one embodiment, as shown in Figure 8, pattern features include structural features and functional features. According to the graph pattern, pattern features and pattern distribution are identified from non-graph data to obtain graph pattern data, including:

[0124] Step 802, identifying each node and its adjacent nodes from the AND-NORMAL graph data according to the graph pattern.

[0125] Among them, nodes can be basic elements in the graph data structure, representing individuals or entities in the graph. In an AND-NOT graph, nodes usually represent logic gates (such as AND gates or NOT gates) and are connected to other nodes through edges, indicating the relationship or signal transmission between them.

[0126] Specifically, based on the predefined graph pattern analysis and non-graph data, each node in the graph is traversed to identify the type and attributes of the node. Then, the connection relationship of each node is checked, the adjacent nodes of the node are determined, and these adjacency relationships are recorded. For each node, an adjacency list or adjacency matrix can be established in the graph to reflect the connection and interaction between the node and its adjacent nodes.

[0127] Step 804: construct a topological structure based on each node and each adjacent node to obtain a structural feature.

[0128] Among them, structural features can be the topological relationship and arrangement of nodes and edges in graph data, which describe the overall layout and connection pattern of the graph. These features include node degree (i.e. the number of connected edges), path length, connectivity, clustering coefficient, etc., which reflect the relationship between nodes in the graph and the complexity of the overall structure.

[0129] Specifically, based on the information of nodes and their adjacent nodes, the topological structure of the graph is constructed, and each node is arranged in the graph according to its connection relationship to form a network of nodes and edges. Then, the topological structure is analyzed to extract key structural features, such as node degree (number of connected edges), path length, connectivity, etc. These structural features reflect the overall layout of the graph and the relationship between nodes.

[0130] Step 806: Determine functional characteristics according to each node and each adjacent node.

[0131] Among them, functional features can be the performance and role of a node or subgraph in a graph in actual applications. These features are usually related to the specific tasks or performance of the node. For example, in a logic circuit, functional features can include indicators such as node delay, power consumption, and logical operation. These features reflect the functional performance and efficiency of the node in the circuit.

[0132] Specifically, identify the type and attributes of each node (such as the function of the logic gate, input and output signals), as well as the types and connection relationships of its adjacent nodes. Then, by analyzing this information, calculate the functional characteristics of the node in the graph, such as the node's delay, power consumption, or complexity of the logic expression in the logic circuit; the functional characteristics combine the node's own attributes with its position and function in the graph, reflecting the functional performance of the node in the entire graph structure.

[0133] Step 808, according to different graph patterns, calculate the distribution corresponding to the non-graph data to obtain the pattern distribution.

[0134] Specifically, all subgraph structures in the NAND graph data that conform to the predefined graph patterns are identified. Then, the occurrence frequency and position of each graph pattern in the entire NAND graph are counted, and the distribution of these patterns in different regions is recorded. Finally, these statistical information is summarized to form pattern distribution data, which describes the overall layout and occurrence density of each graph pattern in the NAND graph.

[0135] Step 810, obtaining graph pattern data according to structural features, functional features and pattern distribution.

[0136] Specifically, the structural features (such as node degree and topological structure), functional features (such as latency and power consumption), and pattern distribution (such as the frequency and position of graph patterns) extracted from the AND-NORMAL graph are integrated to form comprehensive graph pattern data, which comprehensively reflects the graph's topological layout, node functional performance, and the global distribution of patterns.

[0137] In this embodiment, the topological structure of the circuit is accurately constructed by identifying each node and its adjacent nodes in the non-graph data according to the graph pattern, thereby extracting key structural features. Combined with the information of the node and the adjacent nodes, its functional characteristics are determined to further deepen the understanding of the physical performance of the circuit. By calculating the distribution of different graph patterns, the global layout characteristics of the non-graph data are mastered. Finally, by combining these structural features, functional features and pattern distribution, detailed graph pattern data is generated, which enhances the model's overall understanding of the circuit structure and performance, and provides rich and comprehensive data support for the training and optimization of the model.

[0138] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0139] Based on the same inventive concept, the embodiment of the present application also provides a training device for a directed graph neural network model based on a graph pattern for implementing the training method for the directed graph neural network model based on a graph pattern involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of one or more training devices for directed graph neural network models based on graph patterns provided below can be referred to the limitations of the training method for a directed graph neural network model based on a graph pattern above, and will not be repeated here.

[0140] In one embodiment, as shown in FIG13 , a training device for a directed graph neural network model based on a graph mode is provided, comprising: a data acquisition module 1302, a data definition module 1304, a data processing module 1306, a model construction module 1308 and a model training module 1310, wherein:

[0141] The data acquisition module 1302 is used to acquire the AND-NORMAL graph data and the physical data labels corresponding to the AND-NORMAL graph data; the AND-NORMAL graph data includes a two-input AND gate logic network and a one-input NOT gate logic network;

[0142] A data definition module 1304 is used to construct a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network;

[0143] The data processing module 1306 is used to identify pattern features and pattern distribution from non-graph data according to the graph pattern to obtain graph pattern data;

[0144] The model building module 1308 is used to build a directed graph neural network model to be trained according to the structural features of the non-graph and the functional features of the non-graph; the structural features of the non-graph and the functional features of the non-graph are obtained by extracting features from the non-graph data and the physical data labels;

[0145] The model training module 1310 is used to train the directed graph neural network model to be trained according to the non-graph data, physical data labels and graph pattern data to obtain a trained directed graph neural network model.

[0146] In one embodiment, the model training module 1310 is also used to initialize the orthogonal vectors of the directed graph neural network model to be trained with graph pattern features, and to set the number of network iterations and the learning rate of the directed graph neural network model to be trained; and to perform multimodal training on the directed graph neural network model to be trained that has been set according to non-graph data, physical data labels, and graph pattern data to obtain a trained directed graph neural network model.

[0147] In one embodiment, the model training module 1310 is also used to train the directed graph neural network model to be trained based on the initial value of the orthogonal vector, the number of network iterations and the learning rate, using non-graph data, physical data labels and graph pattern data, until the loss value of the mixed loss function of the directed graph neural network model to be trained is the minimum value, thereby obtaining a pre-trained directed graph neural network model; the mixed loss function is constructed by the representation features and physical features in the feature space of the non-graph data and the physical data labels; the pre-trained directed graph neural network model is tested using a test data set, and the pre-trained directed graph neural network model is reversely optimized according to the test results to obtain a trained directed graph neural network model.

[0148] In one embodiment, the model training module 1310 is also used to input the test and non-graph data into the pre-trained directed graph neural network model to obtain test and non-graph physical parameter characteristics; compare the test and non-graph physical parameter characteristics with the actual parameter characteristics corresponding to the test and non-graph data to obtain parameter characteristic difference information; optimize the model parameters of the pre-trained directed graph neural network model according to the parameter characteristic difference information to obtain a trained directed graph neural network model.

[0149] In one embodiment, the model building module 1308 is also used to extract features from the non-AND graph data and physical data labels to obtain the non-AND graph structural features and the non-AND graph functional features; determine the graph perception machine layer parameters, the loop unit parameters and the output layer parameters according to the non-AND graph structural features and the non-AND graph functional features; and construct a directed graph neural network model to be trained according to the graph perception machine layer parameters, the loop unit parameters and the output layer parameters.

[0150] In one embodiment, the model building module 1308 is also used to determine the correlation between each attention mechanism calculation node according to the graph perception machine layer parameters; determine the data flow information of the gated recurrent unit according to the recurrent unit parameters; determine each fully connected layer and each nonlinear activation function in the output layer of the multi-layer perceptron according to the output layer parameters; and construct a directed graph neural network model to be trained based on each correlation, data flow information, each fully connected layer and each nonlinear activation function.

[0151] In one embodiment, the data processing module 1306 is also used to identify each node and its adjacent nodes from non-graph data according to the graph pattern; construct a topological structure according to each node and each adjacent node to obtain structural features; determine functional features according to each node and each adjacent node; calculate the distribution corresponding to the non-graph data according to different graph patterns to obtain pattern distribution; obtain graph pattern data according to the structural features, functional features and pattern distribution.

[0152] Each module in the training device of the directed graph neural network model based on the graph pattern can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each module above.

[0153] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in FIG14. The computer device includes a processor, a memory, and a network interface connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store server data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a training method for a directed graph neural network model based on a graph pattern is implemented.

[0154] Those skilled in the art will understand that the structure shown in FIG. 14 is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0155] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0156] In one embodiment, a computer-readable storage medium is provided, storing a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0157] In one embodiment, a computer program product or computer program is provided, the computer program product or computer program includes computer instructions, the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in the above-mentioned method embodiments.

[0158] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0159] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0160] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A training method for a directed graph neural network model based on a graph pattern, characterized in that: The method comprises: Acquire non-AND graph data and physical data labels corresponding to the non-AND graph data; the non-AND graph data includes a two-input AND gate logic network and a one-input NOT gate logic network; Constructing a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network; According to the graph pattern, pattern features and pattern distribution are identified from the AND-NON graph data to obtain graph pattern data; The pattern features are key attributes and structural features of a specific graph pattern identified in the non-graph data, and the key attributes and structural features include the type and number of nodes, the connection relationship of edges, the shape of the graph, and physical properties related to the graph pattern; the pattern distribution is the frequency of occurrence and position distribution of the specific graph pattern in the entire non-graph data, which characterizes the distribution range, concentration, and number of occurrences of a specific graph pattern in different parts of the graph; The pattern features include structural features and functional features. The pattern features and pattern distribution are identified from the AND / OR graph data according to the graph pattern to obtain the graph pattern data, including: According to the graph pattern, identifying each node and its adjacent nodes from the AND-NOT graph data; Constructing a topological structure according to each of the nodes and each of the adjacent nodes to obtain the structural features; Determine the functional characteristics according to each of the nodes and each of the adjacent nodes; According to different graph patterns, calculating the distribution corresponding to the non-graph data to obtain the pattern distribution; According to the structural features, the functional features and the pattern distribution, the graph pattern data is obtained; According to the structural features of the non-AND graph and the functional features of the non-AND graph, a directed graph neural network model to be trained is constructed; the structural features of the non-AND graph and the functional features of the non-AND graph are obtained by extracting features from the non-AND graph data and the physical data labels; The directed graph neural network model to be trained is trained according to the NAND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model.

2. The method according to claim 1, characterized in that The step of training the directed graph neural network model to be trained according to the non-AND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model includes: Initializing the orthogonal vectors of the directed graph neural network model to be trained using graph pattern features, and setting the number of network iterations and the learning rate of the directed graph neural network model to be trained; According to the non-AND graph data, the physical data label and the graph pattern data, multimodal training is performed on the set directed graph neural network model to be trained to obtain the trained directed graph neural network model.

3. The method according to claim 2, characterized in that The step of performing multimodal training on the set directed graph neural network model to be trained according to the non-AND graph data, the physical data label and the graph pattern data to obtain the trained directed graph neural network model includes: Based on the initial value of the orthogonal vector, the number of network iterations and the learning rate, the directed graph neural network model to be trained is trained using the non-AND graph data, the physical data label and the graph pattern data until the loss value of the mixed loss function of the directed graph neural network model to be trained is the minimum value, thereby obtaining a pre-trained directed graph neural network model; the mixed loss function is constructed by the representation features and physical features in the feature space of the non-AND graph data and the physical data label; The pre-trained directed graph neural network model is tested using a test data set, and the pre-trained directed graph neural network model is reversely optimized according to the test results to obtain the trained directed graph neural network model.

4. The method according to claim 3, characterized in that The method of testing the pre-trained directed graph neural network model using a test data set and reversely optimizing the pre-trained directed graph neural network model according to the test result to obtain the trained directed graph neural network model includes: Inputting the test and non-graph data into the pre-trained directed graph neural network model to obtain the test and non-graph physical parameter characteristics; Comparing the test and non-image physical parameter characteristics with the actual parameter characteristics corresponding to the test and non-image data to obtain parameter characteristic difference information; The model parameters of the pre-trained directed graph neural network model are optimized according to the parameter feature difference information to obtain the trained directed graph neural network model.

5. The method according to any one of claims 1 to 4, characterized in that: The method of constructing a directed graph neural network model to be trained according to the structural features of the non-graph and the functional features of the non-graph includes: Performing feature extraction on the non-AND graph data and the physical data label to obtain the structural features of the non-AND graph and the functional features of the non-AND graph; Determine graph perception machine layer parameters, recurrent unit parameters, and output layer parameters according to the non-graph structural features and the non-graph functional features; The directed graph neural network model to be trained is constructed according to the graph perception machine layer parameters, the cyclic unit parameters and the output layer parameters.

6. The method according to claim 5, characterized in that The step of constructing the directed graph neural network model to be trained according to the graph perception machine layer parameters, the cyclic unit parameters and the output layer parameters includes: Determine the correlation between the attention mechanism calculation nodes according to the graph perception machine layer parameters; Determining data flow information of a gated cycle unit according to the cycle unit parameters; Determine each fully connected layer and each nonlinear activation function in the output layer of the multilayer perceptron according to the output layer parameters; The directed graph neural network model to be trained is constructed according to the correlations, the data flow information, the fully connected layers and the nonlinear activation functions.

7. A training device for a directed graph neural network model based on a graph pattern, characterized in that: The device comprises: A data acquisition module, used to acquire AND-not graph data and physical data labels corresponding to the AND-not graph data; the AND-not graph data includes a two-input AND gate logic network and a one-input NOT gate logic network; A data definition module, used to construct a graph model according to the structural characteristic information of the two-input AND gate logic network and the one-input NOT gate logic network; A data processing module, used for identifying pattern features and pattern distribution from the AND / OR graph data according to the graph pattern, to obtain graph pattern data; Wherein, the pattern features are key attributes and structural features of a specific graph pattern identified in the non-graph data, and the key attributes and structural features include the type and number of nodes, the connection relationship of edges, the shape of the graph, and physical properties related to the graph pattern; wherein, the pattern distribution is the frequency of occurrence and position distribution of the specific graph pattern in the entire non-graph data, characterizing the distribution range, concentration, and number of occurrences of a specific graph pattern in different parts of the graph; The pattern features include structural features and functional features. The pattern features and pattern distribution are identified from the AND / OR graph data according to the graph pattern to obtain the graph pattern data, including: According to the graph pattern, identifying each node and its adjacent nodes from the AND-NOT graph data; Constructing a topological structure according to each of the nodes and each of the adjacent nodes to obtain the structural features; Determine the functional characteristics according to each of the nodes and each of the adjacent nodes; According to different graph patterns, calculating the distribution corresponding to the non-graph data to obtain the pattern distribution; According to the structural features, the functional features and the pattern distribution, the graph pattern data is obtained; A model building module, used to build a directed graph neural network model to be trained according to the structural features of the non-AND graph and the functional features of the non-AND graph; the structural features of the non-AND graph and the functional features of the non-AND graph are obtained by extracting features from the non-AND graph data and the physical data labels; The model training module is used to train the directed graph neural network model to be trained according to the non-AND graph data, the physical data label and the graph pattern data to obtain a trained directed graph neural network model.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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